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1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/* Copyright 2017-2019 NXP */
3
4#include <asm/unaligned.h>
5#include <linux/mdio.h>
6#include <linux/module.h>
7#include <linux/fsl/enetc_mdio.h>
8#include <linux/of_platform.h>
9#include <linux/of_mdio.h>
10#include <linux/of_net.h>
11#include <linux/pcs-lynx.h>
12#include "enetc_ierb.h"
13#include "enetc_pf.h"
14
15#define ENETC_DRV_NAME_STR "ENETC PF driver"
16
17static void enetc_pf_get_primary_mac_addr(struct enetc_hw *hw, int si, u8 *addr)
18{
19 u32 upper = __raw_readl(hw->port + ENETC_PSIPMAR0(si));
20 u16 lower = __raw_readw(hw->port + ENETC_PSIPMAR1(si));
21
22 put_unaligned_le32(upper, addr);
23 put_unaligned_le16(lower, addr + 4);
24}
25
26static void enetc_pf_set_primary_mac_addr(struct enetc_hw *hw, int si,
27 const u8 *addr)
28{
29 u32 upper = get_unaligned_le32(addr);
30 u16 lower = get_unaligned_le16(addr + 4);
31
32 __raw_writel(upper, hw->port + ENETC_PSIPMAR0(si));
33 __raw_writew(lower, hw->port + ENETC_PSIPMAR1(si));
34}
35
36static int enetc_pf_set_mac_addr(struct net_device *ndev, void *addr)
37{
38 struct enetc_ndev_priv *priv = netdev_priv(ndev);
39 struct sockaddr *saddr = addr;
40
41 if (!is_valid_ether_addr(saddr->sa_data))
42 return -EADDRNOTAVAIL;
43
44 eth_hw_addr_set(ndev, saddr->sa_data);
45 enetc_pf_set_primary_mac_addr(&priv->si->hw, 0, saddr->sa_data);
46
47 return 0;
48}
49
50static void enetc_set_vlan_promisc(struct enetc_hw *hw, char si_map)
51{
52 u32 val = enetc_port_rd(hw, ENETC_PSIPVMR);
53
54 val &= ~ENETC_PSIPVMR_SET_VP(ENETC_VLAN_PROMISC_MAP_ALL);
55 enetc_port_wr(hw, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VP(si_map) | val);
56}
57
58static void enetc_enable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
59{
60 pf->vlan_promisc_simap |= BIT(si_idx);
61 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
62}
63
64static void enetc_disable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
65{
66 pf->vlan_promisc_simap &= ~BIT(si_idx);
67 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
68}
69
70static void enetc_set_isol_vlan(struct enetc_hw *hw, int si, u16 vlan, u8 qos)
71{
72 u32 val = 0;
73
74 if (vlan)
75 val = ENETC_PSIVLAN_EN | ENETC_PSIVLAN_SET_QOS(qos) | vlan;
76
77 enetc_port_wr(hw, ENETC_PSIVLANR(si), val);
78}
79
80static int enetc_mac_addr_hash_idx(const u8 *addr)
81{
82 u64 fold = __swab64(ether_addr_to_u64(addr)) >> 16;
83 u64 mask = 0;
84 int res = 0;
85 int i;
86
87 for (i = 0; i < 8; i++)
88 mask |= BIT_ULL(i * 6);
89
90 for (i = 0; i < 6; i++)
91 res |= (hweight64(fold & (mask << i)) & 0x1) << i;
92
93 return res;
94}
95
96static void enetc_reset_mac_addr_filter(struct enetc_mac_filter *filter)
97{
98 filter->mac_addr_cnt = 0;
99
100 bitmap_zero(filter->mac_hash_table,
101 ENETC_MADDR_HASH_TBL_SZ);
102}
103
104static void enetc_add_mac_addr_em_filter(struct enetc_mac_filter *filter,
105 const unsigned char *addr)
106{
107 /* add exact match addr */
108 ether_addr_copy(filter->mac_addr, addr);
109 filter->mac_addr_cnt++;
110}
111
112static void enetc_add_mac_addr_ht_filter(struct enetc_mac_filter *filter,
113 const unsigned char *addr)
114{
115 int idx = enetc_mac_addr_hash_idx(addr);
116
117 /* add hash table entry */
118 __set_bit(idx, filter->mac_hash_table);
119 filter->mac_addr_cnt++;
120}
121
122static void enetc_clear_mac_ht_flt(struct enetc_si *si, int si_idx, int type)
123{
124 bool err = si->errata & ENETC_ERR_UCMCSWP;
125
126 if (type == UC) {
127 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), 0);
128 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), 0);
129 } else { /* MC */
130 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), 0);
131 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), 0);
132 }
133}
134
135static void enetc_set_mac_ht_flt(struct enetc_si *si, int si_idx, int type,
136 unsigned long hash)
137{
138 bool err = si->errata & ENETC_ERR_UCMCSWP;
139
140 if (type == UC) {
141 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err),
142 lower_32_bits(hash));
143 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx),
144 upper_32_bits(hash));
145 } else { /* MC */
146 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err),
147 lower_32_bits(hash));
148 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx),
149 upper_32_bits(hash));
150 }
151}
152
153static void enetc_sync_mac_filters(struct enetc_pf *pf)
154{
155 struct enetc_mac_filter *f = pf->mac_filter;
156 struct enetc_si *si = pf->si;
157 int i, pos;
158
159 pos = EMETC_MAC_ADDR_FILT_RES;
160
161 for (i = 0; i < MADDR_TYPE; i++, f++) {
162 bool em = (f->mac_addr_cnt == 1) && (i == UC);
163 bool clear = !f->mac_addr_cnt;
164
165 if (clear) {
166 if (i == UC)
167 enetc_clear_mac_flt_entry(si, pos);
168
169 enetc_clear_mac_ht_flt(si, 0, i);
170 continue;
171 }
172
173 /* exact match filter */
174 if (em) {
175 int err;
176
177 enetc_clear_mac_ht_flt(si, 0, UC);
178
179 err = enetc_set_mac_flt_entry(si, pos, f->mac_addr,
180 BIT(0));
181 if (!err)
182 continue;
183
184 /* fallback to HT filtering */
185 dev_warn(&si->pdev->dev, "fallback to HT filt (%d)\n",
186 err);
187 }
188
189 /* hash table filter, clear EM filter for UC entries */
190 if (i == UC)
191 enetc_clear_mac_flt_entry(si, pos);
192
193 enetc_set_mac_ht_flt(si, 0, i, *f->mac_hash_table);
194 }
195}
196
197static void enetc_pf_set_rx_mode(struct net_device *ndev)
198{
199 struct enetc_ndev_priv *priv = netdev_priv(ndev);
200 struct enetc_pf *pf = enetc_si_priv(priv->si);
201 struct enetc_hw *hw = &priv->si->hw;
202 bool uprom = false, mprom = false;
203 struct enetc_mac_filter *filter;
204 struct netdev_hw_addr *ha;
205 u32 psipmr = 0;
206 bool em;
207
208 if (ndev->flags & IFF_PROMISC) {
209 /* enable promisc mode for SI0 (PF) */
210 psipmr = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0);
211 uprom = true;
212 mprom = true;
213 } else if (ndev->flags & IFF_ALLMULTI) {
214 /* enable multi cast promisc mode for SI0 (PF) */
215 psipmr = ENETC_PSIPMR_SET_MP(0);
216 mprom = true;
217 }
218
219 /* first 2 filter entries belong to PF */
220 if (!uprom) {
221 /* Update unicast filters */
222 filter = &pf->mac_filter[UC];
223 enetc_reset_mac_addr_filter(filter);
224
225 em = (netdev_uc_count(ndev) == 1);
226 netdev_for_each_uc_addr(ha, ndev) {
227 if (em) {
228 enetc_add_mac_addr_em_filter(filter, ha->addr);
229 break;
230 }
231
232 enetc_add_mac_addr_ht_filter(filter, ha->addr);
233 }
234 }
235
236 if (!mprom) {
237 /* Update multicast filters */
238 filter = &pf->mac_filter[MC];
239 enetc_reset_mac_addr_filter(filter);
240
241 netdev_for_each_mc_addr(ha, ndev) {
242 if (!is_multicast_ether_addr(ha->addr))
243 continue;
244
245 enetc_add_mac_addr_ht_filter(filter, ha->addr);
246 }
247 }
248
249 if (!uprom || !mprom)
250 /* update PF entries */
251 enetc_sync_mac_filters(pf);
252
253 psipmr |= enetc_port_rd(hw, ENETC_PSIPMR) &
254 ~(ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0));
255 enetc_port_wr(hw, ENETC_PSIPMR, psipmr);
256}
257
258static void enetc_set_vlan_ht_filter(struct enetc_hw *hw, int si_idx,
259 unsigned long hash)
260{
261 enetc_port_wr(hw, ENETC_PSIVHFR0(si_idx), lower_32_bits(hash));
262 enetc_port_wr(hw, ENETC_PSIVHFR1(si_idx), upper_32_bits(hash));
263}
264
265static int enetc_vid_hash_idx(unsigned int vid)
266{
267 int res = 0;
268 int i;
269
270 for (i = 0; i < 6; i++)
271 res |= (hweight8(vid & (BIT(i) | BIT(i + 6))) & 0x1) << i;
272
273 return res;
274}
275
276static void enetc_sync_vlan_ht_filter(struct enetc_pf *pf, bool rehash)
277{
278 int i;
279
280 if (rehash) {
281 bitmap_zero(pf->vlan_ht_filter, ENETC_VLAN_HT_SIZE);
282
283 for_each_set_bit(i, pf->active_vlans, VLAN_N_VID) {
284 int hidx = enetc_vid_hash_idx(i);
285
286 __set_bit(hidx, pf->vlan_ht_filter);
287 }
288 }
289
290 enetc_set_vlan_ht_filter(&pf->si->hw, 0, *pf->vlan_ht_filter);
291}
292
293static int enetc_vlan_rx_add_vid(struct net_device *ndev, __be16 prot, u16 vid)
294{
295 struct enetc_ndev_priv *priv = netdev_priv(ndev);
296 struct enetc_pf *pf = enetc_si_priv(priv->si);
297 int idx;
298
299 __set_bit(vid, pf->active_vlans);
300
301 idx = enetc_vid_hash_idx(vid);
302 if (!__test_and_set_bit(idx, pf->vlan_ht_filter))
303 enetc_sync_vlan_ht_filter(pf, false);
304
305 return 0;
306}
307
308static int enetc_vlan_rx_del_vid(struct net_device *ndev, __be16 prot, u16 vid)
309{
310 struct enetc_ndev_priv *priv = netdev_priv(ndev);
311 struct enetc_pf *pf = enetc_si_priv(priv->si);
312
313 __clear_bit(vid, pf->active_vlans);
314 enetc_sync_vlan_ht_filter(pf, true);
315
316 return 0;
317}
318
319static void enetc_set_loopback(struct net_device *ndev, bool en)
320{
321 struct enetc_ndev_priv *priv = netdev_priv(ndev);
322 struct enetc_si *si = priv->si;
323 u32 reg;
324
325 reg = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);
326 if (reg & ENETC_PM0_IFM_RG) {
327 /* RGMII mode */
328 reg = (reg & ~ENETC_PM0_IFM_RLP) |
329 (en ? ENETC_PM0_IFM_RLP : 0);
330 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, reg);
331 } else {
332 /* assume SGMII mode */
333 reg = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);
334 reg = (reg & ~ENETC_PM0_CMD_XGLP) |
335 (en ? ENETC_PM0_CMD_XGLP : 0);
336 reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) |
337 (en ? ENETC_PM0_CMD_PHY_TX_EN : 0);
338 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, reg);
339 }
340}
341
342static int enetc_pf_set_vf_mac(struct net_device *ndev, int vf, u8 *mac)
343{
344 struct enetc_ndev_priv *priv = netdev_priv(ndev);
345 struct enetc_pf *pf = enetc_si_priv(priv->si);
346 struct enetc_vf_state *vf_state;
347
348 if (vf >= pf->total_vfs)
349 return -EINVAL;
350
351 if (!is_valid_ether_addr(mac))
352 return -EADDRNOTAVAIL;
353
354 vf_state = &pf->vf_state[vf];
355 vf_state->flags |= ENETC_VF_FLAG_PF_SET_MAC;
356 enetc_pf_set_primary_mac_addr(&priv->si->hw, vf + 1, mac);
357 return 0;
358}
359
360static int enetc_pf_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan,
361 u8 qos, __be16 proto)
362{
363 struct enetc_ndev_priv *priv = netdev_priv(ndev);
364 struct enetc_pf *pf = enetc_si_priv(priv->si);
365
366 if (priv->si->errata & ENETC_ERR_VLAN_ISOL)
367 return -EOPNOTSUPP;
368
369 if (vf >= pf->total_vfs)
370 return -EINVAL;
371
372 if (proto != htons(ETH_P_8021Q))
373 /* only C-tags supported for now */
374 return -EPROTONOSUPPORT;
375
376 enetc_set_isol_vlan(&priv->si->hw, vf + 1, vlan, qos);
377 return 0;
378}
379
380static int enetc_pf_set_vf_spoofchk(struct net_device *ndev, int vf, bool en)
381{
382 struct enetc_ndev_priv *priv = netdev_priv(ndev);
383 struct enetc_pf *pf = enetc_si_priv(priv->si);
384 u32 cfgr;
385
386 if (vf >= pf->total_vfs)
387 return -EINVAL;
388
389 cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1));
390 cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0);
391 enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr);
392
393 return 0;
394}
395
396static int enetc_setup_mac_address(struct device_node *np, struct enetc_pf *pf,
397 int si)
398{
399 struct device *dev = &pf->si->pdev->dev;
400 struct enetc_hw *hw = &pf->si->hw;
401 u8 mac_addr[ETH_ALEN] = { 0 };
402 int err;
403
404 /* (1) try to get the MAC address from the device tree */
405 if (np) {
406 err = of_get_mac_address(np, mac_addr);
407 if (err == -EPROBE_DEFER)
408 return err;
409 }
410
411 /* (2) bootloader supplied MAC address */
412 if (is_zero_ether_addr(mac_addr))
413 enetc_pf_get_primary_mac_addr(hw, si, mac_addr);
414
415 /* (3) choose a random one */
416 if (is_zero_ether_addr(mac_addr)) {
417 eth_random_addr(mac_addr);
418 dev_info(dev, "no MAC address specified for SI%d, using %pM\n",
419 si, mac_addr);
420 }
421
422 enetc_pf_set_primary_mac_addr(hw, si, mac_addr);
423
424 return 0;
425}
426
427static int enetc_setup_mac_addresses(struct device_node *np,
428 struct enetc_pf *pf)
429{
430 int err, i;
431
432 /* The PF might take its MAC from the device tree */
433 err = enetc_setup_mac_address(np, pf, 0);
434 if (err)
435 return err;
436
437 for (i = 0; i < pf->total_vfs; i++) {
438 err = enetc_setup_mac_address(NULL, pf, i + 1);
439 if (err)
440 return err;
441 }
442
443 return 0;
444}
445
446static void enetc_port_assign_rfs_entries(struct enetc_si *si)
447{
448 struct enetc_pf *pf = enetc_si_priv(si);
449 struct enetc_hw *hw = &si->hw;
450 int num_entries, vf_entries, i;
451 u32 val;
452
453 /* split RFS entries between functions */
454 val = enetc_port_rd(hw, ENETC_PRFSCAPR);
455 num_entries = ENETC_PRFSCAPR_GET_NUM_RFS(val);
456 vf_entries = num_entries / (pf->total_vfs + 1);
457
458 for (i = 0; i < pf->total_vfs; i++)
459 enetc_port_wr(hw, ENETC_PSIRFSCFGR(i + 1), vf_entries);
460 enetc_port_wr(hw, ENETC_PSIRFSCFGR(0),
461 num_entries - vf_entries * pf->total_vfs);
462
463 /* enable RFS on port */
464 enetc_port_wr(hw, ENETC_PRFSMR, ENETC_PRFSMR_RFSE);
465}
466
467static void enetc_port_si_configure(struct enetc_si *si)
468{
469 struct enetc_pf *pf = enetc_si_priv(si);
470 struct enetc_hw *hw = &si->hw;
471 int num_rings, i;
472 u32 val;
473
474 val = enetc_port_rd(hw, ENETC_PCAPR0);
475 num_rings = min(ENETC_PCAPR0_RXBDR(val), ENETC_PCAPR0_TXBDR(val));
476
477 val = ENETC_PSICFGR0_SET_TXBDR(ENETC_PF_NUM_RINGS);
478 val |= ENETC_PSICFGR0_SET_RXBDR(ENETC_PF_NUM_RINGS);
479
480 if (unlikely(num_rings < ENETC_PF_NUM_RINGS)) {
481 val = ENETC_PSICFGR0_SET_TXBDR(num_rings);
482 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
483
484 dev_warn(&si->pdev->dev, "Found %d rings, expected %d!\n",
485 num_rings, ENETC_PF_NUM_RINGS);
486
487 num_rings = 0;
488 }
489
490 /* Add default one-time settings for SI0 (PF) */
491 val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
492
493 enetc_port_wr(hw, ENETC_PSICFGR0(0), val);
494
495 if (num_rings)
496 num_rings -= ENETC_PF_NUM_RINGS;
497
498 /* Configure the SIs for each available VF */
499 val = ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
500 val |= ENETC_PSICFGR0_VTE | ENETC_PSICFGR0_SIVIE;
501
502 if (num_rings) {
503 num_rings /= pf->total_vfs;
504 val |= ENETC_PSICFGR0_SET_TXBDR(num_rings);
505 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
506 }
507
508 for (i = 0; i < pf->total_vfs; i++)
509 enetc_port_wr(hw, ENETC_PSICFGR0(i + 1), val);
510
511 /* Port level VLAN settings */
512 val = ENETC_PVCLCTR_OVTPIDL(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
513 enetc_port_wr(hw, ENETC_PVCLCTR, val);
514 /* use outer tag for VLAN filtering */
515 enetc_port_wr(hw, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS);
516}
517
518void enetc_set_ptcmsdur(struct enetc_hw *hw, u32 *max_sdu)
519{
520 int tc;
521
522 for (tc = 0; tc < 8; tc++) {
523 u32 val = ENETC_MAC_MAXFRM_SIZE;
524
525 if (max_sdu[tc])
526 val = max_sdu[tc] + VLAN_ETH_HLEN;
527
528 enetc_port_wr(hw, ENETC_PTCMSDUR(tc), val);
529 }
530}
531
532void enetc_reset_ptcmsdur(struct enetc_hw *hw)
533{
534 int tc;
535
536 for (tc = 0; tc < 8; tc++)
537 enetc_port_wr(hw, ENETC_PTCMSDUR(tc), ENETC_MAC_MAXFRM_SIZE);
538}
539
540static void enetc_configure_port_mac(struct enetc_si *si)
541{
542 struct enetc_hw *hw = &si->hw;
543
544 enetc_port_mac_wr(si, ENETC_PM0_MAXFRM,
545 ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE));
546
547 enetc_reset_ptcmsdur(hw);
548
549 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
550 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
551
552 /* On LS1028A, the MAC RX FIFO defaults to 2, which is too high
553 * and may lead to RX lock-up under traffic. Set it to 1 instead,
554 * as recommended by the hardware team.
555 */
556 enetc_port_mac_wr(si, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL);
557}
558
559static void enetc_mac_config(struct enetc_si *si, phy_interface_t phy_mode)
560{
561 u32 val;
562
563 if (phy_interface_mode_is_rgmii(phy_mode)) {
564 val = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);
565 val &= ~(ENETC_PM0_IFM_EN_AUTO | ENETC_PM0_IFM_IFMODE_MASK);
566 val |= ENETC_PM0_IFM_IFMODE_GMII | ENETC_PM0_IFM_RG;
567 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);
568 }
569
570 if (phy_mode == PHY_INTERFACE_MODE_USXGMII) {
571 val = ENETC_PM0_IFM_FULL_DPX | ENETC_PM0_IFM_IFMODE_XGMII;
572 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);
573 }
574}
575
576static void enetc_mac_enable(struct enetc_si *si, bool en)
577{
578 u32 val = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);
579
580 val &= ~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
581 val |= en ? (ENETC_PM0_TX_EN | ENETC_PM0_RX_EN) : 0;
582
583 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, val);
584}
585
586static void enetc_configure_port(struct enetc_pf *pf)
587{
588 u8 hash_key[ENETC_RSSHASH_KEY_SIZE];
589 struct enetc_hw *hw = &pf->si->hw;
590
591 enetc_configure_port_mac(pf->si);
592
593 enetc_port_si_configure(pf->si);
594
595 /* set up hash key */
596 get_random_bytes(hash_key, ENETC_RSSHASH_KEY_SIZE);
597 enetc_set_rss_key(hw, hash_key);
598
599 /* split up RFS entries */
600 enetc_port_assign_rfs_entries(pf->si);
601
602 /* enforce VLAN promisc mode for all SIs */
603 pf->vlan_promisc_simap = ENETC_VLAN_PROMISC_MAP_ALL;
604 enetc_set_vlan_promisc(hw, pf->vlan_promisc_simap);
605
606 enetc_port_wr(hw, ENETC_PSIPMR, 0);
607
608 /* enable port */
609 enetc_port_wr(hw, ENETC_PMR, ENETC_PMR_EN);
610}
611
612/* Messaging */
613static u16 enetc_msg_pf_set_vf_primary_mac_addr(struct enetc_pf *pf,
614 int vf_id)
615{
616 struct enetc_vf_state *vf_state = &pf->vf_state[vf_id];
617 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
618 struct enetc_msg_cmd_set_primary_mac *cmd;
619 struct device *dev = &pf->si->pdev->dev;
620 u16 cmd_id;
621 char *addr;
622
623 cmd = (struct enetc_msg_cmd_set_primary_mac *)msg->vaddr;
624 cmd_id = cmd->header.id;
625 if (cmd_id != ENETC_MSG_CMD_MNG_ADD)
626 return ENETC_MSG_CMD_STATUS_FAIL;
627
628 addr = cmd->mac.sa_data;
629 if (vf_state->flags & ENETC_VF_FLAG_PF_SET_MAC)
630 dev_warn(dev, "Attempt to override PF set mac addr for VF%d\n",
631 vf_id);
632 else
633 enetc_pf_set_primary_mac_addr(&pf->si->hw, vf_id + 1, addr);
634
635 return ENETC_MSG_CMD_STATUS_OK;
636}
637
638void enetc_msg_handle_rxmsg(struct enetc_pf *pf, int vf_id, u16 *status)
639{
640 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
641 struct device *dev = &pf->si->pdev->dev;
642 struct enetc_msg_cmd_header *cmd_hdr;
643 u16 cmd_type;
644
645 *status = ENETC_MSG_CMD_STATUS_OK;
646 cmd_hdr = (struct enetc_msg_cmd_header *)msg->vaddr;
647 cmd_type = cmd_hdr->type;
648
649 switch (cmd_type) {
650 case ENETC_MSG_CMD_MNG_MAC:
651 *status = enetc_msg_pf_set_vf_primary_mac_addr(pf, vf_id);
652 break;
653 default:
654 dev_err(dev, "command not supported (cmd_type: 0x%x)\n",
655 cmd_type);
656 }
657}
658
659#ifdef CONFIG_PCI_IOV
660static int enetc_sriov_configure(struct pci_dev *pdev, int num_vfs)
661{
662 struct enetc_si *si = pci_get_drvdata(pdev);
663 struct enetc_pf *pf = enetc_si_priv(si);
664 int err;
665
666 if (!num_vfs) {
667 enetc_msg_psi_free(pf);
668 kfree(pf->vf_state);
669 pf->num_vfs = 0;
670 pci_disable_sriov(pdev);
671 } else {
672 pf->num_vfs = num_vfs;
673
674 pf->vf_state = kcalloc(num_vfs, sizeof(struct enetc_vf_state),
675 GFP_KERNEL);
676 if (!pf->vf_state) {
677 pf->num_vfs = 0;
678 return -ENOMEM;
679 }
680
681 err = enetc_msg_psi_init(pf);
682 if (err) {
683 dev_err(&pdev->dev, "enetc_msg_psi_init (%d)\n", err);
684 goto err_msg_psi;
685 }
686
687 err = pci_enable_sriov(pdev, num_vfs);
688 if (err) {
689 dev_err(&pdev->dev, "pci_enable_sriov err %d\n", err);
690 goto err_en_sriov;
691 }
692 }
693
694 return num_vfs;
695
696err_en_sriov:
697 enetc_msg_psi_free(pf);
698err_msg_psi:
699 kfree(pf->vf_state);
700 pf->num_vfs = 0;
701
702 return err;
703}
704#else
705#define enetc_sriov_configure(pdev, num_vfs) (void)0
706#endif
707
708static int enetc_pf_set_features(struct net_device *ndev,
709 netdev_features_t features)
710{
711 netdev_features_t changed = ndev->features ^ features;
712 struct enetc_ndev_priv *priv = netdev_priv(ndev);
713 int err;
714
715 if (changed & NETIF_F_HW_TC) {
716 err = enetc_set_psfp(ndev, !!(features & NETIF_F_HW_TC));
717 if (err)
718 return err;
719 }
720
721 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
722 struct enetc_pf *pf = enetc_si_priv(priv->si);
723
724 if (!!(features & NETIF_F_HW_VLAN_CTAG_FILTER))
725 enetc_disable_si_vlan_promisc(pf, 0);
726 else
727 enetc_enable_si_vlan_promisc(pf, 0);
728 }
729
730 if (changed & NETIF_F_LOOPBACK)
731 enetc_set_loopback(ndev, !!(features & NETIF_F_LOOPBACK));
732
733 enetc_set_features(ndev, features);
734
735 return 0;
736}
737
738static int enetc_pf_setup_tc(struct net_device *ndev, enum tc_setup_type type,
739 void *type_data)
740{
741 switch (type) {
742 case TC_QUERY_CAPS:
743 return enetc_qos_query_caps(ndev, type_data);
744 case TC_SETUP_QDISC_MQPRIO:
745 return enetc_setup_tc_mqprio(ndev, type_data);
746 case TC_SETUP_QDISC_TAPRIO:
747 return enetc_setup_tc_taprio(ndev, type_data);
748 case TC_SETUP_QDISC_CBS:
749 return enetc_setup_tc_cbs(ndev, type_data);
750 case TC_SETUP_QDISC_ETF:
751 return enetc_setup_tc_txtime(ndev, type_data);
752 case TC_SETUP_BLOCK:
753 return enetc_setup_tc_psfp(ndev, type_data);
754 default:
755 return -EOPNOTSUPP;
756 }
757}
758
759static const struct net_device_ops enetc_ndev_ops = {
760 .ndo_open = enetc_open,
761 .ndo_stop = enetc_close,
762 .ndo_start_xmit = enetc_xmit,
763 .ndo_get_stats = enetc_get_stats,
764 .ndo_set_mac_address = enetc_pf_set_mac_addr,
765 .ndo_set_rx_mode = enetc_pf_set_rx_mode,
766 .ndo_vlan_rx_add_vid = enetc_vlan_rx_add_vid,
767 .ndo_vlan_rx_kill_vid = enetc_vlan_rx_del_vid,
768 .ndo_set_vf_mac = enetc_pf_set_vf_mac,
769 .ndo_set_vf_vlan = enetc_pf_set_vf_vlan,
770 .ndo_set_vf_spoofchk = enetc_pf_set_vf_spoofchk,
771 .ndo_set_features = enetc_pf_set_features,
772 .ndo_eth_ioctl = enetc_ioctl,
773 .ndo_setup_tc = enetc_pf_setup_tc,
774 .ndo_bpf = enetc_setup_bpf,
775 .ndo_xdp_xmit = enetc_xdp_xmit,
776};
777
778static void enetc_pf_netdev_setup(struct enetc_si *si, struct net_device *ndev,
779 const struct net_device_ops *ndev_ops)
780{
781 struct enetc_ndev_priv *priv = netdev_priv(ndev);
782
783 SET_NETDEV_DEV(ndev, &si->pdev->dev);
784 priv->ndev = ndev;
785 priv->si = si;
786 priv->dev = &si->pdev->dev;
787 si->ndev = ndev;
788
789 priv->msg_enable = (NETIF_MSG_WOL << 1) - 1;
790 ndev->netdev_ops = ndev_ops;
791 enetc_set_ethtool_ops(ndev);
792 ndev->watchdog_timeo = 5 * HZ;
793 ndev->max_mtu = ENETC_MAX_MTU;
794
795 ndev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
796 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
797 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_LOOPBACK |
798 NETIF_F_HW_CSUM | NETIF_F_TSO | NETIF_F_TSO6;
799 ndev->features = NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_RXCSUM |
800 NETIF_F_HW_VLAN_CTAG_TX |
801 NETIF_F_HW_VLAN_CTAG_RX |
802 NETIF_F_HW_CSUM | NETIF_F_TSO | NETIF_F_TSO6;
803 ndev->vlan_features = NETIF_F_SG | NETIF_F_HW_CSUM |
804 NETIF_F_TSO | NETIF_F_TSO6;
805
806 if (si->num_rss)
807 ndev->hw_features |= NETIF_F_RXHASH;
808
809 ndev->priv_flags |= IFF_UNICAST_FLT;
810 ndev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT |
811 NETDEV_XDP_ACT_NDO_XMIT | NETDEV_XDP_ACT_RX_SG |
812 NETDEV_XDP_ACT_NDO_XMIT_SG;
813
814 if (si->hw_features & ENETC_SI_F_PSFP && !enetc_psfp_enable(priv)) {
815 priv->active_offloads |= ENETC_F_QCI;
816 ndev->features |= NETIF_F_HW_TC;
817 ndev->hw_features |= NETIF_F_HW_TC;
818 }
819
820 /* pick up primary MAC address from SI */
821 enetc_load_primary_mac_addr(&si->hw, ndev);
822}
823
824static int enetc_mdio_probe(struct enetc_pf *pf, struct device_node *np)
825{
826 struct device *dev = &pf->si->pdev->dev;
827 struct enetc_mdio_priv *mdio_priv;
828 struct mii_bus *bus;
829 int err;
830
831 bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv));
832 if (!bus)
833 return -ENOMEM;
834
835 bus->name = "Freescale ENETC MDIO Bus";
836 bus->read = enetc_mdio_read_c22;
837 bus->write = enetc_mdio_write_c22;
838 bus->read_c45 = enetc_mdio_read_c45;
839 bus->write_c45 = enetc_mdio_write_c45;
840 bus->parent = dev;
841 mdio_priv = bus->priv;
842 mdio_priv->hw = &pf->si->hw;
843 mdio_priv->mdio_base = ENETC_EMDIO_BASE;
844 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev));
845
846 err = of_mdiobus_register(bus, np);
847 if (err)
848 return dev_err_probe(dev, err, "cannot register MDIO bus\n");
849
850 pf->mdio = bus;
851
852 return 0;
853}
854
855static void enetc_mdio_remove(struct enetc_pf *pf)
856{
857 if (pf->mdio)
858 mdiobus_unregister(pf->mdio);
859}
860
861static int enetc_imdio_create(struct enetc_pf *pf)
862{
863 struct device *dev = &pf->si->pdev->dev;
864 struct enetc_mdio_priv *mdio_priv;
865 struct phylink_pcs *phylink_pcs;
866 struct mii_bus *bus;
867 int err;
868
869 bus = mdiobus_alloc_size(sizeof(*mdio_priv));
870 if (!bus)
871 return -ENOMEM;
872
873 bus->name = "Freescale ENETC internal MDIO Bus";
874 bus->read = enetc_mdio_read_c22;
875 bus->write = enetc_mdio_write_c22;
876 bus->read_c45 = enetc_mdio_read_c45;
877 bus->write_c45 = enetc_mdio_write_c45;
878 bus->parent = dev;
879 bus->phy_mask = ~0;
880 mdio_priv = bus->priv;
881 mdio_priv->hw = &pf->si->hw;
882 mdio_priv->mdio_base = ENETC_PM_IMDIO_BASE;
883 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
884
885 err = mdiobus_register(bus);
886 if (err) {
887 dev_err(dev, "cannot register internal MDIO bus (%d)\n", err);
888 goto free_mdio_bus;
889 }
890
891 phylink_pcs = lynx_pcs_create_mdiodev(bus, 0);
892 if (IS_ERR(phylink_pcs)) {
893 err = PTR_ERR(phylink_pcs);
894 dev_err(dev, "cannot create lynx pcs (%d)\n", err);
895 goto unregister_mdiobus;
896 }
897
898 pf->imdio = bus;
899 pf->pcs = phylink_pcs;
900
901 return 0;
902
903unregister_mdiobus:
904 mdiobus_unregister(bus);
905free_mdio_bus:
906 mdiobus_free(bus);
907 return err;
908}
909
910static void enetc_imdio_remove(struct enetc_pf *pf)
911{
912 if (pf->pcs)
913 lynx_pcs_destroy(pf->pcs);
914 if (pf->imdio) {
915 mdiobus_unregister(pf->imdio);
916 mdiobus_free(pf->imdio);
917 }
918}
919
920static bool enetc_port_has_pcs(struct enetc_pf *pf)
921{
922 return (pf->if_mode == PHY_INTERFACE_MODE_SGMII ||
923 pf->if_mode == PHY_INTERFACE_MODE_1000BASEX ||
924 pf->if_mode == PHY_INTERFACE_MODE_2500BASEX ||
925 pf->if_mode == PHY_INTERFACE_MODE_USXGMII);
926}
927
928static int enetc_mdiobus_create(struct enetc_pf *pf, struct device_node *node)
929{
930 struct device_node *mdio_np;
931 int err;
932
933 mdio_np = of_get_child_by_name(node, "mdio");
934 if (mdio_np) {
935 err = enetc_mdio_probe(pf, mdio_np);
936
937 of_node_put(mdio_np);
938 if (err)
939 return err;
940 }
941
942 if (enetc_port_has_pcs(pf)) {
943 err = enetc_imdio_create(pf);
944 if (err) {
945 enetc_mdio_remove(pf);
946 return err;
947 }
948 }
949
950 return 0;
951}
952
953static void enetc_mdiobus_destroy(struct enetc_pf *pf)
954{
955 enetc_mdio_remove(pf);
956 enetc_imdio_remove(pf);
957}
958
959static struct phylink_pcs *
960enetc_pl_mac_select_pcs(struct phylink_config *config, phy_interface_t iface)
961{
962 struct enetc_pf *pf = phylink_to_enetc_pf(config);
963
964 return pf->pcs;
965}
966
967static void enetc_pl_mac_config(struct phylink_config *config,
968 unsigned int mode,
969 const struct phylink_link_state *state)
970{
971 struct enetc_pf *pf = phylink_to_enetc_pf(config);
972
973 enetc_mac_config(pf->si, state->interface);
974}
975
976static void enetc_force_rgmii_mac(struct enetc_si *si, int speed, int duplex)
977{
978 u32 old_val, val;
979
980 old_val = val = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);
981
982 if (speed == SPEED_1000) {
983 val &= ~ENETC_PM0_IFM_SSP_MASK;
984 val |= ENETC_PM0_IFM_SSP_1000;
985 } else if (speed == SPEED_100) {
986 val &= ~ENETC_PM0_IFM_SSP_MASK;
987 val |= ENETC_PM0_IFM_SSP_100;
988 } else if (speed == SPEED_10) {
989 val &= ~ENETC_PM0_IFM_SSP_MASK;
990 val |= ENETC_PM0_IFM_SSP_10;
991 }
992
993 if (duplex == DUPLEX_FULL)
994 val |= ENETC_PM0_IFM_FULL_DPX;
995 else
996 val &= ~ENETC_PM0_IFM_FULL_DPX;
997
998 if (val == old_val)
999 return;
1000
1001 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);
1002}
1003
1004static void enetc_pl_mac_link_up(struct phylink_config *config,
1005 struct phy_device *phy, unsigned int mode,
1006 phy_interface_t interface, int speed,
1007 int duplex, bool tx_pause, bool rx_pause)
1008{
1009 struct enetc_pf *pf = phylink_to_enetc_pf(config);
1010 u32 pause_off_thresh = 0, pause_on_thresh = 0;
1011 u32 init_quanta = 0, refresh_quanta = 0;
1012 struct enetc_hw *hw = &pf->si->hw;
1013 struct enetc_si *si = pf->si;
1014 struct enetc_ndev_priv *priv;
1015 u32 rbmr, cmd_cfg;
1016 int idx;
1017
1018 priv = netdev_priv(pf->si->ndev);
1019
1020 if (pf->si->hw_features & ENETC_SI_F_QBV)
1021 enetc_sched_speed_set(priv, speed);
1022
1023 if (!phylink_autoneg_inband(mode) &&
1024 phy_interface_mode_is_rgmii(interface))
1025 enetc_force_rgmii_mac(si, speed, duplex);
1026
1027 /* Flow control */
1028 for (idx = 0; idx < priv->num_rx_rings; idx++) {
1029 rbmr = enetc_rxbdr_rd(hw, idx, ENETC_RBMR);
1030
1031 if (tx_pause)
1032 rbmr |= ENETC_RBMR_CM;
1033 else
1034 rbmr &= ~ENETC_RBMR_CM;
1035
1036 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr);
1037 }
1038
1039 if (tx_pause) {
1040 /* When the port first enters congestion, send a PAUSE request
1041 * with the maximum number of quanta. When the port exits
1042 * congestion, it will automatically send a PAUSE frame with
1043 * zero quanta.
1044 */
1045 init_quanta = 0xffff;
1046
1047 /* Also, set up the refresh timer to send follow-up PAUSE
1048 * frames at half the quanta value, in case the congestion
1049 * condition persists.
1050 */
1051 refresh_quanta = 0xffff / 2;
1052
1053 /* Start emitting PAUSE frames when 3 large frames (or more
1054 * smaller frames) have accumulated in the FIFO waiting to be
1055 * DMAed to the RX ring.
1056 */
1057 pause_on_thresh = 3 * ENETC_MAC_MAXFRM_SIZE;
1058 pause_off_thresh = 1 * ENETC_MAC_MAXFRM_SIZE;
1059 }
1060
1061 enetc_port_mac_wr(si, ENETC_PM0_PAUSE_QUANTA, init_quanta);
1062 enetc_port_mac_wr(si, ENETC_PM0_PAUSE_THRESH, refresh_quanta);
1063 enetc_port_wr(hw, ENETC_PPAUONTR, pause_on_thresh);
1064 enetc_port_wr(hw, ENETC_PPAUOFFTR, pause_off_thresh);
1065
1066 cmd_cfg = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);
1067
1068 if (rx_pause)
1069 cmd_cfg &= ~ENETC_PM0_PAUSE_IGN;
1070 else
1071 cmd_cfg |= ENETC_PM0_PAUSE_IGN;
1072
1073 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, cmd_cfg);
1074
1075 enetc_mac_enable(si, true);
1076
1077 if (si->hw_features & ENETC_SI_F_QBU)
1078 enetc_mm_link_state_update(priv, true);
1079}
1080
1081static void enetc_pl_mac_link_down(struct phylink_config *config,
1082 unsigned int mode,
1083 phy_interface_t interface)
1084{
1085 struct enetc_pf *pf = phylink_to_enetc_pf(config);
1086 struct enetc_si *si = pf->si;
1087 struct enetc_ndev_priv *priv;
1088
1089 priv = netdev_priv(si->ndev);
1090
1091 if (si->hw_features & ENETC_SI_F_QBU)
1092 enetc_mm_link_state_update(priv, false);
1093
1094 enetc_mac_enable(si, false);
1095}
1096
1097static const struct phylink_mac_ops enetc_mac_phylink_ops = {
1098 .mac_select_pcs = enetc_pl_mac_select_pcs,
1099 .mac_config = enetc_pl_mac_config,
1100 .mac_link_up = enetc_pl_mac_link_up,
1101 .mac_link_down = enetc_pl_mac_link_down,
1102};
1103
1104static int enetc_phylink_create(struct enetc_ndev_priv *priv,
1105 struct device_node *node)
1106{
1107 struct enetc_pf *pf = enetc_si_priv(priv->si);
1108 struct phylink *phylink;
1109 int err;
1110
1111 pf->phylink_config.dev = &priv->ndev->dev;
1112 pf->phylink_config.type = PHYLINK_NETDEV;
1113 pf->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1114 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
1115
1116 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1117 pf->phylink_config.supported_interfaces);
1118 __set_bit(PHY_INTERFACE_MODE_SGMII,
1119 pf->phylink_config.supported_interfaces);
1120 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
1121 pf->phylink_config.supported_interfaces);
1122 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
1123 pf->phylink_config.supported_interfaces);
1124 __set_bit(PHY_INTERFACE_MODE_USXGMII,
1125 pf->phylink_config.supported_interfaces);
1126 phy_interface_set_rgmii(pf->phylink_config.supported_interfaces);
1127
1128 phylink = phylink_create(&pf->phylink_config, of_fwnode_handle(node),
1129 pf->if_mode, &enetc_mac_phylink_ops);
1130 if (IS_ERR(phylink)) {
1131 err = PTR_ERR(phylink);
1132 return err;
1133 }
1134
1135 priv->phylink = phylink;
1136
1137 return 0;
1138}
1139
1140static void enetc_phylink_destroy(struct enetc_ndev_priv *priv)
1141{
1142 phylink_destroy(priv->phylink);
1143}
1144
1145/* Initialize the entire shared memory for the flow steering entries
1146 * of this port (PF + VFs)
1147 */
1148static int enetc_init_port_rfs_memory(struct enetc_si *si)
1149{
1150 struct enetc_cmd_rfse rfse = {0};
1151 struct enetc_hw *hw = &si->hw;
1152 int num_rfs, i, err = 0;
1153 u32 val;
1154
1155 val = enetc_port_rd(hw, ENETC_PRFSCAPR);
1156 num_rfs = ENETC_PRFSCAPR_GET_NUM_RFS(val);
1157
1158 for (i = 0; i < num_rfs; i++) {
1159 err = enetc_set_fs_entry(si, &rfse, i);
1160 if (err)
1161 break;
1162 }
1163
1164 return err;
1165}
1166
1167static int enetc_init_port_rss_memory(struct enetc_si *si)
1168{
1169 struct enetc_hw *hw = &si->hw;
1170 int num_rss, err;
1171 int *rss_table;
1172 u32 val;
1173
1174 val = enetc_port_rd(hw, ENETC_PRSSCAPR);
1175 num_rss = ENETC_PRSSCAPR_GET_NUM_RSS(val);
1176 if (!num_rss)
1177 return 0;
1178
1179 rss_table = kcalloc(num_rss, sizeof(*rss_table), GFP_KERNEL);
1180 if (!rss_table)
1181 return -ENOMEM;
1182
1183 err = enetc_set_rss_table(si, rss_table, num_rss);
1184
1185 kfree(rss_table);
1186
1187 return err;
1188}
1189
1190static int enetc_pf_register_with_ierb(struct pci_dev *pdev)
1191{
1192 struct platform_device *ierb_pdev;
1193 struct device_node *ierb_node;
1194
1195 ierb_node = of_find_compatible_node(NULL, NULL,
1196 "fsl,ls1028a-enetc-ierb");
1197 if (!ierb_node || !of_device_is_available(ierb_node))
1198 return -ENODEV;
1199
1200 ierb_pdev = of_find_device_by_node(ierb_node);
1201 of_node_put(ierb_node);
1202
1203 if (!ierb_pdev)
1204 return -EPROBE_DEFER;
1205
1206 return enetc_ierb_register_pf(ierb_pdev, pdev);
1207}
1208
1209static struct enetc_si *enetc_psi_create(struct pci_dev *pdev)
1210{
1211 struct enetc_si *si;
1212 int err;
1213
1214 err = enetc_pci_probe(pdev, KBUILD_MODNAME, sizeof(struct enetc_pf));
1215 if (err) {
1216 dev_err_probe(&pdev->dev, err, "PCI probing failed\n");
1217 goto out;
1218 }
1219
1220 si = pci_get_drvdata(pdev);
1221 if (!si->hw.port || !si->hw.global) {
1222 err = -ENODEV;
1223 dev_err(&pdev->dev, "could not map PF space, probing a VF?\n");
1224 goto out_pci_remove;
1225 }
1226
1227 err = enetc_setup_cbdr(&pdev->dev, &si->hw, ENETC_CBDR_DEFAULT_SIZE,
1228 &si->cbd_ring);
1229 if (err)
1230 goto out_pci_remove;
1231
1232 err = enetc_init_port_rfs_memory(si);
1233 if (err) {
1234 dev_err(&pdev->dev, "Failed to initialize RFS memory\n");
1235 goto out_teardown_cbdr;
1236 }
1237
1238 err = enetc_init_port_rss_memory(si);
1239 if (err) {
1240 dev_err(&pdev->dev, "Failed to initialize RSS memory\n");
1241 goto out_teardown_cbdr;
1242 }
1243
1244 return si;
1245
1246out_teardown_cbdr:
1247 enetc_teardown_cbdr(&si->cbd_ring);
1248out_pci_remove:
1249 enetc_pci_remove(pdev);
1250out:
1251 return ERR_PTR(err);
1252}
1253
1254static void enetc_psi_destroy(struct pci_dev *pdev)
1255{
1256 struct enetc_si *si = pci_get_drvdata(pdev);
1257
1258 enetc_teardown_cbdr(&si->cbd_ring);
1259 enetc_pci_remove(pdev);
1260}
1261
1262static int enetc_pf_probe(struct pci_dev *pdev,
1263 const struct pci_device_id *ent)
1264{
1265 struct device_node *node = pdev->dev.of_node;
1266 struct enetc_ndev_priv *priv;
1267 struct net_device *ndev;
1268 struct enetc_si *si;
1269 struct enetc_pf *pf;
1270 int err;
1271
1272 err = enetc_pf_register_with_ierb(pdev);
1273 if (err == -EPROBE_DEFER)
1274 return err;
1275 if (err)
1276 dev_warn(&pdev->dev,
1277 "Could not register with IERB driver: %pe, please update the device tree\n",
1278 ERR_PTR(err));
1279
1280 si = enetc_psi_create(pdev);
1281 if (IS_ERR(si)) {
1282 err = PTR_ERR(si);
1283 goto err_psi_create;
1284 }
1285
1286 pf = enetc_si_priv(si);
1287 pf->si = si;
1288 pf->total_vfs = pci_sriov_get_totalvfs(pdev);
1289
1290 err = enetc_setup_mac_addresses(node, pf);
1291 if (err)
1292 goto err_setup_mac_addresses;
1293
1294 enetc_configure_port(pf);
1295
1296 enetc_get_si_caps(si);
1297
1298 ndev = alloc_etherdev_mq(sizeof(*priv), ENETC_MAX_NUM_TXQS);
1299 if (!ndev) {
1300 err = -ENOMEM;
1301 dev_err(&pdev->dev, "netdev creation failed\n");
1302 goto err_alloc_netdev;
1303 }
1304
1305 enetc_pf_netdev_setup(si, ndev, &enetc_ndev_ops);
1306
1307 priv = netdev_priv(ndev);
1308
1309 mutex_init(&priv->mm_lock);
1310
1311 enetc_init_si_rings_params(priv);
1312
1313 err = enetc_alloc_si_resources(priv);
1314 if (err) {
1315 dev_err(&pdev->dev, "SI resource alloc failed\n");
1316 goto err_alloc_si_res;
1317 }
1318
1319 err = enetc_configure_si(priv);
1320 if (err) {
1321 dev_err(&pdev->dev, "Failed to configure SI\n");
1322 goto err_config_si;
1323 }
1324
1325 err = enetc_alloc_msix(priv);
1326 if (err) {
1327 dev_err(&pdev->dev, "MSIX alloc failed\n");
1328 goto err_alloc_msix;
1329 }
1330
1331 err = of_get_phy_mode(node, &pf->if_mode);
1332 if (err) {
1333 dev_err(&pdev->dev, "Failed to read PHY mode\n");
1334 goto err_phy_mode;
1335 }
1336
1337 err = enetc_mdiobus_create(pf, node);
1338 if (err)
1339 goto err_mdiobus_create;
1340
1341 err = enetc_phylink_create(priv, node);
1342 if (err)
1343 goto err_phylink_create;
1344
1345 err = register_netdev(ndev);
1346 if (err)
1347 goto err_reg_netdev;
1348
1349 return 0;
1350
1351err_reg_netdev:
1352 enetc_phylink_destroy(priv);
1353err_phylink_create:
1354 enetc_mdiobus_destroy(pf);
1355err_mdiobus_create:
1356err_phy_mode:
1357 enetc_free_msix(priv);
1358err_config_si:
1359err_alloc_msix:
1360 enetc_free_si_resources(priv);
1361err_alloc_si_res:
1362 si->ndev = NULL;
1363 free_netdev(ndev);
1364err_alloc_netdev:
1365err_setup_mac_addresses:
1366 enetc_psi_destroy(pdev);
1367err_psi_create:
1368 return err;
1369}
1370
1371static void enetc_pf_remove(struct pci_dev *pdev)
1372{
1373 struct enetc_si *si = pci_get_drvdata(pdev);
1374 struct enetc_pf *pf = enetc_si_priv(si);
1375 struct enetc_ndev_priv *priv;
1376
1377 priv = netdev_priv(si->ndev);
1378
1379 if (pf->num_vfs)
1380 enetc_sriov_configure(pdev, 0);
1381
1382 unregister_netdev(si->ndev);
1383
1384 enetc_phylink_destroy(priv);
1385 enetc_mdiobus_destroy(pf);
1386
1387 enetc_free_msix(priv);
1388
1389 enetc_free_si_resources(priv);
1390
1391 free_netdev(si->ndev);
1392
1393 enetc_psi_destroy(pdev);
1394}
1395
1396static void enetc_fixup_clear_rss_rfs(struct pci_dev *pdev)
1397{
1398 struct device_node *node = pdev->dev.of_node;
1399 struct enetc_si *si;
1400
1401 /* Only apply quirk for disabled functions. For the ones
1402 * that are enabled, enetc_pf_probe() will apply it.
1403 */
1404 if (node && of_device_is_available(node))
1405 return;
1406
1407 si = enetc_psi_create(pdev);
1408 if (!IS_ERR(si))
1409 enetc_psi_destroy(pdev);
1410}
1411DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF,
1412 enetc_fixup_clear_rss_rfs);
1413
1414static const struct pci_device_id enetc_pf_id_table[] = {
1415 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF) },
1416 { 0, } /* End of table. */
1417};
1418MODULE_DEVICE_TABLE(pci, enetc_pf_id_table);
1419
1420static struct pci_driver enetc_pf_driver = {
1421 .name = KBUILD_MODNAME,
1422 .id_table = enetc_pf_id_table,
1423 .probe = enetc_pf_probe,
1424 .remove = enetc_pf_remove,
1425#ifdef CONFIG_PCI_IOV
1426 .sriov_configure = enetc_sriov_configure,
1427#endif
1428};
1429module_pci_driver(enetc_pf_driver);
1430
1431MODULE_DESCRIPTION(ENETC_DRV_NAME_STR);
1432MODULE_LICENSE("Dual BSD/GPL");
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/* Copyright 2017-2019 NXP */
3
4#include <asm/unaligned.h>
5#include <linux/mdio.h>
6#include <linux/module.h>
7#include <linux/fsl/enetc_mdio.h>
8#include <linux/of_platform.h>
9#include <linux/of_mdio.h>
10#include <linux/of_net.h>
11#include <linux/pcs-lynx.h>
12#include "enetc_ierb.h"
13#include "enetc_pf.h"
14
15#define ENETC_DRV_NAME_STR "ENETC PF driver"
16
17static void enetc_pf_get_primary_mac_addr(struct enetc_hw *hw, int si, u8 *addr)
18{
19 u32 upper = __raw_readl(hw->port + ENETC_PSIPMAR0(si));
20 u16 lower = __raw_readw(hw->port + ENETC_PSIPMAR1(si));
21
22 put_unaligned_le32(upper, addr);
23 put_unaligned_le16(lower, addr + 4);
24}
25
26static void enetc_pf_set_primary_mac_addr(struct enetc_hw *hw, int si,
27 const u8 *addr)
28{
29 u32 upper = get_unaligned_le32(addr);
30 u16 lower = get_unaligned_le16(addr + 4);
31
32 __raw_writel(upper, hw->port + ENETC_PSIPMAR0(si));
33 __raw_writew(lower, hw->port + ENETC_PSIPMAR1(si));
34}
35
36static int enetc_pf_set_mac_addr(struct net_device *ndev, void *addr)
37{
38 struct enetc_ndev_priv *priv = netdev_priv(ndev);
39 struct sockaddr *saddr = addr;
40
41 if (!is_valid_ether_addr(saddr->sa_data))
42 return -EADDRNOTAVAIL;
43
44 eth_hw_addr_set(ndev, saddr->sa_data);
45 enetc_pf_set_primary_mac_addr(&priv->si->hw, 0, saddr->sa_data);
46
47 return 0;
48}
49
50static void enetc_set_vlan_promisc(struct enetc_hw *hw, char si_map)
51{
52 u32 val = enetc_port_rd(hw, ENETC_PSIPVMR);
53
54 val &= ~ENETC_PSIPVMR_SET_VP(ENETC_VLAN_PROMISC_MAP_ALL);
55 enetc_port_wr(hw, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VP(si_map) | val);
56}
57
58static void enetc_enable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
59{
60 pf->vlan_promisc_simap |= BIT(si_idx);
61 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
62}
63
64static void enetc_disable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
65{
66 pf->vlan_promisc_simap &= ~BIT(si_idx);
67 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
68}
69
70static void enetc_set_isol_vlan(struct enetc_hw *hw, int si, u16 vlan, u8 qos)
71{
72 u32 val = 0;
73
74 if (vlan)
75 val = ENETC_PSIVLAN_EN | ENETC_PSIVLAN_SET_QOS(qos) | vlan;
76
77 enetc_port_wr(hw, ENETC_PSIVLANR(si), val);
78}
79
80static int enetc_mac_addr_hash_idx(const u8 *addr)
81{
82 u64 fold = __swab64(ether_addr_to_u64(addr)) >> 16;
83 u64 mask = 0;
84 int res = 0;
85 int i;
86
87 for (i = 0; i < 8; i++)
88 mask |= BIT_ULL(i * 6);
89
90 for (i = 0; i < 6; i++)
91 res |= (hweight64(fold & (mask << i)) & 0x1) << i;
92
93 return res;
94}
95
96static void enetc_reset_mac_addr_filter(struct enetc_mac_filter *filter)
97{
98 filter->mac_addr_cnt = 0;
99
100 bitmap_zero(filter->mac_hash_table,
101 ENETC_MADDR_HASH_TBL_SZ);
102}
103
104static void enetc_add_mac_addr_em_filter(struct enetc_mac_filter *filter,
105 const unsigned char *addr)
106{
107 /* add exact match addr */
108 ether_addr_copy(filter->mac_addr, addr);
109 filter->mac_addr_cnt++;
110}
111
112static void enetc_add_mac_addr_ht_filter(struct enetc_mac_filter *filter,
113 const unsigned char *addr)
114{
115 int idx = enetc_mac_addr_hash_idx(addr);
116
117 /* add hash table entry */
118 __set_bit(idx, filter->mac_hash_table);
119 filter->mac_addr_cnt++;
120}
121
122static void enetc_clear_mac_ht_flt(struct enetc_si *si, int si_idx, int type)
123{
124 bool err = si->errata & ENETC_ERR_UCMCSWP;
125
126 if (type == UC) {
127 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), 0);
128 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), 0);
129 } else { /* MC */
130 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), 0);
131 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), 0);
132 }
133}
134
135static void enetc_set_mac_ht_flt(struct enetc_si *si, int si_idx, int type,
136 unsigned long hash)
137{
138 bool err = si->errata & ENETC_ERR_UCMCSWP;
139
140 if (type == UC) {
141 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err),
142 lower_32_bits(hash));
143 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx),
144 upper_32_bits(hash));
145 } else { /* MC */
146 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err),
147 lower_32_bits(hash));
148 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx),
149 upper_32_bits(hash));
150 }
151}
152
153static void enetc_sync_mac_filters(struct enetc_pf *pf)
154{
155 struct enetc_mac_filter *f = pf->mac_filter;
156 struct enetc_si *si = pf->si;
157 int i, pos;
158
159 pos = EMETC_MAC_ADDR_FILT_RES;
160
161 for (i = 0; i < MADDR_TYPE; i++, f++) {
162 bool em = (f->mac_addr_cnt == 1) && (i == UC);
163 bool clear = !f->mac_addr_cnt;
164
165 if (clear) {
166 if (i == UC)
167 enetc_clear_mac_flt_entry(si, pos);
168
169 enetc_clear_mac_ht_flt(si, 0, i);
170 continue;
171 }
172
173 /* exact match filter */
174 if (em) {
175 int err;
176
177 enetc_clear_mac_ht_flt(si, 0, UC);
178
179 err = enetc_set_mac_flt_entry(si, pos, f->mac_addr,
180 BIT(0));
181 if (!err)
182 continue;
183
184 /* fallback to HT filtering */
185 dev_warn(&si->pdev->dev, "fallback to HT filt (%d)\n",
186 err);
187 }
188
189 /* hash table filter, clear EM filter for UC entries */
190 if (i == UC)
191 enetc_clear_mac_flt_entry(si, pos);
192
193 enetc_set_mac_ht_flt(si, 0, i, *f->mac_hash_table);
194 }
195}
196
197static void enetc_pf_set_rx_mode(struct net_device *ndev)
198{
199 struct enetc_ndev_priv *priv = netdev_priv(ndev);
200 struct enetc_pf *pf = enetc_si_priv(priv->si);
201 struct enetc_hw *hw = &priv->si->hw;
202 bool uprom = false, mprom = false;
203 struct enetc_mac_filter *filter;
204 struct netdev_hw_addr *ha;
205 u32 psipmr = 0;
206 bool em;
207
208 if (ndev->flags & IFF_PROMISC) {
209 /* enable promisc mode for SI0 (PF) */
210 psipmr = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0);
211 uprom = true;
212 mprom = true;
213 } else if (ndev->flags & IFF_ALLMULTI) {
214 /* enable multi cast promisc mode for SI0 (PF) */
215 psipmr = ENETC_PSIPMR_SET_MP(0);
216 mprom = true;
217 }
218
219 /* first 2 filter entries belong to PF */
220 if (!uprom) {
221 /* Update unicast filters */
222 filter = &pf->mac_filter[UC];
223 enetc_reset_mac_addr_filter(filter);
224
225 em = (netdev_uc_count(ndev) == 1);
226 netdev_for_each_uc_addr(ha, ndev) {
227 if (em) {
228 enetc_add_mac_addr_em_filter(filter, ha->addr);
229 break;
230 }
231
232 enetc_add_mac_addr_ht_filter(filter, ha->addr);
233 }
234 }
235
236 if (!mprom) {
237 /* Update multicast filters */
238 filter = &pf->mac_filter[MC];
239 enetc_reset_mac_addr_filter(filter);
240
241 netdev_for_each_mc_addr(ha, ndev) {
242 if (!is_multicast_ether_addr(ha->addr))
243 continue;
244
245 enetc_add_mac_addr_ht_filter(filter, ha->addr);
246 }
247 }
248
249 if (!uprom || !mprom)
250 /* update PF entries */
251 enetc_sync_mac_filters(pf);
252
253 psipmr |= enetc_port_rd(hw, ENETC_PSIPMR) &
254 ~(ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0));
255 enetc_port_wr(hw, ENETC_PSIPMR, psipmr);
256}
257
258static void enetc_set_vlan_ht_filter(struct enetc_hw *hw, int si_idx,
259 unsigned long hash)
260{
261 enetc_port_wr(hw, ENETC_PSIVHFR0(si_idx), lower_32_bits(hash));
262 enetc_port_wr(hw, ENETC_PSIVHFR1(si_idx), upper_32_bits(hash));
263}
264
265static int enetc_vid_hash_idx(unsigned int vid)
266{
267 int res = 0;
268 int i;
269
270 for (i = 0; i < 6; i++)
271 res |= (hweight8(vid & (BIT(i) | BIT(i + 6))) & 0x1) << i;
272
273 return res;
274}
275
276static void enetc_sync_vlan_ht_filter(struct enetc_pf *pf, bool rehash)
277{
278 int i;
279
280 if (rehash) {
281 bitmap_zero(pf->vlan_ht_filter, ENETC_VLAN_HT_SIZE);
282
283 for_each_set_bit(i, pf->active_vlans, VLAN_N_VID) {
284 int hidx = enetc_vid_hash_idx(i);
285
286 __set_bit(hidx, pf->vlan_ht_filter);
287 }
288 }
289
290 enetc_set_vlan_ht_filter(&pf->si->hw, 0, *pf->vlan_ht_filter);
291}
292
293static int enetc_vlan_rx_add_vid(struct net_device *ndev, __be16 prot, u16 vid)
294{
295 struct enetc_ndev_priv *priv = netdev_priv(ndev);
296 struct enetc_pf *pf = enetc_si_priv(priv->si);
297 int idx;
298
299 __set_bit(vid, pf->active_vlans);
300
301 idx = enetc_vid_hash_idx(vid);
302 if (!__test_and_set_bit(idx, pf->vlan_ht_filter))
303 enetc_sync_vlan_ht_filter(pf, false);
304
305 return 0;
306}
307
308static int enetc_vlan_rx_del_vid(struct net_device *ndev, __be16 prot, u16 vid)
309{
310 struct enetc_ndev_priv *priv = netdev_priv(ndev);
311 struct enetc_pf *pf = enetc_si_priv(priv->si);
312
313 __clear_bit(vid, pf->active_vlans);
314 enetc_sync_vlan_ht_filter(pf, true);
315
316 return 0;
317}
318
319static void enetc_set_loopback(struct net_device *ndev, bool en)
320{
321 struct enetc_ndev_priv *priv = netdev_priv(ndev);
322 struct enetc_hw *hw = &priv->si->hw;
323 u32 reg;
324
325 reg = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
326 if (reg & ENETC_PM0_IFM_RG) {
327 /* RGMII mode */
328 reg = (reg & ~ENETC_PM0_IFM_RLP) |
329 (en ? ENETC_PM0_IFM_RLP : 0);
330 enetc_port_wr(hw, ENETC_PM0_IF_MODE, reg);
331 } else {
332 /* assume SGMII mode */
333 reg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
334 reg = (reg & ~ENETC_PM0_CMD_XGLP) |
335 (en ? ENETC_PM0_CMD_XGLP : 0);
336 reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) |
337 (en ? ENETC_PM0_CMD_PHY_TX_EN : 0);
338 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, reg);
339 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, reg);
340 }
341}
342
343static int enetc_pf_set_vf_mac(struct net_device *ndev, int vf, u8 *mac)
344{
345 struct enetc_ndev_priv *priv = netdev_priv(ndev);
346 struct enetc_pf *pf = enetc_si_priv(priv->si);
347 struct enetc_vf_state *vf_state;
348
349 if (vf >= pf->total_vfs)
350 return -EINVAL;
351
352 if (!is_valid_ether_addr(mac))
353 return -EADDRNOTAVAIL;
354
355 vf_state = &pf->vf_state[vf];
356 vf_state->flags |= ENETC_VF_FLAG_PF_SET_MAC;
357 enetc_pf_set_primary_mac_addr(&priv->si->hw, vf + 1, mac);
358 return 0;
359}
360
361static int enetc_pf_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan,
362 u8 qos, __be16 proto)
363{
364 struct enetc_ndev_priv *priv = netdev_priv(ndev);
365 struct enetc_pf *pf = enetc_si_priv(priv->si);
366
367 if (priv->si->errata & ENETC_ERR_VLAN_ISOL)
368 return -EOPNOTSUPP;
369
370 if (vf >= pf->total_vfs)
371 return -EINVAL;
372
373 if (proto != htons(ETH_P_8021Q))
374 /* only C-tags supported for now */
375 return -EPROTONOSUPPORT;
376
377 enetc_set_isol_vlan(&priv->si->hw, vf + 1, vlan, qos);
378 return 0;
379}
380
381static int enetc_pf_set_vf_spoofchk(struct net_device *ndev, int vf, bool en)
382{
383 struct enetc_ndev_priv *priv = netdev_priv(ndev);
384 struct enetc_pf *pf = enetc_si_priv(priv->si);
385 u32 cfgr;
386
387 if (vf >= pf->total_vfs)
388 return -EINVAL;
389
390 cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1));
391 cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0);
392 enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr);
393
394 return 0;
395}
396
397static int enetc_setup_mac_address(struct device_node *np, struct enetc_pf *pf,
398 int si)
399{
400 struct device *dev = &pf->si->pdev->dev;
401 struct enetc_hw *hw = &pf->si->hw;
402 u8 mac_addr[ETH_ALEN] = { 0 };
403 int err;
404
405 /* (1) try to get the MAC address from the device tree */
406 if (np) {
407 err = of_get_mac_address(np, mac_addr);
408 if (err == -EPROBE_DEFER)
409 return err;
410 }
411
412 /* (2) bootloader supplied MAC address */
413 if (is_zero_ether_addr(mac_addr))
414 enetc_pf_get_primary_mac_addr(hw, si, mac_addr);
415
416 /* (3) choose a random one */
417 if (is_zero_ether_addr(mac_addr)) {
418 eth_random_addr(mac_addr);
419 dev_info(dev, "no MAC address specified for SI%d, using %pM\n",
420 si, mac_addr);
421 }
422
423 enetc_pf_set_primary_mac_addr(hw, si, mac_addr);
424
425 return 0;
426}
427
428static int enetc_setup_mac_addresses(struct device_node *np,
429 struct enetc_pf *pf)
430{
431 int err, i;
432
433 /* The PF might take its MAC from the device tree */
434 err = enetc_setup_mac_address(np, pf, 0);
435 if (err)
436 return err;
437
438 for (i = 0; i < pf->total_vfs; i++) {
439 err = enetc_setup_mac_address(NULL, pf, i + 1);
440 if (err)
441 return err;
442 }
443
444 return 0;
445}
446
447static void enetc_port_assign_rfs_entries(struct enetc_si *si)
448{
449 struct enetc_pf *pf = enetc_si_priv(si);
450 struct enetc_hw *hw = &si->hw;
451 int num_entries, vf_entries, i;
452 u32 val;
453
454 /* split RFS entries between functions */
455 val = enetc_port_rd(hw, ENETC_PRFSCAPR);
456 num_entries = ENETC_PRFSCAPR_GET_NUM_RFS(val);
457 vf_entries = num_entries / (pf->total_vfs + 1);
458
459 for (i = 0; i < pf->total_vfs; i++)
460 enetc_port_wr(hw, ENETC_PSIRFSCFGR(i + 1), vf_entries);
461 enetc_port_wr(hw, ENETC_PSIRFSCFGR(0),
462 num_entries - vf_entries * pf->total_vfs);
463
464 /* enable RFS on port */
465 enetc_port_wr(hw, ENETC_PRFSMR, ENETC_PRFSMR_RFSE);
466}
467
468static void enetc_port_si_configure(struct enetc_si *si)
469{
470 struct enetc_pf *pf = enetc_si_priv(si);
471 struct enetc_hw *hw = &si->hw;
472 int num_rings, i;
473 u32 val;
474
475 val = enetc_port_rd(hw, ENETC_PCAPR0);
476 num_rings = min(ENETC_PCAPR0_RXBDR(val), ENETC_PCAPR0_TXBDR(val));
477
478 val = ENETC_PSICFGR0_SET_TXBDR(ENETC_PF_NUM_RINGS);
479 val |= ENETC_PSICFGR0_SET_RXBDR(ENETC_PF_NUM_RINGS);
480
481 if (unlikely(num_rings < ENETC_PF_NUM_RINGS)) {
482 val = ENETC_PSICFGR0_SET_TXBDR(num_rings);
483 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
484
485 dev_warn(&si->pdev->dev, "Found %d rings, expected %d!\n",
486 num_rings, ENETC_PF_NUM_RINGS);
487
488 num_rings = 0;
489 }
490
491 /* Add default one-time settings for SI0 (PF) */
492 val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
493
494 enetc_port_wr(hw, ENETC_PSICFGR0(0), val);
495
496 if (num_rings)
497 num_rings -= ENETC_PF_NUM_RINGS;
498
499 /* Configure the SIs for each available VF */
500 val = ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
501 val |= ENETC_PSICFGR0_VTE | ENETC_PSICFGR0_SIVIE;
502
503 if (num_rings) {
504 num_rings /= pf->total_vfs;
505 val |= ENETC_PSICFGR0_SET_TXBDR(num_rings);
506 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
507 }
508
509 for (i = 0; i < pf->total_vfs; i++)
510 enetc_port_wr(hw, ENETC_PSICFGR0(i + 1), val);
511
512 /* Port level VLAN settings */
513 val = ENETC_PVCLCTR_OVTPIDL(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
514 enetc_port_wr(hw, ENETC_PVCLCTR, val);
515 /* use outer tag for VLAN filtering */
516 enetc_port_wr(hw, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS);
517}
518
519void enetc_set_ptcmsdur(struct enetc_hw *hw, u32 *max_sdu)
520{
521 int tc;
522
523 for (tc = 0; tc < 8; tc++) {
524 u32 val = ENETC_MAC_MAXFRM_SIZE;
525
526 if (max_sdu[tc])
527 val = max_sdu[tc] + VLAN_ETH_HLEN;
528
529 enetc_port_wr(hw, ENETC_PTCMSDUR(tc), val);
530 }
531}
532
533void enetc_reset_ptcmsdur(struct enetc_hw *hw)
534{
535 int tc;
536
537 for (tc = 0; tc < 8; tc++)
538 enetc_port_wr(hw, ENETC_PTCMSDUR(tc), ENETC_MAC_MAXFRM_SIZE);
539}
540
541static void enetc_configure_port_mac(struct enetc_hw *hw)
542{
543 enetc_port_wr(hw, ENETC_PM0_MAXFRM,
544 ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE));
545
546 enetc_reset_ptcmsdur(hw);
547
548 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
549 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
550
551 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
552 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
553
554 /* On LS1028A, the MAC RX FIFO defaults to 2, which is too high
555 * and may lead to RX lock-up under traffic. Set it to 1 instead,
556 * as recommended by the hardware team.
557 */
558 enetc_port_wr(hw, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL);
559}
560
561static void enetc_mac_config(struct enetc_hw *hw, phy_interface_t phy_mode)
562{
563 u32 val;
564
565 if (phy_interface_mode_is_rgmii(phy_mode)) {
566 val = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
567 val &= ~(ENETC_PM0_IFM_EN_AUTO | ENETC_PM0_IFM_IFMODE_MASK);
568 val |= ENETC_PM0_IFM_IFMODE_GMII | ENETC_PM0_IFM_RG;
569 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
570 }
571
572 if (phy_mode == PHY_INTERFACE_MODE_USXGMII) {
573 val = ENETC_PM0_IFM_FULL_DPX | ENETC_PM0_IFM_IFMODE_XGMII;
574 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
575 }
576}
577
578static void enetc_mac_enable(struct enetc_hw *hw, bool en)
579{
580 u32 val = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
581
582 val &= ~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
583 val |= en ? (ENETC_PM0_TX_EN | ENETC_PM0_RX_EN) : 0;
584
585 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, val);
586 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, val);
587}
588
589static void enetc_configure_port_pmac(struct enetc_hw *hw)
590{
591 u32 temp;
592
593 /* Set pMAC step lock */
594 temp = enetc_port_rd(hw, ENETC_PFPMR);
595 enetc_port_wr(hw, ENETC_PFPMR,
596 temp | ENETC_PFPMR_PMACE | ENETC_PFPMR_MWLM);
597
598 temp = enetc_port_rd(hw, ENETC_MMCSR);
599 enetc_port_wr(hw, ENETC_MMCSR, temp | ENETC_MMCSR_ME);
600}
601
602static void enetc_configure_port(struct enetc_pf *pf)
603{
604 u8 hash_key[ENETC_RSSHASH_KEY_SIZE];
605 struct enetc_hw *hw = &pf->si->hw;
606
607 enetc_configure_port_pmac(hw);
608
609 enetc_configure_port_mac(hw);
610
611 enetc_port_si_configure(pf->si);
612
613 /* set up hash key */
614 get_random_bytes(hash_key, ENETC_RSSHASH_KEY_SIZE);
615 enetc_set_rss_key(hw, hash_key);
616
617 /* split up RFS entries */
618 enetc_port_assign_rfs_entries(pf->si);
619
620 /* enforce VLAN promisc mode for all SIs */
621 pf->vlan_promisc_simap = ENETC_VLAN_PROMISC_MAP_ALL;
622 enetc_set_vlan_promisc(hw, pf->vlan_promisc_simap);
623
624 enetc_port_wr(hw, ENETC_PSIPMR, 0);
625
626 /* enable port */
627 enetc_port_wr(hw, ENETC_PMR, ENETC_PMR_EN);
628}
629
630/* Messaging */
631static u16 enetc_msg_pf_set_vf_primary_mac_addr(struct enetc_pf *pf,
632 int vf_id)
633{
634 struct enetc_vf_state *vf_state = &pf->vf_state[vf_id];
635 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
636 struct enetc_msg_cmd_set_primary_mac *cmd;
637 struct device *dev = &pf->si->pdev->dev;
638 u16 cmd_id;
639 char *addr;
640
641 cmd = (struct enetc_msg_cmd_set_primary_mac *)msg->vaddr;
642 cmd_id = cmd->header.id;
643 if (cmd_id != ENETC_MSG_CMD_MNG_ADD)
644 return ENETC_MSG_CMD_STATUS_FAIL;
645
646 addr = cmd->mac.sa_data;
647 if (vf_state->flags & ENETC_VF_FLAG_PF_SET_MAC)
648 dev_warn(dev, "Attempt to override PF set mac addr for VF%d\n",
649 vf_id);
650 else
651 enetc_pf_set_primary_mac_addr(&pf->si->hw, vf_id + 1, addr);
652
653 return ENETC_MSG_CMD_STATUS_OK;
654}
655
656void enetc_msg_handle_rxmsg(struct enetc_pf *pf, int vf_id, u16 *status)
657{
658 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
659 struct device *dev = &pf->si->pdev->dev;
660 struct enetc_msg_cmd_header *cmd_hdr;
661 u16 cmd_type;
662
663 *status = ENETC_MSG_CMD_STATUS_OK;
664 cmd_hdr = (struct enetc_msg_cmd_header *)msg->vaddr;
665 cmd_type = cmd_hdr->type;
666
667 switch (cmd_type) {
668 case ENETC_MSG_CMD_MNG_MAC:
669 *status = enetc_msg_pf_set_vf_primary_mac_addr(pf, vf_id);
670 break;
671 default:
672 dev_err(dev, "command not supported (cmd_type: 0x%x)\n",
673 cmd_type);
674 }
675}
676
677#ifdef CONFIG_PCI_IOV
678static int enetc_sriov_configure(struct pci_dev *pdev, int num_vfs)
679{
680 struct enetc_si *si = pci_get_drvdata(pdev);
681 struct enetc_pf *pf = enetc_si_priv(si);
682 int err;
683
684 if (!num_vfs) {
685 enetc_msg_psi_free(pf);
686 kfree(pf->vf_state);
687 pf->num_vfs = 0;
688 pci_disable_sriov(pdev);
689 } else {
690 pf->num_vfs = num_vfs;
691
692 pf->vf_state = kcalloc(num_vfs, sizeof(struct enetc_vf_state),
693 GFP_KERNEL);
694 if (!pf->vf_state) {
695 pf->num_vfs = 0;
696 return -ENOMEM;
697 }
698
699 err = enetc_msg_psi_init(pf);
700 if (err) {
701 dev_err(&pdev->dev, "enetc_msg_psi_init (%d)\n", err);
702 goto err_msg_psi;
703 }
704
705 err = pci_enable_sriov(pdev, num_vfs);
706 if (err) {
707 dev_err(&pdev->dev, "pci_enable_sriov err %d\n", err);
708 goto err_en_sriov;
709 }
710 }
711
712 return num_vfs;
713
714err_en_sriov:
715 enetc_msg_psi_free(pf);
716err_msg_psi:
717 kfree(pf->vf_state);
718 pf->num_vfs = 0;
719
720 return err;
721}
722#else
723#define enetc_sriov_configure(pdev, num_vfs) (void)0
724#endif
725
726static int enetc_pf_set_features(struct net_device *ndev,
727 netdev_features_t features)
728{
729 netdev_features_t changed = ndev->features ^ features;
730 struct enetc_ndev_priv *priv = netdev_priv(ndev);
731 int err;
732
733 if (changed & NETIF_F_HW_TC) {
734 err = enetc_set_psfp(ndev, !!(features & NETIF_F_HW_TC));
735 if (err)
736 return err;
737 }
738
739 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
740 struct enetc_pf *pf = enetc_si_priv(priv->si);
741
742 if (!!(features & NETIF_F_HW_VLAN_CTAG_FILTER))
743 enetc_disable_si_vlan_promisc(pf, 0);
744 else
745 enetc_enable_si_vlan_promisc(pf, 0);
746 }
747
748 if (changed & NETIF_F_LOOPBACK)
749 enetc_set_loopback(ndev, !!(features & NETIF_F_LOOPBACK));
750
751 enetc_set_features(ndev, features);
752
753 return 0;
754}
755
756static int enetc_pf_setup_tc(struct net_device *ndev, enum tc_setup_type type,
757 void *type_data)
758{
759 switch (type) {
760 case TC_QUERY_CAPS:
761 return enetc_qos_query_caps(ndev, type_data);
762 case TC_SETUP_QDISC_MQPRIO:
763 return enetc_setup_tc_mqprio(ndev, type_data);
764 case TC_SETUP_QDISC_TAPRIO:
765 return enetc_setup_tc_taprio(ndev, type_data);
766 case TC_SETUP_QDISC_CBS:
767 return enetc_setup_tc_cbs(ndev, type_data);
768 case TC_SETUP_QDISC_ETF:
769 return enetc_setup_tc_txtime(ndev, type_data);
770 case TC_SETUP_BLOCK:
771 return enetc_setup_tc_psfp(ndev, type_data);
772 default:
773 return -EOPNOTSUPP;
774 }
775}
776
777static const struct net_device_ops enetc_ndev_ops = {
778 .ndo_open = enetc_open,
779 .ndo_stop = enetc_close,
780 .ndo_start_xmit = enetc_xmit,
781 .ndo_get_stats = enetc_get_stats,
782 .ndo_set_mac_address = enetc_pf_set_mac_addr,
783 .ndo_set_rx_mode = enetc_pf_set_rx_mode,
784 .ndo_vlan_rx_add_vid = enetc_vlan_rx_add_vid,
785 .ndo_vlan_rx_kill_vid = enetc_vlan_rx_del_vid,
786 .ndo_set_vf_mac = enetc_pf_set_vf_mac,
787 .ndo_set_vf_vlan = enetc_pf_set_vf_vlan,
788 .ndo_set_vf_spoofchk = enetc_pf_set_vf_spoofchk,
789 .ndo_set_features = enetc_pf_set_features,
790 .ndo_eth_ioctl = enetc_ioctl,
791 .ndo_setup_tc = enetc_pf_setup_tc,
792 .ndo_bpf = enetc_setup_bpf,
793 .ndo_xdp_xmit = enetc_xdp_xmit,
794};
795
796static void enetc_pf_netdev_setup(struct enetc_si *si, struct net_device *ndev,
797 const struct net_device_ops *ndev_ops)
798{
799 struct enetc_ndev_priv *priv = netdev_priv(ndev);
800
801 SET_NETDEV_DEV(ndev, &si->pdev->dev);
802 priv->ndev = ndev;
803 priv->si = si;
804 priv->dev = &si->pdev->dev;
805 si->ndev = ndev;
806
807 priv->msg_enable = (NETIF_MSG_WOL << 1) - 1;
808 ndev->netdev_ops = ndev_ops;
809 enetc_set_ethtool_ops(ndev);
810 ndev->watchdog_timeo = 5 * HZ;
811 ndev->max_mtu = ENETC_MAX_MTU;
812
813 ndev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
814 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
815 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_LOOPBACK |
816 NETIF_F_HW_CSUM | NETIF_F_TSO | NETIF_F_TSO6;
817 ndev->features = NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_RXCSUM |
818 NETIF_F_HW_VLAN_CTAG_TX |
819 NETIF_F_HW_VLAN_CTAG_RX |
820 NETIF_F_HW_CSUM | NETIF_F_TSO | NETIF_F_TSO6;
821 ndev->vlan_features = NETIF_F_SG | NETIF_F_HW_CSUM |
822 NETIF_F_TSO | NETIF_F_TSO6;
823
824 if (si->num_rss)
825 ndev->hw_features |= NETIF_F_RXHASH;
826
827 ndev->priv_flags |= IFF_UNICAST_FLT;
828
829 if (si->hw_features & ENETC_SI_F_PSFP && !enetc_psfp_enable(priv)) {
830 priv->active_offloads |= ENETC_F_QCI;
831 ndev->features |= NETIF_F_HW_TC;
832 ndev->hw_features |= NETIF_F_HW_TC;
833 }
834
835 /* pick up primary MAC address from SI */
836 enetc_load_primary_mac_addr(&si->hw, ndev);
837}
838
839static int enetc_mdio_probe(struct enetc_pf *pf, struct device_node *np)
840{
841 struct device *dev = &pf->si->pdev->dev;
842 struct enetc_mdio_priv *mdio_priv;
843 struct mii_bus *bus;
844 int err;
845
846 bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv));
847 if (!bus)
848 return -ENOMEM;
849
850 bus->name = "Freescale ENETC MDIO Bus";
851 bus->read = enetc_mdio_read;
852 bus->write = enetc_mdio_write;
853 bus->parent = dev;
854 mdio_priv = bus->priv;
855 mdio_priv->hw = &pf->si->hw;
856 mdio_priv->mdio_base = ENETC_EMDIO_BASE;
857 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev));
858
859 err = of_mdiobus_register(bus, np);
860 if (err)
861 return dev_err_probe(dev, err, "cannot register MDIO bus\n");
862
863 pf->mdio = bus;
864
865 return 0;
866}
867
868static void enetc_mdio_remove(struct enetc_pf *pf)
869{
870 if (pf->mdio)
871 mdiobus_unregister(pf->mdio);
872}
873
874static int enetc_imdio_create(struct enetc_pf *pf)
875{
876 struct device *dev = &pf->si->pdev->dev;
877 struct enetc_mdio_priv *mdio_priv;
878 struct phylink_pcs *phylink_pcs;
879 struct mdio_device *mdio_device;
880 struct mii_bus *bus;
881 int err;
882
883 bus = mdiobus_alloc_size(sizeof(*mdio_priv));
884 if (!bus)
885 return -ENOMEM;
886
887 bus->name = "Freescale ENETC internal MDIO Bus";
888 bus->read = enetc_mdio_read;
889 bus->write = enetc_mdio_write;
890 bus->parent = dev;
891 bus->phy_mask = ~0;
892 mdio_priv = bus->priv;
893 mdio_priv->hw = &pf->si->hw;
894 mdio_priv->mdio_base = ENETC_PM_IMDIO_BASE;
895 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
896
897 err = mdiobus_register(bus);
898 if (err) {
899 dev_err(dev, "cannot register internal MDIO bus (%d)\n", err);
900 goto free_mdio_bus;
901 }
902
903 mdio_device = mdio_device_create(bus, 0);
904 if (IS_ERR(mdio_device)) {
905 err = PTR_ERR(mdio_device);
906 dev_err(dev, "cannot create mdio device (%d)\n", err);
907 goto unregister_mdiobus;
908 }
909
910 phylink_pcs = lynx_pcs_create(mdio_device);
911 if (!phylink_pcs) {
912 mdio_device_free(mdio_device);
913 err = -ENOMEM;
914 dev_err(dev, "cannot create lynx pcs (%d)\n", err);
915 goto unregister_mdiobus;
916 }
917
918 pf->imdio = bus;
919 pf->pcs = phylink_pcs;
920
921 return 0;
922
923unregister_mdiobus:
924 mdiobus_unregister(bus);
925free_mdio_bus:
926 mdiobus_free(bus);
927 return err;
928}
929
930static void enetc_imdio_remove(struct enetc_pf *pf)
931{
932 struct mdio_device *mdio_device;
933
934 if (pf->pcs) {
935 mdio_device = lynx_get_mdio_device(pf->pcs);
936 mdio_device_free(mdio_device);
937 lynx_pcs_destroy(pf->pcs);
938 }
939 if (pf->imdio) {
940 mdiobus_unregister(pf->imdio);
941 mdiobus_free(pf->imdio);
942 }
943}
944
945static bool enetc_port_has_pcs(struct enetc_pf *pf)
946{
947 return (pf->if_mode == PHY_INTERFACE_MODE_SGMII ||
948 pf->if_mode == PHY_INTERFACE_MODE_2500BASEX ||
949 pf->if_mode == PHY_INTERFACE_MODE_USXGMII);
950}
951
952static int enetc_mdiobus_create(struct enetc_pf *pf, struct device_node *node)
953{
954 struct device_node *mdio_np;
955 int err;
956
957 mdio_np = of_get_child_by_name(node, "mdio");
958 if (mdio_np) {
959 err = enetc_mdio_probe(pf, mdio_np);
960
961 of_node_put(mdio_np);
962 if (err)
963 return err;
964 }
965
966 if (enetc_port_has_pcs(pf)) {
967 err = enetc_imdio_create(pf);
968 if (err) {
969 enetc_mdio_remove(pf);
970 return err;
971 }
972 }
973
974 return 0;
975}
976
977static void enetc_mdiobus_destroy(struct enetc_pf *pf)
978{
979 enetc_mdio_remove(pf);
980 enetc_imdio_remove(pf);
981}
982
983static struct phylink_pcs *
984enetc_pl_mac_select_pcs(struct phylink_config *config, phy_interface_t iface)
985{
986 struct enetc_pf *pf = phylink_to_enetc_pf(config);
987
988 return pf->pcs;
989}
990
991static void enetc_pl_mac_config(struct phylink_config *config,
992 unsigned int mode,
993 const struct phylink_link_state *state)
994{
995 struct enetc_pf *pf = phylink_to_enetc_pf(config);
996
997 enetc_mac_config(&pf->si->hw, state->interface);
998}
999
1000static void enetc_force_rgmii_mac(struct enetc_hw *hw, int speed, int duplex)
1001{
1002 u32 old_val, val;
1003
1004 old_val = val = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
1005
1006 if (speed == SPEED_1000) {
1007 val &= ~ENETC_PM0_IFM_SSP_MASK;
1008 val |= ENETC_PM0_IFM_SSP_1000;
1009 } else if (speed == SPEED_100) {
1010 val &= ~ENETC_PM0_IFM_SSP_MASK;
1011 val |= ENETC_PM0_IFM_SSP_100;
1012 } else if (speed == SPEED_10) {
1013 val &= ~ENETC_PM0_IFM_SSP_MASK;
1014 val |= ENETC_PM0_IFM_SSP_10;
1015 }
1016
1017 if (duplex == DUPLEX_FULL)
1018 val |= ENETC_PM0_IFM_FULL_DPX;
1019 else
1020 val &= ~ENETC_PM0_IFM_FULL_DPX;
1021
1022 if (val == old_val)
1023 return;
1024
1025 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
1026}
1027
1028static void enetc_pl_mac_link_up(struct phylink_config *config,
1029 struct phy_device *phy, unsigned int mode,
1030 phy_interface_t interface, int speed,
1031 int duplex, bool tx_pause, bool rx_pause)
1032{
1033 struct enetc_pf *pf = phylink_to_enetc_pf(config);
1034 u32 pause_off_thresh = 0, pause_on_thresh = 0;
1035 u32 init_quanta = 0, refresh_quanta = 0;
1036 struct enetc_hw *hw = &pf->si->hw;
1037 struct enetc_ndev_priv *priv;
1038 u32 rbmr, cmd_cfg;
1039 int idx;
1040
1041 priv = netdev_priv(pf->si->ndev);
1042
1043 if (pf->si->hw_features & ENETC_SI_F_QBV)
1044 enetc_sched_speed_set(priv, speed);
1045
1046 if (!phylink_autoneg_inband(mode) &&
1047 phy_interface_mode_is_rgmii(interface))
1048 enetc_force_rgmii_mac(hw, speed, duplex);
1049
1050 /* Flow control */
1051 for (idx = 0; idx < priv->num_rx_rings; idx++) {
1052 rbmr = enetc_rxbdr_rd(hw, idx, ENETC_RBMR);
1053
1054 if (tx_pause)
1055 rbmr |= ENETC_RBMR_CM;
1056 else
1057 rbmr &= ~ENETC_RBMR_CM;
1058
1059 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr);
1060 }
1061
1062 if (tx_pause) {
1063 /* When the port first enters congestion, send a PAUSE request
1064 * with the maximum number of quanta. When the port exits
1065 * congestion, it will automatically send a PAUSE frame with
1066 * zero quanta.
1067 */
1068 init_quanta = 0xffff;
1069
1070 /* Also, set up the refresh timer to send follow-up PAUSE
1071 * frames at half the quanta value, in case the congestion
1072 * condition persists.
1073 */
1074 refresh_quanta = 0xffff / 2;
1075
1076 /* Start emitting PAUSE frames when 3 large frames (or more
1077 * smaller frames) have accumulated in the FIFO waiting to be
1078 * DMAed to the RX ring.
1079 */
1080 pause_on_thresh = 3 * ENETC_MAC_MAXFRM_SIZE;
1081 pause_off_thresh = 1 * ENETC_MAC_MAXFRM_SIZE;
1082 }
1083
1084 enetc_port_wr(hw, ENETC_PM0_PAUSE_QUANTA, init_quanta);
1085 enetc_port_wr(hw, ENETC_PM1_PAUSE_QUANTA, init_quanta);
1086 enetc_port_wr(hw, ENETC_PM0_PAUSE_THRESH, refresh_quanta);
1087 enetc_port_wr(hw, ENETC_PM1_PAUSE_THRESH, refresh_quanta);
1088 enetc_port_wr(hw, ENETC_PPAUONTR, pause_on_thresh);
1089 enetc_port_wr(hw, ENETC_PPAUOFFTR, pause_off_thresh);
1090
1091 cmd_cfg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
1092
1093 if (rx_pause)
1094 cmd_cfg &= ~ENETC_PM0_PAUSE_IGN;
1095 else
1096 cmd_cfg |= ENETC_PM0_PAUSE_IGN;
1097
1098 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, cmd_cfg);
1099 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, cmd_cfg);
1100
1101 enetc_mac_enable(hw, true);
1102}
1103
1104static void enetc_pl_mac_link_down(struct phylink_config *config,
1105 unsigned int mode,
1106 phy_interface_t interface)
1107{
1108 struct enetc_pf *pf = phylink_to_enetc_pf(config);
1109
1110 enetc_mac_enable(&pf->si->hw, false);
1111}
1112
1113static const struct phylink_mac_ops enetc_mac_phylink_ops = {
1114 .mac_select_pcs = enetc_pl_mac_select_pcs,
1115 .mac_config = enetc_pl_mac_config,
1116 .mac_link_up = enetc_pl_mac_link_up,
1117 .mac_link_down = enetc_pl_mac_link_down,
1118};
1119
1120static int enetc_phylink_create(struct enetc_ndev_priv *priv,
1121 struct device_node *node)
1122{
1123 struct enetc_pf *pf = enetc_si_priv(priv->si);
1124 struct phylink *phylink;
1125 int err;
1126
1127 pf->phylink_config.dev = &priv->ndev->dev;
1128 pf->phylink_config.type = PHYLINK_NETDEV;
1129 pf->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1130 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
1131
1132 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1133 pf->phylink_config.supported_interfaces);
1134 __set_bit(PHY_INTERFACE_MODE_SGMII,
1135 pf->phylink_config.supported_interfaces);
1136 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
1137 pf->phylink_config.supported_interfaces);
1138 __set_bit(PHY_INTERFACE_MODE_USXGMII,
1139 pf->phylink_config.supported_interfaces);
1140 phy_interface_set_rgmii(pf->phylink_config.supported_interfaces);
1141
1142 phylink = phylink_create(&pf->phylink_config, of_fwnode_handle(node),
1143 pf->if_mode, &enetc_mac_phylink_ops);
1144 if (IS_ERR(phylink)) {
1145 err = PTR_ERR(phylink);
1146 return err;
1147 }
1148
1149 priv->phylink = phylink;
1150
1151 return 0;
1152}
1153
1154static void enetc_phylink_destroy(struct enetc_ndev_priv *priv)
1155{
1156 phylink_destroy(priv->phylink);
1157}
1158
1159/* Initialize the entire shared memory for the flow steering entries
1160 * of this port (PF + VFs)
1161 */
1162static int enetc_init_port_rfs_memory(struct enetc_si *si)
1163{
1164 struct enetc_cmd_rfse rfse = {0};
1165 struct enetc_hw *hw = &si->hw;
1166 int num_rfs, i, err = 0;
1167 u32 val;
1168
1169 val = enetc_port_rd(hw, ENETC_PRFSCAPR);
1170 num_rfs = ENETC_PRFSCAPR_GET_NUM_RFS(val);
1171
1172 for (i = 0; i < num_rfs; i++) {
1173 err = enetc_set_fs_entry(si, &rfse, i);
1174 if (err)
1175 break;
1176 }
1177
1178 return err;
1179}
1180
1181static int enetc_init_port_rss_memory(struct enetc_si *si)
1182{
1183 struct enetc_hw *hw = &si->hw;
1184 int num_rss, err;
1185 int *rss_table;
1186 u32 val;
1187
1188 val = enetc_port_rd(hw, ENETC_PRSSCAPR);
1189 num_rss = ENETC_PRSSCAPR_GET_NUM_RSS(val);
1190 if (!num_rss)
1191 return 0;
1192
1193 rss_table = kcalloc(num_rss, sizeof(*rss_table), GFP_KERNEL);
1194 if (!rss_table)
1195 return -ENOMEM;
1196
1197 err = enetc_set_rss_table(si, rss_table, num_rss);
1198
1199 kfree(rss_table);
1200
1201 return err;
1202}
1203
1204static int enetc_pf_register_with_ierb(struct pci_dev *pdev)
1205{
1206 struct device_node *node = pdev->dev.of_node;
1207 struct platform_device *ierb_pdev;
1208 struct device_node *ierb_node;
1209
1210 /* Don't register with the IERB if the PF itself is disabled */
1211 if (!node || !of_device_is_available(node))
1212 return 0;
1213
1214 ierb_node = of_find_compatible_node(NULL, NULL,
1215 "fsl,ls1028a-enetc-ierb");
1216 if (!ierb_node || !of_device_is_available(ierb_node))
1217 return -ENODEV;
1218
1219 ierb_pdev = of_find_device_by_node(ierb_node);
1220 of_node_put(ierb_node);
1221
1222 if (!ierb_pdev)
1223 return -EPROBE_DEFER;
1224
1225 return enetc_ierb_register_pf(ierb_pdev, pdev);
1226}
1227
1228static int enetc_pf_probe(struct pci_dev *pdev,
1229 const struct pci_device_id *ent)
1230{
1231 struct device_node *node = pdev->dev.of_node;
1232 struct enetc_ndev_priv *priv;
1233 struct net_device *ndev;
1234 struct enetc_si *si;
1235 struct enetc_pf *pf;
1236 int err;
1237
1238 err = enetc_pf_register_with_ierb(pdev);
1239 if (err == -EPROBE_DEFER)
1240 return err;
1241 if (err)
1242 dev_warn(&pdev->dev,
1243 "Could not register with IERB driver: %pe, please update the device tree\n",
1244 ERR_PTR(err));
1245
1246 err = enetc_pci_probe(pdev, KBUILD_MODNAME, sizeof(*pf));
1247 if (err)
1248 return dev_err_probe(&pdev->dev, err, "PCI probing failed\n");
1249
1250 si = pci_get_drvdata(pdev);
1251 if (!si->hw.port || !si->hw.global) {
1252 err = -ENODEV;
1253 dev_err(&pdev->dev, "could not map PF space, probing a VF?\n");
1254 goto err_map_pf_space;
1255 }
1256
1257 err = enetc_setup_cbdr(&pdev->dev, &si->hw, ENETC_CBDR_DEFAULT_SIZE,
1258 &si->cbd_ring);
1259 if (err)
1260 goto err_setup_cbdr;
1261
1262 err = enetc_init_port_rfs_memory(si);
1263 if (err) {
1264 dev_err(&pdev->dev, "Failed to initialize RFS memory\n");
1265 goto err_init_port_rfs;
1266 }
1267
1268 err = enetc_init_port_rss_memory(si);
1269 if (err) {
1270 dev_err(&pdev->dev, "Failed to initialize RSS memory\n");
1271 goto err_init_port_rss;
1272 }
1273
1274 if (node && !of_device_is_available(node)) {
1275 dev_info(&pdev->dev, "device is disabled, skipping\n");
1276 err = -ENODEV;
1277 goto err_device_disabled;
1278 }
1279
1280 pf = enetc_si_priv(si);
1281 pf->si = si;
1282 pf->total_vfs = pci_sriov_get_totalvfs(pdev);
1283
1284 err = enetc_setup_mac_addresses(node, pf);
1285 if (err)
1286 goto err_setup_mac_addresses;
1287
1288 enetc_configure_port(pf);
1289
1290 enetc_get_si_caps(si);
1291
1292 ndev = alloc_etherdev_mq(sizeof(*priv), ENETC_MAX_NUM_TXQS);
1293 if (!ndev) {
1294 err = -ENOMEM;
1295 dev_err(&pdev->dev, "netdev creation failed\n");
1296 goto err_alloc_netdev;
1297 }
1298
1299 enetc_pf_netdev_setup(si, ndev, &enetc_ndev_ops);
1300
1301 priv = netdev_priv(ndev);
1302
1303 enetc_init_si_rings_params(priv);
1304
1305 err = enetc_alloc_si_resources(priv);
1306 if (err) {
1307 dev_err(&pdev->dev, "SI resource alloc failed\n");
1308 goto err_alloc_si_res;
1309 }
1310
1311 err = enetc_configure_si(priv);
1312 if (err) {
1313 dev_err(&pdev->dev, "Failed to configure SI\n");
1314 goto err_config_si;
1315 }
1316
1317 err = enetc_alloc_msix(priv);
1318 if (err) {
1319 dev_err(&pdev->dev, "MSIX alloc failed\n");
1320 goto err_alloc_msix;
1321 }
1322
1323 err = of_get_phy_mode(node, &pf->if_mode);
1324 if (err) {
1325 dev_err(&pdev->dev, "Failed to read PHY mode\n");
1326 goto err_phy_mode;
1327 }
1328
1329 err = enetc_mdiobus_create(pf, node);
1330 if (err)
1331 goto err_mdiobus_create;
1332
1333 err = enetc_phylink_create(priv, node);
1334 if (err)
1335 goto err_phylink_create;
1336
1337 err = register_netdev(ndev);
1338 if (err)
1339 goto err_reg_netdev;
1340
1341 return 0;
1342
1343err_reg_netdev:
1344 enetc_phylink_destroy(priv);
1345err_phylink_create:
1346 enetc_mdiobus_destroy(pf);
1347err_mdiobus_create:
1348err_phy_mode:
1349 enetc_free_msix(priv);
1350err_config_si:
1351err_alloc_msix:
1352 enetc_free_si_resources(priv);
1353err_alloc_si_res:
1354 si->ndev = NULL;
1355 free_netdev(ndev);
1356err_alloc_netdev:
1357err_init_port_rss:
1358err_init_port_rfs:
1359err_device_disabled:
1360err_setup_mac_addresses:
1361 enetc_teardown_cbdr(&si->cbd_ring);
1362err_setup_cbdr:
1363err_map_pf_space:
1364 enetc_pci_remove(pdev);
1365
1366 return err;
1367}
1368
1369static void enetc_pf_remove(struct pci_dev *pdev)
1370{
1371 struct enetc_si *si = pci_get_drvdata(pdev);
1372 struct enetc_pf *pf = enetc_si_priv(si);
1373 struct enetc_ndev_priv *priv;
1374
1375 priv = netdev_priv(si->ndev);
1376
1377 if (pf->num_vfs)
1378 enetc_sriov_configure(pdev, 0);
1379
1380 unregister_netdev(si->ndev);
1381
1382 enetc_phylink_destroy(priv);
1383 enetc_mdiobus_destroy(pf);
1384
1385 enetc_free_msix(priv);
1386
1387 enetc_free_si_resources(priv);
1388 enetc_teardown_cbdr(&si->cbd_ring);
1389
1390 free_netdev(si->ndev);
1391
1392 enetc_pci_remove(pdev);
1393}
1394
1395static const struct pci_device_id enetc_pf_id_table[] = {
1396 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF) },
1397 { 0, } /* End of table. */
1398};
1399MODULE_DEVICE_TABLE(pci, enetc_pf_id_table);
1400
1401static struct pci_driver enetc_pf_driver = {
1402 .name = KBUILD_MODNAME,
1403 .id_table = enetc_pf_id_table,
1404 .probe = enetc_pf_probe,
1405 .remove = enetc_pf_remove,
1406#ifdef CONFIG_PCI_IOV
1407 .sriov_configure = enetc_sriov_configure,
1408#endif
1409};
1410module_pci_driver(enetc_pf_driver);
1411
1412MODULE_DESCRIPTION(ENETC_DRV_NAME_STR);
1413MODULE_LICENSE("Dual BSD/GPL");