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1/* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2018 Broadcom Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
11#ifndef BNXT_H
12#define BNXT_H
13
14#define DRV_MODULE_NAME "bnxt_en"
15
16/* DO NOT CHANGE DRV_VER_* defines
17 * FIXME: Delete them
18 */
19#define DRV_VER_MAJ 1
20#define DRV_VER_MIN 10
21#define DRV_VER_UPD 3
22
23#include <linux/ethtool.h>
24#include <linux/interrupt.h>
25#include <linux/rhashtable.h>
26#include <linux/crash_dump.h>
27#include <linux/auxiliary_bus.h>
28#include <net/devlink.h>
29#include <net/dst_metadata.h>
30#include <net/xdp.h>
31#include <linux/dim.h>
32#include <linux/io-64-nonatomic-lo-hi.h>
33#ifdef CONFIG_TEE_BNXT_FW
34#include <linux/firmware/broadcom/tee_bnxt_fw.h>
35#endif
36
37extern struct list_head bnxt_block_cb_list;
38
39struct page_pool;
40
41struct tx_bd {
42 __le32 tx_bd_len_flags_type;
43 #define TX_BD_TYPE (0x3f << 0)
44 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)
45 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)
46 #define TX_BD_FLAGS_PACKET_END (1 << 6)
47 #define TX_BD_FLAGS_NO_CMPL (1 << 7)
48 #define TX_BD_FLAGS_BD_CNT (0x1f << 8)
49 #define TX_BD_FLAGS_BD_CNT_SHIFT 8
50 #define TX_BD_FLAGS_LHINT (3 << 13)
51 #define TX_BD_FLAGS_LHINT_SHIFT 13
52 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)
53 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13)
54 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13)
55 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13)
56 #define TX_BD_FLAGS_COAL_NOW (1 << 15)
57 #define TX_BD_LEN (0xffff << 16)
58 #define TX_BD_LEN_SHIFT 16
59
60 u32 tx_bd_opaque;
61 __le64 tx_bd_haddr;
62} __packed;
63
64#define TX_OPAQUE_IDX_MASK 0x0000ffff
65#define TX_OPAQUE_BDS_MASK 0x00ff0000
66#define TX_OPAQUE_BDS_SHIFT 16
67#define TX_OPAQUE_RING_MASK 0xff000000
68#define TX_OPAQUE_RING_SHIFT 24
69
70#define SET_TX_OPAQUE(bp, txr, idx, bds) \
71 (((txr)->tx_napi_idx << TX_OPAQUE_RING_SHIFT) | \
72 ((bds) << TX_OPAQUE_BDS_SHIFT) | ((idx) & (bp)->tx_ring_mask))
73
74#define TX_OPAQUE_IDX(opq) ((opq) & TX_OPAQUE_IDX_MASK)
75#define TX_OPAQUE_RING(opq) (((opq) & TX_OPAQUE_RING_MASK) >> \
76 TX_OPAQUE_RING_SHIFT)
77#define TX_OPAQUE_BDS(opq) (((opq) & TX_OPAQUE_BDS_MASK) >> \
78 TX_OPAQUE_BDS_SHIFT)
79#define TX_OPAQUE_PROD(bp, opq) ((TX_OPAQUE_IDX(opq) + TX_OPAQUE_BDS(opq)) &\
80 (bp)->tx_ring_mask)
81
82struct tx_bd_ext {
83 __le32 tx_bd_hsize_lflags;
84 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)
85 #define TX_BD_FLAGS_IP_CKSUM (1 << 1)
86 #define TX_BD_FLAGS_NO_CRC (1 << 2)
87 #define TX_BD_FLAGS_STAMP (1 << 3)
88 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4)
89 #define TX_BD_FLAGS_LSO (1 << 5)
90 #define TX_BD_FLAGS_IPID_FMT (1 << 6)
91 #define TX_BD_FLAGS_T_IPID (1 << 7)
92 #define TX_BD_HSIZE (0xff << 16)
93 #define TX_BD_HSIZE_SHIFT 16
94
95 __le32 tx_bd_mss;
96 __le32 tx_bd_cfa_action;
97 #define TX_BD_CFA_ACTION (0xffff << 16)
98 #define TX_BD_CFA_ACTION_SHIFT 16
99
100 __le32 tx_bd_cfa_meta;
101 #define TX_BD_CFA_META_MASK 0xfffffff
102 #define TX_BD_CFA_META_VID_MASK 0xfff
103 #define TX_BD_CFA_META_PRI_MASK (0xf << 12)
104 #define TX_BD_CFA_META_PRI_SHIFT 12
105 #define TX_BD_CFA_META_TPID_MASK (3 << 16)
106 #define TX_BD_CFA_META_TPID_SHIFT 16
107 #define TX_BD_CFA_META_KEY (0xf << 28)
108 #define TX_BD_CFA_META_KEY_SHIFT 28
109 #define TX_BD_CFA_META_KEY_VLAN (1 << 28)
110};
111
112#define BNXT_TX_PTP_IS_SET(lflags) ((lflags) & cpu_to_le32(TX_BD_FLAGS_STAMP))
113
114struct rx_bd {
115 __le32 rx_bd_len_flags_type;
116 #define RX_BD_TYPE (0x3f << 0)
117 #define RX_BD_TYPE_RX_PACKET_BD 0x4
118 #define RX_BD_TYPE_RX_BUFFER_BD 0x5
119 #define RX_BD_TYPE_RX_AGG_BD 0x6
120 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4)
121 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4)
122 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4)
123 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4)
124 #define RX_BD_FLAGS_SOP (1 << 6)
125 #define RX_BD_FLAGS_EOP (1 << 7)
126 #define RX_BD_FLAGS_BUFFERS (3 << 8)
127 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)
128 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8)
129 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8)
130 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8)
131 #define RX_BD_LEN (0xffff << 16)
132 #define RX_BD_LEN_SHIFT 16
133
134 u32 rx_bd_opaque;
135 __le64 rx_bd_haddr;
136};
137
138struct tx_cmp {
139 __le32 tx_cmp_flags_type;
140 #define CMP_TYPE (0x3f << 0)
141 #define CMP_TYPE_TX_L2_CMP 0
142 #define CMP_TYPE_TX_L2_COAL_CMP 2
143 #define CMP_TYPE_TX_L2_PKT_TS_CMP 4
144 #define CMP_TYPE_RX_L2_CMP 17
145 #define CMP_TYPE_RX_AGG_CMP 18
146 #define CMP_TYPE_RX_L2_TPA_START_CMP 19
147 #define CMP_TYPE_RX_L2_TPA_END_CMP 21
148 #define CMP_TYPE_RX_TPA_AGG_CMP 22
149 #define CMP_TYPE_RX_L2_V3_CMP 23
150 #define CMP_TYPE_RX_L2_TPA_START_V3_CMP 25
151 #define CMP_TYPE_STATUS_CMP 32
152 #define CMP_TYPE_REMOTE_DRIVER_REQ 34
153 #define CMP_TYPE_REMOTE_DRIVER_RESP 36
154 #define CMP_TYPE_ERROR_STATUS 48
155 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
156 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL
157 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL
158 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL
159 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
160
161 #define TX_CMP_FLAGS_ERROR (1 << 6)
162 #define TX_CMP_FLAGS_PUSH (1 << 7)
163
164 u32 tx_cmp_opaque;
165 __le32 tx_cmp_errors_v;
166 #define TX_CMP_V (1 << 0)
167 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1)
168 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0
169 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2
170 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4
171 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5
172 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4)
173 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5)
174 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6)
175 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7)
176
177 __le32 sq_cons_idx;
178 #define TX_CMP_SQ_CONS_IDX_MASK 0x00ffffff
179};
180
181#define TX_CMP_SQ_CONS_IDX(txcmp) \
182 (le32_to_cpu((txcmp)->sq_cons_idx) & TX_CMP_SQ_CONS_IDX_MASK)
183
184struct rx_cmp {
185 __le32 rx_cmp_len_flags_type;
186 #define RX_CMP_CMP_TYPE (0x3f << 0)
187 #define RX_CMP_FLAGS_ERROR (1 << 6)
188 #define RX_CMP_FLAGS_PLACEMENT (7 << 7)
189 #define RX_CMP_FLAGS_RSS_VALID (1 << 10)
190 #define RX_CMP_FLAGS_PKT_METADATA_PRESENT (1 << 11)
191 #define RX_CMP_FLAGS_ITYPES_SHIFT 12
192 #define RX_CMP_FLAGS_ITYPES_MASK 0xf000
193 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
194 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12)
195 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)
196 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12)
197 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12)
198 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12)
199 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12)
200 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12)
201 #define RX_CMP_LEN (0xffff << 16)
202 #define RX_CMP_LEN_SHIFT 16
203
204 u32 rx_cmp_opaque;
205 __le32 rx_cmp_misc_v1;
206 #define RX_CMP_V1 (1 << 0)
207 #define RX_CMP_AGG_BUFS (0x1f << 1)
208 #define RX_CMP_AGG_BUFS_SHIFT 1
209 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9)
210 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9
211 #define RX_CMP_V3_RSS_EXT_OP_LEGACY (0xf << 12)
212 #define RX_CMP_V3_RSS_EXT_OP_LEGACY_SHIFT 12
213 #define RX_CMP_V3_RSS_EXT_OP_NEW (0xf << 8)
214 #define RX_CMP_V3_RSS_EXT_OP_NEW_SHIFT 8
215 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16)
216 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16
217 #define RX_CMP_SUB_NS_TS (0xf << 16)
218 #define RX_CMP_SUB_NS_TS_SHIFT 16
219 #define RX_CMP_METADATA1 (0xf << 28)
220 #define RX_CMP_METADATA1_SHIFT 28
221 #define RX_CMP_METADATA1_TPID_SEL (0x7 << 28)
222 #define RX_CMP_METADATA1_TPID_8021Q (0x1 << 28)
223 #define RX_CMP_METADATA1_TPID_8021AD (0x0 << 28)
224 #define RX_CMP_METADATA1_VALID (0x8 << 28)
225
226 __le32 rx_cmp_rss_hash;
227};
228
229#define BNXT_PTP_RX_TS_VALID(flags) \
230 (((flags) & RX_CMP_FLAGS_ITYPES_MASK) == RX_CMP_FLAGS_ITYPE_PTP_W_TS)
231
232#define BNXT_ALL_RX_TS_VALID(flags) \
233 !((flags) & RX_CMP_FLAGS_PKT_METADATA_PRESENT)
234
235#define RX_CMP_HASH_VALID(rxcmp) \
236 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
237
238#define RSS_PROFILE_ID_MASK 0x1f
239
240#define RX_CMP_HASH_TYPE(rxcmp) \
241 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
242 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
243
244#define RX_CMP_V3_HASH_TYPE_LEGACY(rxcmp) \
245 ((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_V3_RSS_EXT_OP_LEGACY) >>\
246 RX_CMP_V3_RSS_EXT_OP_LEGACY_SHIFT)
247
248#define RX_CMP_V3_HASH_TYPE_NEW(rxcmp) \
249 ((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_V3_RSS_EXT_OP_NEW) >>\
250 RX_CMP_V3_RSS_EXT_OP_NEW_SHIFT)
251
252#define RX_CMP_V3_HASH_TYPE(bp, rxcmp) \
253 (((bp)->rss_cap & BNXT_RSS_CAP_RSS_TCAM) ? \
254 RX_CMP_V3_HASH_TYPE_NEW(rxcmp) : \
255 RX_CMP_V3_HASH_TYPE_LEGACY(rxcmp))
256
257#define EXT_OP_INNER_4 0x0
258#define EXT_OP_OUTER_4 0x2
259#define EXT_OP_INNFL_3 0x8
260#define EXT_OP_OUTFL_3 0xa
261
262#define RX_CMP_VLAN_VALID(rxcmp) \
263 ((rxcmp)->rx_cmp_misc_v1 & cpu_to_le32(RX_CMP_METADATA1_VALID))
264
265#define RX_CMP_VLAN_TPID_SEL(rxcmp) \
266 (le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_METADATA1_TPID_SEL)
267
268struct rx_cmp_ext {
269 __le32 rx_cmp_flags2;
270 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1
271 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
272 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
273 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
274 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)
275 __le32 rx_cmp_meta_data;
276 #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff
277 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff
278 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000
279 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16
280 __le32 rx_cmp_cfa_code_errors_v2;
281 #define RX_CMP_V (1 << 0)
282 #define RX_CMPL_ERRORS_MASK (0x7fff << 1)
283 #define RX_CMPL_ERRORS_SFT 1
284 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
285 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
286 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)
287 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
288 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
289 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)
290 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)
291 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)
292 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)
293 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)
294 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)
295 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)
296 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)
297 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)
298 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)
299 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)
300 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)
301 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)
302 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)
303 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)
304 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)
305 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)
306 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)
307 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)
308 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)
309 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)
310 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
311 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)
312
313 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
314 #define RX_CMPL_CFA_CODE_SFT 16
315 #define RX_CMPL_METADATA0_TCI_MASK (0xffff << 16)
316 #define RX_CMPL_METADATA0_VID_MASK (0x0fff << 16)
317 #define RX_CMPL_METADATA0_SFT 16
318
319 __le32 rx_cmp_timestamp;
320};
321
322#define RX_CMP_L2_ERRORS \
323 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
324
325#define RX_CMP_L4_CS_BITS \
326 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
327
328#define RX_CMP_L4_CS_ERR_BITS \
329 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
330
331#define RX_CMP_L4_CS_OK(rxcmp1) \
332 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \
333 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
334
335#define RX_CMP_ENCAP(rxcmp1) \
336 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \
337 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
338
339#define RX_CMP_CFA_CODE(rxcmpl1) \
340 ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \
341 RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
342
343#define RX_CMP_METADATA0_TCI(rxcmp1) \
344 ((le32_to_cpu((rxcmp1)->rx_cmp_cfa_code_errors_v2) & \
345 RX_CMPL_METADATA0_TCI_MASK) >> RX_CMPL_METADATA0_SFT)
346
347struct rx_agg_cmp {
348 __le32 rx_agg_cmp_len_flags_type;
349 #define RX_AGG_CMP_TYPE (0x3f << 0)
350 #define RX_AGG_CMP_LEN (0xffff << 16)
351 #define RX_AGG_CMP_LEN_SHIFT 16
352 u32 rx_agg_cmp_opaque;
353 __le32 rx_agg_cmp_v;
354 #define RX_AGG_CMP_V (1 << 0)
355 #define RX_AGG_CMP_AGG_ID (0xffff << 16)
356 #define RX_AGG_CMP_AGG_ID_SHIFT 16
357 __le32 rx_agg_cmp_unused;
358};
359
360#define TPA_AGG_AGG_ID(rx_agg) \
361 ((le32_to_cpu((rx_agg)->rx_agg_cmp_v) & \
362 RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)
363
364struct rx_tpa_start_cmp {
365 __le32 rx_tpa_start_cmp_len_flags_type;
366 #define RX_TPA_START_CMP_TYPE (0x3f << 0)
367 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6)
368 #define RX_TPA_START_CMP_FLAGS_SHIFT 6
369 #define RX_TPA_START_CMP_FLAGS_ERROR (0x1 << 6)
370 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)
371 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7
372 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
373 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
374 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
375 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
376 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)
377 #define RX_TPA_START_CMP_FLAGS_TIMESTAMP (0x1 << 11)
378 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)
379 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12
380 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
381 #define RX_TPA_START_CMP_LEN (0xffff << 16)
382 #define RX_TPA_START_CMP_LEN_SHIFT 16
383
384 u32 rx_tpa_start_cmp_opaque;
385 __le32 rx_tpa_start_cmp_misc_v1;
386 #define RX_TPA_START_CMP_V1 (0x1 << 0)
387 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9)
388 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9
389 #define RX_TPA_START_CMP_V3_RSS_HASH_TYPE (0x1ff << 7)
390 #define RX_TPA_START_CMP_V3_RSS_HASH_TYPE_SHIFT 7
391 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25)
392 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25
393 #define RX_TPA_START_CMP_AGG_ID_P5 (0xffff << 16)
394 #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5 16
395 #define RX_TPA_START_CMP_METADATA1 (0xf << 28)
396 #define RX_TPA_START_CMP_METADATA1_SHIFT 28
397 #define RX_TPA_START_METADATA1_TPID_SEL (0x7 << 28)
398 #define RX_TPA_START_METADATA1_TPID_8021Q (0x1 << 28)
399 #define RX_TPA_START_METADATA1_TPID_8021AD (0x0 << 28)
400 #define RX_TPA_START_METADATA1_VALID (0x8 << 28)
401
402 __le32 rx_tpa_start_cmp_rss_hash;
403};
404
405#define TPA_START_HASH_VALID(rx_tpa_start) \
406 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
407 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
408
409#define TPA_START_HASH_TYPE(rx_tpa_start) \
410 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
411 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \
412 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
413
414#define TPA_START_V3_HASH_TYPE(rx_tpa_start) \
415 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
416 RX_TPA_START_CMP_V3_RSS_HASH_TYPE) >> \
417 RX_TPA_START_CMP_V3_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
418
419#define TPA_START_AGG_ID(rx_tpa_start) \
420 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
421 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
422
423#define TPA_START_AGG_ID_P5(rx_tpa_start) \
424 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
425 RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)
426
427#define TPA_START_ERROR(rx_tpa_start) \
428 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
429 cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))
430
431#define TPA_START_VLAN_VALID(rx_tpa_start) \
432 ((rx_tpa_start)->rx_tpa_start_cmp_misc_v1 & \
433 cpu_to_le32(RX_TPA_START_METADATA1_VALID))
434
435#define TPA_START_VLAN_TPID_SEL(rx_tpa_start) \
436 (le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
437 RX_TPA_START_METADATA1_TPID_SEL)
438
439struct rx_tpa_start_cmp_ext {
440 __le32 rx_tpa_start_cmp_flags2;
441 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)
442 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
443 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
444 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
445 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8)
446 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID (0x1 << 9)
447 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT (0x3 << 10)
448 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT 10
449 #define RX_TPA_START_CMP_V3_FLAGS2_T_IP_TYPE (0x1 << 10)
450 #define RX_TPA_START_CMP_V3_FLAGS2_AGG_GRO (0x1 << 11)
451 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL (0xffff << 16)
452 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT 16
453
454 __le32 rx_tpa_start_cmp_metadata;
455 __le32 rx_tpa_start_cmp_cfa_code_v2;
456 #define RX_TPA_START_CMP_V2 (0x1 << 0)
457 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
458 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT 1
459 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
460 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
461 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
462 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)
463 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16
464 #define RX_TPA_START_CMP_METADATA0_TCI_MASK (0xffff << 16)
465 #define RX_TPA_START_CMP_METADATA0_VID_MASK (0x0fff << 16)
466 #define RX_TPA_START_CMP_METADATA0_SFT 16
467 __le32 rx_tpa_start_cmp_hdr_info;
468};
469
470#define TPA_START_CFA_CODE(rx_tpa_start) \
471 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
472 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
473
474#define TPA_START_IS_IPV6(rx_tpa_start) \
475 (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 & \
476 cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
477
478#define TPA_START_ERROR_CODE(rx_tpa_start) \
479 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
480 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >> \
481 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)
482
483#define TPA_START_METADATA0_TCI(rx_tpa_start) \
484 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
485 RX_TPA_START_CMP_METADATA0_TCI_MASK) >> \
486 RX_TPA_START_CMP_METADATA0_SFT)
487
488struct rx_tpa_end_cmp {
489 __le32 rx_tpa_end_cmp_len_flags_type;
490 #define RX_TPA_END_CMP_TYPE (0x3f << 0)
491 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6)
492 #define RX_TPA_END_CMP_FLAGS_SHIFT 6
493 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7)
494 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7
495 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
496 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
497 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
498 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
499 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10)
500 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12)
501 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12
502 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
503 #define RX_TPA_END_CMP_LEN (0xffff << 16)
504 #define RX_TPA_END_CMP_LEN_SHIFT 16
505
506 u32 rx_tpa_end_cmp_opaque;
507 __le32 rx_tpa_end_cmp_misc_v1;
508 #define RX_TPA_END_CMP_V1 (0x1 << 0)
509 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1)
510 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1
511 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8)
512 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8
513 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16)
514 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16
515 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25)
516 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25
517 #define RX_TPA_END_CMP_AGG_ID_P5 (0xffff << 16)
518 #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5 16
519
520 __le32 rx_tpa_end_cmp_tsdelta;
521 #define RX_TPA_END_GRO_TS (0x1 << 31)
522};
523
524#define TPA_END_AGG_ID(rx_tpa_end) \
525 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
526 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
527
528#define TPA_END_AGG_ID_P5(rx_tpa_end) \
529 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
530 RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)
531
532#define TPA_END_PAYLOAD_OFF(rx_tpa_end) \
533 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
534 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)
535
536#define TPA_END_AGG_BUFS(rx_tpa_end) \
537 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
538 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)
539
540#define TPA_END_TPA_SEGS(rx_tpa_end) \
541 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
542 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
543
544#define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \
545 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \
546 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
547
548#define TPA_END_GRO(rx_tpa_end) \
549 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \
550 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
551
552#define TPA_END_GRO_TS(rx_tpa_end) \
553 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \
554 cpu_to_le32(RX_TPA_END_GRO_TS)))
555
556struct rx_tpa_end_cmp_ext {
557 __le32 rx_tpa_end_cmp_dup_acks;
558 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)
559 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5 (0xff << 16)
560 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5 16
561 #define RX_TPA_END_CMP_AGG_BUFS_P5 (0xff << 24)
562 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5 24
563
564 __le32 rx_tpa_end_cmp_seg_len;
565 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)
566
567 __le32 rx_tpa_end_cmp_errors_v2;
568 #define RX_TPA_END_CMP_V2 (0x1 << 0)
569 #define RX_TPA_END_CMP_ERRORS (0x3 << 1)
570 #define RX_TPA_END_CMP_ERRORS_P5 (0x7 << 1)
571 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1
572 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
573 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
574 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
575 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR (0x4 << 1)
576 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
577
578 u32 rx_tpa_end_cmp_start_opaque;
579};
580
581#define TPA_END_ERRORS(rx_tpa_end_ext) \
582 ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \
583 cpu_to_le32(RX_TPA_END_CMP_ERRORS))
584
585#define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext) \
586 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
587 RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >> \
588 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)
589
590#define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext) \
591 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
592 RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)
593
594#define EVENT_DATA1_RESET_NOTIFY_FATAL(data1) \
595 (((data1) & \
596 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
597 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)
598
599#define EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1) \
600 (((data1) & \
601 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
602 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION)
603
604#define EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2) \
605 ((data2) & \
606 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK)
607
608#define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1) \
609 !!((data1) & \
610 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
611
612#define EVENT_DATA1_RECOVERY_ENABLED(data1) \
613 !!((data1) & \
614 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
615
616#define BNXT_EVENT_ERROR_REPORT_TYPE(data1) \
617 (((data1) & \
618 ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >>\
619 ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT)
620
621#define BNXT_EVENT_INVALID_SIGNAL_DATA(data2) \
622 (((data2) & \
623 ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK) >>\
624 ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT)
625
626struct nqe_cn {
627 __le16 type;
628 #define NQ_CN_TYPE_MASK 0x3fUL
629 #define NQ_CN_TYPE_SFT 0
630 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
631 #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
632 #define NQ_CN_TOGGLE_MASK 0xc0UL
633 #define NQ_CN_TOGGLE_SFT 6
634 __le16 reserved16;
635 __le32 cq_handle_low;
636 __le32 v;
637 #define NQ_CN_V 0x1UL
638 __le32 cq_handle_high;
639};
640
641#define BNXT_NQ_HDL_IDX_MASK 0x00ffffff
642#define BNXT_NQ_HDL_TYPE_MASK 0xff000000
643#define BNXT_NQ_HDL_TYPE_SHIFT 24
644#define BNXT_NQ_HDL_TYPE_RX 0x00
645#define BNXT_NQ_HDL_TYPE_TX 0x01
646
647#define BNXT_NQ_HDL_IDX(hdl) ((hdl) & BNXT_NQ_HDL_IDX_MASK)
648#define BNXT_NQ_HDL_TYPE(hdl) (((hdl) & BNXT_NQ_HDL_TYPE_MASK) >> \
649 BNXT_NQ_HDL_TYPE_SHIFT)
650
651#define BNXT_SET_NQ_HDL(cpr) \
652 (((cpr)->cp_ring_type << BNXT_NQ_HDL_TYPE_SHIFT) | (cpr)->cp_idx)
653
654#define NQE_CN_TYPE(type) ((type) & NQ_CN_TYPE_MASK)
655#define NQE_CN_TOGGLE(type) (((type) & NQ_CN_TOGGLE_MASK) >> \
656 NQ_CN_TOGGLE_SFT)
657
658#define DB_IDX_MASK 0xffffff
659#define DB_IDX_VALID (0x1 << 26)
660#define DB_IRQ_DIS (0x1 << 27)
661#define DB_KEY_TX (0x0 << 28)
662#define DB_KEY_RX (0x1 << 28)
663#define DB_KEY_CP (0x2 << 28)
664#define DB_KEY_ST (0x3 << 28)
665#define DB_KEY_TX_PUSH (0x4 << 28)
666#define DB_LONG_TX_PUSH (0x2 << 24)
667
668#define BNXT_MIN_ROCE_CP_RINGS 2
669#define BNXT_MIN_ROCE_STAT_CTXS 1
670
671/* 64-bit doorbell */
672#define DBR_INDEX_MASK 0x0000000000ffffffULL
673#define DBR_EPOCH_MASK 0x01000000UL
674#define DBR_EPOCH_SFT 24
675#define DBR_TOGGLE_MASK 0x06000000UL
676#define DBR_TOGGLE_SFT 25
677#define DBR_XID_MASK 0x000fffff00000000ULL
678#define DBR_XID_SFT 32
679#define DBR_PATH_L2 (0x1ULL << 56)
680#define DBR_VALID (0x1ULL << 58)
681#define DBR_TYPE_SQ (0x0ULL << 60)
682#define DBR_TYPE_RQ (0x1ULL << 60)
683#define DBR_TYPE_SRQ (0x2ULL << 60)
684#define DBR_TYPE_SRQ_ARM (0x3ULL << 60)
685#define DBR_TYPE_CQ (0x4ULL << 60)
686#define DBR_TYPE_CQ_ARMSE (0x5ULL << 60)
687#define DBR_TYPE_CQ_ARMALL (0x6ULL << 60)
688#define DBR_TYPE_CQ_ARMENA (0x7ULL << 60)
689#define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60)
690#define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60)
691#define DBR_TYPE_NQ (0xaULL << 60)
692#define DBR_TYPE_NQ_ARM (0xbULL << 60)
693#define DBR_TYPE_NQ_MASK (0xeULL << 60)
694#define DBR_TYPE_NULL (0xfULL << 60)
695
696#define DB_PF_OFFSET_P5 0x10000
697#define DB_VF_OFFSET_P5 0x4000
698
699#define INVALID_HW_RING_ID ((u16)-1)
700
701/* The hardware supports certain page sizes. Use the supported page sizes
702 * to allocate the rings.
703 */
704#if (PAGE_SHIFT < 12)
705#define BNXT_PAGE_SHIFT 12
706#elif (PAGE_SHIFT <= 13)
707#define BNXT_PAGE_SHIFT PAGE_SHIFT
708#elif (PAGE_SHIFT < 16)
709#define BNXT_PAGE_SHIFT 13
710#else
711#define BNXT_PAGE_SHIFT 16
712#endif
713
714#define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)
715
716/* The RXBD length is 16-bit so we can only support page sizes < 64K */
717#if (PAGE_SHIFT > 15)
718#define BNXT_RX_PAGE_SHIFT 15
719#else
720#define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
721#endif
722
723#define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
724
725#define BNXT_MAX_MTU 9500
726
727/* First RX buffer page in XDP multi-buf mode
728 *
729 * +-------------------------------------------------------------------------+
730 * | XDP_PACKET_HEADROOM | bp->rx_buf_use_size | skb_shared_info|
731 * | (bp->rx_dma_offset) | | |
732 * +-------------------------------------------------------------------------+
733 */
734#define BNXT_MAX_PAGE_MODE_MTU_SBUF \
735 ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \
736 XDP_PACKET_HEADROOM)
737#define BNXT_MAX_PAGE_MODE_MTU \
738 (BNXT_MAX_PAGE_MODE_MTU_SBUF - \
739 SKB_DATA_ALIGN((unsigned int)sizeof(struct skb_shared_info)))
740
741#define BNXT_MIN_PKT_SIZE 52
742
743#define BNXT_DEFAULT_RX_RING_SIZE 511
744#define BNXT_DEFAULT_TX_RING_SIZE 511
745
746#define MAX_TPA 64
747#define MAX_TPA_P5 256
748#define MAX_TPA_P5_MASK (MAX_TPA_P5 - 1)
749#define MAX_TPA_SEGS_P5 0x3f
750
751#if (BNXT_PAGE_SHIFT == 16)
752#define MAX_RX_PAGES_AGG_ENA 1
753#define MAX_RX_PAGES 4
754#define MAX_RX_AGG_PAGES 4
755#define MAX_TX_PAGES 1
756#define MAX_CP_PAGES 16
757#else
758#define MAX_RX_PAGES_AGG_ENA 8
759#define MAX_RX_PAGES 32
760#define MAX_RX_AGG_PAGES 32
761#define MAX_TX_PAGES 8
762#define MAX_CP_PAGES 128
763#endif
764
765#define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
766#define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
767#define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
768
769#define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
770#define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
771
772#define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
773
774#define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
775#define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
776
777#define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
778
779#define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1)
780#define BNXT_MAX_RX_DESC_CNT_JUM_ENA (RX_DESC_CNT * MAX_RX_PAGES_AGG_ENA - 1)
781#define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
782#define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)
783
784/* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1. We need one extra
785 * BD because the first TX BD is always a long BD.
786 */
787#define BNXT_MIN_TX_DESC_CNT (MAX_SKB_FRAGS + 2)
788
789#define RX_RING(bp, x) (((x) & (bp)->rx_ring_mask) >> (BNXT_PAGE_SHIFT - 4))
790#define RX_AGG_RING(bp, x) (((x) & (bp)->rx_agg_ring_mask) >> \
791 (BNXT_PAGE_SHIFT - 4))
792#define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
793
794#define TX_RING(bp, x) (((x) & (bp)->tx_ring_mask) >> (BNXT_PAGE_SHIFT - 4))
795#define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))
796
797#define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
798#define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))
799
800#define TX_CMP_VALID(txcmp, raw_cons) \
801 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \
802 !((raw_cons) & bp->cp_bit))
803
804#define RX_CMP_VALID(rxcmp1, raw_cons) \
805 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
806 !((raw_cons) & bp->cp_bit))
807
808#define RX_AGG_CMP_VALID(agg, raw_cons) \
809 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
810 !((raw_cons) & bp->cp_bit))
811
812#define NQ_CMP_VALID(nqcmp, raw_cons) \
813 (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
814
815#define TX_CMP_TYPE(txcmp) \
816 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
817
818#define RX_CMP_TYPE(rxcmp) \
819 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
820
821#define RING_RX(bp, idx) ((idx) & (bp)->rx_ring_mask)
822#define NEXT_RX(idx) ((idx) + 1)
823
824#define RING_RX_AGG(bp, idx) ((idx) & (bp)->rx_agg_ring_mask)
825#define NEXT_RX_AGG(idx) ((idx) + 1)
826
827#define RING_TX(bp, idx) ((idx) & (bp)->tx_ring_mask)
828#define NEXT_TX(idx) ((idx) + 1)
829
830#define ADV_RAW_CMP(idx, n) ((idx) + (n))
831#define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1)
832#define RING_CMP(idx) ((idx) & bp->cp_ring_mask)
833#define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1))
834
835#define DFLT_HWRM_CMD_TIMEOUT 500
836
837#define BNXT_RX_EVENT 1
838#define BNXT_AGG_EVENT 2
839#define BNXT_TX_EVENT 4
840#define BNXT_REDIRECT_EVENT 8
841#define BNXT_TX_CMP_EVENT 0x10
842
843struct bnxt_sw_tx_bd {
844 union {
845 struct sk_buff *skb;
846 struct xdp_frame *xdpf;
847 };
848 DEFINE_DMA_UNMAP_ADDR(mapping);
849 DEFINE_DMA_UNMAP_LEN(len);
850 struct page *page;
851 u8 is_gso;
852 u8 is_push;
853 u8 action;
854 unsigned short nr_frags;
855 u16 rx_prod;
856};
857
858struct bnxt_sw_rx_bd {
859 void *data;
860 u8 *data_ptr;
861 dma_addr_t mapping;
862};
863
864struct bnxt_sw_rx_agg_bd {
865 struct page *page;
866 unsigned int offset;
867 dma_addr_t mapping;
868};
869
870struct bnxt_ring_mem_info {
871 int nr_pages;
872 int page_size;
873 u16 flags;
874#define BNXT_RMEM_VALID_PTE_FLAG 1
875#define BNXT_RMEM_RING_PTE_FLAG 2
876#define BNXT_RMEM_USE_FULL_PAGE_FLAG 4
877
878 u16 depth;
879 struct bnxt_ctx_mem_type *ctx_mem;
880
881 void **pg_arr;
882 dma_addr_t *dma_arr;
883
884 __le64 *pg_tbl;
885 dma_addr_t pg_tbl_map;
886
887 int vmem_size;
888 void **vmem;
889};
890
891struct bnxt_ring_struct {
892 struct bnxt_ring_mem_info ring_mem;
893
894 u16 fw_ring_id; /* Ring id filled by Chimp FW */
895 union {
896 u16 grp_idx;
897 u16 map_idx; /* Used by cmpl rings */
898 };
899 u32 handle;
900 u8 queue_id;
901};
902
903struct tx_push_bd {
904 __le32 doorbell;
905 __le32 tx_bd_len_flags_type;
906 u32 tx_bd_opaque;
907 struct tx_bd_ext txbd2;
908};
909
910struct tx_push_buffer {
911 struct tx_push_bd push_bd;
912 u32 data[25];
913};
914
915struct bnxt_db_info {
916 void __iomem *doorbell;
917 union {
918 u64 db_key64;
919 u32 db_key32;
920 };
921 u32 db_ring_mask;
922 u32 db_epoch_mask;
923 u8 db_epoch_shift;
924};
925
926#define DB_EPOCH(db, idx) (((idx) & (db)->db_epoch_mask) << \
927 ((db)->db_epoch_shift))
928
929#define DB_TOGGLE(tgl) ((tgl) << DBR_TOGGLE_SFT)
930
931#define DB_RING_IDX(db, idx) (((idx) & (db)->db_ring_mask) | \
932 DB_EPOCH(db, idx))
933
934struct bnxt_tx_ring_info {
935 struct bnxt_napi *bnapi;
936 struct bnxt_cp_ring_info *tx_cpr;
937 u16 tx_prod;
938 u16 tx_cons;
939 u16 tx_hw_cons;
940 u16 txq_index;
941 u8 tx_napi_idx;
942 u8 kick_pending;
943 struct bnxt_db_info tx_db;
944
945 struct tx_bd *tx_desc_ring[MAX_TX_PAGES];
946 struct bnxt_sw_tx_bd *tx_buf_ring;
947
948 dma_addr_t tx_desc_mapping[MAX_TX_PAGES];
949
950 struct tx_push_buffer *tx_push;
951 dma_addr_t tx_push_mapping;
952 __le64 data_mapping;
953
954#define BNXT_DEV_STATE_CLOSING 0x1
955 u32 dev_state;
956
957 struct bnxt_ring_struct tx_ring_struct;
958 /* Synchronize simultaneous xdp_xmit on same ring */
959 spinlock_t xdp_tx_lock;
960};
961
962#define BNXT_LEGACY_COAL_CMPL_PARAMS \
963 (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN | \
964 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX | \
965 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET | \
966 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE | \
967 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR | \
968 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
969 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR | \
970 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
971 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
972
973#define BNXT_COAL_CMPL_ENABLES \
974 (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
975 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
976 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
977 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
978
979#define BNXT_COAL_CMPL_MIN_TMR_ENABLE \
980 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
981
982#define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE \
983 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
984
985struct bnxt_coal_cap {
986 u32 cmpl_params;
987 u32 nq_params;
988 u16 num_cmpl_dma_aggr_max;
989 u16 num_cmpl_dma_aggr_during_int_max;
990 u16 cmpl_aggr_dma_tmr_max;
991 u16 cmpl_aggr_dma_tmr_during_int_max;
992 u16 int_lat_tmr_min_max;
993 u16 int_lat_tmr_max_max;
994 u16 num_cmpl_aggr_int_max;
995 u16 timer_units;
996};
997
998struct bnxt_coal {
999 u16 coal_ticks;
1000 u16 coal_ticks_irq;
1001 u16 coal_bufs;
1002 u16 coal_bufs_irq;
1003 /* RING_IDLE enabled when coal ticks < idle_thresh */
1004 u16 idle_thresh;
1005 u8 bufs_per_record;
1006 u8 budget;
1007 u16 flags;
1008};
1009
1010struct bnxt_tpa_info {
1011 void *data;
1012 u8 *data_ptr;
1013 dma_addr_t mapping;
1014 u16 len;
1015 unsigned short gso_type;
1016 u32 flags2;
1017 u32 metadata;
1018 enum pkt_hash_types hash_type;
1019 u32 rss_hash;
1020 u32 hdr_info;
1021
1022#define BNXT_TPA_L4_SIZE(hdr_info) \
1023 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
1024
1025#define BNXT_TPA_INNER_L3_OFF(hdr_info) \
1026 (((hdr_info) >> 18) & 0x1ff)
1027
1028#define BNXT_TPA_INNER_L2_OFF(hdr_info) \
1029 (((hdr_info) >> 9) & 0x1ff)
1030
1031#define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
1032 ((hdr_info) & 0x1ff)
1033
1034 u16 cfa_code; /* cfa_code in TPA start compl */
1035 u8 agg_count;
1036 u8 vlan_valid:1;
1037 u8 cfa_code_valid:1;
1038 struct rx_agg_cmp *agg_arr;
1039};
1040
1041#define BNXT_AGG_IDX_BMAP_SIZE (MAX_TPA_P5 / BITS_PER_LONG)
1042
1043struct bnxt_tpa_idx_map {
1044 u16 agg_id_tbl[1024];
1045 unsigned long agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];
1046};
1047
1048struct bnxt_rx_ring_info {
1049 struct bnxt_napi *bnapi;
1050 struct bnxt_cp_ring_info *rx_cpr;
1051 u16 rx_prod;
1052 u16 rx_agg_prod;
1053 u16 rx_sw_agg_prod;
1054 u16 rx_next_cons;
1055 struct bnxt_db_info rx_db;
1056 struct bnxt_db_info rx_agg_db;
1057
1058 struct bpf_prog *xdp_prog;
1059
1060 struct rx_bd *rx_desc_ring[MAX_RX_PAGES];
1061 struct bnxt_sw_rx_bd *rx_buf_ring;
1062
1063 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
1064 struct bnxt_sw_rx_agg_bd *rx_agg_ring;
1065
1066 unsigned long *rx_agg_bmap;
1067 u16 rx_agg_bmap_size;
1068
1069 dma_addr_t rx_desc_mapping[MAX_RX_PAGES];
1070 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
1071
1072 struct bnxt_tpa_info *rx_tpa;
1073 struct bnxt_tpa_idx_map *rx_tpa_idx_map;
1074
1075 struct bnxt_ring_struct rx_ring_struct;
1076 struct bnxt_ring_struct rx_agg_ring_struct;
1077 struct xdp_rxq_info xdp_rxq;
1078 struct page_pool *page_pool;
1079};
1080
1081struct bnxt_rx_sw_stats {
1082 u64 rx_l4_csum_errors;
1083 u64 rx_resets;
1084 u64 rx_buf_errors;
1085 u64 rx_oom_discards;
1086 u64 rx_netpoll_discards;
1087};
1088
1089struct bnxt_tx_sw_stats {
1090 u64 tx_resets;
1091};
1092
1093struct bnxt_cmn_sw_stats {
1094 u64 missed_irqs;
1095};
1096
1097struct bnxt_sw_stats {
1098 struct bnxt_rx_sw_stats rx;
1099 struct bnxt_tx_sw_stats tx;
1100 struct bnxt_cmn_sw_stats cmn;
1101};
1102
1103struct bnxt_total_ring_err_stats {
1104 u64 rx_total_l4_csum_errors;
1105 u64 rx_total_resets;
1106 u64 rx_total_buf_errors;
1107 u64 rx_total_oom_discards;
1108 u64 rx_total_netpoll_discards;
1109 u64 rx_total_ring_discards;
1110 u64 tx_total_resets;
1111 u64 tx_total_ring_discards;
1112 u64 total_missed_irqs;
1113};
1114
1115struct bnxt_stats_mem {
1116 u64 *sw_stats;
1117 u64 *hw_masks;
1118 void *hw_stats;
1119 dma_addr_t hw_stats_map;
1120 int len;
1121};
1122
1123struct bnxt_cp_ring_info {
1124 struct bnxt_napi *bnapi;
1125 u32 cp_raw_cons;
1126 struct bnxt_db_info cp_db;
1127
1128 u8 had_work_done:1;
1129 u8 has_more_work:1;
1130 u8 had_nqe_notify:1;
1131 u8 toggle;
1132
1133 u8 cp_ring_type;
1134 u8 cp_idx;
1135
1136 u32 last_cp_raw_cons;
1137
1138 struct bnxt_coal rx_ring_coal;
1139 u64 rx_packets;
1140 u64 rx_bytes;
1141 u64 event_ctr;
1142
1143 struct dim dim;
1144
1145 union {
1146 struct tx_cmp **cp_desc_ring;
1147 struct nqe_cn **nq_desc_ring;
1148 };
1149
1150 dma_addr_t *cp_desc_mapping;
1151
1152 struct bnxt_stats_mem stats;
1153 u32 hw_stats_ctx_id;
1154
1155 struct bnxt_sw_stats sw_stats;
1156
1157 struct bnxt_ring_struct cp_ring_struct;
1158
1159 int cp_ring_count;
1160 struct bnxt_cp_ring_info *cp_ring_arr;
1161};
1162
1163#define BNXT_MAX_QUEUE 8
1164#define BNXT_MAX_TXR_PER_NAPI BNXT_MAX_QUEUE
1165
1166#define bnxt_for_each_napi_tx(iter, bnapi, txr) \
1167 for (iter = 0, txr = (bnapi)->tx_ring[0]; txr; \
1168 txr = (iter < BNXT_MAX_TXR_PER_NAPI - 1) ? \
1169 (bnapi)->tx_ring[++iter] : NULL)
1170
1171struct bnxt_napi {
1172 struct napi_struct napi;
1173 struct bnxt *bp;
1174
1175 int index;
1176 struct bnxt_cp_ring_info cp_ring;
1177 struct bnxt_rx_ring_info *rx_ring;
1178 struct bnxt_tx_ring_info *tx_ring[BNXT_MAX_TXR_PER_NAPI];
1179
1180 void (*tx_int)(struct bnxt *, struct bnxt_napi *,
1181 int budget);
1182 u8 events;
1183 u8 tx_fault:1;
1184
1185 u32 flags;
1186#define BNXT_NAPI_FLAG_XDP 0x1
1187
1188 bool in_reset;
1189};
1190
1191struct bnxt_irq {
1192 irq_handler_t handler;
1193 unsigned int vector;
1194 u8 requested:1;
1195 u8 have_cpumask:1;
1196 char name[IFNAMSIZ + 2];
1197 cpumask_var_t cpu_mask;
1198};
1199
1200#define HWRM_RING_ALLOC_TX 0x1
1201#define HWRM_RING_ALLOC_RX 0x2
1202#define HWRM_RING_ALLOC_AGG 0x4
1203#define HWRM_RING_ALLOC_CMPL 0x8
1204#define HWRM_RING_ALLOC_NQ 0x10
1205
1206#define INVALID_STATS_CTX_ID -1
1207
1208struct bnxt_ring_grp_info {
1209 u16 fw_stats_ctx;
1210 u16 fw_grp_id;
1211 u16 rx_fw_ring_id;
1212 u16 agg_fw_ring_id;
1213 u16 cp_fw_ring_id;
1214};
1215
1216struct bnxt_vnic_info {
1217 u16 fw_vnic_id; /* returned by Chimp during alloc */
1218#define BNXT_MAX_CTX_PER_VNIC 8
1219 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
1220 u16 fw_l2_ctx_id;
1221#define BNXT_MAX_UC_ADDRS 4
1222 struct bnxt_l2_filter *l2_filters[BNXT_MAX_UC_ADDRS];
1223 /* index 0 always dev_addr */
1224 u16 uc_filter_count;
1225 u8 *uc_list;
1226
1227 u16 *fw_grp_ids;
1228 dma_addr_t rss_table_dma_addr;
1229 __le16 *rss_table;
1230 dma_addr_t rss_hash_key_dma_addr;
1231 u64 *rss_hash_key;
1232 int rss_table_size;
1233#define BNXT_RSS_TABLE_ENTRIES_P5 64
1234#define BNXT_RSS_TABLE_SIZE_P5 (BNXT_RSS_TABLE_ENTRIES_P5 * 4)
1235#define BNXT_RSS_TABLE_MAX_TBL_P5 8
1236#define BNXT_MAX_RSS_TABLE_SIZE_P5 \
1237 (BNXT_RSS_TABLE_SIZE_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1238#define BNXT_MAX_RSS_TABLE_ENTRIES_P5 \
1239 (BNXT_RSS_TABLE_ENTRIES_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1240
1241 u32 rx_mask;
1242
1243 u8 *mc_list;
1244 int mc_list_size;
1245 int mc_list_count;
1246 dma_addr_t mc_list_mapping;
1247#define BNXT_MAX_MC_ADDRS 16
1248
1249 u32 flags;
1250#define BNXT_VNIC_RSS_FLAG 1
1251#define BNXT_VNIC_RFS_FLAG 2
1252#define BNXT_VNIC_MCAST_FLAG 4
1253#define BNXT_VNIC_UCAST_FLAG 8
1254#define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10
1255};
1256
1257struct bnxt_hw_resc {
1258 u16 min_rsscos_ctxs;
1259 u16 max_rsscos_ctxs;
1260 u16 min_cp_rings;
1261 u16 max_cp_rings;
1262 u16 resv_cp_rings;
1263 u16 min_tx_rings;
1264 u16 max_tx_rings;
1265 u16 resv_tx_rings;
1266 u16 max_tx_sch_inputs;
1267 u16 min_rx_rings;
1268 u16 max_rx_rings;
1269 u16 resv_rx_rings;
1270 u16 min_hw_ring_grps;
1271 u16 max_hw_ring_grps;
1272 u16 resv_hw_ring_grps;
1273 u16 min_l2_ctxs;
1274 u16 max_l2_ctxs;
1275 u16 min_vnics;
1276 u16 max_vnics;
1277 u16 resv_vnics;
1278 u16 min_stat_ctxs;
1279 u16 max_stat_ctxs;
1280 u16 resv_stat_ctxs;
1281 u16 max_nqs;
1282 u16 max_irqs;
1283 u16 resv_irqs;
1284};
1285
1286#if defined(CONFIG_BNXT_SRIOV)
1287struct bnxt_vf_info {
1288 u16 fw_fid;
1289 u8 mac_addr[ETH_ALEN]; /* PF assigned MAC Address */
1290 u8 vf_mac_addr[ETH_ALEN]; /* VF assigned MAC address, only
1291 * stored by PF.
1292 */
1293 u16 vlan;
1294 u16 func_qcfg_flags;
1295 u32 flags;
1296#define BNXT_VF_QOS 0x1
1297#define BNXT_VF_SPOOFCHK 0x2
1298#define BNXT_VF_LINK_FORCED 0x4
1299#define BNXT_VF_LINK_UP 0x8
1300#define BNXT_VF_TRUST 0x10
1301 u32 min_tx_rate;
1302 u32 max_tx_rate;
1303 void *hwrm_cmd_req_addr;
1304 dma_addr_t hwrm_cmd_req_dma_addr;
1305};
1306#endif
1307
1308struct bnxt_pf_info {
1309#define BNXT_FIRST_PF_FID 1
1310#define BNXT_FIRST_VF_FID 128
1311 u16 fw_fid;
1312 u16 port_id;
1313 u8 mac_addr[ETH_ALEN];
1314 u32 first_vf_id;
1315 u16 active_vfs;
1316 u16 registered_vfs;
1317 u16 max_vfs;
1318 u32 max_encap_records;
1319 u32 max_decap_records;
1320 u32 max_tx_em_flows;
1321 u32 max_tx_wm_flows;
1322 u32 max_rx_em_flows;
1323 u32 max_rx_wm_flows;
1324 unsigned long *vf_event_bmap;
1325 u16 hwrm_cmd_req_pages;
1326 u8 vf_resv_strategy;
1327#define BNXT_VF_RESV_STRATEGY_MAXIMAL 0
1328#define BNXT_VF_RESV_STRATEGY_MINIMAL 1
1329#define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC 2
1330 void *hwrm_cmd_req_addr[4];
1331 dma_addr_t hwrm_cmd_req_dma_addr[4];
1332 struct bnxt_vf_info *vf;
1333};
1334
1335struct bnxt_filter_base {
1336 struct hlist_node hash;
1337 __le64 filter_id;
1338 u8 type;
1339#define BNXT_FLTR_TYPE_NTUPLE 1
1340#define BNXT_FLTR_TYPE_L2 2
1341 u8 flags;
1342#define BNXT_ACT_DROP 1
1343#define BNXT_ACT_RING_DST 2
1344#define BNXT_ACT_FUNC_DST 4
1345#define BNXT_ACT_NO_AGING 8
1346 u16 sw_id;
1347 u16 rxq;
1348 u16 fw_vnic_id;
1349 u16 vf_idx;
1350 unsigned long state;
1351#define BNXT_FLTR_VALID 0
1352#define BNXT_FLTR_INSERTED 1
1353#define BNXT_FLTR_FW_DELETED 2
1354
1355 struct rcu_head rcu;
1356};
1357
1358struct bnxt_ntuple_filter {
1359 struct bnxt_filter_base base;
1360 struct flow_keys fkeys;
1361 struct bnxt_l2_filter *l2_fltr;
1362 u32 ntuple_flags;
1363#define BNXT_NTUPLE_MATCH_SRC_IP 1
1364#define BNXT_NTUPLE_MATCH_DST_IP 2
1365#define BNXT_NTUPLE_MATCH_SRC_PORT 4
1366#define BNXT_NTUPLE_MATCH_DST_PORT 8
1367#define BNXT_NTUPLE_MATCH_ALL (BNXT_NTUPLE_MATCH_SRC_IP | \
1368 BNXT_NTUPLE_MATCH_DST_IP | \
1369 BNXT_NTUPLE_MATCH_SRC_PORT | \
1370 BNXT_NTUPLE_MATCH_DST_PORT)
1371 u32 flow_id;
1372};
1373
1374struct bnxt_l2_key {
1375 union {
1376 struct {
1377 u8 dst_mac_addr[ETH_ALEN];
1378 u16 vlan;
1379 };
1380 u32 filter_key;
1381 };
1382};
1383
1384struct bnxt_ipv4_tuple {
1385 struct flow_dissector_key_ipv4_addrs v4addrs;
1386 struct flow_dissector_key_ports ports;
1387};
1388
1389struct bnxt_ipv6_tuple {
1390 struct flow_dissector_key_ipv6_addrs v6addrs;
1391 struct flow_dissector_key_ports ports;
1392};
1393
1394#define BNXT_L2_KEY_SIZE (sizeof(struct bnxt_l2_key) / 4)
1395
1396struct bnxt_l2_filter {
1397 struct bnxt_filter_base base;
1398 struct bnxt_l2_key l2_key;
1399 atomic_t refcnt;
1400};
1401
1402struct bnxt_link_info {
1403 u8 phy_type;
1404 u8 media_type;
1405 u8 transceiver;
1406 u8 phy_addr;
1407 u8 phy_link_status;
1408#define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK
1409#define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL
1410#define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK
1411 u8 wire_speed;
1412 u8 phy_state;
1413#define BNXT_PHY_STATE_ENABLED 0
1414#define BNXT_PHY_STATE_DISABLED 1
1415
1416 u8 link_state;
1417#define BNXT_LINK_STATE_UNKNOWN 0
1418#define BNXT_LINK_STATE_DOWN 1
1419#define BNXT_LINK_STATE_UP 2
1420#define BNXT_LINK_IS_UP(bp) ((bp)->link_info.link_state == BNXT_LINK_STATE_UP)
1421 u8 active_lanes;
1422 u8 duplex;
1423#define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1424#define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1425 u8 pause;
1426#define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX
1427#define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX
1428#define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \
1429 PORT_PHY_QCFG_RESP_PAUSE_TX)
1430 u8 lp_pause;
1431 u8 auto_pause_setting;
1432 u8 force_pause_setting;
1433 u8 duplex_setting;
1434 u8 auto_mode;
1435#define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \
1436 (mode) <= BNXT_LINK_AUTO_MSK)
1437#define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1438#define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1439#define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1440#define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1441#define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1442#define PHY_VER_LEN 3
1443 u8 phy_ver[PHY_VER_LEN];
1444 u16 link_speed;
1445#define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1446#define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1447#define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1448#define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1449#define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1450#define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1451#define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1452#define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1453#define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1454#define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1455#define BNXT_LINK_SPEED_200GB PORT_PHY_QCFG_RESP_LINK_SPEED_200GB
1456#define BNXT_LINK_SPEED_400GB PORT_PHY_QCFG_RESP_LINK_SPEED_400GB
1457 u16 support_speeds;
1458 u16 support_pam4_speeds;
1459 u16 support_speeds2;
1460
1461 u16 auto_link_speeds; /* fw adv setting */
1462#define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1463#define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1464#define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1465#define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1466#define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1467#define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1468#define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1469#define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1470#define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1471#define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1472 u16 auto_pam4_link_speeds;
1473#define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G
1474#define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G
1475#define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G
1476 u16 auto_link_speeds2;
1477#define BNXT_LINK_SPEEDS2_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB
1478#define BNXT_LINK_SPEEDS2_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB
1479#define BNXT_LINK_SPEEDS2_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_25GB
1480#define BNXT_LINK_SPEEDS2_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_40GB
1481#define BNXT_LINK_SPEEDS2_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB
1482#define BNXT_LINK_SPEEDS2_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB
1483#define BNXT_LINK_SPEEDS2_MSK_50GB_PAM4 \
1484 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB_PAM4_56
1485#define BNXT_LINK_SPEEDS2_MSK_100GB_PAM4 \
1486 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_56
1487#define BNXT_LINK_SPEEDS2_MSK_200GB_PAM4 \
1488 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_56
1489#define BNXT_LINK_SPEEDS2_MSK_400GB_PAM4 \
1490 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_56
1491#define BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112 \
1492 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_112
1493#define BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112 \
1494 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_112
1495#define BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112 \
1496 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_112
1497
1498 u16 support_auto_speeds;
1499 u16 support_pam4_auto_speeds;
1500 u16 support_auto_speeds2;
1501
1502 u16 lp_auto_link_speeds;
1503 u16 lp_auto_pam4_link_speeds;
1504 u16 force_link_speed;
1505 u16 force_pam4_link_speed;
1506 u16 force_link_speed2;
1507#define BNXT_LINK_SPEED_50GB_PAM4 \
1508 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56
1509#define BNXT_LINK_SPEED_100GB_PAM4 \
1510 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56
1511#define BNXT_LINK_SPEED_200GB_PAM4 \
1512 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56
1513#define BNXT_LINK_SPEED_400GB_PAM4 \
1514 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56
1515#define BNXT_LINK_SPEED_100GB_PAM4_112 \
1516 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112
1517#define BNXT_LINK_SPEED_200GB_PAM4_112 \
1518 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112
1519#define BNXT_LINK_SPEED_400GB_PAM4_112 \
1520 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112
1521
1522 u32 preemphasis;
1523 u8 module_status;
1524 u8 active_fec_sig_mode;
1525 u16 fec_cfg;
1526#define BNXT_FEC_NONE PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
1527#define BNXT_FEC_AUTONEG_CAP PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED
1528#define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1529#define BNXT_FEC_ENC_BASE_R_CAP \
1530 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED
1531#define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1532#define BNXT_FEC_ENC_RS_CAP \
1533 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED
1534#define BNXT_FEC_ENC_LLRS_CAP \
1535 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED | \
1536 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED)
1537#define BNXT_FEC_ENC_RS \
1538 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED | \
1539 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED | \
1540 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED)
1541#define BNXT_FEC_ENC_LLRS \
1542 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED | \
1543 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED)
1544
1545 /* copy of requested setting from ethtool cmd */
1546 u8 autoneg;
1547#define BNXT_AUTONEG_SPEED 1
1548#define BNXT_AUTONEG_FLOW_CTRL 2
1549 u8 req_signal_mode;
1550#define BNXT_SIG_MODE_NRZ PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ
1551#define BNXT_SIG_MODE_PAM4 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
1552#define BNXT_SIG_MODE_PAM4_112 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112
1553#define BNXT_SIG_MODE_MAX (PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST + 1)
1554 u8 req_duplex;
1555 u8 req_flow_ctrl;
1556 u16 req_link_speed;
1557 u16 advertising; /* user adv setting */
1558 u16 advertising_pam4;
1559 bool force_link_chng;
1560
1561 bool phy_retry;
1562 unsigned long phy_retry_expires;
1563
1564 /* a copy of phy_qcfg output used to report link
1565 * info to VF
1566 */
1567 struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1568};
1569
1570#define BNXT_FEC_RS544_ON \
1571 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE | \
1572 PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE)
1573
1574#define BNXT_FEC_RS544_OFF \
1575 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE | \
1576 PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE)
1577
1578#define BNXT_FEC_RS272_ON \
1579 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE | \
1580 PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE)
1581
1582#define BNXT_FEC_RS272_OFF \
1583 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE | \
1584 PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE)
1585
1586#define BNXT_PAM4_SUPPORTED(link_info) \
1587 ((link_info)->support_pam4_speeds)
1588
1589#define BNXT_FEC_RS_ON(link_info) \
1590 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \
1591 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1592 (BNXT_PAM4_SUPPORTED(link_info) ? \
1593 (BNXT_FEC_RS544_ON | BNXT_FEC_RS272_OFF) : 0))
1594
1595#define BNXT_FEC_LLRS_ON \
1596 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \
1597 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1598 BNXT_FEC_RS272_ON | BNXT_FEC_RS544_OFF)
1599
1600#define BNXT_FEC_RS_OFF(link_info) \
1601 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE | \
1602 (BNXT_PAM4_SUPPORTED(link_info) ? \
1603 (BNXT_FEC_RS544_OFF | BNXT_FEC_RS272_OFF) : 0))
1604
1605#define BNXT_FEC_BASE_R_ON(link_info) \
1606 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE | \
1607 BNXT_FEC_RS_OFF(link_info))
1608
1609#define BNXT_FEC_ALL_OFF(link_info) \
1610 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1611 BNXT_FEC_RS_OFF(link_info))
1612
1613struct bnxt_queue_info {
1614 u8 queue_id;
1615 u8 queue_profile;
1616};
1617
1618#define BNXT_MAX_LED 4
1619
1620struct bnxt_led_info {
1621 u8 led_id;
1622 u8 led_type;
1623 u8 led_group_id;
1624 u8 unused;
1625 __le16 led_state_caps;
1626#define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
1627 cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1628
1629 __le16 led_color_caps;
1630};
1631
1632#define BNXT_MAX_TEST 8
1633
1634struct bnxt_test_info {
1635 u8 offline_mask;
1636 u16 timeout;
1637 char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1638};
1639
1640#define CHIMP_REG_VIEW_ADDR \
1641 ((bp->flags & BNXT_FLAG_CHIP_P5_PLUS) ? 0x80000000 : 0xb1000000)
1642
1643#define BNXT_GRCPF_REG_CHIMP_COMM 0x0
1644#define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
1645#define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
1646#define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014
1647#define BNXT_CAG_REG_BASE 0x300000
1648
1649#define BNXT_GRC_REG_STATUS_P5 0x520
1650
1651#define BNXT_GRCPF_REG_KONG_COMM 0xA00
1652#define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00
1653
1654#define BNXT_GRC_REG_CHIP_NUM 0x48
1655#define BNXT_GRC_REG_BASE 0x260000
1656
1657#define BNXT_TS_REG_TIMESYNC_TS0_LOWER 0x640180c
1658#define BNXT_TS_REG_TIMESYNC_TS0_UPPER 0x6401810
1659
1660#define BNXT_GRC_BASE_MASK 0xfffff000
1661#define BNXT_GRC_OFFSET_MASK 0x00000ffc
1662
1663struct bnxt_tc_flow_stats {
1664 u64 packets;
1665 u64 bytes;
1666};
1667
1668#ifdef CONFIG_BNXT_FLOWER_OFFLOAD
1669struct bnxt_flower_indr_block_cb_priv {
1670 struct net_device *tunnel_netdev;
1671 struct bnxt *bp;
1672 struct list_head list;
1673};
1674#endif
1675
1676struct bnxt_tc_info {
1677 bool enabled;
1678
1679 /* hash table to store TC offloaded flows */
1680 struct rhashtable flow_table;
1681 struct rhashtable_params flow_ht_params;
1682
1683 /* hash table to store L2 keys of TC flows */
1684 struct rhashtable l2_table;
1685 struct rhashtable_params l2_ht_params;
1686 /* hash table to store L2 keys for TC tunnel decap */
1687 struct rhashtable decap_l2_table;
1688 struct rhashtable_params decap_l2_ht_params;
1689 /* hash table to store tunnel decap entries */
1690 struct rhashtable decap_table;
1691 struct rhashtable_params decap_ht_params;
1692 /* hash table to store tunnel encap entries */
1693 struct rhashtable encap_table;
1694 struct rhashtable_params encap_ht_params;
1695
1696 /* lock to atomically add/del an l2 node when a flow is
1697 * added or deleted.
1698 */
1699 struct mutex lock;
1700
1701 /* Fields used for batching stats query */
1702 struct rhashtable_iter iter;
1703#define BNXT_FLOW_STATS_BATCH_MAX 10
1704 struct bnxt_tc_stats_batch {
1705 void *flow_node;
1706 struct bnxt_tc_flow_stats hw_stats;
1707 } stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1708
1709 /* Stat counter mask (width) */
1710 u64 bytes_mask;
1711 u64 packets_mask;
1712};
1713
1714struct bnxt_vf_rep_stats {
1715 u64 packets;
1716 u64 bytes;
1717 u64 dropped;
1718};
1719
1720struct bnxt_vf_rep {
1721 struct bnxt *bp;
1722 struct net_device *dev;
1723 struct metadata_dst *dst;
1724 u16 vf_idx;
1725 u16 tx_cfa_action;
1726 u16 rx_cfa_code;
1727
1728 struct bnxt_vf_rep_stats rx_stats;
1729 struct bnxt_vf_rep_stats tx_stats;
1730};
1731
1732#define PTU_PTE_VALID 0x1UL
1733#define PTU_PTE_LAST 0x2UL
1734#define PTU_PTE_NEXT_TO_LAST 0x4UL
1735
1736#define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
1737#define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES)
1738
1739struct bnxt_ctx_pg_info {
1740 u32 entries;
1741 u32 nr_pages;
1742 void *ctx_pg_arr[MAX_CTX_PAGES];
1743 dma_addr_t ctx_dma_arr[MAX_CTX_PAGES];
1744 struct bnxt_ring_mem_info ring_mem;
1745 struct bnxt_ctx_pg_info **ctx_pg_tbl;
1746};
1747
1748#define BNXT_MAX_TQM_SP_RINGS 1
1749#define BNXT_MAX_TQM_FP_RINGS 8
1750#define BNXT_MAX_TQM_RINGS \
1751 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
1752
1753#define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256
1754
1755#define BNXT_SET_CTX_PAGE_ATTR(attr) \
1756do { \
1757 if (BNXT_PAGE_SIZE == 0x2000) \
1758 attr = FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K; \
1759 else if (BNXT_PAGE_SIZE == 0x10000) \
1760 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K; \
1761 else \
1762 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K; \
1763} while (0)
1764
1765struct bnxt_ctx_mem_type {
1766 u16 type;
1767 u16 entry_size;
1768 u32 flags;
1769#define BNXT_CTX_MEM_TYPE_VALID FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID
1770 u32 instance_bmap;
1771 u8 init_value;
1772 u8 entry_multiple;
1773 u16 init_offset;
1774#define BNXT_CTX_INIT_INVALID_OFFSET 0xffff
1775 u32 max_entries;
1776 u32 min_entries;
1777 u8 last:1;
1778 u8 split_entry_cnt;
1779#define BNXT_MAX_SPLIT_ENTRY 4
1780 union {
1781 struct {
1782 u32 qp_l2_entries;
1783 u32 qp_qp1_entries;
1784 u32 qp_fast_qpmd_entries;
1785 };
1786 u32 srq_l2_entries;
1787 u32 cq_l2_entries;
1788 u32 vnic_entries;
1789 struct {
1790 u32 mrav_av_entries;
1791 u32 mrav_num_entries_units;
1792 };
1793 u32 split[BNXT_MAX_SPLIT_ENTRY];
1794 };
1795 struct bnxt_ctx_pg_info *pg_info;
1796};
1797
1798#define BNXT_CTX_MRAV_AV_SPLIT_ENTRY 0
1799
1800#define BNXT_CTX_QP FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP
1801#define BNXT_CTX_SRQ FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ
1802#define BNXT_CTX_CQ FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ
1803#define BNXT_CTX_VNIC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC
1804#define BNXT_CTX_STAT FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT
1805#define BNXT_CTX_STQM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING
1806#define BNXT_CTX_FTQM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING
1807#define BNXT_CTX_MRAV FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV
1808#define BNXT_CTX_TIM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM
1809#define BNXT_CTX_TKC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TKC
1810#define BNXT_CTX_RKC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RKC
1811#define BNXT_CTX_MTQM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING
1812#define BNXT_CTX_SQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW
1813#define BNXT_CTX_RQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW
1814#define BNXT_CTX_SRQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW
1815#define BNXT_CTX_CQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW
1816#define BNXT_CTX_QTKC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_TKC
1817#define BNXT_CTX_QRKC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_RKC
1818#define BNXT_CTX_TBLSC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TBL_SCOPE
1819#define BNXT_CTX_XPAR FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_XID_PARTITION
1820
1821#define BNXT_CTX_MAX (BNXT_CTX_TIM + 1)
1822#define BNXT_CTX_L2_MAX (BNXT_CTX_FTQM + 1)
1823#define BNXT_CTX_V2_MAX (BNXT_CTX_XPAR + 1)
1824#define BNXT_CTX_INV ((u16)-1)
1825
1826struct bnxt_ctx_mem_info {
1827 u8 tqm_fp_rings_count;
1828
1829 u32 flags;
1830 #define BNXT_CTX_FLAG_INITED 0x01
1831 struct bnxt_ctx_mem_type ctx_arr[BNXT_CTX_V2_MAX];
1832};
1833
1834enum bnxt_health_severity {
1835 SEVERITY_NORMAL = 0,
1836 SEVERITY_WARNING,
1837 SEVERITY_RECOVERABLE,
1838 SEVERITY_FATAL,
1839};
1840
1841enum bnxt_health_remedy {
1842 REMEDY_DEVLINK_RECOVER,
1843 REMEDY_POWER_CYCLE_DEVICE,
1844 REMEDY_POWER_CYCLE_HOST,
1845 REMEDY_FW_UPDATE,
1846 REMEDY_HW_REPLACE,
1847};
1848
1849struct bnxt_fw_health {
1850 u32 flags;
1851 u32 polling_dsecs;
1852 u32 master_func_wait_dsecs;
1853 u32 normal_func_wait_dsecs;
1854 u32 post_reset_wait_dsecs;
1855 u32 post_reset_max_wait_dsecs;
1856 u32 regs[4];
1857 u32 mapped_regs[4];
1858#define BNXT_FW_HEALTH_REG 0
1859#define BNXT_FW_HEARTBEAT_REG 1
1860#define BNXT_FW_RESET_CNT_REG 2
1861#define BNXT_FW_RESET_INPROG_REG 3
1862 u32 fw_reset_inprog_reg_mask;
1863 u32 last_fw_heartbeat;
1864 u32 last_fw_reset_cnt;
1865 u8 enabled:1;
1866 u8 primary:1;
1867 u8 status_reliable:1;
1868 u8 resets_reliable:1;
1869 u8 tmr_multiplier;
1870 u8 tmr_counter;
1871 u8 fw_reset_seq_cnt;
1872 u32 fw_reset_seq_regs[16];
1873 u32 fw_reset_seq_vals[16];
1874 u32 fw_reset_seq_delay_msec[16];
1875 u32 echo_req_data1;
1876 u32 echo_req_data2;
1877 struct devlink_health_reporter *fw_reporter;
1878 /* Protects severity and remedy */
1879 struct mutex lock;
1880 enum bnxt_health_severity severity;
1881 enum bnxt_health_remedy remedy;
1882 u32 arrests;
1883 u32 discoveries;
1884 u32 survivals;
1885 u32 fatalities;
1886 u32 diagnoses;
1887};
1888
1889#define BNXT_FW_HEALTH_REG_TYPE_MASK 3
1890#define BNXT_FW_HEALTH_REG_TYPE_CFG 0
1891#define BNXT_FW_HEALTH_REG_TYPE_GRC 1
1892#define BNXT_FW_HEALTH_REG_TYPE_BAR0 2
1893#define BNXT_FW_HEALTH_REG_TYPE_BAR1 3
1894
1895#define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
1896#define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
1897
1898#define BNXT_FW_HEALTH_WIN_BASE 0x3000
1899#define BNXT_FW_HEALTH_WIN_MAP_OFF 8
1900
1901#define BNXT_FW_HEALTH_WIN_OFF(reg) (BNXT_FW_HEALTH_WIN_BASE + \
1902 ((reg) & BNXT_GRC_OFFSET_MASK))
1903
1904#define BNXT_FW_STATUS_HEALTH_MSK 0xffff
1905#define BNXT_FW_STATUS_HEALTHY 0x8000
1906#define BNXT_FW_STATUS_SHUTDOWN 0x100000
1907#define BNXT_FW_STATUS_RECOVERING 0x400000
1908
1909#define BNXT_FW_IS_HEALTHY(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\
1910 BNXT_FW_STATUS_HEALTHY)
1911
1912#define BNXT_FW_IS_BOOTING(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \
1913 BNXT_FW_STATUS_HEALTHY)
1914
1915#define BNXT_FW_IS_ERR(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \
1916 BNXT_FW_STATUS_HEALTHY)
1917
1918#define BNXT_FW_IS_RECOVERING(sts) (BNXT_FW_IS_ERR(sts) && \
1919 ((sts) & BNXT_FW_STATUS_RECOVERING))
1920
1921#define BNXT_FW_RETRY 5
1922#define BNXT_FW_IF_RETRY 10
1923#define BNXT_FW_SLOT_RESET_RETRY 4
1924
1925struct bnxt_aux_priv {
1926 struct auxiliary_device aux_dev;
1927 struct bnxt_en_dev *edev;
1928 int id;
1929};
1930
1931enum board_idx {
1932 BCM57301,
1933 BCM57302,
1934 BCM57304,
1935 BCM57417_NPAR,
1936 BCM58700,
1937 BCM57311,
1938 BCM57312,
1939 BCM57402,
1940 BCM57404,
1941 BCM57406,
1942 BCM57402_NPAR,
1943 BCM57407,
1944 BCM57412,
1945 BCM57414,
1946 BCM57416,
1947 BCM57417,
1948 BCM57412_NPAR,
1949 BCM57314,
1950 BCM57417_SFP,
1951 BCM57416_SFP,
1952 BCM57404_NPAR,
1953 BCM57406_NPAR,
1954 BCM57407_SFP,
1955 BCM57407_NPAR,
1956 BCM57414_NPAR,
1957 BCM57416_NPAR,
1958 BCM57452,
1959 BCM57454,
1960 BCM5745x_NPAR,
1961 BCM57508,
1962 BCM57504,
1963 BCM57502,
1964 BCM57508_NPAR,
1965 BCM57504_NPAR,
1966 BCM57502_NPAR,
1967 BCM57608,
1968 BCM57604,
1969 BCM57602,
1970 BCM57601,
1971 BCM58802,
1972 BCM58804,
1973 BCM58808,
1974 NETXTREME_E_VF,
1975 NETXTREME_C_VF,
1976 NETXTREME_S_VF,
1977 NETXTREME_C_VF_HV,
1978 NETXTREME_E_VF_HV,
1979 NETXTREME_E_P5_VF,
1980 NETXTREME_E_P5_VF_HV,
1981};
1982
1983struct bnxt {
1984 void __iomem *bar0;
1985 void __iomem *bar1;
1986 void __iomem *bar2;
1987
1988 u32 reg_base;
1989 u16 chip_num;
1990#define CHIP_NUM_57301 0x16c8
1991#define CHIP_NUM_57302 0x16c9
1992#define CHIP_NUM_57304 0x16ca
1993#define CHIP_NUM_58700 0x16cd
1994#define CHIP_NUM_57402 0x16d0
1995#define CHIP_NUM_57404 0x16d1
1996#define CHIP_NUM_57406 0x16d2
1997#define CHIP_NUM_57407 0x16d5
1998
1999#define CHIP_NUM_57311 0x16ce
2000#define CHIP_NUM_57312 0x16cf
2001#define CHIP_NUM_57314 0x16df
2002#define CHIP_NUM_57317 0x16e0
2003#define CHIP_NUM_57412 0x16d6
2004#define CHIP_NUM_57414 0x16d7
2005#define CHIP_NUM_57416 0x16d8
2006#define CHIP_NUM_57417 0x16d9
2007#define CHIP_NUM_57412L 0x16da
2008#define CHIP_NUM_57414L 0x16db
2009
2010#define CHIP_NUM_5745X 0xd730
2011#define CHIP_NUM_57452 0xc452
2012#define CHIP_NUM_57454 0xc454
2013
2014#define CHIP_NUM_57508 0x1750
2015#define CHIP_NUM_57504 0x1751
2016#define CHIP_NUM_57502 0x1752
2017
2018#define CHIP_NUM_57608 0x1760
2019
2020#define CHIP_NUM_58802 0xd802
2021#define CHIP_NUM_58804 0xd804
2022#define CHIP_NUM_58808 0xd808
2023
2024 u8 chip_rev;
2025
2026#define BNXT_CHIP_NUM_5730X(chip_num) \
2027 ((chip_num) >= CHIP_NUM_57301 && \
2028 (chip_num) <= CHIP_NUM_57304)
2029
2030#define BNXT_CHIP_NUM_5740X(chip_num) \
2031 (((chip_num) >= CHIP_NUM_57402 && \
2032 (chip_num) <= CHIP_NUM_57406) || \
2033 (chip_num) == CHIP_NUM_57407)
2034
2035#define BNXT_CHIP_NUM_5731X(chip_num) \
2036 ((chip_num) == CHIP_NUM_57311 || \
2037 (chip_num) == CHIP_NUM_57312 || \
2038 (chip_num) == CHIP_NUM_57314 || \
2039 (chip_num) == CHIP_NUM_57317)
2040
2041#define BNXT_CHIP_NUM_5741X(chip_num) \
2042 ((chip_num) >= CHIP_NUM_57412 && \
2043 (chip_num) <= CHIP_NUM_57414L)
2044
2045#define BNXT_CHIP_NUM_58700(chip_num) \
2046 ((chip_num) == CHIP_NUM_58700)
2047
2048#define BNXT_CHIP_NUM_5745X(chip_num) \
2049 ((chip_num) == CHIP_NUM_5745X || \
2050 (chip_num) == CHIP_NUM_57452 || \
2051 (chip_num) == CHIP_NUM_57454)
2052
2053
2054#define BNXT_CHIP_NUM_57X0X(chip_num) \
2055 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
2056
2057#define BNXT_CHIP_NUM_57X1X(chip_num) \
2058 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
2059
2060#define BNXT_CHIP_NUM_588XX(chip_num) \
2061 ((chip_num) == CHIP_NUM_58802 || \
2062 (chip_num) == CHIP_NUM_58804 || \
2063 (chip_num) == CHIP_NUM_58808)
2064
2065#define BNXT_VPD_FLD_LEN 32
2066 char board_partno[BNXT_VPD_FLD_LEN];
2067 char board_serialno[BNXT_VPD_FLD_LEN];
2068
2069 struct net_device *dev;
2070 struct pci_dev *pdev;
2071
2072 atomic_t intr_sem;
2073
2074 u32 flags;
2075 #define BNXT_FLAG_CHIP_P5_PLUS 0x1
2076 #define BNXT_FLAG_VF 0x2
2077 #define BNXT_FLAG_LRO 0x4
2078#ifdef CONFIG_INET
2079 #define BNXT_FLAG_GRO 0x8
2080#else
2081 /* Cannot support hardware GRO if CONFIG_INET is not set */
2082 #define BNXT_FLAG_GRO 0x0
2083#endif
2084 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
2085 #define BNXT_FLAG_JUMBO 0x10
2086 #define BNXT_FLAG_STRIP_VLAN 0x20
2087 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
2088 BNXT_FLAG_LRO)
2089 #define BNXT_FLAG_USING_MSIX 0x40
2090 #define BNXT_FLAG_MSIX_CAP 0x80
2091 #define BNXT_FLAG_RFS 0x100
2092 #define BNXT_FLAG_SHARED_RINGS 0x200
2093 #define BNXT_FLAG_PORT_STATS 0x400
2094 #define BNXT_FLAG_WOL_CAP 0x4000
2095 #define BNXT_FLAG_ROCEV1_CAP 0x8000
2096 #define BNXT_FLAG_ROCEV2_CAP 0x10000
2097 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \
2098 BNXT_FLAG_ROCEV2_CAP)
2099 #define BNXT_FLAG_NO_AGG_RINGS 0x20000
2100 #define BNXT_FLAG_RX_PAGE_MODE 0x40000
2101 #define BNXT_FLAG_CHIP_P7 0x80000
2102 #define BNXT_FLAG_MULTI_HOST 0x100000
2103 #define BNXT_FLAG_DSN_VALID 0x200000
2104 #define BNXT_FLAG_DOUBLE_DB 0x400000
2105 #define BNXT_FLAG_UDP_GSO_CAP 0x800000
2106 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
2107 #define BNXT_FLAG_DIM 0x2000000
2108 #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000
2109 #define BNXT_FLAG_TX_COAL_CMPL 0x8000000
2110 #define BNXT_FLAG_PORT_STATS_EXT 0x10000000
2111
2112 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \
2113 BNXT_FLAG_RFS | \
2114 BNXT_FLAG_STRIP_VLAN)
2115
2116#define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
2117#define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
2118#define BNXT_NPAR(bp) ((bp)->port_partition_type)
2119#define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
2120#define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
2121#define BNXT_SH_PORT_CFG_OK(bp) (BNXT_PF(bp) && \
2122 ((bp)->phy_flags & BNXT_PHY_FL_SHARED_PORT_CFG))
2123#define BNXT_PHY_CFG_ABLE(bp) ((BNXT_SINGLE_PF(bp) || \
2124 BNXT_SH_PORT_CFG_OK(bp)) && \
2125 (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED)
2126#define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
2127#define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
2128#define BNXT_SUPPORTS_TPA(bp) (!BNXT_CHIP_TYPE_NITRO_A0(bp) && \
2129 (!((bp)->flags & BNXT_FLAG_CHIP_P5_PLUS) ||\
2130 (bp)->max_tpa_v2) && !is_kdump_kernel())
2131#define BNXT_RX_JUMBO_MODE(bp) ((bp)->flags & BNXT_FLAG_JUMBO)
2132
2133#define BNXT_CHIP_P7(bp) \
2134 ((bp)->chip_num == CHIP_NUM_57608)
2135
2136#define BNXT_CHIP_P5(bp) \
2137 ((bp)->chip_num == CHIP_NUM_57508 || \
2138 (bp)->chip_num == CHIP_NUM_57504 || \
2139 (bp)->chip_num == CHIP_NUM_57502)
2140
2141/* Chip class phase 5 */
2142#define BNXT_CHIP_P5_PLUS(bp) \
2143 (BNXT_CHIP_P5(bp) || BNXT_CHIP_P7(bp))
2144
2145/* Chip class phase 4.x */
2146#define BNXT_CHIP_P4(bp) \
2147 (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
2148 BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
2149 BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
2150 (BNXT_CHIP_NUM_58700((bp)->chip_num) && \
2151 !BNXT_CHIP_TYPE_NITRO_A0(bp)))
2152
2153#define BNXT_CHIP_P4_PLUS(bp) \
2154 (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5_PLUS(bp))
2155
2156 struct bnxt_aux_priv *aux_priv;
2157 struct bnxt_en_dev *edev;
2158
2159 struct bnxt_napi **bnapi;
2160
2161 struct bnxt_rx_ring_info *rx_ring;
2162 struct bnxt_tx_ring_info *tx_ring;
2163 u16 *tx_ring_map;
2164
2165 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int,
2166 struct sk_buff *);
2167
2168 struct sk_buff * (*rx_skb_func)(struct bnxt *,
2169 struct bnxt_rx_ring_info *,
2170 u16, void *, u8 *, dma_addr_t,
2171 unsigned int);
2172
2173 u16 max_tpa_v2;
2174 u16 max_tpa;
2175 u32 rx_buf_size;
2176 u32 rx_buf_use_size; /* useable size */
2177 u16 rx_offset;
2178 u16 rx_dma_offset;
2179 enum dma_data_direction rx_dir;
2180 u32 rx_ring_size;
2181 u32 rx_agg_ring_size;
2182 u32 rx_copy_thresh;
2183 u32 rx_ring_mask;
2184 u32 rx_agg_ring_mask;
2185 int rx_nr_pages;
2186 int rx_agg_nr_pages;
2187 int rx_nr_rings;
2188 int rsscos_nr_ctxs;
2189
2190 u32 tx_ring_size;
2191 u32 tx_ring_mask;
2192 int tx_nr_pages;
2193 int tx_nr_rings;
2194 int tx_nr_rings_per_tc;
2195 int tx_nr_rings_xdp;
2196
2197 int tx_wake_thresh;
2198 int tx_push_thresh;
2199 int tx_push_size;
2200
2201 u32 cp_ring_size;
2202 u32 cp_ring_mask;
2203 u32 cp_bit;
2204 int cp_nr_pages;
2205 int cp_nr_rings;
2206
2207 /* grp_info indexed by completion ring index */
2208 struct bnxt_ring_grp_info *grp_info;
2209 struct bnxt_vnic_info *vnic_info;
2210 int nr_vnics;
2211 u16 *rss_indir_tbl;
2212 u16 rss_indir_tbl_entries;
2213 u32 rss_hash_cfg;
2214 u32 rss_hash_delta;
2215 u32 rss_cap;
2216#define BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA BIT(0)
2217#define BNXT_RSS_CAP_UDP_RSS_CAP BIT(1)
2218#define BNXT_RSS_CAP_NEW_RSS_CAP BIT(2)
2219#define BNXT_RSS_CAP_RSS_TCAM BIT(3)
2220
2221 u16 max_mtu;
2222 u8 max_tc;
2223 u8 max_lltc; /* lossless TCs */
2224 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE];
2225 u8 tc_to_qidx[BNXT_MAX_QUEUE];
2226 u8 q_ids[BNXT_MAX_QUEUE];
2227 u8 max_q;
2228 u8 num_tc;
2229
2230 unsigned int current_interval;
2231#define BNXT_TIMER_INTERVAL HZ
2232
2233 struct timer_list timer;
2234
2235 unsigned long state;
2236#define BNXT_STATE_OPEN 0
2237#define BNXT_STATE_IN_SP_TASK 1
2238#define BNXT_STATE_READ_STATS 2
2239#define BNXT_STATE_FW_RESET_DET 3
2240#define BNXT_STATE_IN_FW_RESET 4
2241#define BNXT_STATE_ABORT_ERR 5
2242#define BNXT_STATE_FW_FATAL_COND 6
2243#define BNXT_STATE_DRV_REGISTERED 7
2244#define BNXT_STATE_PCI_CHANNEL_IO_FROZEN 8
2245#define BNXT_STATE_NAPI_DISABLED 9
2246#define BNXT_STATE_L2_FILTER_RETRY 10
2247#define BNXT_STATE_FW_ACTIVATE 11
2248#define BNXT_STATE_RECOVER 12
2249#define BNXT_STATE_FW_NON_FATAL_COND 13
2250#define BNXT_STATE_FW_ACTIVATE_RESET 14
2251#define BNXT_STATE_HALF_OPEN 15 /* For offline ethtool tests */
2252
2253#define BNXT_NO_FW_ACCESS(bp) \
2254 (test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) || \
2255 pci_channel_offline((bp)->pdev))
2256
2257 struct bnxt_irq *irq_tbl;
2258 int total_irqs;
2259 u8 mac_addr[ETH_ALEN];
2260
2261#ifdef CONFIG_BNXT_DCB
2262 struct ieee_pfc *ieee_pfc;
2263 struct ieee_ets *ieee_ets;
2264 u8 dcbx_cap;
2265 u8 default_pri;
2266 u8 max_dscp_value;
2267#endif /* CONFIG_BNXT_DCB */
2268
2269 u32 msg_enable;
2270
2271 u64 fw_cap;
2272 #define BNXT_FW_CAP_SHORT_CMD BIT_ULL(0)
2273 #define BNXT_FW_CAP_LLDP_AGENT BIT_ULL(1)
2274 #define BNXT_FW_CAP_DCBX_AGENT BIT_ULL(2)
2275 #define BNXT_FW_CAP_NEW_RM BIT_ULL(3)
2276 #define BNXT_FW_CAP_IF_CHANGE BIT_ULL(4)
2277 #define BNXT_FW_CAP_KONG_MB_CHNL BIT_ULL(7)
2278 #define BNXT_FW_CAP_OVS_64BIT_HANDLE BIT_ULL(10)
2279 #define BNXT_FW_CAP_TRUSTED_VF BIT_ULL(11)
2280 #define BNXT_FW_CAP_ERROR_RECOVERY BIT_ULL(13)
2281 #define BNXT_FW_CAP_PKG_VER BIT_ULL(14)
2282 #define BNXT_FW_CAP_CFA_ADV_FLOW BIT_ULL(15)
2283 #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 BIT_ULL(16)
2284 #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED BIT_ULL(17)
2285 #define BNXT_FW_CAP_EXT_STATS_SUPPORTED BIT_ULL(18)
2286 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT_ULL(20)
2287 #define BNXT_FW_CAP_HOT_RESET BIT_ULL(21)
2288 #define BNXT_FW_CAP_PTP_RTC BIT_ULL(22)
2289 #define BNXT_FW_CAP_RX_ALL_PKT_TS BIT_ULL(23)
2290 #define BNXT_FW_CAP_VLAN_RX_STRIP BIT_ULL(24)
2291 #define BNXT_FW_CAP_VLAN_TX_INSERT BIT_ULL(25)
2292 #define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED BIT_ULL(26)
2293 #define BNXT_FW_CAP_LIVEPATCH BIT_ULL(27)
2294 #define BNXT_FW_CAP_PTP_PPS BIT_ULL(28)
2295 #define BNXT_FW_CAP_HOT_RESET_IF BIT_ULL(29)
2296 #define BNXT_FW_CAP_RING_MONITOR BIT_ULL(30)
2297 #define BNXT_FW_CAP_DBG_QCAPS BIT_ULL(31)
2298 #define BNXT_FW_CAP_PTP BIT_ULL(32)
2299 #define BNXT_FW_CAP_THRESHOLD_TEMP_SUPPORTED BIT_ULL(33)
2300 #define BNXT_FW_CAP_DFLT_VLAN_TPID_PCP BIT_ULL(34)
2301 #define BNXT_FW_CAP_PRE_RESV_VNICS BIT_ULL(35)
2302 #define BNXT_FW_CAP_BACKING_STORE_V2 BIT_ULL(36)
2303 #define BNXT_FW_CAP_VNIC_TUNNEL_TPA BIT_ULL(37)
2304
2305 u32 fw_dbg_cap;
2306
2307#define BNXT_NEW_RM(bp) ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
2308#define BNXT_PTP_USE_RTC(bp) (!BNXT_MH(bp) && \
2309 ((bp)->fw_cap & BNXT_FW_CAP_PTP_RTC))
2310 u32 hwrm_spec_code;
2311 u16 hwrm_cmd_seq;
2312 u16 hwrm_cmd_kong_seq;
2313 struct dma_pool *hwrm_dma_pool;
2314 struct hlist_head hwrm_pending_list;
2315
2316 struct rtnl_link_stats64 net_stats_prev;
2317 struct bnxt_stats_mem port_stats;
2318 struct bnxt_stats_mem rx_port_stats_ext;
2319 struct bnxt_stats_mem tx_port_stats_ext;
2320 u16 fw_rx_stats_ext_size;
2321 u16 fw_tx_stats_ext_size;
2322 u16 hw_ring_stats_size;
2323 u8 pri2cos_idx[8];
2324 u8 pri2cos_valid;
2325
2326 struct bnxt_total_ring_err_stats ring_err_stats_prev;
2327
2328 u16 hwrm_max_req_len;
2329 u16 hwrm_max_ext_req_len;
2330 unsigned int hwrm_cmd_timeout;
2331 unsigned int hwrm_cmd_max_timeout;
2332 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */
2333 struct hwrm_ver_get_output ver_resp;
2334#define FW_VER_STR_LEN 32
2335#define BC_HWRM_STR_LEN 21
2336#define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
2337 char fw_ver_str[FW_VER_STR_LEN];
2338 char hwrm_ver_supp[FW_VER_STR_LEN];
2339 char nvm_cfg_ver[FW_VER_STR_LEN];
2340 u64 fw_ver_code;
2341#define BNXT_FW_VER_CODE(maj, min, bld, rsv) \
2342 ((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv))
2343#define BNXT_FW_MAJ(bp) ((bp)->fw_ver_code >> 48)
2344#define BNXT_FW_BLD(bp) (((bp)->fw_ver_code >> 16) & 0xffff)
2345
2346 u16 vxlan_fw_dst_port_id;
2347 u16 nge_fw_dst_port_id;
2348 u16 vxlan_gpe_fw_dst_port_id;
2349 __be16 vxlan_port;
2350 __be16 nge_port;
2351 __be16 vxlan_gpe_port;
2352 u8 port_partition_type;
2353 u8 port_count;
2354 u16 br_mode;
2355
2356 struct bnxt_coal_cap coal_cap;
2357 struct bnxt_coal rx_coal;
2358 struct bnxt_coal tx_coal;
2359
2360 u32 stats_coal_ticks;
2361#define BNXT_DEF_STATS_COAL_TICKS 1000000
2362#define BNXT_MIN_STATS_COAL_TICKS 250000
2363#define BNXT_MAX_STATS_COAL_TICKS 1000000
2364
2365 struct work_struct sp_task;
2366 unsigned long sp_event;
2367#define BNXT_RX_MASK_SP_EVENT 0
2368#define BNXT_RX_NTP_FLTR_SP_EVENT 1
2369#define BNXT_LINK_CHNG_SP_EVENT 2
2370#define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
2371#define BNXT_RESET_TASK_SP_EVENT 6
2372#define BNXT_RST_RING_SP_EVENT 7
2373#define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8
2374#define BNXT_PERIODIC_STATS_SP_EVENT 9
2375#define BNXT_HWRM_PORT_MODULE_SP_EVENT 10
2376#define BNXT_RESET_TASK_SILENT_SP_EVENT 11
2377#define BNXT_LINK_SPEED_CHNG_SP_EVENT 14
2378#define BNXT_FLOW_STATS_SP_EVENT 15
2379#define BNXT_UPDATE_PHY_SP_EVENT 16
2380#define BNXT_RING_COAL_NOW_SP_EVENT 17
2381#define BNXT_FW_RESET_NOTIFY_SP_EVENT 18
2382#define BNXT_FW_EXCEPTION_SP_EVENT 19
2383#define BNXT_LINK_CFG_CHANGE_SP_EVENT 21
2384#define BNXT_THERMAL_THRESHOLD_SP_EVENT 22
2385#define BNXT_FW_ECHO_REQUEST_SP_EVENT 23
2386
2387 struct delayed_work fw_reset_task;
2388 int fw_reset_state;
2389#define BNXT_FW_RESET_STATE_POLL_VF 1
2390#define BNXT_FW_RESET_STATE_RESET_FW 2
2391#define BNXT_FW_RESET_STATE_ENABLE_DEV 3
2392#define BNXT_FW_RESET_STATE_POLL_FW 4
2393#define BNXT_FW_RESET_STATE_OPENING 5
2394#define BNXT_FW_RESET_STATE_POLL_FW_DOWN 6
2395
2396 u16 fw_reset_min_dsecs;
2397#define BNXT_DFLT_FW_RST_MIN_DSECS 20
2398 u16 fw_reset_max_dsecs;
2399#define BNXT_DFLT_FW_RST_MAX_DSECS 60
2400 unsigned long fw_reset_timestamp;
2401
2402 struct bnxt_fw_health *fw_health;
2403
2404 struct bnxt_hw_resc hw_resc;
2405 struct bnxt_pf_info pf;
2406 struct bnxt_ctx_mem_info *ctx;
2407#ifdef CONFIG_BNXT_SRIOV
2408 int nr_vfs;
2409 struct bnxt_vf_info vf;
2410 wait_queue_head_t sriov_cfg_wait;
2411 bool sriov_cfg;
2412#define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
2413#endif
2414
2415#if BITS_PER_LONG == 32
2416 /* ensure atomic 64-bit doorbell writes on 32-bit systems. */
2417 spinlock_t db_lock;
2418#endif
2419 int db_offset; /* db_offset within db_size */
2420 int db_size;
2421
2422#define BNXT_NTP_FLTR_MAX_FLTR 4096
2423#define BNXT_MAX_FLTR (BNXT_NTP_FLTR_MAX_FLTR + BNXT_L2_FLTR_MAX_FLTR)
2424#define BNXT_NTP_FLTR_HASH_SIZE 512
2425#define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
2426 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
2427 spinlock_t ntp_fltr_lock; /* for hash table add, del */
2428
2429 unsigned long *ntp_fltr_bmap;
2430 int ntp_fltr_count;
2431
2432#define BNXT_L2_FLTR_MAX_FLTR 1024
2433#define BNXT_L2_FLTR_HASH_SIZE 32
2434#define BNXT_L2_FLTR_HASH_MASK (BNXT_L2_FLTR_HASH_SIZE - 1)
2435 struct hlist_head l2_fltr_hash_tbl[BNXT_L2_FLTR_HASH_SIZE];
2436
2437 u32 hash_seed;
2438 u64 toeplitz_prefix;
2439
2440 /* To protect link related settings during link changes and
2441 * ethtool settings changes.
2442 */
2443 struct mutex link_lock;
2444 struct bnxt_link_info link_info;
2445 struct ethtool_eee eee;
2446 u32 lpi_tmr_lo;
2447 u32 lpi_tmr_hi;
2448
2449 /* copied from flags and flags2 in hwrm_port_phy_qcaps_output */
2450 u32 phy_flags;
2451#define BNXT_PHY_FL_EEE_CAP PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED
2452#define BNXT_PHY_FL_EXT_LPBK PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED
2453#define BNXT_PHY_FL_AN_PHY_LPBK PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED
2454#define BNXT_PHY_FL_SHARED_PORT_CFG PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED
2455#define BNXT_PHY_FL_PORT_STATS_NO_RESET PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET
2456#define BNXT_PHY_FL_NO_PHY_LPBK PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED
2457#define BNXT_PHY_FL_FW_MANAGED_LKDN PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN
2458#define BNXT_PHY_FL_NO_FCS PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS
2459#define BNXT_PHY_FL_NO_PAUSE (PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED << 8)
2460#define BNXT_PHY_FL_NO_PFC (PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED << 8)
2461#define BNXT_PHY_FL_BANK_SEL (PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED << 8)
2462#define BNXT_PHY_FL_SPEEDS2 (PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED << 8)
2463
2464 u8 num_tests;
2465 struct bnxt_test_info *test_info;
2466
2467 u8 wol_filter_id;
2468 u8 wol;
2469
2470 u8 num_leds;
2471 struct bnxt_led_info leds[BNXT_MAX_LED];
2472 u16 dump_flag;
2473#define BNXT_DUMP_LIVE 0
2474#define BNXT_DUMP_CRASH 1
2475
2476 struct bpf_prog *xdp_prog;
2477
2478 struct bnxt_ptp_cfg *ptp_cfg;
2479 u8 ptp_all_rx_tstamp;
2480
2481 /* devlink interface and vf-rep structs */
2482 struct devlink *dl;
2483 struct devlink_port dl_port;
2484 enum devlink_eswitch_mode eswitch_mode;
2485 struct bnxt_vf_rep **vf_reps; /* array of vf-rep ptrs */
2486 u16 *cfa_code_map; /* cfa_code -> vf_idx map */
2487 u8 dsn[8];
2488 struct bnxt_tc_info *tc_info;
2489 struct list_head tc_indr_block_list;
2490 struct dentry *debugfs_pdev;
2491#ifdef CONFIG_BNXT_HWMON
2492 struct device *hwmon_dev;
2493 u8 warn_thresh_temp;
2494 u8 crit_thresh_temp;
2495 u8 fatal_thresh_temp;
2496 u8 shutdown_thresh_temp;
2497#endif
2498 u32 thermal_threshold_type;
2499 enum board_idx board_idx;
2500};
2501
2502#define BNXT_NUM_RX_RING_STATS 8
2503#define BNXT_NUM_TX_RING_STATS 8
2504#define BNXT_NUM_TPA_RING_STATS 4
2505#define BNXT_NUM_TPA_RING_STATS_P5 5
2506#define BNXT_NUM_TPA_RING_STATS_P7 6
2507
2508#define BNXT_RING_STATS_SIZE_P5 \
2509 ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \
2510 BNXT_NUM_TPA_RING_STATS_P5) * 8)
2511
2512#define BNXT_RING_STATS_SIZE_P7 \
2513 ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \
2514 BNXT_NUM_TPA_RING_STATS_P7) * 8)
2515
2516#define BNXT_GET_RING_STATS64(sw, counter) \
2517 (*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))
2518
2519#define BNXT_GET_RX_PORT_STATS64(sw, counter) \
2520 (*((sw) + offsetof(struct rx_port_stats, counter) / 8))
2521
2522#define BNXT_GET_TX_PORT_STATS64(sw, counter) \
2523 (*((sw) + offsetof(struct tx_port_stats, counter) / 8))
2524
2525#define BNXT_PORT_STATS_SIZE \
2526 (sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024)
2527
2528#define BNXT_TX_PORT_STATS_BYTE_OFFSET \
2529 (sizeof(struct rx_port_stats) + 512)
2530
2531#define BNXT_RX_STATS_OFFSET(counter) \
2532 (offsetof(struct rx_port_stats, counter) / 8)
2533
2534#define BNXT_TX_STATS_OFFSET(counter) \
2535 ((offsetof(struct tx_port_stats, counter) + \
2536 BNXT_TX_PORT_STATS_BYTE_OFFSET) / 8)
2537
2538#define BNXT_RX_STATS_EXT_OFFSET(counter) \
2539 (offsetof(struct rx_port_stats_ext, counter) / 8)
2540
2541#define BNXT_RX_STATS_EXT_NUM_LEGACY \
2542 BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)
2543
2544#define BNXT_TX_STATS_EXT_OFFSET(counter) \
2545 (offsetof(struct tx_port_stats_ext, counter) / 8)
2546
2547#define BNXT_HW_FEATURE_VLAN_ALL_RX \
2548 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)
2549#define BNXT_HW_FEATURE_VLAN_ALL_TX \
2550 (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX)
2551
2552#define I2C_DEV_ADDR_A0 0xa0
2553#define I2C_DEV_ADDR_A2 0xa2
2554#define SFF_DIAG_SUPPORT_OFFSET 0x5c
2555#define SFF_MODULE_ID_SFP 0x3
2556#define SFF_MODULE_ID_QSFP 0xc
2557#define SFF_MODULE_ID_QSFP_PLUS 0xd
2558#define SFF_MODULE_ID_QSFP28 0x11
2559#define BNXT_MAX_PHY_I2C_RESP_SIZE 64
2560
2561static inline u32 bnxt_tx_avail(struct bnxt *bp,
2562 const struct bnxt_tx_ring_info *txr)
2563{
2564 u32 used = READ_ONCE(txr->tx_prod) - READ_ONCE(txr->tx_cons);
2565
2566 return bp->tx_ring_size - (used & bp->tx_ring_mask);
2567}
2568
2569static inline void bnxt_writeq(struct bnxt *bp, u64 val,
2570 volatile void __iomem *addr)
2571{
2572#if BITS_PER_LONG == 32
2573 spin_lock(&bp->db_lock);
2574 lo_hi_writeq(val, addr);
2575 spin_unlock(&bp->db_lock);
2576#else
2577 writeq(val, addr);
2578#endif
2579}
2580
2581static inline void bnxt_writeq_relaxed(struct bnxt *bp, u64 val,
2582 volatile void __iomem *addr)
2583{
2584#if BITS_PER_LONG == 32
2585 spin_lock(&bp->db_lock);
2586 lo_hi_writeq_relaxed(val, addr);
2587 spin_unlock(&bp->db_lock);
2588#else
2589 writeq_relaxed(val, addr);
2590#endif
2591}
2592
2593/* For TX and RX ring doorbells with no ordering guarantee*/
2594static inline void bnxt_db_write_relaxed(struct bnxt *bp,
2595 struct bnxt_db_info *db, u32 idx)
2596{
2597 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
2598 bnxt_writeq_relaxed(bp, db->db_key64 | DB_RING_IDX(db, idx),
2599 db->doorbell);
2600 } else {
2601 u32 db_val = db->db_key32 | DB_RING_IDX(db, idx);
2602
2603 writel_relaxed(db_val, db->doorbell);
2604 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2605 writel_relaxed(db_val, db->doorbell);
2606 }
2607}
2608
2609/* For TX and RX ring doorbells */
2610static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
2611 u32 idx)
2612{
2613 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
2614 bnxt_writeq(bp, db->db_key64 | DB_RING_IDX(db, idx),
2615 db->doorbell);
2616 } else {
2617 u32 db_val = db->db_key32 | DB_RING_IDX(db, idx);
2618
2619 writel(db_val, db->doorbell);
2620 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2621 writel(db_val, db->doorbell);
2622 }
2623}
2624
2625/* Must hold rtnl_lock */
2626static inline bool bnxt_sriov_cfg(struct bnxt *bp)
2627{
2628#if defined(CONFIG_BNXT_SRIOV)
2629 return BNXT_PF(bp) && (bp->pf.active_vfs || bp->sriov_cfg);
2630#else
2631 return false;
2632#endif
2633}
2634
2635extern const u16 bnxt_lhint_arr[];
2636
2637int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
2638 u16 prod, gfp_t gfp);
2639void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
2640u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);
2641void bnxt_set_tpa_flags(struct bnxt *bp);
2642void bnxt_set_ring_params(struct bnxt *);
2643int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
2644int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap,
2645 int bmap_size, bool async_only);
2646int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp);
2647void bnxt_del_l2_filter(struct bnxt *bp, struct bnxt_l2_filter *fltr);
2648int bnxt_hwrm_l2_filter_free(struct bnxt *bp, struct bnxt_l2_filter *fltr);
2649int bnxt_hwrm_l2_filter_alloc(struct bnxt *bp, struct bnxt_l2_filter *fltr);
2650int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
2651 struct bnxt_ntuple_filter *fltr);
2652int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
2653 struct bnxt_ntuple_filter *fltr);
2654void bnxt_fill_ipv6_mask(__be32 mask[4]);
2655int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings);
2656int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
2657int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
2658int bnxt_nq_rings_in_use(struct bnxt *bp);
2659int bnxt_hwrm_set_coal(struct bnxt *);
2660void bnxt_free_ctx_mem(struct bnxt *bp);
2661int bnxt_num_tx_to_cp(struct bnxt *bp, int tx);
2662unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
2663unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
2664unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
2665unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
2666int bnxt_get_avail_msix(struct bnxt *bp, int num);
2667int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
2668void bnxt_tx_disable(struct bnxt *bp);
2669void bnxt_tx_enable(struct bnxt *bp);
2670void bnxt_sched_reset_txr(struct bnxt *bp, struct bnxt_tx_ring_info *txr,
2671 u16 curr);
2672void bnxt_report_link(struct bnxt *bp);
2673int bnxt_update_link(struct bnxt *bp, bool chng_link_state);
2674int bnxt_hwrm_set_pause(struct bnxt *);
2675int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
2676int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset);
2677int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
2678int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
2679int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
2680int bnxt_hwrm_func_qcaps(struct bnxt *bp);
2681int bnxt_hwrm_fw_set_time(struct bnxt *);
2682int bnxt_open_nic(struct bnxt *, bool, bool);
2683int bnxt_half_open_nic(struct bnxt *bp);
2684void bnxt_half_close_nic(struct bnxt *bp);
2685void bnxt_reenable_sriov(struct bnxt *bp);
2686void bnxt_close_nic(struct bnxt *, bool, bool);
2687void bnxt_get_ring_err_stats(struct bnxt *bp,
2688 struct bnxt_total_ring_err_stats *stats);
2689int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
2690 u32 *reg_buf);
2691void bnxt_fw_exception(struct bnxt *bp);
2692void bnxt_fw_reset(struct bnxt *bp);
2693int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
2694 int tx_xdp);
2695int bnxt_fw_init_one(struct bnxt *bp);
2696bool bnxt_hwrm_reset_permitted(struct bnxt *bp);
2697int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
2698struct bnxt_ntuple_filter *bnxt_lookup_ntp_filter_from_idx(struct bnxt *bp,
2699 struct bnxt_ntuple_filter *fltr, u32 idx);
2700u32 bnxt_get_ntp_filter_idx(struct bnxt *bp, struct flow_keys *fkeys,
2701 const struct sk_buff *skb);
2702int bnxt_insert_ntp_filter(struct bnxt *bp, struct bnxt_ntuple_filter *fltr,
2703 u32 idx);
2704void bnxt_del_ntp_filter(struct bnxt *bp, struct bnxt_ntuple_filter *fltr);
2705int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
2706int bnxt_restore_pf_fw_resources(struct bnxt *bp);
2707int bnxt_get_port_parent_id(struct net_device *dev,
2708 struct netdev_phys_item_id *ppid);
2709void bnxt_dim_work(struct work_struct *work);
2710int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);
2711void bnxt_print_device_info(struct bnxt *bp);
2712#endif
1/* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2018 Broadcom Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
11#ifndef BNXT_H
12#define BNXT_H
13
14#define DRV_MODULE_NAME "bnxt_en"
15
16/* DO NOT CHANGE DRV_VER_* defines
17 * FIXME: Delete them
18 */
19#define DRV_VER_MAJ 1
20#define DRV_VER_MIN 10
21#define DRV_VER_UPD 2
22
23#include <linux/ethtool.h>
24#include <linux/interrupt.h>
25#include <linux/rhashtable.h>
26#include <linux/crash_dump.h>
27#include <net/devlink.h>
28#include <net/dst_metadata.h>
29#include <net/xdp.h>
30#include <linux/dim.h>
31#include <linux/io-64-nonatomic-lo-hi.h>
32#ifdef CONFIG_TEE_BNXT_FW
33#include <linux/firmware/broadcom/tee_bnxt_fw.h>
34#endif
35
36extern struct list_head bnxt_block_cb_list;
37
38struct page_pool;
39
40struct tx_bd {
41 __le32 tx_bd_len_flags_type;
42 #define TX_BD_TYPE (0x3f << 0)
43 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)
44 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)
45 #define TX_BD_FLAGS_PACKET_END (1 << 6)
46 #define TX_BD_FLAGS_NO_CMPL (1 << 7)
47 #define TX_BD_FLAGS_BD_CNT (0x1f << 8)
48 #define TX_BD_FLAGS_BD_CNT_SHIFT 8
49 #define TX_BD_FLAGS_LHINT (3 << 13)
50 #define TX_BD_FLAGS_LHINT_SHIFT 13
51 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)
52 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13)
53 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13)
54 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13)
55 #define TX_BD_FLAGS_COAL_NOW (1 << 15)
56 #define TX_BD_LEN (0xffff << 16)
57 #define TX_BD_LEN_SHIFT 16
58
59 u32 tx_bd_opaque;
60 __le64 tx_bd_haddr;
61} __packed;
62
63struct tx_bd_ext {
64 __le32 tx_bd_hsize_lflags;
65 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)
66 #define TX_BD_FLAGS_IP_CKSUM (1 << 1)
67 #define TX_BD_FLAGS_NO_CRC (1 << 2)
68 #define TX_BD_FLAGS_STAMP (1 << 3)
69 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4)
70 #define TX_BD_FLAGS_LSO (1 << 5)
71 #define TX_BD_FLAGS_IPID_FMT (1 << 6)
72 #define TX_BD_FLAGS_T_IPID (1 << 7)
73 #define TX_BD_HSIZE (0xff << 16)
74 #define TX_BD_HSIZE_SHIFT 16
75
76 __le32 tx_bd_mss;
77 __le32 tx_bd_cfa_action;
78 #define TX_BD_CFA_ACTION (0xffff << 16)
79 #define TX_BD_CFA_ACTION_SHIFT 16
80
81 __le32 tx_bd_cfa_meta;
82 #define TX_BD_CFA_META_MASK 0xfffffff
83 #define TX_BD_CFA_META_VID_MASK 0xfff
84 #define TX_BD_CFA_META_PRI_MASK (0xf << 12)
85 #define TX_BD_CFA_META_PRI_SHIFT 12
86 #define TX_BD_CFA_META_TPID_MASK (3 << 16)
87 #define TX_BD_CFA_META_TPID_SHIFT 16
88 #define TX_BD_CFA_META_KEY (0xf << 28)
89 #define TX_BD_CFA_META_KEY_SHIFT 28
90 #define TX_BD_CFA_META_KEY_VLAN (1 << 28)
91};
92
93#define BNXT_TX_PTP_IS_SET(lflags) ((lflags) & cpu_to_le32(TX_BD_FLAGS_STAMP))
94
95struct rx_bd {
96 __le32 rx_bd_len_flags_type;
97 #define RX_BD_TYPE (0x3f << 0)
98 #define RX_BD_TYPE_RX_PACKET_BD 0x4
99 #define RX_BD_TYPE_RX_BUFFER_BD 0x5
100 #define RX_BD_TYPE_RX_AGG_BD 0x6
101 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4)
102 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4)
103 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4)
104 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4)
105 #define RX_BD_FLAGS_SOP (1 << 6)
106 #define RX_BD_FLAGS_EOP (1 << 7)
107 #define RX_BD_FLAGS_BUFFERS (3 << 8)
108 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)
109 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8)
110 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8)
111 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8)
112 #define RX_BD_LEN (0xffff << 16)
113 #define RX_BD_LEN_SHIFT 16
114
115 u32 rx_bd_opaque;
116 __le64 rx_bd_haddr;
117};
118
119struct tx_cmp {
120 __le32 tx_cmp_flags_type;
121 #define CMP_TYPE (0x3f << 0)
122 #define CMP_TYPE_TX_L2_CMP 0
123 #define CMP_TYPE_RX_L2_CMP 17
124 #define CMP_TYPE_RX_AGG_CMP 18
125 #define CMP_TYPE_RX_L2_TPA_START_CMP 19
126 #define CMP_TYPE_RX_L2_TPA_END_CMP 21
127 #define CMP_TYPE_RX_TPA_AGG_CMP 22
128 #define CMP_TYPE_STATUS_CMP 32
129 #define CMP_TYPE_REMOTE_DRIVER_REQ 34
130 #define CMP_TYPE_REMOTE_DRIVER_RESP 36
131 #define CMP_TYPE_ERROR_STATUS 48
132 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
133 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL
134 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL
135 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL
136 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
137
138 #define TX_CMP_FLAGS_ERROR (1 << 6)
139 #define TX_CMP_FLAGS_PUSH (1 << 7)
140
141 u32 tx_cmp_opaque;
142 __le32 tx_cmp_errors_v;
143 #define TX_CMP_V (1 << 0)
144 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1)
145 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0
146 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2
147 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4
148 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5
149 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4)
150 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5)
151 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6)
152 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7)
153
154 __le32 tx_cmp_unsed_3;
155};
156
157struct rx_cmp {
158 __le32 rx_cmp_len_flags_type;
159 #define RX_CMP_CMP_TYPE (0x3f << 0)
160 #define RX_CMP_FLAGS_ERROR (1 << 6)
161 #define RX_CMP_FLAGS_PLACEMENT (7 << 7)
162 #define RX_CMP_FLAGS_RSS_VALID (1 << 10)
163 #define RX_CMP_FLAGS_UNUSED (1 << 11)
164 #define RX_CMP_FLAGS_ITYPES_SHIFT 12
165 #define RX_CMP_FLAGS_ITYPES_MASK 0xf000
166 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
167 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12)
168 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)
169 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12)
170 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12)
171 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12)
172 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12)
173 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12)
174 #define RX_CMP_LEN (0xffff << 16)
175 #define RX_CMP_LEN_SHIFT 16
176
177 u32 rx_cmp_opaque;
178 __le32 rx_cmp_misc_v1;
179 #define RX_CMP_V1 (1 << 0)
180 #define RX_CMP_AGG_BUFS (0x1f << 1)
181 #define RX_CMP_AGG_BUFS_SHIFT 1
182 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9)
183 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9
184 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16)
185 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16
186
187 __le32 rx_cmp_rss_hash;
188};
189
190#define RX_CMP_HASH_VALID(rxcmp) \
191 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
192
193#define RSS_PROFILE_ID_MASK 0x1f
194
195#define RX_CMP_HASH_TYPE(rxcmp) \
196 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
197 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
198
199struct rx_cmp_ext {
200 __le32 rx_cmp_flags2;
201 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1
202 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
203 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
204 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
205 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)
206 __le32 rx_cmp_meta_data;
207 #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff
208 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff
209 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000
210 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16
211 __le32 rx_cmp_cfa_code_errors_v2;
212 #define RX_CMP_V (1 << 0)
213 #define RX_CMPL_ERRORS_MASK (0x7fff << 1)
214 #define RX_CMPL_ERRORS_SFT 1
215 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
216 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
217 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)
218 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
219 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
220 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)
221 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)
222 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)
223 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)
224 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)
225 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)
226 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)
227 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)
228 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)
229 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)
230 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)
231 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)
232 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)
233 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)
234 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)
235 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)
236 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)
237 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)
238 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)
239 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)
240 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)
241 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
242 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)
243
244 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
245 #define RX_CMPL_CFA_CODE_SFT 16
246
247 __le32 rx_cmp_timestamp;
248};
249
250#define RX_CMP_L2_ERRORS \
251 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
252
253#define RX_CMP_L4_CS_BITS \
254 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
255
256#define RX_CMP_L4_CS_ERR_BITS \
257 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
258
259#define RX_CMP_L4_CS_OK(rxcmp1) \
260 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \
261 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
262
263#define RX_CMP_ENCAP(rxcmp1) \
264 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \
265 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
266
267#define RX_CMP_CFA_CODE(rxcmpl1) \
268 ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \
269 RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
270
271struct rx_agg_cmp {
272 __le32 rx_agg_cmp_len_flags_type;
273 #define RX_AGG_CMP_TYPE (0x3f << 0)
274 #define RX_AGG_CMP_LEN (0xffff << 16)
275 #define RX_AGG_CMP_LEN_SHIFT 16
276 u32 rx_agg_cmp_opaque;
277 __le32 rx_agg_cmp_v;
278 #define RX_AGG_CMP_V (1 << 0)
279 #define RX_AGG_CMP_AGG_ID (0xffff << 16)
280 #define RX_AGG_CMP_AGG_ID_SHIFT 16
281 __le32 rx_agg_cmp_unused;
282};
283
284#define TPA_AGG_AGG_ID(rx_agg) \
285 ((le32_to_cpu((rx_agg)->rx_agg_cmp_v) & \
286 RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)
287
288struct rx_tpa_start_cmp {
289 __le32 rx_tpa_start_cmp_len_flags_type;
290 #define RX_TPA_START_CMP_TYPE (0x3f << 0)
291 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6)
292 #define RX_TPA_START_CMP_FLAGS_SHIFT 6
293 #define RX_TPA_START_CMP_FLAGS_ERROR (0x1 << 6)
294 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)
295 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7
296 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
297 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
298 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
299 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
300 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)
301 #define RX_TPA_START_CMP_FLAGS_TIMESTAMP (0x1 << 11)
302 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)
303 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12
304 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
305 #define RX_TPA_START_CMP_LEN (0xffff << 16)
306 #define RX_TPA_START_CMP_LEN_SHIFT 16
307
308 u32 rx_tpa_start_cmp_opaque;
309 __le32 rx_tpa_start_cmp_misc_v1;
310 #define RX_TPA_START_CMP_V1 (0x1 << 0)
311 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9)
312 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9
313 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25)
314 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25
315 #define RX_TPA_START_CMP_AGG_ID_P5 (0xffff << 16)
316 #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5 16
317
318 __le32 rx_tpa_start_cmp_rss_hash;
319};
320
321#define TPA_START_HASH_VALID(rx_tpa_start) \
322 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
323 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
324
325#define TPA_START_HASH_TYPE(rx_tpa_start) \
326 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
327 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \
328 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
329
330#define TPA_START_AGG_ID(rx_tpa_start) \
331 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
332 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
333
334#define TPA_START_AGG_ID_P5(rx_tpa_start) \
335 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
336 RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)
337
338#define TPA_START_ERROR(rx_tpa_start) \
339 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
340 cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))
341
342struct rx_tpa_start_cmp_ext {
343 __le32 rx_tpa_start_cmp_flags2;
344 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)
345 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
346 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
347 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
348 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8)
349 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID (0x1 << 9)
350 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT (0x3 << 10)
351 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT 10
352 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL (0xffff << 16)
353 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT 16
354
355 __le32 rx_tpa_start_cmp_metadata;
356 __le32 rx_tpa_start_cmp_cfa_code_v2;
357 #define RX_TPA_START_CMP_V2 (0x1 << 0)
358 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
359 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT 1
360 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
361 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
362 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
363 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)
364 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16
365 __le32 rx_tpa_start_cmp_hdr_info;
366};
367
368#define TPA_START_CFA_CODE(rx_tpa_start) \
369 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
370 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
371
372#define TPA_START_IS_IPV6(rx_tpa_start) \
373 (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 & \
374 cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
375
376#define TPA_START_ERROR_CODE(rx_tpa_start) \
377 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
378 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >> \
379 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)
380
381struct rx_tpa_end_cmp {
382 __le32 rx_tpa_end_cmp_len_flags_type;
383 #define RX_TPA_END_CMP_TYPE (0x3f << 0)
384 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6)
385 #define RX_TPA_END_CMP_FLAGS_SHIFT 6
386 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7)
387 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7
388 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
389 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
390 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
391 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
392 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10)
393 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12)
394 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12
395 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
396 #define RX_TPA_END_CMP_LEN (0xffff << 16)
397 #define RX_TPA_END_CMP_LEN_SHIFT 16
398
399 u32 rx_tpa_end_cmp_opaque;
400 __le32 rx_tpa_end_cmp_misc_v1;
401 #define RX_TPA_END_CMP_V1 (0x1 << 0)
402 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1)
403 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1
404 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8)
405 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8
406 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16)
407 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16
408 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25)
409 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25
410 #define RX_TPA_END_CMP_AGG_ID_P5 (0xffff << 16)
411 #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5 16
412
413 __le32 rx_tpa_end_cmp_tsdelta;
414 #define RX_TPA_END_GRO_TS (0x1 << 31)
415};
416
417#define TPA_END_AGG_ID(rx_tpa_end) \
418 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
419 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
420
421#define TPA_END_AGG_ID_P5(rx_tpa_end) \
422 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
423 RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)
424
425#define TPA_END_PAYLOAD_OFF(rx_tpa_end) \
426 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
427 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)
428
429#define TPA_END_AGG_BUFS(rx_tpa_end) \
430 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
431 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)
432
433#define TPA_END_TPA_SEGS(rx_tpa_end) \
434 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
435 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
436
437#define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \
438 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \
439 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
440
441#define TPA_END_GRO(rx_tpa_end) \
442 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \
443 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
444
445#define TPA_END_GRO_TS(rx_tpa_end) \
446 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \
447 cpu_to_le32(RX_TPA_END_GRO_TS)))
448
449struct rx_tpa_end_cmp_ext {
450 __le32 rx_tpa_end_cmp_dup_acks;
451 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)
452 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5 (0xff << 16)
453 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5 16
454 #define RX_TPA_END_CMP_AGG_BUFS_P5 (0xff << 24)
455 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5 24
456
457 __le32 rx_tpa_end_cmp_seg_len;
458 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)
459
460 __le32 rx_tpa_end_cmp_errors_v2;
461 #define RX_TPA_END_CMP_V2 (0x1 << 0)
462 #define RX_TPA_END_CMP_ERRORS (0x3 << 1)
463 #define RX_TPA_END_CMP_ERRORS_P5 (0x7 << 1)
464 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1
465 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
466 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
467 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
468 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR (0x4 << 1)
469 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
470
471 u32 rx_tpa_end_cmp_start_opaque;
472};
473
474#define TPA_END_ERRORS(rx_tpa_end_ext) \
475 ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \
476 cpu_to_le32(RX_TPA_END_CMP_ERRORS))
477
478#define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext) \
479 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
480 RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >> \
481 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)
482
483#define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext) \
484 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
485 RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)
486
487#define EVENT_DATA1_RESET_NOTIFY_FATAL(data1) \
488 (((data1) & \
489 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
490 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)
491
492#define EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1) \
493 (((data1) & \
494 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
495 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION)
496
497#define EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2) \
498 ((data2) & \
499 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK)
500
501#define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1) \
502 !!((data1) & \
503 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
504
505#define EVENT_DATA1_RECOVERY_ENABLED(data1) \
506 !!((data1) & \
507 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
508
509#define BNXT_EVENT_ERROR_REPORT_TYPE(data1) \
510 (((data1) & \
511 ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >>\
512 ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT)
513
514#define BNXT_EVENT_INVALID_SIGNAL_DATA(data2) \
515 (((data2) & \
516 ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK) >>\
517 ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT)
518
519struct nqe_cn {
520 __le16 type;
521 #define NQ_CN_TYPE_MASK 0x3fUL
522 #define NQ_CN_TYPE_SFT 0
523 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
524 #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
525 __le16 reserved16;
526 __le32 cq_handle_low;
527 __le32 v;
528 #define NQ_CN_V 0x1UL
529 __le32 cq_handle_high;
530};
531
532#define DB_IDX_MASK 0xffffff
533#define DB_IDX_VALID (0x1 << 26)
534#define DB_IRQ_DIS (0x1 << 27)
535#define DB_KEY_TX (0x0 << 28)
536#define DB_KEY_RX (0x1 << 28)
537#define DB_KEY_CP (0x2 << 28)
538#define DB_KEY_ST (0x3 << 28)
539#define DB_KEY_TX_PUSH (0x4 << 28)
540#define DB_LONG_TX_PUSH (0x2 << 24)
541
542#define BNXT_MIN_ROCE_CP_RINGS 2
543#define BNXT_MIN_ROCE_STAT_CTXS 1
544
545/* 64-bit doorbell */
546#define DBR_INDEX_MASK 0x0000000000ffffffULL
547#define DBR_XID_MASK 0x000fffff00000000ULL
548#define DBR_XID_SFT 32
549#define DBR_PATH_L2 (0x1ULL << 56)
550#define DBR_TYPE_SQ (0x0ULL << 60)
551#define DBR_TYPE_RQ (0x1ULL << 60)
552#define DBR_TYPE_SRQ (0x2ULL << 60)
553#define DBR_TYPE_SRQ_ARM (0x3ULL << 60)
554#define DBR_TYPE_CQ (0x4ULL << 60)
555#define DBR_TYPE_CQ_ARMSE (0x5ULL << 60)
556#define DBR_TYPE_CQ_ARMALL (0x6ULL << 60)
557#define DBR_TYPE_CQ_ARMENA (0x7ULL << 60)
558#define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60)
559#define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60)
560#define DBR_TYPE_NQ (0xaULL << 60)
561#define DBR_TYPE_NQ_ARM (0xbULL << 60)
562#define DBR_TYPE_NULL (0xfULL << 60)
563
564#define DB_PF_OFFSET_P5 0x10000
565#define DB_VF_OFFSET_P5 0x4000
566
567#define INVALID_HW_RING_ID ((u16)-1)
568
569/* The hardware supports certain page sizes. Use the supported page sizes
570 * to allocate the rings.
571 */
572#if (PAGE_SHIFT < 12)
573#define BNXT_PAGE_SHIFT 12
574#elif (PAGE_SHIFT <= 13)
575#define BNXT_PAGE_SHIFT PAGE_SHIFT
576#elif (PAGE_SHIFT < 16)
577#define BNXT_PAGE_SHIFT 13
578#else
579#define BNXT_PAGE_SHIFT 16
580#endif
581
582#define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)
583
584/* The RXBD length is 16-bit so we can only support page sizes < 64K */
585#if (PAGE_SHIFT > 15)
586#define BNXT_RX_PAGE_SHIFT 15
587#else
588#define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
589#endif
590
591#define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
592
593#define BNXT_MAX_MTU 9500
594
595/* First RX buffer page in XDP multi-buf mode
596 *
597 * +-------------------------------------------------------------------------+
598 * | XDP_PACKET_HEADROOM | bp->rx_buf_use_size | skb_shared_info|
599 * | (bp->rx_dma_offset) | | |
600 * +-------------------------------------------------------------------------+
601 */
602#define BNXT_MAX_PAGE_MODE_MTU_SBUF \
603 ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \
604 XDP_PACKET_HEADROOM)
605#define BNXT_MAX_PAGE_MODE_MTU \
606 (BNXT_MAX_PAGE_MODE_MTU_SBUF - \
607 SKB_DATA_ALIGN((unsigned int)sizeof(struct skb_shared_info)))
608
609#define BNXT_MIN_PKT_SIZE 52
610
611#define BNXT_DEFAULT_RX_RING_SIZE 511
612#define BNXT_DEFAULT_TX_RING_SIZE 511
613
614#define MAX_TPA 64
615#define MAX_TPA_P5 256
616#define MAX_TPA_P5_MASK (MAX_TPA_P5 - 1)
617#define MAX_TPA_SEGS_P5 0x3f
618
619#if (BNXT_PAGE_SHIFT == 16)
620#define MAX_RX_PAGES_AGG_ENA 1
621#define MAX_RX_PAGES 4
622#define MAX_RX_AGG_PAGES 4
623#define MAX_TX_PAGES 1
624#define MAX_CP_PAGES 16
625#else
626#define MAX_RX_PAGES_AGG_ENA 8
627#define MAX_RX_PAGES 32
628#define MAX_RX_AGG_PAGES 32
629#define MAX_TX_PAGES 8
630#define MAX_CP_PAGES 128
631#endif
632
633#define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
634#define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
635#define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
636
637#define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
638#define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
639
640#define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
641
642#define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
643#define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
644
645#define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
646
647#define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1)
648#define BNXT_MAX_RX_DESC_CNT_JUM_ENA (RX_DESC_CNT * MAX_RX_PAGES_AGG_ENA - 1)
649#define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
650#define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)
651
652/* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1. We need one extra
653 * BD because the first TX BD is always a long BD.
654 */
655#define BNXT_MIN_TX_DESC_CNT (MAX_SKB_FRAGS + 2)
656
657#define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
658#define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
659
660#define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
661#define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))
662
663#define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
664#define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))
665
666#define TX_CMP_VALID(txcmp, raw_cons) \
667 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \
668 !((raw_cons) & bp->cp_bit))
669
670#define RX_CMP_VALID(rxcmp1, raw_cons) \
671 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
672 !((raw_cons) & bp->cp_bit))
673
674#define RX_AGG_CMP_VALID(agg, raw_cons) \
675 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
676 !((raw_cons) & bp->cp_bit))
677
678#define NQ_CMP_VALID(nqcmp, raw_cons) \
679 (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
680
681#define TX_CMP_TYPE(txcmp) \
682 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
683
684#define RX_CMP_TYPE(rxcmp) \
685 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
686
687#define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask)
688
689#define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask)
690
691#define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask)
692
693#define ADV_RAW_CMP(idx, n) ((idx) + (n))
694#define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1)
695#define RING_CMP(idx) ((idx) & bp->cp_ring_mask)
696#define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1))
697
698#define DFLT_HWRM_CMD_TIMEOUT 500
699
700#define BNXT_RX_EVENT 1
701#define BNXT_AGG_EVENT 2
702#define BNXT_TX_EVENT 4
703#define BNXT_REDIRECT_EVENT 8
704
705struct bnxt_sw_tx_bd {
706 union {
707 struct sk_buff *skb;
708 struct xdp_frame *xdpf;
709 };
710 DEFINE_DMA_UNMAP_ADDR(mapping);
711 DEFINE_DMA_UNMAP_LEN(len);
712 struct page *page;
713 u8 is_gso;
714 u8 is_push;
715 u8 action;
716 unsigned short nr_frags;
717 u16 rx_prod;
718};
719
720struct bnxt_sw_rx_bd {
721 void *data;
722 u8 *data_ptr;
723 dma_addr_t mapping;
724};
725
726struct bnxt_sw_rx_agg_bd {
727 struct page *page;
728 unsigned int offset;
729 dma_addr_t mapping;
730};
731
732struct bnxt_mem_init {
733 u8 init_val;
734 u16 offset;
735#define BNXT_MEM_INVALID_OFFSET 0xffff
736 u16 size;
737};
738
739struct bnxt_ring_mem_info {
740 int nr_pages;
741 int page_size;
742 u16 flags;
743#define BNXT_RMEM_VALID_PTE_FLAG 1
744#define BNXT_RMEM_RING_PTE_FLAG 2
745#define BNXT_RMEM_USE_FULL_PAGE_FLAG 4
746
747 u16 depth;
748 struct bnxt_mem_init *mem_init;
749
750 void **pg_arr;
751 dma_addr_t *dma_arr;
752
753 __le64 *pg_tbl;
754 dma_addr_t pg_tbl_map;
755
756 int vmem_size;
757 void **vmem;
758};
759
760struct bnxt_ring_struct {
761 struct bnxt_ring_mem_info ring_mem;
762
763 u16 fw_ring_id; /* Ring id filled by Chimp FW */
764 union {
765 u16 grp_idx;
766 u16 map_idx; /* Used by cmpl rings */
767 };
768 u32 handle;
769 u8 queue_id;
770};
771
772struct tx_push_bd {
773 __le32 doorbell;
774 __le32 tx_bd_len_flags_type;
775 u32 tx_bd_opaque;
776 struct tx_bd_ext txbd2;
777};
778
779struct tx_push_buffer {
780 struct tx_push_bd push_bd;
781 u32 data[25];
782};
783
784struct bnxt_db_info {
785 void __iomem *doorbell;
786 union {
787 u64 db_key64;
788 u32 db_key32;
789 };
790};
791
792struct bnxt_tx_ring_info {
793 struct bnxt_napi *bnapi;
794 u16 tx_prod;
795 u16 tx_cons;
796 u16 txq_index;
797 u8 kick_pending;
798 struct bnxt_db_info tx_db;
799
800 struct tx_bd *tx_desc_ring[MAX_TX_PAGES];
801 struct bnxt_sw_tx_bd *tx_buf_ring;
802
803 dma_addr_t tx_desc_mapping[MAX_TX_PAGES];
804
805 struct tx_push_buffer *tx_push;
806 dma_addr_t tx_push_mapping;
807 __le64 data_mapping;
808
809#define BNXT_DEV_STATE_CLOSING 0x1
810 u32 dev_state;
811
812 struct bnxt_ring_struct tx_ring_struct;
813 /* Synchronize simultaneous xdp_xmit on same ring */
814 spinlock_t xdp_tx_lock;
815};
816
817#define BNXT_LEGACY_COAL_CMPL_PARAMS \
818 (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN | \
819 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX | \
820 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET | \
821 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE | \
822 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR | \
823 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
824 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR | \
825 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
826 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
827
828#define BNXT_COAL_CMPL_ENABLES \
829 (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
830 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
831 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
832 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
833
834#define BNXT_COAL_CMPL_MIN_TMR_ENABLE \
835 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
836
837#define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE \
838 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
839
840struct bnxt_coal_cap {
841 u32 cmpl_params;
842 u32 nq_params;
843 u16 num_cmpl_dma_aggr_max;
844 u16 num_cmpl_dma_aggr_during_int_max;
845 u16 cmpl_aggr_dma_tmr_max;
846 u16 cmpl_aggr_dma_tmr_during_int_max;
847 u16 int_lat_tmr_min_max;
848 u16 int_lat_tmr_max_max;
849 u16 num_cmpl_aggr_int_max;
850 u16 timer_units;
851};
852
853struct bnxt_coal {
854 u16 coal_ticks;
855 u16 coal_ticks_irq;
856 u16 coal_bufs;
857 u16 coal_bufs_irq;
858 /* RING_IDLE enabled when coal ticks < idle_thresh */
859 u16 idle_thresh;
860 u8 bufs_per_record;
861 u8 budget;
862 u16 flags;
863};
864
865struct bnxt_tpa_info {
866 void *data;
867 u8 *data_ptr;
868 dma_addr_t mapping;
869 u16 len;
870 unsigned short gso_type;
871 u32 flags2;
872 u32 metadata;
873 enum pkt_hash_types hash_type;
874 u32 rss_hash;
875 u32 hdr_info;
876
877#define BNXT_TPA_L4_SIZE(hdr_info) \
878 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
879
880#define BNXT_TPA_INNER_L3_OFF(hdr_info) \
881 (((hdr_info) >> 18) & 0x1ff)
882
883#define BNXT_TPA_INNER_L2_OFF(hdr_info) \
884 (((hdr_info) >> 9) & 0x1ff)
885
886#define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
887 ((hdr_info) & 0x1ff)
888
889 u16 cfa_code; /* cfa_code in TPA start compl */
890 u8 agg_count;
891 struct rx_agg_cmp *agg_arr;
892};
893
894#define BNXT_AGG_IDX_BMAP_SIZE (MAX_TPA_P5 / BITS_PER_LONG)
895
896struct bnxt_tpa_idx_map {
897 u16 agg_id_tbl[1024];
898 unsigned long agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];
899};
900
901struct bnxt_rx_ring_info {
902 struct bnxt_napi *bnapi;
903 u16 rx_prod;
904 u16 rx_agg_prod;
905 u16 rx_sw_agg_prod;
906 u16 rx_next_cons;
907 struct bnxt_db_info rx_db;
908 struct bnxt_db_info rx_agg_db;
909
910 struct bpf_prog *xdp_prog;
911
912 struct rx_bd *rx_desc_ring[MAX_RX_PAGES];
913 struct bnxt_sw_rx_bd *rx_buf_ring;
914
915 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
916 struct bnxt_sw_rx_agg_bd *rx_agg_ring;
917
918 unsigned long *rx_agg_bmap;
919 u16 rx_agg_bmap_size;
920
921 struct page *rx_page;
922 unsigned int rx_page_offset;
923
924 dma_addr_t rx_desc_mapping[MAX_RX_PAGES];
925 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
926
927 struct bnxt_tpa_info *rx_tpa;
928 struct bnxt_tpa_idx_map *rx_tpa_idx_map;
929
930 struct bnxt_ring_struct rx_ring_struct;
931 struct bnxt_ring_struct rx_agg_ring_struct;
932 struct xdp_rxq_info xdp_rxq;
933 struct page_pool *page_pool;
934};
935
936struct bnxt_rx_sw_stats {
937 u64 rx_l4_csum_errors;
938 u64 rx_resets;
939 u64 rx_buf_errors;
940 u64 rx_oom_discards;
941 u64 rx_netpoll_discards;
942};
943
944struct bnxt_cmn_sw_stats {
945 u64 missed_irqs;
946};
947
948struct bnxt_sw_stats {
949 struct bnxt_rx_sw_stats rx;
950 struct bnxt_cmn_sw_stats cmn;
951};
952
953struct bnxt_stats_mem {
954 u64 *sw_stats;
955 u64 *hw_masks;
956 void *hw_stats;
957 dma_addr_t hw_stats_map;
958 int len;
959};
960
961struct bnxt_cp_ring_info {
962 struct bnxt_napi *bnapi;
963 u32 cp_raw_cons;
964 struct bnxt_db_info cp_db;
965
966 u8 had_work_done:1;
967 u8 has_more_work:1;
968
969 u32 last_cp_raw_cons;
970
971 struct bnxt_coal rx_ring_coal;
972 u64 rx_packets;
973 u64 rx_bytes;
974 u64 event_ctr;
975
976 struct dim dim;
977
978 union {
979 struct tx_cmp **cp_desc_ring;
980 struct nqe_cn **nq_desc_ring;
981 };
982
983 dma_addr_t *cp_desc_mapping;
984
985 struct bnxt_stats_mem stats;
986 u32 hw_stats_ctx_id;
987
988 struct bnxt_sw_stats sw_stats;
989
990 struct bnxt_ring_struct cp_ring_struct;
991
992 struct bnxt_cp_ring_info *cp_ring_arr[2];
993#define BNXT_RX_HDL 0
994#define BNXT_TX_HDL 1
995};
996
997struct bnxt_napi {
998 struct napi_struct napi;
999 struct bnxt *bp;
1000
1001 int index;
1002 struct bnxt_cp_ring_info cp_ring;
1003 struct bnxt_rx_ring_info *rx_ring;
1004 struct bnxt_tx_ring_info *tx_ring;
1005
1006 void (*tx_int)(struct bnxt *, struct bnxt_napi *,
1007 int);
1008 int tx_pkts;
1009 u8 events;
1010
1011 u32 flags;
1012#define BNXT_NAPI_FLAG_XDP 0x1
1013
1014 bool in_reset;
1015};
1016
1017struct bnxt_irq {
1018 irq_handler_t handler;
1019 unsigned int vector;
1020 u8 requested:1;
1021 u8 have_cpumask:1;
1022 char name[IFNAMSIZ + 2];
1023 cpumask_var_t cpu_mask;
1024};
1025
1026#define HWRM_RING_ALLOC_TX 0x1
1027#define HWRM_RING_ALLOC_RX 0x2
1028#define HWRM_RING_ALLOC_AGG 0x4
1029#define HWRM_RING_ALLOC_CMPL 0x8
1030#define HWRM_RING_ALLOC_NQ 0x10
1031
1032#define INVALID_STATS_CTX_ID -1
1033
1034struct bnxt_ring_grp_info {
1035 u16 fw_stats_ctx;
1036 u16 fw_grp_id;
1037 u16 rx_fw_ring_id;
1038 u16 agg_fw_ring_id;
1039 u16 cp_fw_ring_id;
1040};
1041
1042struct bnxt_vnic_info {
1043 u16 fw_vnic_id; /* returned by Chimp during alloc */
1044#define BNXT_MAX_CTX_PER_VNIC 8
1045 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
1046 u16 fw_l2_ctx_id;
1047#define BNXT_MAX_UC_ADDRS 4
1048 __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
1049 /* index 0 always dev_addr */
1050 u16 uc_filter_count;
1051 u8 *uc_list;
1052
1053 u16 *fw_grp_ids;
1054 dma_addr_t rss_table_dma_addr;
1055 __le16 *rss_table;
1056 dma_addr_t rss_hash_key_dma_addr;
1057 u64 *rss_hash_key;
1058 int rss_table_size;
1059#define BNXT_RSS_TABLE_ENTRIES_P5 64
1060#define BNXT_RSS_TABLE_SIZE_P5 (BNXT_RSS_TABLE_ENTRIES_P5 * 4)
1061#define BNXT_RSS_TABLE_MAX_TBL_P5 8
1062#define BNXT_MAX_RSS_TABLE_SIZE_P5 \
1063 (BNXT_RSS_TABLE_SIZE_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1064#define BNXT_MAX_RSS_TABLE_ENTRIES_P5 \
1065 (BNXT_RSS_TABLE_ENTRIES_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1066
1067 u32 rx_mask;
1068
1069 u8 *mc_list;
1070 int mc_list_size;
1071 int mc_list_count;
1072 dma_addr_t mc_list_mapping;
1073#define BNXT_MAX_MC_ADDRS 16
1074
1075 u32 flags;
1076#define BNXT_VNIC_RSS_FLAG 1
1077#define BNXT_VNIC_RFS_FLAG 2
1078#define BNXT_VNIC_MCAST_FLAG 4
1079#define BNXT_VNIC_UCAST_FLAG 8
1080#define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10
1081};
1082
1083struct bnxt_hw_resc {
1084 u16 min_rsscos_ctxs;
1085 u16 max_rsscos_ctxs;
1086 u16 min_cp_rings;
1087 u16 max_cp_rings;
1088 u16 resv_cp_rings;
1089 u16 min_tx_rings;
1090 u16 max_tx_rings;
1091 u16 resv_tx_rings;
1092 u16 max_tx_sch_inputs;
1093 u16 min_rx_rings;
1094 u16 max_rx_rings;
1095 u16 resv_rx_rings;
1096 u16 min_hw_ring_grps;
1097 u16 max_hw_ring_grps;
1098 u16 resv_hw_ring_grps;
1099 u16 min_l2_ctxs;
1100 u16 max_l2_ctxs;
1101 u16 min_vnics;
1102 u16 max_vnics;
1103 u16 resv_vnics;
1104 u16 min_stat_ctxs;
1105 u16 max_stat_ctxs;
1106 u16 resv_stat_ctxs;
1107 u16 max_nqs;
1108 u16 max_irqs;
1109 u16 resv_irqs;
1110};
1111
1112#if defined(CONFIG_BNXT_SRIOV)
1113struct bnxt_vf_info {
1114 u16 fw_fid;
1115 u8 mac_addr[ETH_ALEN]; /* PF assigned MAC Address */
1116 u8 vf_mac_addr[ETH_ALEN]; /* VF assigned MAC address, only
1117 * stored by PF.
1118 */
1119 u16 vlan;
1120 u16 func_qcfg_flags;
1121 u32 flags;
1122#define BNXT_VF_QOS 0x1
1123#define BNXT_VF_SPOOFCHK 0x2
1124#define BNXT_VF_LINK_FORCED 0x4
1125#define BNXT_VF_LINK_UP 0x8
1126#define BNXT_VF_TRUST 0x10
1127 u32 min_tx_rate;
1128 u32 max_tx_rate;
1129 void *hwrm_cmd_req_addr;
1130 dma_addr_t hwrm_cmd_req_dma_addr;
1131};
1132#endif
1133
1134struct bnxt_pf_info {
1135#define BNXT_FIRST_PF_FID 1
1136#define BNXT_FIRST_VF_FID 128
1137 u16 fw_fid;
1138 u16 port_id;
1139 u8 mac_addr[ETH_ALEN];
1140 u32 first_vf_id;
1141 u16 active_vfs;
1142 u16 registered_vfs;
1143 u16 max_vfs;
1144 u32 max_encap_records;
1145 u32 max_decap_records;
1146 u32 max_tx_em_flows;
1147 u32 max_tx_wm_flows;
1148 u32 max_rx_em_flows;
1149 u32 max_rx_wm_flows;
1150 unsigned long *vf_event_bmap;
1151 u16 hwrm_cmd_req_pages;
1152 u8 vf_resv_strategy;
1153#define BNXT_VF_RESV_STRATEGY_MAXIMAL 0
1154#define BNXT_VF_RESV_STRATEGY_MINIMAL 1
1155#define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC 2
1156 void *hwrm_cmd_req_addr[4];
1157 dma_addr_t hwrm_cmd_req_dma_addr[4];
1158 struct bnxt_vf_info *vf;
1159};
1160
1161struct bnxt_ntuple_filter {
1162 struct hlist_node hash;
1163 u8 dst_mac_addr[ETH_ALEN];
1164 u8 src_mac_addr[ETH_ALEN];
1165 struct flow_keys fkeys;
1166 __le64 filter_id;
1167 u16 sw_id;
1168 u8 l2_fltr_idx;
1169 u16 rxq;
1170 u32 flow_id;
1171 unsigned long state;
1172#define BNXT_FLTR_VALID 0
1173#define BNXT_FLTR_UPDATE 1
1174};
1175
1176struct bnxt_link_info {
1177 u8 phy_type;
1178 u8 media_type;
1179 u8 transceiver;
1180 u8 phy_addr;
1181 u8 phy_link_status;
1182#define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK
1183#define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL
1184#define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK
1185 u8 wire_speed;
1186 u8 phy_state;
1187#define BNXT_PHY_STATE_ENABLED 0
1188#define BNXT_PHY_STATE_DISABLED 1
1189
1190 u8 link_state;
1191#define BNXT_LINK_STATE_UNKNOWN 0
1192#define BNXT_LINK_STATE_DOWN 1
1193#define BNXT_LINK_STATE_UP 2
1194#define BNXT_LINK_IS_UP(bp) ((bp)->link_info.link_state == BNXT_LINK_STATE_UP)
1195 u8 duplex;
1196#define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1197#define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1198 u8 pause;
1199#define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX
1200#define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX
1201#define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \
1202 PORT_PHY_QCFG_RESP_PAUSE_TX)
1203 u8 lp_pause;
1204 u8 auto_pause_setting;
1205 u8 force_pause_setting;
1206 u8 duplex_setting;
1207 u8 auto_mode;
1208#define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \
1209 (mode) <= BNXT_LINK_AUTO_MSK)
1210#define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1211#define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1212#define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1213#define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1214#define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1215#define PHY_VER_LEN 3
1216 u8 phy_ver[PHY_VER_LEN];
1217 u16 link_speed;
1218#define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1219#define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1220#define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1221#define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1222#define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1223#define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1224#define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1225#define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1226#define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1227#define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1228 u16 support_speeds;
1229 u16 support_pam4_speeds;
1230 u16 auto_link_speeds; /* fw adv setting */
1231#define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1232#define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1233#define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1234#define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1235#define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1236#define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1237#define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1238#define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1239#define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1240#define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1241 u16 auto_pam4_link_speeds;
1242#define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G
1243#define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G
1244#define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G
1245 u16 support_auto_speeds;
1246 u16 support_pam4_auto_speeds;
1247 u16 lp_auto_link_speeds;
1248 u16 lp_auto_pam4_link_speeds;
1249 u16 force_link_speed;
1250 u16 force_pam4_link_speed;
1251 u32 preemphasis;
1252 u8 module_status;
1253 u8 active_fec_sig_mode;
1254 u16 fec_cfg;
1255#define BNXT_FEC_NONE PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
1256#define BNXT_FEC_AUTONEG_CAP PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED
1257#define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1258#define BNXT_FEC_ENC_BASE_R_CAP \
1259 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED
1260#define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1261#define BNXT_FEC_ENC_RS_CAP \
1262 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED
1263#define BNXT_FEC_ENC_LLRS_CAP \
1264 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED | \
1265 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED)
1266#define BNXT_FEC_ENC_RS \
1267 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED | \
1268 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED | \
1269 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED)
1270#define BNXT_FEC_ENC_LLRS \
1271 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED | \
1272 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED)
1273
1274 /* copy of requested setting from ethtool cmd */
1275 u8 autoneg;
1276#define BNXT_AUTONEG_SPEED 1
1277#define BNXT_AUTONEG_FLOW_CTRL 2
1278 u8 req_signal_mode;
1279#define BNXT_SIG_MODE_NRZ PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ
1280#define BNXT_SIG_MODE_PAM4 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
1281 u8 req_duplex;
1282 u8 req_flow_ctrl;
1283 u16 req_link_speed;
1284 u16 advertising; /* user adv setting */
1285 u16 advertising_pam4;
1286 bool force_link_chng;
1287
1288 bool phy_retry;
1289 unsigned long phy_retry_expires;
1290
1291 /* a copy of phy_qcfg output used to report link
1292 * info to VF
1293 */
1294 struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1295};
1296
1297#define BNXT_FEC_RS544_ON \
1298 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE | \
1299 PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE)
1300
1301#define BNXT_FEC_RS544_OFF \
1302 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE | \
1303 PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE)
1304
1305#define BNXT_FEC_RS272_ON \
1306 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE | \
1307 PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE)
1308
1309#define BNXT_FEC_RS272_OFF \
1310 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE | \
1311 PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE)
1312
1313#define BNXT_PAM4_SUPPORTED(link_info) \
1314 ((link_info)->support_pam4_speeds)
1315
1316#define BNXT_FEC_RS_ON(link_info) \
1317 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \
1318 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1319 (BNXT_PAM4_SUPPORTED(link_info) ? \
1320 (BNXT_FEC_RS544_ON | BNXT_FEC_RS272_OFF) : 0))
1321
1322#define BNXT_FEC_LLRS_ON \
1323 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \
1324 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1325 BNXT_FEC_RS272_ON | BNXT_FEC_RS544_OFF)
1326
1327#define BNXT_FEC_RS_OFF(link_info) \
1328 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE | \
1329 (BNXT_PAM4_SUPPORTED(link_info) ? \
1330 (BNXT_FEC_RS544_OFF | BNXT_FEC_RS272_OFF) : 0))
1331
1332#define BNXT_FEC_BASE_R_ON(link_info) \
1333 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE | \
1334 BNXT_FEC_RS_OFF(link_info))
1335
1336#define BNXT_FEC_ALL_OFF(link_info) \
1337 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1338 BNXT_FEC_RS_OFF(link_info))
1339
1340#define BNXT_MAX_QUEUE 8
1341
1342struct bnxt_queue_info {
1343 u8 queue_id;
1344 u8 queue_profile;
1345};
1346
1347#define BNXT_MAX_LED 4
1348
1349struct bnxt_led_info {
1350 u8 led_id;
1351 u8 led_type;
1352 u8 led_group_id;
1353 u8 unused;
1354 __le16 led_state_caps;
1355#define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
1356 cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1357
1358 __le16 led_color_caps;
1359};
1360
1361#define BNXT_MAX_TEST 8
1362
1363struct bnxt_test_info {
1364 u8 offline_mask;
1365 u16 timeout;
1366 char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1367};
1368
1369#define CHIMP_REG_VIEW_ADDR \
1370 ((bp->flags & BNXT_FLAG_CHIP_P5) ? 0x80000000 : 0xb1000000)
1371
1372#define BNXT_GRCPF_REG_CHIMP_COMM 0x0
1373#define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
1374#define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
1375#define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014
1376#define BNXT_CAG_REG_BASE 0x300000
1377
1378#define BNXT_GRC_REG_STATUS_P5 0x520
1379
1380#define BNXT_GRCPF_REG_KONG_COMM 0xA00
1381#define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00
1382
1383#define BNXT_GRC_REG_CHIP_NUM 0x48
1384#define BNXT_GRC_REG_BASE 0x260000
1385
1386#define BNXT_TS_REG_TIMESYNC_TS0_LOWER 0x640180c
1387#define BNXT_TS_REG_TIMESYNC_TS0_UPPER 0x6401810
1388
1389#define BNXT_GRC_BASE_MASK 0xfffff000
1390#define BNXT_GRC_OFFSET_MASK 0x00000ffc
1391
1392struct bnxt_tc_flow_stats {
1393 u64 packets;
1394 u64 bytes;
1395};
1396
1397#ifdef CONFIG_BNXT_FLOWER_OFFLOAD
1398struct bnxt_flower_indr_block_cb_priv {
1399 struct net_device *tunnel_netdev;
1400 struct bnxt *bp;
1401 struct list_head list;
1402};
1403#endif
1404
1405struct bnxt_tc_info {
1406 bool enabled;
1407
1408 /* hash table to store TC offloaded flows */
1409 struct rhashtable flow_table;
1410 struct rhashtable_params flow_ht_params;
1411
1412 /* hash table to store L2 keys of TC flows */
1413 struct rhashtable l2_table;
1414 struct rhashtable_params l2_ht_params;
1415 /* hash table to store L2 keys for TC tunnel decap */
1416 struct rhashtable decap_l2_table;
1417 struct rhashtable_params decap_l2_ht_params;
1418 /* hash table to store tunnel decap entries */
1419 struct rhashtable decap_table;
1420 struct rhashtable_params decap_ht_params;
1421 /* hash table to store tunnel encap entries */
1422 struct rhashtable encap_table;
1423 struct rhashtable_params encap_ht_params;
1424
1425 /* lock to atomically add/del an l2 node when a flow is
1426 * added or deleted.
1427 */
1428 struct mutex lock;
1429
1430 /* Fields used for batching stats query */
1431 struct rhashtable_iter iter;
1432#define BNXT_FLOW_STATS_BATCH_MAX 10
1433 struct bnxt_tc_stats_batch {
1434 void *flow_node;
1435 struct bnxt_tc_flow_stats hw_stats;
1436 } stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1437
1438 /* Stat counter mask (width) */
1439 u64 bytes_mask;
1440 u64 packets_mask;
1441};
1442
1443struct bnxt_vf_rep_stats {
1444 u64 packets;
1445 u64 bytes;
1446 u64 dropped;
1447};
1448
1449struct bnxt_vf_rep {
1450 struct bnxt *bp;
1451 struct net_device *dev;
1452 struct metadata_dst *dst;
1453 u16 vf_idx;
1454 u16 tx_cfa_action;
1455 u16 rx_cfa_code;
1456
1457 struct bnxt_vf_rep_stats rx_stats;
1458 struct bnxt_vf_rep_stats tx_stats;
1459};
1460
1461#define PTU_PTE_VALID 0x1UL
1462#define PTU_PTE_LAST 0x2UL
1463#define PTU_PTE_NEXT_TO_LAST 0x4UL
1464
1465#define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
1466#define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES)
1467
1468struct bnxt_ctx_pg_info {
1469 u32 entries;
1470 u32 nr_pages;
1471 void *ctx_pg_arr[MAX_CTX_PAGES];
1472 dma_addr_t ctx_dma_arr[MAX_CTX_PAGES];
1473 struct bnxt_ring_mem_info ring_mem;
1474 struct bnxt_ctx_pg_info **ctx_pg_tbl;
1475};
1476
1477#define BNXT_MAX_TQM_SP_RINGS 1
1478#define BNXT_MAX_TQM_FP_RINGS 8
1479#define BNXT_MAX_TQM_RINGS \
1480 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
1481
1482#define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256
1483
1484#define BNXT_SET_CTX_PAGE_ATTR(attr) \
1485do { \
1486 if (BNXT_PAGE_SIZE == 0x2000) \
1487 attr = FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K; \
1488 else if (BNXT_PAGE_SIZE == 0x10000) \
1489 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K; \
1490 else \
1491 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K; \
1492} while (0)
1493
1494struct bnxt_ctx_mem_info {
1495 u32 qp_max_entries;
1496 u16 qp_min_qp1_entries;
1497 u16 qp_max_l2_entries;
1498 u16 qp_entry_size;
1499 u16 srq_max_l2_entries;
1500 u32 srq_max_entries;
1501 u16 srq_entry_size;
1502 u16 cq_max_l2_entries;
1503 u32 cq_max_entries;
1504 u16 cq_entry_size;
1505 u16 vnic_max_vnic_entries;
1506 u16 vnic_max_ring_table_entries;
1507 u16 vnic_entry_size;
1508 u32 stat_max_entries;
1509 u16 stat_entry_size;
1510 u16 tqm_entry_size;
1511 u32 tqm_min_entries_per_ring;
1512 u32 tqm_max_entries_per_ring;
1513 u32 mrav_max_entries;
1514 u16 mrav_entry_size;
1515 u16 tim_entry_size;
1516 u32 tim_max_entries;
1517 u16 mrav_num_entries_units;
1518 u8 tqm_entries_multiple;
1519 u8 tqm_fp_rings_count;
1520
1521 u32 flags;
1522 #define BNXT_CTX_FLAG_INITED 0x01
1523
1524 struct bnxt_ctx_pg_info qp_mem;
1525 struct bnxt_ctx_pg_info srq_mem;
1526 struct bnxt_ctx_pg_info cq_mem;
1527 struct bnxt_ctx_pg_info vnic_mem;
1528 struct bnxt_ctx_pg_info stat_mem;
1529 struct bnxt_ctx_pg_info mrav_mem;
1530 struct bnxt_ctx_pg_info tim_mem;
1531 struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS];
1532
1533#define BNXT_CTX_MEM_INIT_QP 0
1534#define BNXT_CTX_MEM_INIT_SRQ 1
1535#define BNXT_CTX_MEM_INIT_CQ 2
1536#define BNXT_CTX_MEM_INIT_VNIC 3
1537#define BNXT_CTX_MEM_INIT_STAT 4
1538#define BNXT_CTX_MEM_INIT_MRAV 5
1539#define BNXT_CTX_MEM_INIT_MAX 6
1540 struct bnxt_mem_init mem_init[BNXT_CTX_MEM_INIT_MAX];
1541};
1542
1543enum bnxt_health_severity {
1544 SEVERITY_NORMAL = 0,
1545 SEVERITY_WARNING,
1546 SEVERITY_RECOVERABLE,
1547 SEVERITY_FATAL,
1548};
1549
1550enum bnxt_health_remedy {
1551 REMEDY_DEVLINK_RECOVER,
1552 REMEDY_POWER_CYCLE_DEVICE,
1553 REMEDY_POWER_CYCLE_HOST,
1554 REMEDY_FW_UPDATE,
1555 REMEDY_HW_REPLACE,
1556};
1557
1558struct bnxt_fw_health {
1559 u32 flags;
1560 u32 polling_dsecs;
1561 u32 master_func_wait_dsecs;
1562 u32 normal_func_wait_dsecs;
1563 u32 post_reset_wait_dsecs;
1564 u32 post_reset_max_wait_dsecs;
1565 u32 regs[4];
1566 u32 mapped_regs[4];
1567#define BNXT_FW_HEALTH_REG 0
1568#define BNXT_FW_HEARTBEAT_REG 1
1569#define BNXT_FW_RESET_CNT_REG 2
1570#define BNXT_FW_RESET_INPROG_REG 3
1571 u32 fw_reset_inprog_reg_mask;
1572 u32 last_fw_heartbeat;
1573 u32 last_fw_reset_cnt;
1574 u8 enabled:1;
1575 u8 primary:1;
1576 u8 status_reliable:1;
1577 u8 resets_reliable:1;
1578 u8 tmr_multiplier;
1579 u8 tmr_counter;
1580 u8 fw_reset_seq_cnt;
1581 u32 fw_reset_seq_regs[16];
1582 u32 fw_reset_seq_vals[16];
1583 u32 fw_reset_seq_delay_msec[16];
1584 u32 echo_req_data1;
1585 u32 echo_req_data2;
1586 struct devlink_health_reporter *fw_reporter;
1587 /* Protects severity and remedy */
1588 struct mutex lock;
1589 enum bnxt_health_severity severity;
1590 enum bnxt_health_remedy remedy;
1591 u32 arrests;
1592 u32 discoveries;
1593 u32 survivals;
1594 u32 fatalities;
1595 u32 diagnoses;
1596};
1597
1598#define BNXT_FW_HEALTH_REG_TYPE_MASK 3
1599#define BNXT_FW_HEALTH_REG_TYPE_CFG 0
1600#define BNXT_FW_HEALTH_REG_TYPE_GRC 1
1601#define BNXT_FW_HEALTH_REG_TYPE_BAR0 2
1602#define BNXT_FW_HEALTH_REG_TYPE_BAR1 3
1603
1604#define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
1605#define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
1606
1607#define BNXT_FW_HEALTH_WIN_BASE 0x3000
1608#define BNXT_FW_HEALTH_WIN_MAP_OFF 8
1609
1610#define BNXT_FW_HEALTH_WIN_OFF(reg) (BNXT_FW_HEALTH_WIN_BASE + \
1611 ((reg) & BNXT_GRC_OFFSET_MASK))
1612
1613#define BNXT_FW_STATUS_HEALTH_MSK 0xffff
1614#define BNXT_FW_STATUS_HEALTHY 0x8000
1615#define BNXT_FW_STATUS_SHUTDOWN 0x100000
1616#define BNXT_FW_STATUS_RECOVERING 0x400000
1617
1618#define BNXT_FW_IS_HEALTHY(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\
1619 BNXT_FW_STATUS_HEALTHY)
1620
1621#define BNXT_FW_IS_BOOTING(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \
1622 BNXT_FW_STATUS_HEALTHY)
1623
1624#define BNXT_FW_IS_ERR(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \
1625 BNXT_FW_STATUS_HEALTHY)
1626
1627#define BNXT_FW_IS_RECOVERING(sts) (BNXT_FW_IS_ERR(sts) && \
1628 ((sts) & BNXT_FW_STATUS_RECOVERING))
1629
1630#define BNXT_FW_RETRY 5
1631#define BNXT_FW_IF_RETRY 10
1632#define BNXT_FW_SLOT_RESET_RETRY 4
1633
1634enum board_idx {
1635 BCM57301,
1636 BCM57302,
1637 BCM57304,
1638 BCM57417_NPAR,
1639 BCM58700,
1640 BCM57311,
1641 BCM57312,
1642 BCM57402,
1643 BCM57404,
1644 BCM57406,
1645 BCM57402_NPAR,
1646 BCM57407,
1647 BCM57412,
1648 BCM57414,
1649 BCM57416,
1650 BCM57417,
1651 BCM57412_NPAR,
1652 BCM57314,
1653 BCM57417_SFP,
1654 BCM57416_SFP,
1655 BCM57404_NPAR,
1656 BCM57406_NPAR,
1657 BCM57407_SFP,
1658 BCM57407_NPAR,
1659 BCM57414_NPAR,
1660 BCM57416_NPAR,
1661 BCM57452,
1662 BCM57454,
1663 BCM5745x_NPAR,
1664 BCM57508,
1665 BCM57504,
1666 BCM57502,
1667 BCM57508_NPAR,
1668 BCM57504_NPAR,
1669 BCM57502_NPAR,
1670 BCM58802,
1671 BCM58804,
1672 BCM58808,
1673 NETXTREME_E_VF,
1674 NETXTREME_C_VF,
1675 NETXTREME_S_VF,
1676 NETXTREME_C_VF_HV,
1677 NETXTREME_E_VF_HV,
1678 NETXTREME_E_P5_VF,
1679 NETXTREME_E_P5_VF_HV,
1680};
1681
1682struct bnxt {
1683 void __iomem *bar0;
1684 void __iomem *bar1;
1685 void __iomem *bar2;
1686
1687 u32 reg_base;
1688 u16 chip_num;
1689#define CHIP_NUM_57301 0x16c8
1690#define CHIP_NUM_57302 0x16c9
1691#define CHIP_NUM_57304 0x16ca
1692#define CHIP_NUM_58700 0x16cd
1693#define CHIP_NUM_57402 0x16d0
1694#define CHIP_NUM_57404 0x16d1
1695#define CHIP_NUM_57406 0x16d2
1696#define CHIP_NUM_57407 0x16d5
1697
1698#define CHIP_NUM_57311 0x16ce
1699#define CHIP_NUM_57312 0x16cf
1700#define CHIP_NUM_57314 0x16df
1701#define CHIP_NUM_57317 0x16e0
1702#define CHIP_NUM_57412 0x16d6
1703#define CHIP_NUM_57414 0x16d7
1704#define CHIP_NUM_57416 0x16d8
1705#define CHIP_NUM_57417 0x16d9
1706#define CHIP_NUM_57412L 0x16da
1707#define CHIP_NUM_57414L 0x16db
1708
1709#define CHIP_NUM_5745X 0xd730
1710#define CHIP_NUM_57452 0xc452
1711#define CHIP_NUM_57454 0xc454
1712
1713#define CHIP_NUM_57508 0x1750
1714#define CHIP_NUM_57504 0x1751
1715#define CHIP_NUM_57502 0x1752
1716
1717#define CHIP_NUM_58802 0xd802
1718#define CHIP_NUM_58804 0xd804
1719#define CHIP_NUM_58808 0xd808
1720
1721 u8 chip_rev;
1722
1723#define CHIP_NUM_58818 0xd818
1724
1725#define BNXT_CHIP_NUM_5730X(chip_num) \
1726 ((chip_num) >= CHIP_NUM_57301 && \
1727 (chip_num) <= CHIP_NUM_57304)
1728
1729#define BNXT_CHIP_NUM_5740X(chip_num) \
1730 (((chip_num) >= CHIP_NUM_57402 && \
1731 (chip_num) <= CHIP_NUM_57406) || \
1732 (chip_num) == CHIP_NUM_57407)
1733
1734#define BNXT_CHIP_NUM_5731X(chip_num) \
1735 ((chip_num) == CHIP_NUM_57311 || \
1736 (chip_num) == CHIP_NUM_57312 || \
1737 (chip_num) == CHIP_NUM_57314 || \
1738 (chip_num) == CHIP_NUM_57317)
1739
1740#define BNXT_CHIP_NUM_5741X(chip_num) \
1741 ((chip_num) >= CHIP_NUM_57412 && \
1742 (chip_num) <= CHIP_NUM_57414L)
1743
1744#define BNXT_CHIP_NUM_58700(chip_num) \
1745 ((chip_num) == CHIP_NUM_58700)
1746
1747#define BNXT_CHIP_NUM_5745X(chip_num) \
1748 ((chip_num) == CHIP_NUM_5745X || \
1749 (chip_num) == CHIP_NUM_57452 || \
1750 (chip_num) == CHIP_NUM_57454)
1751
1752
1753#define BNXT_CHIP_NUM_57X0X(chip_num) \
1754 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
1755
1756#define BNXT_CHIP_NUM_57X1X(chip_num) \
1757 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
1758
1759#define BNXT_CHIP_NUM_588XX(chip_num) \
1760 ((chip_num) == CHIP_NUM_58802 || \
1761 (chip_num) == CHIP_NUM_58804 || \
1762 (chip_num) == CHIP_NUM_58808)
1763
1764#define BNXT_VPD_FLD_LEN 32
1765 char board_partno[BNXT_VPD_FLD_LEN];
1766 char board_serialno[BNXT_VPD_FLD_LEN];
1767
1768 struct net_device *dev;
1769 struct pci_dev *pdev;
1770
1771 atomic_t intr_sem;
1772
1773 u32 flags;
1774 #define BNXT_FLAG_CHIP_P5 0x1
1775 #define BNXT_FLAG_VF 0x2
1776 #define BNXT_FLAG_LRO 0x4
1777#ifdef CONFIG_INET
1778 #define BNXT_FLAG_GRO 0x8
1779#else
1780 /* Cannot support hardware GRO if CONFIG_INET is not set */
1781 #define BNXT_FLAG_GRO 0x0
1782#endif
1783 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
1784 #define BNXT_FLAG_JUMBO 0x10
1785 #define BNXT_FLAG_STRIP_VLAN 0x20
1786 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
1787 BNXT_FLAG_LRO)
1788 #define BNXT_FLAG_USING_MSIX 0x40
1789 #define BNXT_FLAG_MSIX_CAP 0x80
1790 #define BNXT_FLAG_RFS 0x100
1791 #define BNXT_FLAG_SHARED_RINGS 0x200
1792 #define BNXT_FLAG_PORT_STATS 0x400
1793 #define BNXT_FLAG_UDP_RSS_CAP 0x800
1794 #define BNXT_FLAG_NEW_RSS_CAP 0x2000
1795 #define BNXT_FLAG_WOL_CAP 0x4000
1796 #define BNXT_FLAG_ROCEV1_CAP 0x8000
1797 #define BNXT_FLAG_ROCEV2_CAP 0x10000
1798 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \
1799 BNXT_FLAG_ROCEV2_CAP)
1800 #define BNXT_FLAG_NO_AGG_RINGS 0x20000
1801 #define BNXT_FLAG_RX_PAGE_MODE 0x40000
1802 #define BNXT_FLAG_CHIP_SR2 0x80000
1803 #define BNXT_FLAG_MULTI_HOST 0x100000
1804 #define BNXT_FLAG_DSN_VALID 0x200000
1805 #define BNXT_FLAG_DOUBLE_DB 0x400000
1806 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
1807 #define BNXT_FLAG_DIM 0x2000000
1808 #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000
1809 #define BNXT_FLAG_PORT_STATS_EXT 0x10000000
1810
1811 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \
1812 BNXT_FLAG_RFS | \
1813 BNXT_FLAG_STRIP_VLAN)
1814
1815#define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
1816#define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
1817#define BNXT_NPAR(bp) ((bp)->port_partition_type)
1818#define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
1819#define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1820#define BNXT_SH_PORT_CFG_OK(bp) (BNXT_PF(bp) && \
1821 ((bp)->phy_flags & BNXT_PHY_FL_SHARED_PORT_CFG))
1822#define BNXT_PHY_CFG_ABLE(bp) ((BNXT_SINGLE_PF(bp) || \
1823 BNXT_SH_PORT_CFG_OK(bp)) && \
1824 (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED)
1825#define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1826#define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1827#define BNXT_SUPPORTS_TPA(bp) (!BNXT_CHIP_TYPE_NITRO_A0(bp) && \
1828 (!((bp)->flags & BNXT_FLAG_CHIP_P5) || \
1829 (bp)->max_tpa_v2) && !is_kdump_kernel())
1830#define BNXT_RX_JUMBO_MODE(bp) ((bp)->flags & BNXT_FLAG_JUMBO)
1831
1832#define BNXT_CHIP_SR2(bp) \
1833 ((bp)->chip_num == CHIP_NUM_58818)
1834
1835#define BNXT_CHIP_P5_THOR(bp) \
1836 ((bp)->chip_num == CHIP_NUM_57508 || \
1837 (bp)->chip_num == CHIP_NUM_57504 || \
1838 (bp)->chip_num == CHIP_NUM_57502)
1839
1840/* Chip class phase 5 */
1841#define BNXT_CHIP_P5(bp) \
1842 (BNXT_CHIP_P5_THOR(bp) || BNXT_CHIP_SR2(bp))
1843
1844/* Chip class phase 4.x */
1845#define BNXT_CHIP_P4(bp) \
1846 (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
1847 BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
1848 BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
1849 (BNXT_CHIP_NUM_58700((bp)->chip_num) && \
1850 !BNXT_CHIP_TYPE_NITRO_A0(bp)))
1851
1852#define BNXT_CHIP_P4_PLUS(bp) \
1853 (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
1854
1855 struct bnxt_en_dev *edev;
1856
1857 struct bnxt_napi **bnapi;
1858
1859 struct bnxt_rx_ring_info *rx_ring;
1860 struct bnxt_tx_ring_info *tx_ring;
1861 u16 *tx_ring_map;
1862
1863 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int,
1864 struct sk_buff *);
1865
1866 struct sk_buff * (*rx_skb_func)(struct bnxt *,
1867 struct bnxt_rx_ring_info *,
1868 u16, void *, u8 *, dma_addr_t,
1869 unsigned int);
1870
1871 u16 max_tpa_v2;
1872 u16 max_tpa;
1873 u32 rx_buf_size;
1874 u32 rx_buf_use_size; /* useable size */
1875 u16 rx_offset;
1876 u16 rx_dma_offset;
1877 enum dma_data_direction rx_dir;
1878 u32 rx_ring_size;
1879 u32 rx_agg_ring_size;
1880 u32 rx_copy_thresh;
1881 u32 rx_ring_mask;
1882 u32 rx_agg_ring_mask;
1883 int rx_nr_pages;
1884 int rx_agg_nr_pages;
1885 int rx_nr_rings;
1886 int rsscos_nr_ctxs;
1887
1888 u32 tx_ring_size;
1889 u32 tx_ring_mask;
1890 int tx_nr_pages;
1891 int tx_nr_rings;
1892 int tx_nr_rings_per_tc;
1893 int tx_nr_rings_xdp;
1894
1895 int tx_wake_thresh;
1896 int tx_push_thresh;
1897 int tx_push_size;
1898
1899 u32 cp_ring_size;
1900 u32 cp_ring_mask;
1901 u32 cp_bit;
1902 int cp_nr_pages;
1903 int cp_nr_rings;
1904
1905 /* grp_info indexed by completion ring index */
1906 struct bnxt_ring_grp_info *grp_info;
1907 struct bnxt_vnic_info *vnic_info;
1908 int nr_vnics;
1909 u16 *rss_indir_tbl;
1910 u16 rss_indir_tbl_entries;
1911 u32 rss_hash_cfg;
1912 u32 rss_hash_delta;
1913
1914 u16 max_mtu;
1915 u8 max_tc;
1916 u8 max_lltc; /* lossless TCs */
1917 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE];
1918 u8 tc_to_qidx[BNXT_MAX_QUEUE];
1919 u8 q_ids[BNXT_MAX_QUEUE];
1920 u8 max_q;
1921
1922 unsigned int current_interval;
1923#define BNXT_TIMER_INTERVAL HZ
1924
1925 struct timer_list timer;
1926
1927 unsigned long state;
1928#define BNXT_STATE_OPEN 0
1929#define BNXT_STATE_IN_SP_TASK 1
1930#define BNXT_STATE_READ_STATS 2
1931#define BNXT_STATE_FW_RESET_DET 3
1932#define BNXT_STATE_IN_FW_RESET 4
1933#define BNXT_STATE_ABORT_ERR 5
1934#define BNXT_STATE_FW_FATAL_COND 6
1935#define BNXT_STATE_DRV_REGISTERED 7
1936#define BNXT_STATE_PCI_CHANNEL_IO_FROZEN 8
1937#define BNXT_STATE_NAPI_DISABLED 9
1938#define BNXT_STATE_L2_FILTER_RETRY 10
1939#define BNXT_STATE_FW_ACTIVATE 11
1940#define BNXT_STATE_RECOVER 12
1941#define BNXT_STATE_FW_NON_FATAL_COND 13
1942#define BNXT_STATE_FW_ACTIVATE_RESET 14
1943#define BNXT_STATE_HALF_OPEN 15 /* For offline ethtool tests */
1944
1945#define BNXT_NO_FW_ACCESS(bp) \
1946 (test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) || \
1947 pci_channel_offline((bp)->pdev))
1948
1949 struct bnxt_irq *irq_tbl;
1950 int total_irqs;
1951 u8 mac_addr[ETH_ALEN];
1952
1953#ifdef CONFIG_BNXT_DCB
1954 struct ieee_pfc *ieee_pfc;
1955 struct ieee_ets *ieee_ets;
1956 u8 dcbx_cap;
1957 u8 default_pri;
1958 u8 max_dscp_value;
1959#endif /* CONFIG_BNXT_DCB */
1960
1961 u32 msg_enable;
1962
1963 u32 fw_cap;
1964 #define BNXT_FW_CAP_SHORT_CMD 0x00000001
1965 #define BNXT_FW_CAP_LLDP_AGENT 0x00000002
1966 #define BNXT_FW_CAP_DCBX_AGENT 0x00000004
1967 #define BNXT_FW_CAP_NEW_RM 0x00000008
1968 #define BNXT_FW_CAP_IF_CHANGE 0x00000010
1969 #define BNXT_FW_CAP_KONG_MB_CHNL 0x00000080
1970 #define BNXT_FW_CAP_OVS_64BIT_HANDLE 0x00000400
1971 #define BNXT_FW_CAP_TRUSTED_VF 0x00000800
1972 #define BNXT_FW_CAP_ERROR_RECOVERY 0x00002000
1973 #define BNXT_FW_CAP_PKG_VER 0x00004000
1974 #define BNXT_FW_CAP_CFA_ADV_FLOW 0x00008000
1975 #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 0x00010000
1976 #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED 0x00020000
1977 #define BNXT_FW_CAP_EXT_STATS_SUPPORTED 0x00040000
1978 #define BNXT_FW_CAP_RSS_HASH_TYPE_DELTA 0x00080000
1979 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD 0x00100000
1980 #define BNXT_FW_CAP_HOT_RESET 0x00200000
1981 #define BNXT_FW_CAP_PTP_RTC 0x00400000
1982 #define BNXT_FW_CAP_RX_ALL_PKT_TS 0x00800000
1983 #define BNXT_FW_CAP_VLAN_RX_STRIP 0x01000000
1984 #define BNXT_FW_CAP_VLAN_TX_INSERT 0x02000000
1985 #define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED 0x04000000
1986 #define BNXT_FW_CAP_LIVEPATCH 0x08000000
1987 #define BNXT_FW_CAP_PTP_PPS 0x10000000
1988 #define BNXT_FW_CAP_HOT_RESET_IF 0x20000000
1989 #define BNXT_FW_CAP_RING_MONITOR 0x40000000
1990 #define BNXT_FW_CAP_DBG_QCAPS 0x80000000
1991
1992 u32 fw_dbg_cap;
1993
1994#define BNXT_NEW_RM(bp) ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
1995 u32 hwrm_spec_code;
1996 u16 hwrm_cmd_seq;
1997 u16 hwrm_cmd_kong_seq;
1998 struct dma_pool *hwrm_dma_pool;
1999 struct hlist_head hwrm_pending_list;
2000
2001 struct rtnl_link_stats64 net_stats_prev;
2002 struct bnxt_stats_mem port_stats;
2003 struct bnxt_stats_mem rx_port_stats_ext;
2004 struct bnxt_stats_mem tx_port_stats_ext;
2005 u16 fw_rx_stats_ext_size;
2006 u16 fw_tx_stats_ext_size;
2007 u16 hw_ring_stats_size;
2008 u8 pri2cos_idx[8];
2009 u8 pri2cos_valid;
2010
2011 u16 hwrm_max_req_len;
2012 u16 hwrm_max_ext_req_len;
2013 unsigned int hwrm_cmd_timeout;
2014 unsigned int hwrm_cmd_max_timeout;
2015 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */
2016 struct hwrm_ver_get_output ver_resp;
2017#define FW_VER_STR_LEN 32
2018#define BC_HWRM_STR_LEN 21
2019#define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
2020 char fw_ver_str[FW_VER_STR_LEN];
2021 char hwrm_ver_supp[FW_VER_STR_LEN];
2022 char nvm_cfg_ver[FW_VER_STR_LEN];
2023 u64 fw_ver_code;
2024#define BNXT_FW_VER_CODE(maj, min, bld, rsv) \
2025 ((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv))
2026#define BNXT_FW_MAJ(bp) ((bp)->fw_ver_code >> 48)
2027
2028 u16 vxlan_fw_dst_port_id;
2029 u16 nge_fw_dst_port_id;
2030 __be16 vxlan_port;
2031 __be16 nge_port;
2032 u8 port_partition_type;
2033 u8 port_count;
2034 u16 br_mode;
2035
2036 struct bnxt_coal_cap coal_cap;
2037 struct bnxt_coal rx_coal;
2038 struct bnxt_coal tx_coal;
2039
2040 u32 stats_coal_ticks;
2041#define BNXT_DEF_STATS_COAL_TICKS 1000000
2042#define BNXT_MIN_STATS_COAL_TICKS 250000
2043#define BNXT_MAX_STATS_COAL_TICKS 1000000
2044
2045 struct work_struct sp_task;
2046 unsigned long sp_event;
2047#define BNXT_RX_MASK_SP_EVENT 0
2048#define BNXT_RX_NTP_FLTR_SP_EVENT 1
2049#define BNXT_LINK_CHNG_SP_EVENT 2
2050#define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
2051#define BNXT_RESET_TASK_SP_EVENT 6
2052#define BNXT_RST_RING_SP_EVENT 7
2053#define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8
2054#define BNXT_PERIODIC_STATS_SP_EVENT 9
2055#define BNXT_HWRM_PORT_MODULE_SP_EVENT 10
2056#define BNXT_RESET_TASK_SILENT_SP_EVENT 11
2057#define BNXT_LINK_SPEED_CHNG_SP_EVENT 14
2058#define BNXT_FLOW_STATS_SP_EVENT 15
2059#define BNXT_UPDATE_PHY_SP_EVENT 16
2060#define BNXT_RING_COAL_NOW_SP_EVENT 17
2061#define BNXT_FW_RESET_NOTIFY_SP_EVENT 18
2062#define BNXT_FW_EXCEPTION_SP_EVENT 19
2063#define BNXT_LINK_CFG_CHANGE_SP_EVENT 21
2064#define BNXT_FW_ECHO_REQUEST_SP_EVENT 23
2065
2066 struct delayed_work fw_reset_task;
2067 int fw_reset_state;
2068#define BNXT_FW_RESET_STATE_POLL_VF 1
2069#define BNXT_FW_RESET_STATE_RESET_FW 2
2070#define BNXT_FW_RESET_STATE_ENABLE_DEV 3
2071#define BNXT_FW_RESET_STATE_POLL_FW 4
2072#define BNXT_FW_RESET_STATE_OPENING 5
2073#define BNXT_FW_RESET_STATE_POLL_FW_DOWN 6
2074
2075 u16 fw_reset_min_dsecs;
2076#define BNXT_DFLT_FW_RST_MIN_DSECS 20
2077 u16 fw_reset_max_dsecs;
2078#define BNXT_DFLT_FW_RST_MAX_DSECS 60
2079 unsigned long fw_reset_timestamp;
2080
2081 struct bnxt_fw_health *fw_health;
2082
2083 struct bnxt_hw_resc hw_resc;
2084 struct bnxt_pf_info pf;
2085 struct bnxt_ctx_mem_info *ctx;
2086#ifdef CONFIG_BNXT_SRIOV
2087 int nr_vfs;
2088 struct bnxt_vf_info vf;
2089 wait_queue_head_t sriov_cfg_wait;
2090 bool sriov_cfg;
2091#define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
2092#endif
2093
2094#if BITS_PER_LONG == 32
2095 /* ensure atomic 64-bit doorbell writes on 32-bit systems. */
2096 spinlock_t db_lock;
2097#endif
2098 int db_size;
2099
2100#define BNXT_NTP_FLTR_MAX_FLTR 4096
2101#define BNXT_NTP_FLTR_HASH_SIZE 512
2102#define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
2103 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
2104 spinlock_t ntp_fltr_lock; /* for hash table add, del */
2105
2106 unsigned long *ntp_fltr_bmap;
2107 int ntp_fltr_count;
2108
2109 /* To protect link related settings during link changes and
2110 * ethtool settings changes.
2111 */
2112 struct mutex link_lock;
2113 struct bnxt_link_info link_info;
2114 struct ethtool_eee eee;
2115 u32 lpi_tmr_lo;
2116 u32 lpi_tmr_hi;
2117
2118 /* copied from flags and flags2 in hwrm_port_phy_qcaps_output */
2119 u32 phy_flags;
2120#define BNXT_PHY_FL_EEE_CAP PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED
2121#define BNXT_PHY_FL_EXT_LPBK PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED
2122#define BNXT_PHY_FL_AN_PHY_LPBK PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED
2123#define BNXT_PHY_FL_SHARED_PORT_CFG PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED
2124#define BNXT_PHY_FL_PORT_STATS_NO_RESET PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET
2125#define BNXT_PHY_FL_NO_PHY_LPBK PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED
2126#define BNXT_PHY_FL_FW_MANAGED_LKDN PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN
2127#define BNXT_PHY_FL_NO_FCS PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS
2128#define BNXT_PHY_FL_NO_PAUSE (PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED << 8)
2129#define BNXT_PHY_FL_NO_PFC (PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED << 8)
2130#define BNXT_PHY_FL_BANK_SEL (PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED << 8)
2131
2132 u8 num_tests;
2133 struct bnxt_test_info *test_info;
2134
2135 u8 wol_filter_id;
2136 u8 wol;
2137
2138 u8 num_leds;
2139 struct bnxt_led_info leds[BNXT_MAX_LED];
2140 u16 dump_flag;
2141#define BNXT_DUMP_LIVE 0
2142#define BNXT_DUMP_CRASH 1
2143
2144 struct bpf_prog *xdp_prog;
2145
2146 struct bnxt_ptp_cfg *ptp_cfg;
2147 u8 ptp_all_rx_tstamp;
2148
2149 /* devlink interface and vf-rep structs */
2150 struct devlink *dl;
2151 struct devlink_port dl_port;
2152 enum devlink_eswitch_mode eswitch_mode;
2153 struct bnxt_vf_rep **vf_reps; /* array of vf-rep ptrs */
2154 u16 *cfa_code_map; /* cfa_code -> vf_idx map */
2155 u8 dsn[8];
2156 struct bnxt_tc_info *tc_info;
2157 struct list_head tc_indr_block_list;
2158 struct dentry *debugfs_pdev;
2159 struct device *hwmon_dev;
2160 enum board_idx board_idx;
2161};
2162
2163#define BNXT_NUM_RX_RING_STATS 8
2164#define BNXT_NUM_TX_RING_STATS 8
2165#define BNXT_NUM_TPA_RING_STATS 4
2166#define BNXT_NUM_TPA_RING_STATS_P5 5
2167#define BNXT_NUM_TPA_RING_STATS_P5_SR2 6
2168
2169#define BNXT_RING_STATS_SIZE_P5 \
2170 ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \
2171 BNXT_NUM_TPA_RING_STATS_P5) * 8)
2172
2173#define BNXT_RING_STATS_SIZE_P5_SR2 \
2174 ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \
2175 BNXT_NUM_TPA_RING_STATS_P5_SR2) * 8)
2176
2177#define BNXT_GET_RING_STATS64(sw, counter) \
2178 (*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))
2179
2180#define BNXT_GET_RX_PORT_STATS64(sw, counter) \
2181 (*((sw) + offsetof(struct rx_port_stats, counter) / 8))
2182
2183#define BNXT_GET_TX_PORT_STATS64(sw, counter) \
2184 (*((sw) + offsetof(struct tx_port_stats, counter) / 8))
2185
2186#define BNXT_PORT_STATS_SIZE \
2187 (sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024)
2188
2189#define BNXT_TX_PORT_STATS_BYTE_OFFSET \
2190 (sizeof(struct rx_port_stats) + 512)
2191
2192#define BNXT_RX_STATS_OFFSET(counter) \
2193 (offsetof(struct rx_port_stats, counter) / 8)
2194
2195#define BNXT_TX_STATS_OFFSET(counter) \
2196 ((offsetof(struct tx_port_stats, counter) + \
2197 BNXT_TX_PORT_STATS_BYTE_OFFSET) / 8)
2198
2199#define BNXT_RX_STATS_EXT_OFFSET(counter) \
2200 (offsetof(struct rx_port_stats_ext, counter) / 8)
2201
2202#define BNXT_RX_STATS_EXT_NUM_LEGACY \
2203 BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)
2204
2205#define BNXT_TX_STATS_EXT_OFFSET(counter) \
2206 (offsetof(struct tx_port_stats_ext, counter) / 8)
2207
2208#define BNXT_HW_FEATURE_VLAN_ALL_RX \
2209 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)
2210#define BNXT_HW_FEATURE_VLAN_ALL_TX \
2211 (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX)
2212
2213#define I2C_DEV_ADDR_A0 0xa0
2214#define I2C_DEV_ADDR_A2 0xa2
2215#define SFF_DIAG_SUPPORT_OFFSET 0x5c
2216#define SFF_MODULE_ID_SFP 0x3
2217#define SFF_MODULE_ID_QSFP 0xc
2218#define SFF_MODULE_ID_QSFP_PLUS 0xd
2219#define SFF_MODULE_ID_QSFP28 0x11
2220#define BNXT_MAX_PHY_I2C_RESP_SIZE 64
2221
2222static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
2223{
2224 /* Tell compiler to fetch tx indices from memory. */
2225 barrier();
2226
2227 return bp->tx_ring_size -
2228 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
2229}
2230
2231static inline void bnxt_writeq(struct bnxt *bp, u64 val,
2232 volatile void __iomem *addr)
2233{
2234#if BITS_PER_LONG == 32
2235 spin_lock(&bp->db_lock);
2236 lo_hi_writeq(val, addr);
2237 spin_unlock(&bp->db_lock);
2238#else
2239 writeq(val, addr);
2240#endif
2241}
2242
2243static inline void bnxt_writeq_relaxed(struct bnxt *bp, u64 val,
2244 volatile void __iomem *addr)
2245{
2246#if BITS_PER_LONG == 32
2247 spin_lock(&bp->db_lock);
2248 lo_hi_writeq_relaxed(val, addr);
2249 spin_unlock(&bp->db_lock);
2250#else
2251 writeq_relaxed(val, addr);
2252#endif
2253}
2254
2255/* For TX and RX ring doorbells with no ordering guarantee*/
2256static inline void bnxt_db_write_relaxed(struct bnxt *bp,
2257 struct bnxt_db_info *db, u32 idx)
2258{
2259 if (bp->flags & BNXT_FLAG_CHIP_P5) {
2260 bnxt_writeq_relaxed(bp, db->db_key64 | idx, db->doorbell);
2261 } else {
2262 u32 db_val = db->db_key32 | idx;
2263
2264 writel_relaxed(db_val, db->doorbell);
2265 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2266 writel_relaxed(db_val, db->doorbell);
2267 }
2268}
2269
2270/* For TX and RX ring doorbells */
2271static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
2272 u32 idx)
2273{
2274 if (bp->flags & BNXT_FLAG_CHIP_P5) {
2275 bnxt_writeq(bp, db->db_key64 | idx, db->doorbell);
2276 } else {
2277 u32 db_val = db->db_key32 | idx;
2278
2279 writel(db_val, db->doorbell);
2280 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2281 writel(db_val, db->doorbell);
2282 }
2283}
2284
2285/* Must hold rtnl_lock */
2286static inline bool bnxt_sriov_cfg(struct bnxt *bp)
2287{
2288#if defined(CONFIG_BNXT_SRIOV)
2289 return BNXT_PF(bp) && (bp->pf.active_vfs || bp->sriov_cfg);
2290#else
2291 return false;
2292#endif
2293}
2294
2295extern const u16 bnxt_lhint_arr[];
2296
2297int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
2298 u16 prod, gfp_t gfp);
2299void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
2300u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);
2301void bnxt_set_tpa_flags(struct bnxt *bp);
2302void bnxt_set_ring_params(struct bnxt *);
2303int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
2304int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap,
2305 int bmap_size, bool async_only);
2306int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp);
2307int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings);
2308int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
2309int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
2310int bnxt_nq_rings_in_use(struct bnxt *bp);
2311int bnxt_hwrm_set_coal(struct bnxt *);
2312void bnxt_free_ctx_mem(struct bnxt *bp);
2313unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
2314unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
2315unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
2316unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
2317int bnxt_get_avail_msix(struct bnxt *bp, int num);
2318int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
2319void bnxt_tx_disable(struct bnxt *bp);
2320void bnxt_tx_enable(struct bnxt *bp);
2321void bnxt_report_link(struct bnxt *bp);
2322int bnxt_update_link(struct bnxt *bp, bool chng_link_state);
2323int bnxt_hwrm_set_pause(struct bnxt *);
2324int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
2325int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset);
2326int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
2327int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
2328int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
2329int bnxt_hwrm_func_qcaps(struct bnxt *bp);
2330int bnxt_hwrm_fw_set_time(struct bnxt *);
2331int bnxt_open_nic(struct bnxt *, bool, bool);
2332int bnxt_half_open_nic(struct bnxt *bp);
2333void bnxt_half_close_nic(struct bnxt *bp);
2334void bnxt_reenable_sriov(struct bnxt *bp);
2335int bnxt_close_nic(struct bnxt *, bool, bool);
2336int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
2337 u32 *reg_buf);
2338void bnxt_fw_exception(struct bnxt *bp);
2339void bnxt_fw_reset(struct bnxt *bp);
2340int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
2341 int tx_xdp);
2342int bnxt_fw_init_one(struct bnxt *bp);
2343bool bnxt_hwrm_reset_permitted(struct bnxt *bp);
2344int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
2345int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
2346int bnxt_restore_pf_fw_resources(struct bnxt *bp);
2347int bnxt_get_port_parent_id(struct net_device *dev,
2348 struct netdev_phys_item_id *ppid);
2349void bnxt_dim_work(struct work_struct *work);
2350int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);
2351void bnxt_print_device_info(struct bnxt *bp);
2352#endif