Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * TI HECC (CAN) device driver
4 *
5 * This driver supports TI's HECC (High End CAN Controller module) and the
6 * specs for the same is available at <http://www.ti.com>
7 *
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
9 * Copyright (C) 2019 Jeroen Hofstee <jhofstee@victronenergy.com>
10 */
11
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/errno.h>
17#include <linux/ethtool.h>
18#include <linux/netdevice.h>
19#include <linux/skbuff.h>
20#include <linux/platform_device.h>
21#include <linux/clk.h>
22#include <linux/io.h>
23#include <linux/of.h>
24#include <linux/regulator/consumer.h>
25
26#include <linux/can/dev.h>
27#include <linux/can/error.h>
28#include <linux/can/rx-offload.h>
29
30#define DRV_NAME "ti_hecc"
31#define HECC_MODULE_VERSION "0.7"
32MODULE_VERSION(HECC_MODULE_VERSION);
33#define DRV_DESC "TI High End CAN Controller Driver " HECC_MODULE_VERSION
34
35/* TX / RX Mailbox Configuration */
36#define HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */
37#define MAX_TX_PRIO 0x3F /* hardware value - do not change */
38
39/* Important Note: TX mailbox configuration
40 * TX mailboxes should be restricted to the number of SKB buffers to avoid
41 * maintaining SKB buffers separately. TX mailboxes should be a power of 2
42 * for the mailbox logic to work. Top mailbox numbers are reserved for RX
43 * and lower mailboxes for TX.
44 *
45 * HECC_MAX_TX_MBOX HECC_MB_TX_SHIFT
46 * 4 (default) 2
47 * 8 3
48 * 16 4
49 */
50#define HECC_MB_TX_SHIFT 2 /* as per table above */
51#define HECC_MAX_TX_MBOX BIT(HECC_MB_TX_SHIFT)
52
53#define HECC_TX_PRIO_SHIFT (HECC_MB_TX_SHIFT)
54#define HECC_TX_PRIO_MASK (MAX_TX_PRIO << HECC_MB_TX_SHIFT)
55#define HECC_TX_MB_MASK (HECC_MAX_TX_MBOX - 1)
56#define HECC_TX_MASK ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK)
57
58/* RX mailbox configuration
59 *
60 * The remaining mailboxes are used for reception and are delivered
61 * based on their timestamp, to avoid a hardware race when CANME is
62 * changed while CAN-bus traffic is being received.
63 */
64#define HECC_MAX_RX_MBOX (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX)
65#define HECC_RX_FIRST_MBOX (HECC_MAX_MAILBOXES - 1)
66#define HECC_RX_LAST_MBOX (HECC_MAX_TX_MBOX)
67
68/* TI HECC module registers */
69#define HECC_CANME 0x0 /* Mailbox enable */
70#define HECC_CANMD 0x4 /* Mailbox direction */
71#define HECC_CANTRS 0x8 /* Transmit request set */
72#define HECC_CANTRR 0xC /* Transmit request */
73#define HECC_CANTA 0x10 /* Transmission acknowledge */
74#define HECC_CANAA 0x14 /* Abort acknowledge */
75#define HECC_CANRMP 0x18 /* Receive message pending */
76#define HECC_CANRML 0x1C /* Receive message lost */
77#define HECC_CANRFP 0x20 /* Remote frame pending */
78#define HECC_CANGAM 0x24 /* SECC only:Global acceptance mask */
79#define HECC_CANMC 0x28 /* Master control */
80#define HECC_CANBTC 0x2C /* Bit timing configuration */
81#define HECC_CANES 0x30 /* Error and status */
82#define HECC_CANTEC 0x34 /* Transmit error counter */
83#define HECC_CANREC 0x38 /* Receive error counter */
84#define HECC_CANGIF0 0x3C /* Global interrupt flag 0 */
85#define HECC_CANGIM 0x40 /* Global interrupt mask */
86#define HECC_CANGIF1 0x44 /* Global interrupt flag 1 */
87#define HECC_CANMIM 0x48 /* Mailbox interrupt mask */
88#define HECC_CANMIL 0x4C /* Mailbox interrupt level */
89#define HECC_CANOPC 0x50 /* Overwrite protection control */
90#define HECC_CANTIOC 0x54 /* Transmit I/O control */
91#define HECC_CANRIOC 0x58 /* Receive I/O control */
92#define HECC_CANLNT 0x5C /* HECC only: Local network time */
93#define HECC_CANTOC 0x60 /* HECC only: Time-out control */
94#define HECC_CANTOS 0x64 /* HECC only: Time-out status */
95#define HECC_CANTIOCE 0x68 /* SCC only:Enhanced TX I/O control */
96#define HECC_CANRIOCE 0x6C /* SCC only:Enhanced RX I/O control */
97
98/* TI HECC RAM registers */
99#define HECC_CANMOTS 0x80 /* Message object time stamp */
100
101/* Mailbox registers */
102#define HECC_CANMID 0x0
103#define HECC_CANMCF 0x4
104#define HECC_CANMDL 0x8
105#define HECC_CANMDH 0xC
106
107#define HECC_SET_REG 0xFFFFFFFF
108#define HECC_CANID_MASK 0x3FF /* 18 bits mask for extended id's */
109#define HECC_CCE_WAIT_COUNT 100 /* Wait for ~1 sec for CCE bit */
110
111#define HECC_CANMC_SCM BIT(13) /* SCC compat mode */
112#define HECC_CANMC_CCR BIT(12) /* Change config request */
113#define HECC_CANMC_PDR BIT(11) /* Local Power down - for sleep mode */
114#define HECC_CANMC_ABO BIT(7) /* Auto Bus On */
115#define HECC_CANMC_STM BIT(6) /* Self test mode - loopback */
116#define HECC_CANMC_SRES BIT(5) /* Software reset */
117
118#define HECC_CANTIOC_EN BIT(3) /* Enable CAN TX I/O pin */
119#define HECC_CANRIOC_EN BIT(3) /* Enable CAN RX I/O pin */
120
121#define HECC_CANMID_IDE BIT(31) /* Extended frame format */
122#define HECC_CANMID_AME BIT(30) /* Acceptance mask enable */
123#define HECC_CANMID_AAM BIT(29) /* Auto answer mode */
124
125#define HECC_CANES_FE BIT(24) /* form error */
126#define HECC_CANES_BE BIT(23) /* bit error */
127#define HECC_CANES_SA1 BIT(22) /* stuck at dominant error */
128#define HECC_CANES_CRCE BIT(21) /* CRC error */
129#define HECC_CANES_SE BIT(20) /* stuff bit error */
130#define HECC_CANES_ACKE BIT(19) /* ack error */
131#define HECC_CANES_BO BIT(18) /* Bus off status */
132#define HECC_CANES_EP BIT(17) /* Error passive status */
133#define HECC_CANES_EW BIT(16) /* Error warning status */
134#define HECC_CANES_SMA BIT(5) /* suspend mode ack */
135#define HECC_CANES_CCE BIT(4) /* Change config enabled */
136#define HECC_CANES_PDA BIT(3) /* Power down mode ack */
137
138#define HECC_CANBTC_SAM BIT(7) /* sample points */
139
140#define HECC_BUS_ERROR (HECC_CANES_FE | HECC_CANES_BE |\
141 HECC_CANES_CRCE | HECC_CANES_SE |\
142 HECC_CANES_ACKE)
143#define HECC_CANES_FLAGS (HECC_BUS_ERROR | HECC_CANES_BO |\
144 HECC_CANES_EP | HECC_CANES_EW)
145
146#define HECC_CANMCF_RTR BIT(4) /* Remote transmit request */
147
148#define HECC_CANGIF_MAIF BIT(17) /* Message alarm interrupt */
149#define HECC_CANGIF_TCOIF BIT(16) /* Timer counter overflow int */
150#define HECC_CANGIF_GMIF BIT(15) /* Global mailbox interrupt */
151#define HECC_CANGIF_AAIF BIT(14) /* Abort ack interrupt */
152#define HECC_CANGIF_WDIF BIT(13) /* Write denied interrupt */
153#define HECC_CANGIF_WUIF BIT(12) /* Wake up interrupt */
154#define HECC_CANGIF_RMLIF BIT(11) /* Receive message lost interrupt */
155#define HECC_CANGIF_BOIF BIT(10) /* Bus off interrupt */
156#define HECC_CANGIF_EPIF BIT(9) /* Error passive interrupt */
157#define HECC_CANGIF_WLIF BIT(8) /* Warning level interrupt */
158#define HECC_CANGIF_MBOX_MASK 0x1F /* Mailbox number mask */
159#define HECC_CANGIM_I1EN BIT(1) /* Int line 1 enable */
160#define HECC_CANGIM_I0EN BIT(0) /* Int line 0 enable */
161#define HECC_CANGIM_DEF_MASK 0x700 /* only busoff/warning/passive */
162#define HECC_CANGIM_SIL BIT(2) /* system interrupts to int line 1 */
163
164/* CAN Bittiming constants as per HECC specs */
165static const struct can_bittiming_const ti_hecc_bittiming_const = {
166 .name = DRV_NAME,
167 .tseg1_min = 1,
168 .tseg1_max = 16,
169 .tseg2_min = 1,
170 .tseg2_max = 8,
171 .sjw_max = 4,
172 .brp_min = 1,
173 .brp_max = 256,
174 .brp_inc = 1,
175};
176
177struct ti_hecc_priv {
178 struct can_priv can; /* MUST be first member/field */
179 struct can_rx_offload offload;
180 struct net_device *ndev;
181 struct clk *clk;
182 void __iomem *base;
183 void __iomem *hecc_ram;
184 void __iomem *mbx;
185 bool use_hecc1int;
186 spinlock_t mbx_lock; /* CANME register needs protection */
187 u32 tx_head;
188 u32 tx_tail;
189 struct regulator *reg_xceiver;
190};
191
192static inline int get_tx_head_mb(struct ti_hecc_priv *priv)
193{
194 return priv->tx_head & HECC_TX_MB_MASK;
195}
196
197static inline int get_tx_tail_mb(struct ti_hecc_priv *priv)
198{
199 return priv->tx_tail & HECC_TX_MB_MASK;
200}
201
202static inline int get_tx_head_prio(struct ti_hecc_priv *priv)
203{
204 return (priv->tx_head >> HECC_TX_PRIO_SHIFT) & MAX_TX_PRIO;
205}
206
207static inline void hecc_write_lam(struct ti_hecc_priv *priv, u32 mbxno, u32 val)
208{
209 __raw_writel(val, priv->hecc_ram + mbxno * 4);
210}
211
212static inline u32 hecc_read_stamp(struct ti_hecc_priv *priv, u32 mbxno)
213{
214 return __raw_readl(priv->hecc_ram + HECC_CANMOTS + mbxno * 4);
215}
216
217static inline void hecc_write_mbx(struct ti_hecc_priv *priv, u32 mbxno,
218 u32 reg, u32 val)
219{
220 __raw_writel(val, priv->mbx + mbxno * 0x10 + reg);
221}
222
223static inline u32 hecc_read_mbx(struct ti_hecc_priv *priv, u32 mbxno, u32 reg)
224{
225 return __raw_readl(priv->mbx + mbxno * 0x10 + reg);
226}
227
228static inline void hecc_write(struct ti_hecc_priv *priv, u32 reg, u32 val)
229{
230 __raw_writel(val, priv->base + reg);
231}
232
233static inline u32 hecc_read(struct ti_hecc_priv *priv, int reg)
234{
235 return __raw_readl(priv->base + reg);
236}
237
238static inline void hecc_set_bit(struct ti_hecc_priv *priv, int reg,
239 u32 bit_mask)
240{
241 hecc_write(priv, reg, hecc_read(priv, reg) | bit_mask);
242}
243
244static inline void hecc_clear_bit(struct ti_hecc_priv *priv, int reg,
245 u32 bit_mask)
246{
247 hecc_write(priv, reg, hecc_read(priv, reg) & ~bit_mask);
248}
249
250static inline u32 hecc_get_bit(struct ti_hecc_priv *priv, int reg, u32 bit_mask)
251{
252 return (hecc_read(priv, reg) & bit_mask) ? 1 : 0;
253}
254
255static int ti_hecc_set_btc(struct ti_hecc_priv *priv)
256{
257 struct can_bittiming *bit_timing = &priv->can.bittiming;
258 u32 can_btc;
259
260 can_btc = (bit_timing->phase_seg2 - 1) & 0x7;
261 can_btc |= ((bit_timing->phase_seg1 + bit_timing->prop_seg - 1)
262 & 0xF) << 3;
263 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) {
264 if (bit_timing->brp > 4)
265 can_btc |= HECC_CANBTC_SAM;
266 else
267 netdev_warn(priv->ndev,
268 "WARN: Triple sampling not set due to h/w limitations");
269 }
270 can_btc |= ((bit_timing->sjw - 1) & 0x3) << 8;
271 can_btc |= ((bit_timing->brp - 1) & 0xFF) << 16;
272
273 /* ERM being set to 0 by default meaning resync at falling edge */
274
275 hecc_write(priv, HECC_CANBTC, can_btc);
276 netdev_info(priv->ndev, "setting CANBTC=%#x\n", can_btc);
277
278 return 0;
279}
280
281static int ti_hecc_transceiver_switch(const struct ti_hecc_priv *priv,
282 int on)
283{
284 if (!priv->reg_xceiver)
285 return 0;
286
287 if (on)
288 return regulator_enable(priv->reg_xceiver);
289 else
290 return regulator_disable(priv->reg_xceiver);
291}
292
293static void ti_hecc_reset(struct net_device *ndev)
294{
295 u32 cnt;
296 struct ti_hecc_priv *priv = netdev_priv(ndev);
297
298 netdev_dbg(ndev, "resetting hecc ...\n");
299 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SRES);
300
301 /* Set change control request and wait till enabled */
302 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
303
304 /* INFO: It has been observed that at times CCE bit may not be
305 * set and hw seems to be ok even if this bit is not set so
306 * timing out with a timing of 1ms to respect the specs
307 */
308 cnt = HECC_CCE_WAIT_COUNT;
309 while (!hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {
310 --cnt;
311 udelay(10);
312 }
313
314 /* Note: On HECC, BTC can be programmed only in initialization mode, so
315 * it is expected that the can bittiming parameters are set via ip
316 * utility before the device is opened
317 */
318 ti_hecc_set_btc(priv);
319
320 /* Clear CCR (and CANMC register) and wait for CCE = 0 enable */
321 hecc_write(priv, HECC_CANMC, 0);
322
323 /* INFO: CAN net stack handles bus off and hence disabling auto-bus-on
324 * hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_ABO);
325 */
326
327 /* INFO: It has been observed that at times CCE bit may not be
328 * set and hw seems to be ok even if this bit is not set so
329 */
330 cnt = HECC_CCE_WAIT_COUNT;
331 while (hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {
332 --cnt;
333 udelay(10);
334 }
335
336 /* Enable TX and RX I/O Control pins */
337 hecc_write(priv, HECC_CANTIOC, HECC_CANTIOC_EN);
338 hecc_write(priv, HECC_CANRIOC, HECC_CANRIOC_EN);
339
340 /* Clear registers for clean operation */
341 hecc_write(priv, HECC_CANTA, HECC_SET_REG);
342 hecc_write(priv, HECC_CANRMP, HECC_SET_REG);
343 hecc_write(priv, HECC_CANGIF0, HECC_SET_REG);
344 hecc_write(priv, HECC_CANGIF1, HECC_SET_REG);
345 hecc_write(priv, HECC_CANME, 0);
346 hecc_write(priv, HECC_CANMD, 0);
347
348 /* SCC compat mode NOT supported (and not needed too) */
349 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SCM);
350}
351
352static void ti_hecc_start(struct net_device *ndev)
353{
354 struct ti_hecc_priv *priv = netdev_priv(ndev);
355 u32 cnt, mbxno, mbx_mask;
356
357 /* put HECC in initialization mode and set btc */
358 ti_hecc_reset(ndev);
359
360 priv->tx_head = HECC_TX_MASK;
361 priv->tx_tail = HECC_TX_MASK;
362
363 /* Enable local and global acceptance mask registers */
364 hecc_write(priv, HECC_CANGAM, HECC_SET_REG);
365
366 /* Prepare configured mailboxes to receive messages */
367 for (cnt = 0; cnt < HECC_MAX_RX_MBOX; cnt++) {
368 mbxno = HECC_MAX_MAILBOXES - 1 - cnt;
369 mbx_mask = BIT(mbxno);
370 hecc_clear_bit(priv, HECC_CANME, mbx_mask);
371 hecc_write_mbx(priv, mbxno, HECC_CANMID, HECC_CANMID_AME);
372 hecc_write_lam(priv, mbxno, HECC_SET_REG);
373 hecc_set_bit(priv, HECC_CANMD, mbx_mask);
374 hecc_set_bit(priv, HECC_CANME, mbx_mask);
375 hecc_set_bit(priv, HECC_CANMIM, mbx_mask);
376 }
377
378 /* Enable tx interrupts */
379 hecc_set_bit(priv, HECC_CANMIM, BIT(HECC_MAX_TX_MBOX) - 1);
380
381 /* Prevent message over-write to create a rx fifo, but not for
382 * the lowest priority mailbox, since that allows detecting
383 * overflows instead of the hardware silently dropping the
384 * messages.
385 */
386 mbx_mask = ~BIT(HECC_RX_LAST_MBOX);
387 hecc_write(priv, HECC_CANOPC, mbx_mask);
388
389 /* Enable interrupts */
390 if (priv->use_hecc1int) {
391 hecc_write(priv, HECC_CANMIL, HECC_SET_REG);
392 hecc_write(priv, HECC_CANGIM, HECC_CANGIM_DEF_MASK |
393 HECC_CANGIM_I1EN | HECC_CANGIM_SIL);
394 } else {
395 hecc_write(priv, HECC_CANMIL, 0);
396 hecc_write(priv, HECC_CANGIM,
397 HECC_CANGIM_DEF_MASK | HECC_CANGIM_I0EN);
398 }
399 priv->can.state = CAN_STATE_ERROR_ACTIVE;
400}
401
402static void ti_hecc_stop(struct net_device *ndev)
403{
404 struct ti_hecc_priv *priv = netdev_priv(ndev);
405
406 /* Disable the CPK; stop sending, erroring and acking */
407 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
408
409 /* Disable interrupts and disable mailboxes */
410 hecc_write(priv, HECC_CANGIM, 0);
411 hecc_write(priv, HECC_CANMIM, 0);
412 hecc_write(priv, HECC_CANME, 0);
413 priv->can.state = CAN_STATE_STOPPED;
414}
415
416static int ti_hecc_do_set_mode(struct net_device *ndev, enum can_mode mode)
417{
418 int ret = 0;
419
420 switch (mode) {
421 case CAN_MODE_START:
422 ti_hecc_start(ndev);
423 netif_wake_queue(ndev);
424 break;
425 default:
426 ret = -EOPNOTSUPP;
427 break;
428 }
429
430 return ret;
431}
432
433static int ti_hecc_get_berr_counter(const struct net_device *ndev,
434 struct can_berr_counter *bec)
435{
436 struct ti_hecc_priv *priv = netdev_priv(ndev);
437
438 bec->txerr = hecc_read(priv, HECC_CANTEC);
439 bec->rxerr = hecc_read(priv, HECC_CANREC);
440
441 return 0;
442}
443
444/* ti_hecc_xmit: HECC Transmit
445 *
446 * The transmit mailboxes start from 0 to HECC_MAX_TX_MBOX. In HECC the
447 * priority of the mailbox for transmission is dependent upon priority setting
448 * field in mailbox registers. The mailbox with highest value in priority field
449 * is transmitted first. Only when two mailboxes have the same value in
450 * priority field the highest numbered mailbox is transmitted first.
451 *
452 * To utilize the HECC priority feature as described above we start with the
453 * highest numbered mailbox with highest priority level and move on to the next
454 * mailbox with the same priority level and so on. Once we loop through all the
455 * transmit mailboxes we choose the next priority level (lower) and so on
456 * until we reach the lowest priority level on the lowest numbered mailbox
457 * when we stop transmission until all mailboxes are transmitted and then
458 * restart at highest numbered mailbox with highest priority.
459 *
460 * Two counters (head and tail) are used to track the next mailbox to transmit
461 * and to track the echo buffer for already transmitted mailbox. The queue
462 * is stopped when all the mailboxes are busy or when there is a priority
463 * value roll-over happens.
464 */
465static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev)
466{
467 struct ti_hecc_priv *priv = netdev_priv(ndev);
468 struct can_frame *cf = (struct can_frame *)skb->data;
469 u32 mbxno, mbx_mask, data;
470 unsigned long flags;
471
472 if (can_dev_dropped_skb(ndev, skb))
473 return NETDEV_TX_OK;
474
475 mbxno = get_tx_head_mb(priv);
476 mbx_mask = BIT(mbxno);
477 spin_lock_irqsave(&priv->mbx_lock, flags);
478 if (unlikely(hecc_read(priv, HECC_CANME) & mbx_mask)) {
479 spin_unlock_irqrestore(&priv->mbx_lock, flags);
480 netif_stop_queue(ndev);
481 netdev_err(priv->ndev,
482 "BUG: TX mbx not ready tx_head=%08X, tx_tail=%08X\n",
483 priv->tx_head, priv->tx_tail);
484 return NETDEV_TX_BUSY;
485 }
486 spin_unlock_irqrestore(&priv->mbx_lock, flags);
487
488 /* Prepare mailbox for transmission */
489 data = cf->len | (get_tx_head_prio(priv) << 8);
490 if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */
491 data |= HECC_CANMCF_RTR;
492 hecc_write_mbx(priv, mbxno, HECC_CANMCF, data);
493
494 if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */
495 data = (cf->can_id & CAN_EFF_MASK) | HECC_CANMID_IDE;
496 else /* Standard frame format */
497 data = (cf->can_id & CAN_SFF_MASK) << 18;
498 hecc_write_mbx(priv, mbxno, HECC_CANMID, data);
499 hecc_write_mbx(priv, mbxno, HECC_CANMDL,
500 be32_to_cpu(*(__be32 *)(cf->data)));
501 if (cf->len > 4)
502 hecc_write_mbx(priv, mbxno, HECC_CANMDH,
503 be32_to_cpu(*(__be32 *)(cf->data + 4)));
504 else
505 *(u32 *)(cf->data + 4) = 0;
506 can_put_echo_skb(skb, ndev, mbxno, 0);
507
508 spin_lock_irqsave(&priv->mbx_lock, flags);
509 --priv->tx_head;
510 if ((hecc_read(priv, HECC_CANME) & BIT(get_tx_head_mb(priv))) ||
511 (priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK) {
512 netif_stop_queue(ndev);
513 }
514 hecc_set_bit(priv, HECC_CANME, mbx_mask);
515 spin_unlock_irqrestore(&priv->mbx_lock, flags);
516
517 hecc_write(priv, HECC_CANTRS, mbx_mask);
518
519 return NETDEV_TX_OK;
520}
521
522static inline
523struct ti_hecc_priv *rx_offload_to_priv(struct can_rx_offload *offload)
524{
525 return container_of(offload, struct ti_hecc_priv, offload);
526}
527
528static struct sk_buff *ti_hecc_mailbox_read(struct can_rx_offload *offload,
529 unsigned int mbxno, u32 *timestamp,
530 bool drop)
531{
532 struct ti_hecc_priv *priv = rx_offload_to_priv(offload);
533 struct sk_buff *skb;
534 struct can_frame *cf;
535 u32 data, mbx_mask;
536
537 mbx_mask = BIT(mbxno);
538
539 if (unlikely(drop)) {
540 skb = ERR_PTR(-ENOBUFS);
541 goto mark_as_read;
542 }
543
544 skb = alloc_can_skb(offload->dev, &cf);
545 if (unlikely(!skb)) {
546 skb = ERR_PTR(-ENOMEM);
547 goto mark_as_read;
548 }
549
550 data = hecc_read_mbx(priv, mbxno, HECC_CANMID);
551 if (data & HECC_CANMID_IDE)
552 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG;
553 else
554 cf->can_id = (data >> 18) & CAN_SFF_MASK;
555
556 data = hecc_read_mbx(priv, mbxno, HECC_CANMCF);
557 if (data & HECC_CANMCF_RTR)
558 cf->can_id |= CAN_RTR_FLAG;
559 cf->len = can_cc_dlc2len(data & 0xF);
560
561 data = hecc_read_mbx(priv, mbxno, HECC_CANMDL);
562 *(__be32 *)(cf->data) = cpu_to_be32(data);
563 if (cf->len > 4) {
564 data = hecc_read_mbx(priv, mbxno, HECC_CANMDH);
565 *(__be32 *)(cf->data + 4) = cpu_to_be32(data);
566 }
567
568 *timestamp = hecc_read_stamp(priv, mbxno);
569
570 /* Check for FIFO overrun.
571 *
572 * All but the last RX mailbox have activated overwrite
573 * protection. So skip check for overrun, if we're not
574 * handling the last RX mailbox.
575 *
576 * As the overwrite protection for the last RX mailbox is
577 * disabled, the CAN core might update while we're reading
578 * it. This means the skb might be inconsistent.
579 *
580 * Return an error to let rx-offload discard this CAN frame.
581 */
582 if (unlikely(mbxno == HECC_RX_LAST_MBOX &&
583 hecc_read(priv, HECC_CANRML) & mbx_mask))
584 skb = ERR_PTR(-ENOBUFS);
585
586 mark_as_read:
587 hecc_write(priv, HECC_CANRMP, mbx_mask);
588
589 return skb;
590}
591
592static int ti_hecc_error(struct net_device *ndev, int int_status,
593 int err_status)
594{
595 struct ti_hecc_priv *priv = netdev_priv(ndev);
596 struct can_frame *cf;
597 struct sk_buff *skb;
598 u32 timestamp;
599 int err;
600
601 if (err_status & HECC_BUS_ERROR) {
602 /* propagate the error condition to the can stack */
603 skb = alloc_can_err_skb(ndev, &cf);
604 if (!skb) {
605 if (net_ratelimit())
606 netdev_err(priv->ndev,
607 "%s: alloc_can_err_skb() failed\n",
608 __func__);
609 return -ENOMEM;
610 }
611
612 ++priv->can.can_stats.bus_error;
613 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
614 if (err_status & HECC_CANES_FE)
615 cf->data[2] |= CAN_ERR_PROT_FORM;
616 if (err_status & HECC_CANES_BE)
617 cf->data[2] |= CAN_ERR_PROT_BIT;
618 if (err_status & HECC_CANES_SE)
619 cf->data[2] |= CAN_ERR_PROT_STUFF;
620 if (err_status & HECC_CANES_CRCE)
621 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
622 if (err_status & HECC_CANES_ACKE)
623 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
624
625 timestamp = hecc_read(priv, HECC_CANLNT);
626 err = can_rx_offload_queue_timestamp(&priv->offload, skb,
627 timestamp);
628 if (err)
629 ndev->stats.rx_fifo_errors++;
630 }
631
632 hecc_write(priv, HECC_CANES, HECC_CANES_FLAGS);
633
634 return 0;
635}
636
637static void ti_hecc_change_state(struct net_device *ndev,
638 enum can_state rx_state,
639 enum can_state tx_state)
640{
641 struct ti_hecc_priv *priv = netdev_priv(ndev);
642 struct can_frame *cf;
643 struct sk_buff *skb;
644 u32 timestamp;
645 int err;
646
647 skb = alloc_can_err_skb(priv->ndev, &cf);
648 if (unlikely(!skb)) {
649 priv->can.state = max(tx_state, rx_state);
650 return;
651 }
652
653 can_change_state(priv->ndev, cf, tx_state, rx_state);
654
655 if (max(tx_state, rx_state) != CAN_STATE_BUS_OFF) {
656 cf->can_id |= CAN_ERR_CNT;
657 cf->data[6] = hecc_read(priv, HECC_CANTEC);
658 cf->data[7] = hecc_read(priv, HECC_CANREC);
659 }
660
661 timestamp = hecc_read(priv, HECC_CANLNT);
662 err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp);
663 if (err)
664 ndev->stats.rx_fifo_errors++;
665}
666
667static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id)
668{
669 struct net_device *ndev = (struct net_device *)dev_id;
670 struct ti_hecc_priv *priv = netdev_priv(ndev);
671 struct net_device_stats *stats = &ndev->stats;
672 u32 mbxno, mbx_mask, int_status, err_status, stamp;
673 unsigned long flags, rx_pending;
674 u32 handled = 0;
675
676 int_status = hecc_read(priv,
677 priv->use_hecc1int ?
678 HECC_CANGIF1 : HECC_CANGIF0);
679
680 if (!int_status)
681 return IRQ_NONE;
682
683 err_status = hecc_read(priv, HECC_CANES);
684 if (unlikely(err_status & HECC_CANES_FLAGS))
685 ti_hecc_error(ndev, int_status, err_status);
686
687 if (unlikely(int_status & HECC_CANGIM_DEF_MASK)) {
688 enum can_state rx_state, tx_state;
689 u32 rec = hecc_read(priv, HECC_CANREC);
690 u32 tec = hecc_read(priv, HECC_CANTEC);
691
692 if (int_status & HECC_CANGIF_WLIF) {
693 handled |= HECC_CANGIF_WLIF;
694 rx_state = rec >= tec ? CAN_STATE_ERROR_WARNING : 0;
695 tx_state = rec <= tec ? CAN_STATE_ERROR_WARNING : 0;
696 netdev_dbg(priv->ndev, "Error Warning interrupt\n");
697 ti_hecc_change_state(ndev, rx_state, tx_state);
698 }
699
700 if (int_status & HECC_CANGIF_EPIF) {
701 handled |= HECC_CANGIF_EPIF;
702 rx_state = rec >= tec ? CAN_STATE_ERROR_PASSIVE : 0;
703 tx_state = rec <= tec ? CAN_STATE_ERROR_PASSIVE : 0;
704 netdev_dbg(priv->ndev, "Error passive interrupt\n");
705 ti_hecc_change_state(ndev, rx_state, tx_state);
706 }
707
708 if (int_status & HECC_CANGIF_BOIF) {
709 handled |= HECC_CANGIF_BOIF;
710 rx_state = CAN_STATE_BUS_OFF;
711 tx_state = CAN_STATE_BUS_OFF;
712 netdev_dbg(priv->ndev, "Bus off interrupt\n");
713
714 /* Disable all interrupts */
715 hecc_write(priv, HECC_CANGIM, 0);
716 can_bus_off(ndev);
717 ti_hecc_change_state(ndev, rx_state, tx_state);
718 }
719 } else if (unlikely(priv->can.state != CAN_STATE_ERROR_ACTIVE)) {
720 enum can_state new_state, tx_state, rx_state;
721 u32 rec = hecc_read(priv, HECC_CANREC);
722 u32 tec = hecc_read(priv, HECC_CANTEC);
723
724 if (rec >= 128 || tec >= 128)
725 new_state = CAN_STATE_ERROR_PASSIVE;
726 else if (rec >= 96 || tec >= 96)
727 new_state = CAN_STATE_ERROR_WARNING;
728 else
729 new_state = CAN_STATE_ERROR_ACTIVE;
730
731 if (new_state < priv->can.state) {
732 rx_state = rec >= tec ? new_state : 0;
733 tx_state = rec <= tec ? new_state : 0;
734 ti_hecc_change_state(ndev, rx_state, tx_state);
735 }
736 }
737
738 if (int_status & HECC_CANGIF_GMIF) {
739 while (priv->tx_tail - priv->tx_head > 0) {
740 mbxno = get_tx_tail_mb(priv);
741 mbx_mask = BIT(mbxno);
742 if (!(mbx_mask & hecc_read(priv, HECC_CANTA)))
743 break;
744 hecc_write(priv, HECC_CANTA, mbx_mask);
745 spin_lock_irqsave(&priv->mbx_lock, flags);
746 hecc_clear_bit(priv, HECC_CANME, mbx_mask);
747 spin_unlock_irqrestore(&priv->mbx_lock, flags);
748 stamp = hecc_read_stamp(priv, mbxno);
749 stats->tx_bytes +=
750 can_rx_offload_get_echo_skb_queue_timestamp(&priv->offload,
751 mbxno, stamp, NULL);
752 stats->tx_packets++;
753 --priv->tx_tail;
754 }
755
756 /* restart queue if wrap-up or if queue stalled on last pkt */
757 if ((priv->tx_head == priv->tx_tail &&
758 ((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) ||
759 (((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) &&
760 ((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK)))
761 netif_wake_queue(ndev);
762
763 /* offload RX mailboxes and let NAPI deliver them */
764 while ((rx_pending = hecc_read(priv, HECC_CANRMP))) {
765 can_rx_offload_irq_offload_timestamp(&priv->offload,
766 rx_pending);
767 }
768 }
769
770 /* clear all interrupt conditions - read back to avoid spurious ints */
771 if (priv->use_hecc1int) {
772 hecc_write(priv, HECC_CANGIF1, handled);
773 int_status = hecc_read(priv, HECC_CANGIF1);
774 } else {
775 hecc_write(priv, HECC_CANGIF0, handled);
776 int_status = hecc_read(priv, HECC_CANGIF0);
777 }
778
779 can_rx_offload_irq_finish(&priv->offload);
780
781 return IRQ_HANDLED;
782}
783
784static int ti_hecc_open(struct net_device *ndev)
785{
786 struct ti_hecc_priv *priv = netdev_priv(ndev);
787 int err;
788
789 err = request_irq(ndev->irq, ti_hecc_interrupt, IRQF_SHARED,
790 ndev->name, ndev);
791 if (err) {
792 netdev_err(ndev, "error requesting interrupt\n");
793 return err;
794 }
795
796 ti_hecc_transceiver_switch(priv, 1);
797
798 /* Open common can device */
799 err = open_candev(ndev);
800 if (err) {
801 netdev_err(ndev, "open_candev() failed %d\n", err);
802 ti_hecc_transceiver_switch(priv, 0);
803 free_irq(ndev->irq, ndev);
804 return err;
805 }
806
807 ti_hecc_start(ndev);
808 can_rx_offload_enable(&priv->offload);
809 netif_start_queue(ndev);
810
811 return 0;
812}
813
814static int ti_hecc_close(struct net_device *ndev)
815{
816 struct ti_hecc_priv *priv = netdev_priv(ndev);
817
818 netif_stop_queue(ndev);
819 can_rx_offload_disable(&priv->offload);
820 ti_hecc_stop(ndev);
821 free_irq(ndev->irq, ndev);
822 close_candev(ndev);
823 ti_hecc_transceiver_switch(priv, 0);
824
825 return 0;
826}
827
828static const struct net_device_ops ti_hecc_netdev_ops = {
829 .ndo_open = ti_hecc_open,
830 .ndo_stop = ti_hecc_close,
831 .ndo_start_xmit = ti_hecc_xmit,
832 .ndo_change_mtu = can_change_mtu,
833};
834
835static const struct ethtool_ops ti_hecc_ethtool_ops = {
836 .get_ts_info = ethtool_op_get_ts_info,
837};
838
839static const struct of_device_id ti_hecc_dt_ids[] = {
840 {
841 .compatible = "ti,am3517-hecc",
842 },
843 { }
844};
845MODULE_DEVICE_TABLE(of, ti_hecc_dt_ids);
846
847static int ti_hecc_probe(struct platform_device *pdev)
848{
849 struct net_device *ndev = (struct net_device *)0;
850 struct ti_hecc_priv *priv;
851 struct device_node *np = pdev->dev.of_node;
852 struct regulator *reg_xceiver;
853 int err = -ENODEV;
854
855 if (!IS_ENABLED(CONFIG_OF) || !np)
856 return -EINVAL;
857
858 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
859 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
860 return -EPROBE_DEFER;
861 else if (IS_ERR(reg_xceiver))
862 reg_xceiver = NULL;
863
864 ndev = alloc_candev(sizeof(struct ti_hecc_priv), HECC_MAX_TX_MBOX);
865 if (!ndev) {
866 dev_err(&pdev->dev, "alloc_candev failed\n");
867 return -ENOMEM;
868 }
869 priv = netdev_priv(ndev);
870
871 /* handle hecc memory */
872 priv->base = devm_platform_ioremap_resource_byname(pdev, "hecc");
873 if (IS_ERR(priv->base)) {
874 dev_err(&pdev->dev, "hecc ioremap failed\n");
875 err = PTR_ERR(priv->base);
876 goto probe_exit_candev;
877 }
878
879 /* handle hecc-ram memory */
880 priv->hecc_ram = devm_platform_ioremap_resource_byname(pdev,
881 "hecc-ram");
882 if (IS_ERR(priv->hecc_ram)) {
883 dev_err(&pdev->dev, "hecc-ram ioremap failed\n");
884 err = PTR_ERR(priv->hecc_ram);
885 goto probe_exit_candev;
886 }
887
888 /* handle mbx memory */
889 priv->mbx = devm_platform_ioremap_resource_byname(pdev, "mbx");
890 if (IS_ERR(priv->mbx)) {
891 dev_err(&pdev->dev, "mbx ioremap failed\n");
892 err = PTR_ERR(priv->mbx);
893 goto probe_exit_candev;
894 }
895
896 ndev->irq = platform_get_irq(pdev, 0);
897 if (ndev->irq < 0) {
898 err = ndev->irq;
899 goto probe_exit_candev;
900 }
901
902 priv->ndev = ndev;
903 priv->reg_xceiver = reg_xceiver;
904 priv->use_hecc1int = of_property_read_bool(np, "ti,use-hecc1int");
905
906 priv->can.bittiming_const = &ti_hecc_bittiming_const;
907 priv->can.do_set_mode = ti_hecc_do_set_mode;
908 priv->can.do_get_berr_counter = ti_hecc_get_berr_counter;
909 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
910
911 spin_lock_init(&priv->mbx_lock);
912 ndev->flags |= IFF_ECHO;
913 platform_set_drvdata(pdev, ndev);
914 SET_NETDEV_DEV(ndev, &pdev->dev);
915 ndev->netdev_ops = &ti_hecc_netdev_ops;
916 ndev->ethtool_ops = &ti_hecc_ethtool_ops;
917
918 priv->clk = clk_get(&pdev->dev, "hecc_ck");
919 if (IS_ERR(priv->clk)) {
920 dev_err(&pdev->dev, "No clock available\n");
921 err = PTR_ERR(priv->clk);
922 priv->clk = NULL;
923 goto probe_exit_candev;
924 }
925 priv->can.clock.freq = clk_get_rate(priv->clk);
926
927 err = clk_prepare_enable(priv->clk);
928 if (err) {
929 dev_err(&pdev->dev, "clk_prepare_enable() failed\n");
930 goto probe_exit_release_clk;
931 }
932
933 priv->offload.mailbox_read = ti_hecc_mailbox_read;
934 priv->offload.mb_first = HECC_RX_FIRST_MBOX;
935 priv->offload.mb_last = HECC_RX_LAST_MBOX;
936 err = can_rx_offload_add_timestamp(ndev, &priv->offload);
937 if (err) {
938 dev_err(&pdev->dev, "can_rx_offload_add_timestamp() failed\n");
939 goto probe_exit_disable_clk;
940 }
941
942 err = register_candev(ndev);
943 if (err) {
944 dev_err(&pdev->dev, "register_candev() failed\n");
945 goto probe_exit_offload;
946 }
947
948 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n",
949 priv->base, (u32)ndev->irq);
950
951 return 0;
952
953probe_exit_offload:
954 can_rx_offload_del(&priv->offload);
955probe_exit_disable_clk:
956 clk_disable_unprepare(priv->clk);
957probe_exit_release_clk:
958 clk_put(priv->clk);
959probe_exit_candev:
960 free_candev(ndev);
961
962 return err;
963}
964
965static void ti_hecc_remove(struct platform_device *pdev)
966{
967 struct net_device *ndev = platform_get_drvdata(pdev);
968 struct ti_hecc_priv *priv = netdev_priv(ndev);
969
970 unregister_candev(ndev);
971 clk_disable_unprepare(priv->clk);
972 clk_put(priv->clk);
973 can_rx_offload_del(&priv->offload);
974 free_candev(ndev);
975}
976
977#ifdef CONFIG_PM
978static int ti_hecc_suspend(struct platform_device *pdev, pm_message_t state)
979{
980 struct net_device *dev = platform_get_drvdata(pdev);
981 struct ti_hecc_priv *priv = netdev_priv(dev);
982
983 if (netif_running(dev)) {
984 netif_stop_queue(dev);
985 netif_device_detach(dev);
986 }
987
988 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_PDR);
989 priv->can.state = CAN_STATE_SLEEPING;
990
991 clk_disable_unprepare(priv->clk);
992
993 return 0;
994}
995
996static int ti_hecc_resume(struct platform_device *pdev)
997{
998 struct net_device *dev = platform_get_drvdata(pdev);
999 struct ti_hecc_priv *priv = netdev_priv(dev);
1000 int err;
1001
1002 err = clk_prepare_enable(priv->clk);
1003 if (err)
1004 return err;
1005
1006 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_PDR);
1007 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1008
1009 if (netif_running(dev)) {
1010 netif_device_attach(dev);
1011 netif_start_queue(dev);
1012 }
1013
1014 return 0;
1015}
1016#else
1017#define ti_hecc_suspend NULL
1018#define ti_hecc_resume NULL
1019#endif
1020
1021/* TI HECC netdevice driver: platform driver structure */
1022static struct platform_driver ti_hecc_driver = {
1023 .driver = {
1024 .name = DRV_NAME,
1025 .of_match_table = ti_hecc_dt_ids,
1026 },
1027 .probe = ti_hecc_probe,
1028 .remove_new = ti_hecc_remove,
1029 .suspend = ti_hecc_suspend,
1030 .resume = ti_hecc_resume,
1031};
1032
1033module_platform_driver(ti_hecc_driver);
1034
1035MODULE_AUTHOR("Anant Gole <anantgole@ti.com>");
1036MODULE_LICENSE("GPL v2");
1037MODULE_DESCRIPTION(DRV_DESC);
1038MODULE_ALIAS("platform:" DRV_NAME);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * TI HECC (CAN) device driver
4 *
5 * This driver supports TI's HECC (High End CAN Controller module) and the
6 * specs for the same is available at <http://www.ti.com>
7 *
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
9 * Copyright (C) 2019 Jeroen Hofstee <jhofstee@victronenergy.com>
10 */
11
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/errno.h>
17#include <linux/ethtool.h>
18#include <linux/netdevice.h>
19#include <linux/skbuff.h>
20#include <linux/platform_device.h>
21#include <linux/clk.h>
22#include <linux/io.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/regulator/consumer.h>
26
27#include <linux/can/dev.h>
28#include <linux/can/error.h>
29#include <linux/can/rx-offload.h>
30
31#define DRV_NAME "ti_hecc"
32#define HECC_MODULE_VERSION "0.7"
33MODULE_VERSION(HECC_MODULE_VERSION);
34#define DRV_DESC "TI High End CAN Controller Driver " HECC_MODULE_VERSION
35
36/* TX / RX Mailbox Configuration */
37#define HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */
38#define MAX_TX_PRIO 0x3F /* hardware value - do not change */
39
40/* Important Note: TX mailbox configuration
41 * TX mailboxes should be restricted to the number of SKB buffers to avoid
42 * maintaining SKB buffers separately. TX mailboxes should be a power of 2
43 * for the mailbox logic to work. Top mailbox numbers are reserved for RX
44 * and lower mailboxes for TX.
45 *
46 * HECC_MAX_TX_MBOX HECC_MB_TX_SHIFT
47 * 4 (default) 2
48 * 8 3
49 * 16 4
50 */
51#define HECC_MB_TX_SHIFT 2 /* as per table above */
52#define HECC_MAX_TX_MBOX BIT(HECC_MB_TX_SHIFT)
53
54#define HECC_TX_PRIO_SHIFT (HECC_MB_TX_SHIFT)
55#define HECC_TX_PRIO_MASK (MAX_TX_PRIO << HECC_MB_TX_SHIFT)
56#define HECC_TX_MB_MASK (HECC_MAX_TX_MBOX - 1)
57#define HECC_TX_MASK ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK)
58
59/* RX mailbox configuration
60 *
61 * The remaining mailboxes are used for reception and are delivered
62 * based on their timestamp, to avoid a hardware race when CANME is
63 * changed while CAN-bus traffic is being received.
64 */
65#define HECC_MAX_RX_MBOX (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX)
66#define HECC_RX_FIRST_MBOX (HECC_MAX_MAILBOXES - 1)
67#define HECC_RX_LAST_MBOX (HECC_MAX_TX_MBOX)
68
69/* TI HECC module registers */
70#define HECC_CANME 0x0 /* Mailbox enable */
71#define HECC_CANMD 0x4 /* Mailbox direction */
72#define HECC_CANTRS 0x8 /* Transmit request set */
73#define HECC_CANTRR 0xC /* Transmit request */
74#define HECC_CANTA 0x10 /* Transmission acknowledge */
75#define HECC_CANAA 0x14 /* Abort acknowledge */
76#define HECC_CANRMP 0x18 /* Receive message pending */
77#define HECC_CANRML 0x1C /* Receive message lost */
78#define HECC_CANRFP 0x20 /* Remote frame pending */
79#define HECC_CANGAM 0x24 /* SECC only:Global acceptance mask */
80#define HECC_CANMC 0x28 /* Master control */
81#define HECC_CANBTC 0x2C /* Bit timing configuration */
82#define HECC_CANES 0x30 /* Error and status */
83#define HECC_CANTEC 0x34 /* Transmit error counter */
84#define HECC_CANREC 0x38 /* Receive error counter */
85#define HECC_CANGIF0 0x3C /* Global interrupt flag 0 */
86#define HECC_CANGIM 0x40 /* Global interrupt mask */
87#define HECC_CANGIF1 0x44 /* Global interrupt flag 1 */
88#define HECC_CANMIM 0x48 /* Mailbox interrupt mask */
89#define HECC_CANMIL 0x4C /* Mailbox interrupt level */
90#define HECC_CANOPC 0x50 /* Overwrite protection control */
91#define HECC_CANTIOC 0x54 /* Transmit I/O control */
92#define HECC_CANRIOC 0x58 /* Receive I/O control */
93#define HECC_CANLNT 0x5C /* HECC only: Local network time */
94#define HECC_CANTOC 0x60 /* HECC only: Time-out control */
95#define HECC_CANTOS 0x64 /* HECC only: Time-out status */
96#define HECC_CANTIOCE 0x68 /* SCC only:Enhanced TX I/O control */
97#define HECC_CANRIOCE 0x6C /* SCC only:Enhanced RX I/O control */
98
99/* TI HECC RAM registers */
100#define HECC_CANMOTS 0x80 /* Message object time stamp */
101
102/* Mailbox registers */
103#define HECC_CANMID 0x0
104#define HECC_CANMCF 0x4
105#define HECC_CANMDL 0x8
106#define HECC_CANMDH 0xC
107
108#define HECC_SET_REG 0xFFFFFFFF
109#define HECC_CANID_MASK 0x3FF /* 18 bits mask for extended id's */
110#define HECC_CCE_WAIT_COUNT 100 /* Wait for ~1 sec for CCE bit */
111
112#define HECC_CANMC_SCM BIT(13) /* SCC compat mode */
113#define HECC_CANMC_CCR BIT(12) /* Change config request */
114#define HECC_CANMC_PDR BIT(11) /* Local Power down - for sleep mode */
115#define HECC_CANMC_ABO BIT(7) /* Auto Bus On */
116#define HECC_CANMC_STM BIT(6) /* Self test mode - loopback */
117#define HECC_CANMC_SRES BIT(5) /* Software reset */
118
119#define HECC_CANTIOC_EN BIT(3) /* Enable CAN TX I/O pin */
120#define HECC_CANRIOC_EN BIT(3) /* Enable CAN RX I/O pin */
121
122#define HECC_CANMID_IDE BIT(31) /* Extended frame format */
123#define HECC_CANMID_AME BIT(30) /* Acceptance mask enable */
124#define HECC_CANMID_AAM BIT(29) /* Auto answer mode */
125
126#define HECC_CANES_FE BIT(24) /* form error */
127#define HECC_CANES_BE BIT(23) /* bit error */
128#define HECC_CANES_SA1 BIT(22) /* stuck at dominant error */
129#define HECC_CANES_CRCE BIT(21) /* CRC error */
130#define HECC_CANES_SE BIT(20) /* stuff bit error */
131#define HECC_CANES_ACKE BIT(19) /* ack error */
132#define HECC_CANES_BO BIT(18) /* Bus off status */
133#define HECC_CANES_EP BIT(17) /* Error passive status */
134#define HECC_CANES_EW BIT(16) /* Error warning status */
135#define HECC_CANES_SMA BIT(5) /* suspend mode ack */
136#define HECC_CANES_CCE BIT(4) /* Change config enabled */
137#define HECC_CANES_PDA BIT(3) /* Power down mode ack */
138
139#define HECC_CANBTC_SAM BIT(7) /* sample points */
140
141#define HECC_BUS_ERROR (HECC_CANES_FE | HECC_CANES_BE |\
142 HECC_CANES_CRCE | HECC_CANES_SE |\
143 HECC_CANES_ACKE)
144#define HECC_CANES_FLAGS (HECC_BUS_ERROR | HECC_CANES_BO |\
145 HECC_CANES_EP | HECC_CANES_EW)
146
147#define HECC_CANMCF_RTR BIT(4) /* Remote transmit request */
148
149#define HECC_CANGIF_MAIF BIT(17) /* Message alarm interrupt */
150#define HECC_CANGIF_TCOIF BIT(16) /* Timer counter overflow int */
151#define HECC_CANGIF_GMIF BIT(15) /* Global mailbox interrupt */
152#define HECC_CANGIF_AAIF BIT(14) /* Abort ack interrupt */
153#define HECC_CANGIF_WDIF BIT(13) /* Write denied interrupt */
154#define HECC_CANGIF_WUIF BIT(12) /* Wake up interrupt */
155#define HECC_CANGIF_RMLIF BIT(11) /* Receive message lost interrupt */
156#define HECC_CANGIF_BOIF BIT(10) /* Bus off interrupt */
157#define HECC_CANGIF_EPIF BIT(9) /* Error passive interrupt */
158#define HECC_CANGIF_WLIF BIT(8) /* Warning level interrupt */
159#define HECC_CANGIF_MBOX_MASK 0x1F /* Mailbox number mask */
160#define HECC_CANGIM_I1EN BIT(1) /* Int line 1 enable */
161#define HECC_CANGIM_I0EN BIT(0) /* Int line 0 enable */
162#define HECC_CANGIM_DEF_MASK 0x700 /* only busoff/warning/passive */
163#define HECC_CANGIM_SIL BIT(2) /* system interrupts to int line 1 */
164
165/* CAN Bittiming constants as per HECC specs */
166static const struct can_bittiming_const ti_hecc_bittiming_const = {
167 .name = DRV_NAME,
168 .tseg1_min = 1,
169 .tseg1_max = 16,
170 .tseg2_min = 1,
171 .tseg2_max = 8,
172 .sjw_max = 4,
173 .brp_min = 1,
174 .brp_max = 256,
175 .brp_inc = 1,
176};
177
178struct ti_hecc_priv {
179 struct can_priv can; /* MUST be first member/field */
180 struct can_rx_offload offload;
181 struct net_device *ndev;
182 struct clk *clk;
183 void __iomem *base;
184 void __iomem *hecc_ram;
185 void __iomem *mbx;
186 bool use_hecc1int;
187 spinlock_t mbx_lock; /* CANME register needs protection */
188 u32 tx_head;
189 u32 tx_tail;
190 struct regulator *reg_xceiver;
191};
192
193static inline int get_tx_head_mb(struct ti_hecc_priv *priv)
194{
195 return priv->tx_head & HECC_TX_MB_MASK;
196}
197
198static inline int get_tx_tail_mb(struct ti_hecc_priv *priv)
199{
200 return priv->tx_tail & HECC_TX_MB_MASK;
201}
202
203static inline int get_tx_head_prio(struct ti_hecc_priv *priv)
204{
205 return (priv->tx_head >> HECC_TX_PRIO_SHIFT) & MAX_TX_PRIO;
206}
207
208static inline void hecc_write_lam(struct ti_hecc_priv *priv, u32 mbxno, u32 val)
209{
210 __raw_writel(val, priv->hecc_ram + mbxno * 4);
211}
212
213static inline u32 hecc_read_stamp(struct ti_hecc_priv *priv, u32 mbxno)
214{
215 return __raw_readl(priv->hecc_ram + HECC_CANMOTS + mbxno * 4);
216}
217
218static inline void hecc_write_mbx(struct ti_hecc_priv *priv, u32 mbxno,
219 u32 reg, u32 val)
220{
221 __raw_writel(val, priv->mbx + mbxno * 0x10 + reg);
222}
223
224static inline u32 hecc_read_mbx(struct ti_hecc_priv *priv, u32 mbxno, u32 reg)
225{
226 return __raw_readl(priv->mbx + mbxno * 0x10 + reg);
227}
228
229static inline void hecc_write(struct ti_hecc_priv *priv, u32 reg, u32 val)
230{
231 __raw_writel(val, priv->base + reg);
232}
233
234static inline u32 hecc_read(struct ti_hecc_priv *priv, int reg)
235{
236 return __raw_readl(priv->base + reg);
237}
238
239static inline void hecc_set_bit(struct ti_hecc_priv *priv, int reg,
240 u32 bit_mask)
241{
242 hecc_write(priv, reg, hecc_read(priv, reg) | bit_mask);
243}
244
245static inline void hecc_clear_bit(struct ti_hecc_priv *priv, int reg,
246 u32 bit_mask)
247{
248 hecc_write(priv, reg, hecc_read(priv, reg) & ~bit_mask);
249}
250
251static inline u32 hecc_get_bit(struct ti_hecc_priv *priv, int reg, u32 bit_mask)
252{
253 return (hecc_read(priv, reg) & bit_mask) ? 1 : 0;
254}
255
256static int ti_hecc_set_btc(struct ti_hecc_priv *priv)
257{
258 struct can_bittiming *bit_timing = &priv->can.bittiming;
259 u32 can_btc;
260
261 can_btc = (bit_timing->phase_seg2 - 1) & 0x7;
262 can_btc |= ((bit_timing->phase_seg1 + bit_timing->prop_seg - 1)
263 & 0xF) << 3;
264 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) {
265 if (bit_timing->brp > 4)
266 can_btc |= HECC_CANBTC_SAM;
267 else
268 netdev_warn(priv->ndev,
269 "WARN: Triple sampling not set due to h/w limitations");
270 }
271 can_btc |= ((bit_timing->sjw - 1) & 0x3) << 8;
272 can_btc |= ((bit_timing->brp - 1) & 0xFF) << 16;
273
274 /* ERM being set to 0 by default meaning resync at falling edge */
275
276 hecc_write(priv, HECC_CANBTC, can_btc);
277 netdev_info(priv->ndev, "setting CANBTC=%#x\n", can_btc);
278
279 return 0;
280}
281
282static int ti_hecc_transceiver_switch(const struct ti_hecc_priv *priv,
283 int on)
284{
285 if (!priv->reg_xceiver)
286 return 0;
287
288 if (on)
289 return regulator_enable(priv->reg_xceiver);
290 else
291 return regulator_disable(priv->reg_xceiver);
292}
293
294static void ti_hecc_reset(struct net_device *ndev)
295{
296 u32 cnt;
297 struct ti_hecc_priv *priv = netdev_priv(ndev);
298
299 netdev_dbg(ndev, "resetting hecc ...\n");
300 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SRES);
301
302 /* Set change control request and wait till enabled */
303 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
304
305 /* INFO: It has been observed that at times CCE bit may not be
306 * set and hw seems to be ok even if this bit is not set so
307 * timing out with a timing of 1ms to respect the specs
308 */
309 cnt = HECC_CCE_WAIT_COUNT;
310 while (!hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {
311 --cnt;
312 udelay(10);
313 }
314
315 /* Note: On HECC, BTC can be programmed only in initialization mode, so
316 * it is expected that the can bittiming parameters are set via ip
317 * utility before the device is opened
318 */
319 ti_hecc_set_btc(priv);
320
321 /* Clear CCR (and CANMC register) and wait for CCE = 0 enable */
322 hecc_write(priv, HECC_CANMC, 0);
323
324 /* INFO: CAN net stack handles bus off and hence disabling auto-bus-on
325 * hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_ABO);
326 */
327
328 /* INFO: It has been observed that at times CCE bit may not be
329 * set and hw seems to be ok even if this bit is not set so
330 */
331 cnt = HECC_CCE_WAIT_COUNT;
332 while (hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {
333 --cnt;
334 udelay(10);
335 }
336
337 /* Enable TX and RX I/O Control pins */
338 hecc_write(priv, HECC_CANTIOC, HECC_CANTIOC_EN);
339 hecc_write(priv, HECC_CANRIOC, HECC_CANRIOC_EN);
340
341 /* Clear registers for clean operation */
342 hecc_write(priv, HECC_CANTA, HECC_SET_REG);
343 hecc_write(priv, HECC_CANRMP, HECC_SET_REG);
344 hecc_write(priv, HECC_CANGIF0, HECC_SET_REG);
345 hecc_write(priv, HECC_CANGIF1, HECC_SET_REG);
346 hecc_write(priv, HECC_CANME, 0);
347 hecc_write(priv, HECC_CANMD, 0);
348
349 /* SCC compat mode NOT supported (and not needed too) */
350 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SCM);
351}
352
353static void ti_hecc_start(struct net_device *ndev)
354{
355 struct ti_hecc_priv *priv = netdev_priv(ndev);
356 u32 cnt, mbxno, mbx_mask;
357
358 /* put HECC in initialization mode and set btc */
359 ti_hecc_reset(ndev);
360
361 priv->tx_head = HECC_TX_MASK;
362 priv->tx_tail = HECC_TX_MASK;
363
364 /* Enable local and global acceptance mask registers */
365 hecc_write(priv, HECC_CANGAM, HECC_SET_REG);
366
367 /* Prepare configured mailboxes to receive messages */
368 for (cnt = 0; cnt < HECC_MAX_RX_MBOX; cnt++) {
369 mbxno = HECC_MAX_MAILBOXES - 1 - cnt;
370 mbx_mask = BIT(mbxno);
371 hecc_clear_bit(priv, HECC_CANME, mbx_mask);
372 hecc_write_mbx(priv, mbxno, HECC_CANMID, HECC_CANMID_AME);
373 hecc_write_lam(priv, mbxno, HECC_SET_REG);
374 hecc_set_bit(priv, HECC_CANMD, mbx_mask);
375 hecc_set_bit(priv, HECC_CANME, mbx_mask);
376 hecc_set_bit(priv, HECC_CANMIM, mbx_mask);
377 }
378
379 /* Enable tx interrupts */
380 hecc_set_bit(priv, HECC_CANMIM, BIT(HECC_MAX_TX_MBOX) - 1);
381
382 /* Prevent message over-write to create a rx fifo, but not for
383 * the lowest priority mailbox, since that allows detecting
384 * overflows instead of the hardware silently dropping the
385 * messages.
386 */
387 mbx_mask = ~BIT(HECC_RX_LAST_MBOX);
388 hecc_write(priv, HECC_CANOPC, mbx_mask);
389
390 /* Enable interrupts */
391 if (priv->use_hecc1int) {
392 hecc_write(priv, HECC_CANMIL, HECC_SET_REG);
393 hecc_write(priv, HECC_CANGIM, HECC_CANGIM_DEF_MASK |
394 HECC_CANGIM_I1EN | HECC_CANGIM_SIL);
395 } else {
396 hecc_write(priv, HECC_CANMIL, 0);
397 hecc_write(priv, HECC_CANGIM,
398 HECC_CANGIM_DEF_MASK | HECC_CANGIM_I0EN);
399 }
400 priv->can.state = CAN_STATE_ERROR_ACTIVE;
401}
402
403static void ti_hecc_stop(struct net_device *ndev)
404{
405 struct ti_hecc_priv *priv = netdev_priv(ndev);
406
407 /* Disable the CPK; stop sending, erroring and acking */
408 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
409
410 /* Disable interrupts and disable mailboxes */
411 hecc_write(priv, HECC_CANGIM, 0);
412 hecc_write(priv, HECC_CANMIM, 0);
413 hecc_write(priv, HECC_CANME, 0);
414 priv->can.state = CAN_STATE_STOPPED;
415}
416
417static int ti_hecc_do_set_mode(struct net_device *ndev, enum can_mode mode)
418{
419 int ret = 0;
420
421 switch (mode) {
422 case CAN_MODE_START:
423 ti_hecc_start(ndev);
424 netif_wake_queue(ndev);
425 break;
426 default:
427 ret = -EOPNOTSUPP;
428 break;
429 }
430
431 return ret;
432}
433
434static int ti_hecc_get_berr_counter(const struct net_device *ndev,
435 struct can_berr_counter *bec)
436{
437 struct ti_hecc_priv *priv = netdev_priv(ndev);
438
439 bec->txerr = hecc_read(priv, HECC_CANTEC);
440 bec->rxerr = hecc_read(priv, HECC_CANREC);
441
442 return 0;
443}
444
445/* ti_hecc_xmit: HECC Transmit
446 *
447 * The transmit mailboxes start from 0 to HECC_MAX_TX_MBOX. In HECC the
448 * priority of the mailbox for transmission is dependent upon priority setting
449 * field in mailbox registers. The mailbox with highest value in priority field
450 * is transmitted first. Only when two mailboxes have the same value in
451 * priority field the highest numbered mailbox is transmitted first.
452 *
453 * To utilize the HECC priority feature as described above we start with the
454 * highest numbered mailbox with highest priority level and move on to the next
455 * mailbox with the same priority level and so on. Once we loop through all the
456 * transmit mailboxes we choose the next priority level (lower) and so on
457 * until we reach the lowest priority level on the lowest numbered mailbox
458 * when we stop transmission until all mailboxes are transmitted and then
459 * restart at highest numbered mailbox with highest priority.
460 *
461 * Two counters (head and tail) are used to track the next mailbox to transmit
462 * and to track the echo buffer for already transmitted mailbox. The queue
463 * is stopped when all the mailboxes are busy or when there is a priority
464 * value roll-over happens.
465 */
466static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev)
467{
468 struct ti_hecc_priv *priv = netdev_priv(ndev);
469 struct can_frame *cf = (struct can_frame *)skb->data;
470 u32 mbxno, mbx_mask, data;
471 unsigned long flags;
472
473 if (can_dev_dropped_skb(ndev, skb))
474 return NETDEV_TX_OK;
475
476 mbxno = get_tx_head_mb(priv);
477 mbx_mask = BIT(mbxno);
478 spin_lock_irqsave(&priv->mbx_lock, flags);
479 if (unlikely(hecc_read(priv, HECC_CANME) & mbx_mask)) {
480 spin_unlock_irqrestore(&priv->mbx_lock, flags);
481 netif_stop_queue(ndev);
482 netdev_err(priv->ndev,
483 "BUG: TX mbx not ready tx_head=%08X, tx_tail=%08X\n",
484 priv->tx_head, priv->tx_tail);
485 return NETDEV_TX_BUSY;
486 }
487 spin_unlock_irqrestore(&priv->mbx_lock, flags);
488
489 /* Prepare mailbox for transmission */
490 data = cf->len | (get_tx_head_prio(priv) << 8);
491 if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */
492 data |= HECC_CANMCF_RTR;
493 hecc_write_mbx(priv, mbxno, HECC_CANMCF, data);
494
495 if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */
496 data = (cf->can_id & CAN_EFF_MASK) | HECC_CANMID_IDE;
497 else /* Standard frame format */
498 data = (cf->can_id & CAN_SFF_MASK) << 18;
499 hecc_write_mbx(priv, mbxno, HECC_CANMID, data);
500 hecc_write_mbx(priv, mbxno, HECC_CANMDL,
501 be32_to_cpu(*(__be32 *)(cf->data)));
502 if (cf->len > 4)
503 hecc_write_mbx(priv, mbxno, HECC_CANMDH,
504 be32_to_cpu(*(__be32 *)(cf->data + 4)));
505 else
506 *(u32 *)(cf->data + 4) = 0;
507 can_put_echo_skb(skb, ndev, mbxno, 0);
508
509 spin_lock_irqsave(&priv->mbx_lock, flags);
510 --priv->tx_head;
511 if ((hecc_read(priv, HECC_CANME) & BIT(get_tx_head_mb(priv))) ||
512 (priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK) {
513 netif_stop_queue(ndev);
514 }
515 hecc_set_bit(priv, HECC_CANME, mbx_mask);
516 spin_unlock_irqrestore(&priv->mbx_lock, flags);
517
518 hecc_write(priv, HECC_CANTRS, mbx_mask);
519
520 return NETDEV_TX_OK;
521}
522
523static inline
524struct ti_hecc_priv *rx_offload_to_priv(struct can_rx_offload *offload)
525{
526 return container_of(offload, struct ti_hecc_priv, offload);
527}
528
529static struct sk_buff *ti_hecc_mailbox_read(struct can_rx_offload *offload,
530 unsigned int mbxno, u32 *timestamp,
531 bool drop)
532{
533 struct ti_hecc_priv *priv = rx_offload_to_priv(offload);
534 struct sk_buff *skb;
535 struct can_frame *cf;
536 u32 data, mbx_mask;
537
538 mbx_mask = BIT(mbxno);
539
540 if (unlikely(drop)) {
541 skb = ERR_PTR(-ENOBUFS);
542 goto mark_as_read;
543 }
544
545 skb = alloc_can_skb(offload->dev, &cf);
546 if (unlikely(!skb)) {
547 skb = ERR_PTR(-ENOMEM);
548 goto mark_as_read;
549 }
550
551 data = hecc_read_mbx(priv, mbxno, HECC_CANMID);
552 if (data & HECC_CANMID_IDE)
553 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG;
554 else
555 cf->can_id = (data >> 18) & CAN_SFF_MASK;
556
557 data = hecc_read_mbx(priv, mbxno, HECC_CANMCF);
558 if (data & HECC_CANMCF_RTR)
559 cf->can_id |= CAN_RTR_FLAG;
560 cf->len = can_cc_dlc2len(data & 0xF);
561
562 data = hecc_read_mbx(priv, mbxno, HECC_CANMDL);
563 *(__be32 *)(cf->data) = cpu_to_be32(data);
564 if (cf->len > 4) {
565 data = hecc_read_mbx(priv, mbxno, HECC_CANMDH);
566 *(__be32 *)(cf->data + 4) = cpu_to_be32(data);
567 }
568
569 *timestamp = hecc_read_stamp(priv, mbxno);
570
571 /* Check for FIFO overrun.
572 *
573 * All but the last RX mailbox have activated overwrite
574 * protection. So skip check for overrun, if we're not
575 * handling the last RX mailbox.
576 *
577 * As the overwrite protection for the last RX mailbox is
578 * disabled, the CAN core might update while we're reading
579 * it. This means the skb might be inconsistent.
580 *
581 * Return an error to let rx-offload discard this CAN frame.
582 */
583 if (unlikely(mbxno == HECC_RX_LAST_MBOX &&
584 hecc_read(priv, HECC_CANRML) & mbx_mask))
585 skb = ERR_PTR(-ENOBUFS);
586
587 mark_as_read:
588 hecc_write(priv, HECC_CANRMP, mbx_mask);
589
590 return skb;
591}
592
593static int ti_hecc_error(struct net_device *ndev, int int_status,
594 int err_status)
595{
596 struct ti_hecc_priv *priv = netdev_priv(ndev);
597 struct can_frame *cf;
598 struct sk_buff *skb;
599 u32 timestamp;
600 int err;
601
602 if (err_status & HECC_BUS_ERROR) {
603 /* propagate the error condition to the can stack */
604 skb = alloc_can_err_skb(ndev, &cf);
605 if (!skb) {
606 if (net_ratelimit())
607 netdev_err(priv->ndev,
608 "%s: alloc_can_err_skb() failed\n",
609 __func__);
610 return -ENOMEM;
611 }
612
613 ++priv->can.can_stats.bus_error;
614 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
615 if (err_status & HECC_CANES_FE)
616 cf->data[2] |= CAN_ERR_PROT_FORM;
617 if (err_status & HECC_CANES_BE)
618 cf->data[2] |= CAN_ERR_PROT_BIT;
619 if (err_status & HECC_CANES_SE)
620 cf->data[2] |= CAN_ERR_PROT_STUFF;
621 if (err_status & HECC_CANES_CRCE)
622 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
623 if (err_status & HECC_CANES_ACKE)
624 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
625
626 timestamp = hecc_read(priv, HECC_CANLNT);
627 err = can_rx_offload_queue_timestamp(&priv->offload, skb,
628 timestamp);
629 if (err)
630 ndev->stats.rx_fifo_errors++;
631 }
632
633 hecc_write(priv, HECC_CANES, HECC_CANES_FLAGS);
634
635 return 0;
636}
637
638static void ti_hecc_change_state(struct net_device *ndev,
639 enum can_state rx_state,
640 enum can_state tx_state)
641{
642 struct ti_hecc_priv *priv = netdev_priv(ndev);
643 struct can_frame *cf;
644 struct sk_buff *skb;
645 u32 timestamp;
646 int err;
647
648 skb = alloc_can_err_skb(priv->ndev, &cf);
649 if (unlikely(!skb)) {
650 priv->can.state = max(tx_state, rx_state);
651 return;
652 }
653
654 can_change_state(priv->ndev, cf, tx_state, rx_state);
655
656 if (max(tx_state, rx_state) != CAN_STATE_BUS_OFF) {
657 cf->can_id |= CAN_ERR_CNT;
658 cf->data[6] = hecc_read(priv, HECC_CANTEC);
659 cf->data[7] = hecc_read(priv, HECC_CANREC);
660 }
661
662 timestamp = hecc_read(priv, HECC_CANLNT);
663 err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp);
664 if (err)
665 ndev->stats.rx_fifo_errors++;
666}
667
668static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id)
669{
670 struct net_device *ndev = (struct net_device *)dev_id;
671 struct ti_hecc_priv *priv = netdev_priv(ndev);
672 struct net_device_stats *stats = &ndev->stats;
673 u32 mbxno, mbx_mask, int_status, err_status, stamp;
674 unsigned long flags, rx_pending;
675 u32 handled = 0;
676
677 int_status = hecc_read(priv,
678 priv->use_hecc1int ?
679 HECC_CANGIF1 : HECC_CANGIF0);
680
681 if (!int_status)
682 return IRQ_NONE;
683
684 err_status = hecc_read(priv, HECC_CANES);
685 if (unlikely(err_status & HECC_CANES_FLAGS))
686 ti_hecc_error(ndev, int_status, err_status);
687
688 if (unlikely(int_status & HECC_CANGIM_DEF_MASK)) {
689 enum can_state rx_state, tx_state;
690 u32 rec = hecc_read(priv, HECC_CANREC);
691 u32 tec = hecc_read(priv, HECC_CANTEC);
692
693 if (int_status & HECC_CANGIF_WLIF) {
694 handled |= HECC_CANGIF_WLIF;
695 rx_state = rec >= tec ? CAN_STATE_ERROR_WARNING : 0;
696 tx_state = rec <= tec ? CAN_STATE_ERROR_WARNING : 0;
697 netdev_dbg(priv->ndev, "Error Warning interrupt\n");
698 ti_hecc_change_state(ndev, rx_state, tx_state);
699 }
700
701 if (int_status & HECC_CANGIF_EPIF) {
702 handled |= HECC_CANGIF_EPIF;
703 rx_state = rec >= tec ? CAN_STATE_ERROR_PASSIVE : 0;
704 tx_state = rec <= tec ? CAN_STATE_ERROR_PASSIVE : 0;
705 netdev_dbg(priv->ndev, "Error passive interrupt\n");
706 ti_hecc_change_state(ndev, rx_state, tx_state);
707 }
708
709 if (int_status & HECC_CANGIF_BOIF) {
710 handled |= HECC_CANGIF_BOIF;
711 rx_state = CAN_STATE_BUS_OFF;
712 tx_state = CAN_STATE_BUS_OFF;
713 netdev_dbg(priv->ndev, "Bus off interrupt\n");
714
715 /* Disable all interrupts */
716 hecc_write(priv, HECC_CANGIM, 0);
717 can_bus_off(ndev);
718 ti_hecc_change_state(ndev, rx_state, tx_state);
719 }
720 } else if (unlikely(priv->can.state != CAN_STATE_ERROR_ACTIVE)) {
721 enum can_state new_state, tx_state, rx_state;
722 u32 rec = hecc_read(priv, HECC_CANREC);
723 u32 tec = hecc_read(priv, HECC_CANTEC);
724
725 if (rec >= 128 || tec >= 128)
726 new_state = CAN_STATE_ERROR_PASSIVE;
727 else if (rec >= 96 || tec >= 96)
728 new_state = CAN_STATE_ERROR_WARNING;
729 else
730 new_state = CAN_STATE_ERROR_ACTIVE;
731
732 if (new_state < priv->can.state) {
733 rx_state = rec >= tec ? new_state : 0;
734 tx_state = rec <= tec ? new_state : 0;
735 ti_hecc_change_state(ndev, rx_state, tx_state);
736 }
737 }
738
739 if (int_status & HECC_CANGIF_GMIF) {
740 while (priv->tx_tail - priv->tx_head > 0) {
741 mbxno = get_tx_tail_mb(priv);
742 mbx_mask = BIT(mbxno);
743 if (!(mbx_mask & hecc_read(priv, HECC_CANTA)))
744 break;
745 hecc_write(priv, HECC_CANTA, mbx_mask);
746 spin_lock_irqsave(&priv->mbx_lock, flags);
747 hecc_clear_bit(priv, HECC_CANME, mbx_mask);
748 spin_unlock_irqrestore(&priv->mbx_lock, flags);
749 stamp = hecc_read_stamp(priv, mbxno);
750 stats->tx_bytes +=
751 can_rx_offload_get_echo_skb(&priv->offload,
752 mbxno, stamp, NULL);
753 stats->tx_packets++;
754 --priv->tx_tail;
755 }
756
757 /* restart queue if wrap-up or if queue stalled on last pkt */
758 if ((priv->tx_head == priv->tx_tail &&
759 ((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) ||
760 (((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) &&
761 ((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK)))
762 netif_wake_queue(ndev);
763
764 /* offload RX mailboxes and let NAPI deliver them */
765 while ((rx_pending = hecc_read(priv, HECC_CANRMP))) {
766 can_rx_offload_irq_offload_timestamp(&priv->offload,
767 rx_pending);
768 }
769 }
770
771 /* clear all interrupt conditions - read back to avoid spurious ints */
772 if (priv->use_hecc1int) {
773 hecc_write(priv, HECC_CANGIF1, handled);
774 int_status = hecc_read(priv, HECC_CANGIF1);
775 } else {
776 hecc_write(priv, HECC_CANGIF0, handled);
777 int_status = hecc_read(priv, HECC_CANGIF0);
778 }
779
780 can_rx_offload_irq_finish(&priv->offload);
781
782 return IRQ_HANDLED;
783}
784
785static int ti_hecc_open(struct net_device *ndev)
786{
787 struct ti_hecc_priv *priv = netdev_priv(ndev);
788 int err;
789
790 err = request_irq(ndev->irq, ti_hecc_interrupt, IRQF_SHARED,
791 ndev->name, ndev);
792 if (err) {
793 netdev_err(ndev, "error requesting interrupt\n");
794 return err;
795 }
796
797 ti_hecc_transceiver_switch(priv, 1);
798
799 /* Open common can device */
800 err = open_candev(ndev);
801 if (err) {
802 netdev_err(ndev, "open_candev() failed %d\n", err);
803 ti_hecc_transceiver_switch(priv, 0);
804 free_irq(ndev->irq, ndev);
805 return err;
806 }
807
808 ti_hecc_start(ndev);
809 can_rx_offload_enable(&priv->offload);
810 netif_start_queue(ndev);
811
812 return 0;
813}
814
815static int ti_hecc_close(struct net_device *ndev)
816{
817 struct ti_hecc_priv *priv = netdev_priv(ndev);
818
819 netif_stop_queue(ndev);
820 can_rx_offload_disable(&priv->offload);
821 ti_hecc_stop(ndev);
822 free_irq(ndev->irq, ndev);
823 close_candev(ndev);
824 ti_hecc_transceiver_switch(priv, 0);
825
826 return 0;
827}
828
829static const struct net_device_ops ti_hecc_netdev_ops = {
830 .ndo_open = ti_hecc_open,
831 .ndo_stop = ti_hecc_close,
832 .ndo_start_xmit = ti_hecc_xmit,
833 .ndo_change_mtu = can_change_mtu,
834};
835
836static const struct ethtool_ops ti_hecc_ethtool_ops = {
837 .get_ts_info = ethtool_op_get_ts_info,
838};
839
840static const struct of_device_id ti_hecc_dt_ids[] = {
841 {
842 .compatible = "ti,am3517-hecc",
843 },
844 { }
845};
846MODULE_DEVICE_TABLE(of, ti_hecc_dt_ids);
847
848static int ti_hecc_probe(struct platform_device *pdev)
849{
850 struct net_device *ndev = (struct net_device *)0;
851 struct ti_hecc_priv *priv;
852 struct device_node *np = pdev->dev.of_node;
853 struct regulator *reg_xceiver;
854 int err = -ENODEV;
855
856 if (!IS_ENABLED(CONFIG_OF) || !np)
857 return -EINVAL;
858
859 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
860 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
861 return -EPROBE_DEFER;
862 else if (IS_ERR(reg_xceiver))
863 reg_xceiver = NULL;
864
865 ndev = alloc_candev(sizeof(struct ti_hecc_priv), HECC_MAX_TX_MBOX);
866 if (!ndev) {
867 dev_err(&pdev->dev, "alloc_candev failed\n");
868 return -ENOMEM;
869 }
870 priv = netdev_priv(ndev);
871
872 /* handle hecc memory */
873 priv->base = devm_platform_ioremap_resource_byname(pdev, "hecc");
874 if (IS_ERR(priv->base)) {
875 dev_err(&pdev->dev, "hecc ioremap failed\n");
876 err = PTR_ERR(priv->base);
877 goto probe_exit_candev;
878 }
879
880 /* handle hecc-ram memory */
881 priv->hecc_ram = devm_platform_ioremap_resource_byname(pdev,
882 "hecc-ram");
883 if (IS_ERR(priv->hecc_ram)) {
884 dev_err(&pdev->dev, "hecc-ram ioremap failed\n");
885 err = PTR_ERR(priv->hecc_ram);
886 goto probe_exit_candev;
887 }
888
889 /* handle mbx memory */
890 priv->mbx = devm_platform_ioremap_resource_byname(pdev, "mbx");
891 if (IS_ERR(priv->mbx)) {
892 dev_err(&pdev->dev, "mbx ioremap failed\n");
893 err = PTR_ERR(priv->mbx);
894 goto probe_exit_candev;
895 }
896
897 ndev->irq = platform_get_irq(pdev, 0);
898 if (ndev->irq < 0) {
899 err = ndev->irq;
900 goto probe_exit_candev;
901 }
902
903 priv->ndev = ndev;
904 priv->reg_xceiver = reg_xceiver;
905 priv->use_hecc1int = of_property_read_bool(np, "ti,use-hecc1int");
906
907 priv->can.bittiming_const = &ti_hecc_bittiming_const;
908 priv->can.do_set_mode = ti_hecc_do_set_mode;
909 priv->can.do_get_berr_counter = ti_hecc_get_berr_counter;
910 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
911
912 spin_lock_init(&priv->mbx_lock);
913 ndev->flags |= IFF_ECHO;
914 platform_set_drvdata(pdev, ndev);
915 SET_NETDEV_DEV(ndev, &pdev->dev);
916 ndev->netdev_ops = &ti_hecc_netdev_ops;
917 ndev->ethtool_ops = &ti_hecc_ethtool_ops;
918
919 priv->clk = clk_get(&pdev->dev, "hecc_ck");
920 if (IS_ERR(priv->clk)) {
921 dev_err(&pdev->dev, "No clock available\n");
922 err = PTR_ERR(priv->clk);
923 priv->clk = NULL;
924 goto probe_exit_candev;
925 }
926 priv->can.clock.freq = clk_get_rate(priv->clk);
927
928 err = clk_prepare_enable(priv->clk);
929 if (err) {
930 dev_err(&pdev->dev, "clk_prepare_enable() failed\n");
931 goto probe_exit_release_clk;
932 }
933
934 priv->offload.mailbox_read = ti_hecc_mailbox_read;
935 priv->offload.mb_first = HECC_RX_FIRST_MBOX;
936 priv->offload.mb_last = HECC_RX_LAST_MBOX;
937 err = can_rx_offload_add_timestamp(ndev, &priv->offload);
938 if (err) {
939 dev_err(&pdev->dev, "can_rx_offload_add_timestamp() failed\n");
940 goto probe_exit_disable_clk;
941 }
942
943 err = register_candev(ndev);
944 if (err) {
945 dev_err(&pdev->dev, "register_candev() failed\n");
946 goto probe_exit_offload;
947 }
948
949 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n",
950 priv->base, (u32)ndev->irq);
951
952 return 0;
953
954probe_exit_offload:
955 can_rx_offload_del(&priv->offload);
956probe_exit_disable_clk:
957 clk_disable_unprepare(priv->clk);
958probe_exit_release_clk:
959 clk_put(priv->clk);
960probe_exit_candev:
961 free_candev(ndev);
962
963 return err;
964}
965
966static int ti_hecc_remove(struct platform_device *pdev)
967{
968 struct net_device *ndev = platform_get_drvdata(pdev);
969 struct ti_hecc_priv *priv = netdev_priv(ndev);
970
971 unregister_candev(ndev);
972 clk_disable_unprepare(priv->clk);
973 clk_put(priv->clk);
974 can_rx_offload_del(&priv->offload);
975 free_candev(ndev);
976
977 return 0;
978}
979
980#ifdef CONFIG_PM
981static int ti_hecc_suspend(struct platform_device *pdev, pm_message_t state)
982{
983 struct net_device *dev = platform_get_drvdata(pdev);
984 struct ti_hecc_priv *priv = netdev_priv(dev);
985
986 if (netif_running(dev)) {
987 netif_stop_queue(dev);
988 netif_device_detach(dev);
989 }
990
991 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_PDR);
992 priv->can.state = CAN_STATE_SLEEPING;
993
994 clk_disable_unprepare(priv->clk);
995
996 return 0;
997}
998
999static int ti_hecc_resume(struct platform_device *pdev)
1000{
1001 struct net_device *dev = platform_get_drvdata(pdev);
1002 struct ti_hecc_priv *priv = netdev_priv(dev);
1003 int err;
1004
1005 err = clk_prepare_enable(priv->clk);
1006 if (err)
1007 return err;
1008
1009 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_PDR);
1010 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1011
1012 if (netif_running(dev)) {
1013 netif_device_attach(dev);
1014 netif_start_queue(dev);
1015 }
1016
1017 return 0;
1018}
1019#else
1020#define ti_hecc_suspend NULL
1021#define ti_hecc_resume NULL
1022#endif
1023
1024/* TI HECC netdevice driver: platform driver structure */
1025static struct platform_driver ti_hecc_driver = {
1026 .driver = {
1027 .name = DRV_NAME,
1028 .of_match_table = ti_hecc_dt_ids,
1029 },
1030 .probe = ti_hecc_probe,
1031 .remove = ti_hecc_remove,
1032 .suspend = ti_hecc_suspend,
1033 .resume = ti_hecc_resume,
1034};
1035
1036module_platform_driver(ti_hecc_driver);
1037
1038MODULE_AUTHOR("Anant Gole <anantgole@ti.com>");
1039MODULE_LICENSE("GPL v2");
1040MODULE_DESCRIPTION(DRV_DESC);
1041MODULE_ALIAS("platform:" DRV_NAME);