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1// SPDX-License-Identifier: GPL-2.0-or-later
2/* Driver for Realtek PCI-Express card reader
3 *
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Ricky Wu <ricky_wu@realtek.com>
8 */
9
10#include <linux/module.h>
11#include <linux/delay.h>
12#include <linux/rtsx_pci.h>
13
14#include "rts5264.h"
15#include "rtsx_pcr.h"
16
17static u8 rts5264_get_ic_version(struct rtsx_pcr *pcr)
18{
19 u8 val;
20
21 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
22 return val & 0x0F;
23}
24
25static void rts5264_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
26{
27 u8 driving_3v3[4][3] = {
28 {0x88, 0x88, 0x88},
29 {0x77, 0x77, 0x77},
30 {0x99, 0x99, 0x99},
31 {0x66, 0x66, 0x66},
32 };
33 u8 driving_1v8[4][3] = {
34 {0x99, 0x99, 0x99},
35 {0x77, 0x77, 0x77},
36 {0xBB, 0xBB, 0xBB},
37 {0x65, 0x65, 0x65},
38 };
39 u8 (*driving)[3], drive_sel;
40
41 if (voltage == OUTPUT_3V3) {
42 driving = driving_3v3;
43 drive_sel = pcr->sd30_drive_sel_3v3;
44 } else {
45 driving = driving_1v8;
46 drive_sel = pcr->sd30_drive_sel_1v8;
47 }
48
49 rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
50 0xFF, driving[drive_sel][0]);
51 rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
52 0xFF, driving[drive_sel][1]);
53 rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
54 0xFF, driving[drive_sel][2]);
55}
56
57static void rts5264_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
58{
59 /* Set relink_time to 0 */
60 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
61 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
62 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
63 RELINK_TIME_MASK, 0);
64
65 if (pm_state == HOST_ENTER_S3)
66 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
67 D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
68
69 if (!runtime) {
70 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG1,
71 CD_RESUME_EN_MASK, 0);
72 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
73 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL,
74 FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
75 } else {
76 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL,
77 FORCE_PM_CONTROL | FORCE_PM_VALUE, 0);
78 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x01);
79 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
80 D3_DELINK_MODE_EN, 0);
81 rtsx_pci_write_register(pcr, RTS5264_FW_CTL,
82 RTS5264_INFORM_RTD3_COLD, RTS5264_INFORM_RTD3_COLD);
83 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG4,
84 RTS5264_FORCE_PRSNT_LOW, RTS5264_FORCE_PRSNT_LOW);
85 }
86
87 rtsx_pci_write_register(pcr, RTS5264_REG_FPDCTL,
88 SSC_POWER_DOWN, SSC_POWER_DOWN);
89}
90
91static int rts5264_enable_auto_blink(struct rtsx_pcr *pcr)
92{
93 return rtsx_pci_write_register(pcr, OLT_LED_CTL,
94 LED_SHINE_MASK, LED_SHINE_EN);
95}
96
97static int rts5264_disable_auto_blink(struct rtsx_pcr *pcr)
98{
99 return rtsx_pci_write_register(pcr, OLT_LED_CTL,
100 LED_SHINE_MASK, LED_SHINE_DISABLE);
101}
102
103static int rts5264_turn_on_led(struct rtsx_pcr *pcr)
104{
105 return rtsx_pci_write_register(pcr, GPIO_CTL,
106 0x02, 0x02);
107}
108
109static int rts5264_turn_off_led(struct rtsx_pcr *pcr)
110{
111 return rtsx_pci_write_register(pcr, GPIO_CTL,
112 0x02, 0x00);
113}
114
115/* SD Pull Control Enable:
116 * SD_DAT[3:0] ==> pull up
117 * SD_CD ==> pull up
118 * SD_WP ==> pull up
119 * SD_CMD ==> pull up
120 * SD_CLK ==> pull down
121 */
122static const u32 rts5264_sd_pull_ctl_enable_tbl[] = {
123 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
124 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
125 0,
126};
127
128/* SD Pull Control Disable:
129 * SD_DAT[3:0] ==> pull down
130 * SD_CD ==> pull up
131 * SD_WP ==> pull down
132 * SD_CMD ==> pull down
133 * SD_CLK ==> pull down
134 */
135static const u32 rts5264_sd_pull_ctl_disable_tbl[] = {
136 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
137 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
138 0,
139};
140
141static int rts5264_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
142{
143 rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
144 | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
145 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
146 rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
147 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
148 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
149
150 return 0;
151}
152
153static int rts5264_card_power_on(struct rtsx_pcr *pcr, int card)
154{
155 struct rtsx_cr_option *option = &pcr->option;
156
157 if (option->ocp_en)
158 rtsx_pci_enable_ocp(pcr);
159
160 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
161 CFG_SD_POW_AUTO_PD, CFG_SD_POW_AUTO_PD);
162
163 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG1,
164 RTS5264_LDO1_TUNE_MASK, RTS5264_LDO1_33);
165 rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL,
166 RTS5264_LDO1_POWERON, RTS5264_LDO1_POWERON);
167 rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL,
168 RTS5264_LDO3318_POWERON, RTS5264_LDO3318_POWERON);
169
170 msleep(20);
171
172 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
173
174 /* Initialize SD_CFG1 register */
175 rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
176 SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1BIT);
177 rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
178 0xFF, SD20_RX_POS_EDGE);
179 rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
180 rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
181 SD_STOP | SD_CLR_ERR);
182
183 /* Reset SD_CFG3 register */
184 rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
185 rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
186 SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
187 SD30_CLK_STOP_CFG0, 0);
188
189 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
190 pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
191 rts5264_sd_set_sample_push_timing_sd30(pcr);
192
193 return 0;
194}
195
196static int rts5264_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
197{
198 rtsx_pci_write_register(pcr, RTS5264_CARD_PWR_CTL,
199 RTS5264_PUPDC, RTS5264_PUPDC);
200
201 switch (voltage) {
202 case OUTPUT_3V3:
203 rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL,
204 RTS5264_TUNE_REF_LDO3318, RTS5264_TUNE_REF_LDO3318);
205 rtsx_pci_write_register(pcr, RTS5264_DV3318_CFG,
206 RTS5264_DV3318_TUNE_MASK, RTS5264_DV3318_33);
207 rtsx_pci_write_register(pcr, SD_PAD_CTL,
208 SD_IO_USING_1V8, 0);
209 break;
210 case OUTPUT_1V8:
211 rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL,
212 RTS5264_TUNE_REF_LDO3318, RTS5264_TUNE_REF_LDO3318_DFT);
213 rtsx_pci_write_register(pcr, RTS5264_DV3318_CFG,
214 RTS5264_DV3318_TUNE_MASK, RTS5264_DV3318_18);
215 rtsx_pci_write_register(pcr, SD_PAD_CTL,
216 SD_IO_USING_1V8, SD_IO_USING_1V8);
217 break;
218 default:
219 return -EINVAL;
220 }
221
222 /* set pad drive */
223 rts5264_fill_driving(pcr, voltage);
224
225 return 0;
226}
227
228static void rts5264_stop_cmd(struct rtsx_pcr *pcr)
229{
230 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
231 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
232 rtsx_pci_write_register(pcr, DMACTL, DMA_RST, DMA_RST);
233 rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
234}
235
236static void rts5264_card_before_power_off(struct rtsx_pcr *pcr)
237{
238 rts5264_stop_cmd(pcr);
239 rts5264_switch_output_voltage(pcr, OUTPUT_3V3);
240}
241
242static int rts5264_card_power_off(struct rtsx_pcr *pcr, int card)
243{
244 int err = 0;
245
246 rts5264_card_before_power_off(pcr);
247 err = rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL,
248 RTS5264_LDO_POWERON_MASK, 0);
249
250 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
251 CFG_SD_POW_AUTO_PD, 0);
252 if (pcr->option.ocp_en)
253 rtsx_pci_disable_ocp(pcr);
254
255 return err;
256}
257
258static void rts5264_enable_ocp(struct rtsx_pcr *pcr)
259{
260 u8 mask = 0;
261 u8 val = 0;
262
263 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0,
264 RTS5264_LDO1_OCP_EN | RTS5264_LDO1_OCP_LMT_EN,
265 RTS5264_LDO1_OCP_EN | RTS5264_LDO1_OCP_LMT_EN);
266 rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0,
267 RTS5264_LDO2_OCP_EN | RTS5264_LDO2_OCP_LMT_EN,
268 RTS5264_LDO2_OCP_EN | RTS5264_LDO2_OCP_LMT_EN);
269 rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0,
270 RTS5264_LDO3_OCP_EN | RTS5264_LDO3_OCP_LMT_EN,
271 RTS5264_LDO3_OCP_EN | RTS5264_LDO3_OCP_LMT_EN);
272 rtsx_pci_write_register(pcr, RTS5264_OVP_DET,
273 RTS5264_POW_VDET, RTS5264_POW_VDET);
274
275 mask = SD_OCP_INT_EN | SD_DETECT_EN;
276 mask |= SDVIO_OCP_INT_EN | SDVIO_DETECT_EN;
277 val = mask;
278 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
279
280 mask = SD_VDD3_OCP_INT_EN | SD_VDD3_DETECT_EN;
281 val = mask;
282 rtsx_pci_write_register(pcr, RTS5264_OCP_VDD3_CTL, mask, val);
283
284 mask = RTS5264_OVP_INT_EN | RTS5264_OVP_DETECT_EN;
285 val = mask;
286 rtsx_pci_write_register(pcr, RTS5264_OVP_CTL, mask, val);
287}
288
289static void rts5264_disable_ocp(struct rtsx_pcr *pcr)
290{
291 u8 mask = 0;
292
293 mask = SD_OCP_INT_EN | SD_DETECT_EN;
294 mask |= SDVIO_OCP_INT_EN | SDVIO_DETECT_EN;
295 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
296
297 mask = SD_VDD3_OCP_INT_EN | SD_VDD3_DETECT_EN;
298 rtsx_pci_write_register(pcr, RTS5264_OCP_VDD3_CTL, mask, 0);
299
300 mask = RTS5264_OVP_INT_EN | RTS5264_OVP_DETECT_EN;
301 rtsx_pci_write_register(pcr, RTS5264_OVP_CTL, mask, 0);
302
303 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0,
304 RTS5264_LDO1_OCP_EN | RTS5264_LDO1_OCP_LMT_EN, 0);
305 rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0,
306 RTS5264_LDO2_OCP_EN | RTS5264_LDO2_OCP_LMT_EN, 0);
307 rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0,
308 RTS5264_LDO3_OCP_EN | RTS5264_LDO3_OCP_LMT_EN, 0);
309 rtsx_pci_write_register(pcr, RTS5264_OVP_DET, RTS5264_POW_VDET, 0);
310}
311
312static void rts5264_init_ocp(struct rtsx_pcr *pcr)
313{
314 struct rtsx_cr_option *option = &pcr->option;
315
316 if (option->ocp_en) {
317 u8 mask, val;
318
319 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0,
320 RTS5264_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd);
321 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0,
322 RTS5264_LDO1_OCP_LMT_THD_MASK,
323 RTS5264_LDO1_LMT_THD_2000);
324
325 rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0,
326 RTS5264_LDO2_OCP_THD_MASK, RTS5264_LDO2_OCP_THD_950);
327 rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0,
328 RTS5264_LDO2_OCP_LMT_THD_MASK,
329 RTS5264_LDO2_LMT_THD_2000);
330
331 rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0,
332 RTS5264_LDO3_OCP_THD_MASK, RTS5264_LDO3_OCP_THD_710);
333 rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0,
334 RTS5264_LDO3_OCP_LMT_THD_MASK,
335 RTS5264_LDO3_LMT_THD_1500);
336
337 rtsx_pci_write_register(pcr, RTS5264_OVP_DET,
338 RTS5264_TUNE_VROV_MASK, RTS5264_TUNE_VROV_1V6);
339
340 mask = SD_OCP_GLITCH_MASK | SDVIO_OCP_GLITCH_MASK;
341 val = pcr->hw_param.ocp_glitch;
342 rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
343
344 } else {
345 rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0,
346 RTS5264_LDO1_OCP_EN | RTS5264_LDO1_OCP_LMT_EN, 0);
347 rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0,
348 RTS5264_LDO2_OCP_EN | RTS5264_LDO2_OCP_LMT_EN, 0);
349 rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0,
350 RTS5264_LDO3_OCP_EN | RTS5264_LDO3_OCP_LMT_EN, 0);
351 rtsx_pci_write_register(pcr, RTS5264_OVP_DET,
352 RTS5264_POW_VDET, 0);
353 }
354}
355
356static int rts5264_get_ocpstat2(struct rtsx_pcr *pcr, u8 *val)
357{
358 return rtsx_pci_read_register(pcr, RTS5264_OCP_VDD3_STS, val);
359}
360
361static int rts5264_get_ovpstat(struct rtsx_pcr *pcr, u8 *val)
362{
363 return rtsx_pci_read_register(pcr, RTS5264_OVP_STS, val);
364}
365
366static void rts5264_clear_ocpstat(struct rtsx_pcr *pcr)
367{
368 u8 mask = 0;
369 u8 val = 0;
370
371 mask = SD_OCP_INT_CLR | SD_OC_CLR;
372 mask |= SDVIO_OCP_INT_CLR | SDVIO_OC_CLR;
373 val = mask;
374 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
375 rtsx_pci_write_register(pcr, RTS5264_OCP_VDD3_CTL,
376 SD_VDD3_OCP_INT_CLR | SD_VDD3_OC_CLR,
377 SD_VDD3_OCP_INT_CLR | SD_VDD3_OC_CLR);
378 rtsx_pci_write_register(pcr, RTS5264_OVP_CTL,
379 RTS5264_OVP_INT_CLR | RTS5264_OVP_CLR,
380 RTS5264_OVP_INT_CLR | RTS5264_OVP_CLR);
381
382 udelay(1000);
383
384 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
385 rtsx_pci_write_register(pcr, RTS5264_OCP_VDD3_CTL,
386 SD_VDD3_OCP_INT_CLR | SD_VDD3_OC_CLR, 0);
387 rtsx_pci_write_register(pcr, RTS5264_OVP_CTL,
388 RTS5264_OVP_INT_CLR | RTS5264_OVP_CLR, 0);
389}
390
391static void rts5264_process_ocp(struct rtsx_pcr *pcr)
392{
393 if (!pcr->option.ocp_en)
394 return;
395
396 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
397 rts5264_get_ocpstat2(pcr, &pcr->ocp_stat2);
398 rts5264_get_ovpstat(pcr, &pcr->ovp_stat);
399
400 if ((pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER | SDVIO_OC_NOW | SDVIO_OC_EVER)) ||
401 (pcr->ocp_stat2 & (SD_VDD3_OC_NOW | SD_VDD3_OC_EVER)) ||
402 (pcr->ovp_stat & (RTS5264_OVP_NOW | RTS5264_OVP_EVER))) {
403 rts5264_clear_ocpstat(pcr);
404 rts5264_card_power_off(pcr, RTSX_SD_CARD);
405 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
406 pcr->ocp_stat = 0;
407 pcr->ocp_stat2 = 0;
408 pcr->ovp_stat = 0;
409 }
410}
411
412static void rts5264_init_from_hw(struct rtsx_pcr *pcr)
413{
414 struct pci_dev *pdev = pcr->pci;
415 u32 lval1, lval2, i;
416 u16 setting_reg1, setting_reg2;
417 u8 valid, efuse_valid, tmp;
418
419 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL,
420 REG_EFUSE_POR | REG_EFUSE_POWER_MASK,
421 REG_EFUSE_POR | REG_EFUSE_POWERON);
422 udelay(1);
423 rtsx_pci_write_register(pcr, RTS5264_EFUSE_ADDR,
424 RTS5264_EFUSE_ADDR_MASK, 0x00);
425 rtsx_pci_write_register(pcr, RTS5264_EFUSE_CTL,
426 RTS5264_EFUSE_ENABLE | RTS5264_EFUSE_MODE_MASK,
427 RTS5264_EFUSE_ENABLE);
428
429 /* Wait transfer end */
430 for (i = 0; i < MAX_RW_REG_CNT; i++) {
431 rtsx_pci_read_register(pcr, RTS5264_EFUSE_CTL, &tmp);
432 if ((tmp & 0x80) == 0)
433 break;
434 }
435 rtsx_pci_read_register(pcr, RTS5264_EFUSE_READ_DATA, &tmp);
436 efuse_valid = ((tmp & 0x0C) >> 2);
437 pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid);
438
439 pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval2);
440 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, lval2);
441 /* 0x816 */
442 valid = (u8)((lval2 >> 16) & 0x03);
443
444 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL,
445 REG_EFUSE_POR, 0);
446 pcr_dbg(pcr, "Disable efuse por!\n");
447
448 if (efuse_valid == 2 || efuse_valid == 3) {
449 if (valid == 3) {
450 /* Bypass efuse */
451 setting_reg1 = PCR_SETTING_REG1;
452 setting_reg2 = PCR_SETTING_REG2;
453 } else {
454 /* Use efuse data */
455 setting_reg1 = PCR_SETTING_REG4;
456 setting_reg2 = PCR_SETTING_REG5;
457 }
458 } else if (efuse_valid == 0) {
459 // default
460 setting_reg1 = PCR_SETTING_REG1;
461 setting_reg2 = PCR_SETTING_REG2;
462 } else {
463 return;
464 }
465
466 pci_read_config_dword(pdev, setting_reg2, &lval2);
467 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg2, lval2);
468
469 if (!rts5264_vendor_setting_valid(lval2)) {
470 pcr_dbg(pcr, "skip fetch vendor setting\n");
471 return;
472 }
473
474 pcr->rtd3_en = rts5264_reg_to_rtd3(lval2);
475
476 if (rts5264_reg_check_reverse_socket(lval2))
477 pcr->flags |= PCR_REVERSE_SOCKET;
478
479 pci_read_config_dword(pdev, setting_reg1, &lval1);
480 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg1, lval1);
481
482 pcr->aspm_en = rts5264_reg_to_aspm(lval1);
483 pcr->sd30_drive_sel_1v8 = rts5264_reg_to_sd30_drive_sel_1v8(lval1);
484 pcr->sd30_drive_sel_3v3 = rts5264_reg_to_sd30_drive_sel_3v3(lval1);
485
486 if (setting_reg1 == PCR_SETTING_REG1) {
487 /* store setting */
488 rtsx_pci_write_register(pcr, 0xFF0C, 0xFF, (u8)(lval1 & 0xFF));
489 rtsx_pci_write_register(pcr, 0xFF0D, 0xFF, (u8)((lval1 >> 8) & 0xFF));
490 rtsx_pci_write_register(pcr, 0xFF0E, 0xFF, (u8)((lval1 >> 16) & 0xFF));
491 rtsx_pci_write_register(pcr, 0xFF0F, 0xFF, (u8)((lval1 >> 24) & 0xFF));
492 rtsx_pci_write_register(pcr, 0xFF10, 0xFF, (u8)(lval2 & 0xFF));
493 rtsx_pci_write_register(pcr, 0xFF11, 0xFF, (u8)((lval2 >> 8) & 0xFF));
494 rtsx_pci_write_register(pcr, 0xFF12, 0xFF, (u8)((lval2 >> 16) & 0xFF));
495
496 pci_write_config_dword(pdev, PCR_SETTING_REG4, lval1);
497 lval2 = lval2 & 0x00FFFFFF;
498 pci_write_config_dword(pdev, PCR_SETTING_REG5, lval2);
499 }
500}
501
502static void rts5264_init_from_cfg(struct rtsx_pcr *pcr)
503{
504 struct rtsx_cr_option *option = &pcr->option;
505
506 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
507 | PM_L1_1_EN | PM_L1_2_EN))
508 rtsx_pci_disable_oobs_polling(pcr);
509 else
510 rtsx_pci_enable_oobs_polling(pcr);
511
512 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
513
514 if (option->ltr_en) {
515 if (option->ltr_enabled)
516 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
517 }
518}
519
520static int rts5264_extra_init_hw(struct rtsx_pcr *pcr)
521{
522 struct rtsx_cr_option *option = &pcr->option;
523
524 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG1,
525 CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
526 rtsx_pci_write_register(pcr, REG_VREF, PWD_SUSPND_EN, PWD_SUSPND_EN);
527
528 rts5264_init_from_cfg(pcr);
529 rts5264_init_from_hw(pcr);
530
531 /* power off efuse */
532 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL,
533 REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF);
534 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG2,
535 RTS5264_CHIP_RST_N_SEL, 0);
536 rtsx_pci_write_register(pcr, RTS5264_REG_LDO12_CFG,
537 RTS5264_LDO12_SR_MASK, RTS5264_LDO12_SR_0_0_MS);
538 rtsx_pci_write_register(pcr, CDGW, 0xFF, 0x01);
539 rtsx_pci_write_register(pcr, RTS5264_CKMUX_MBIAS_PWR,
540 RTS5264_POW_CKMUX, RTS5264_POW_CKMUX);
541 rtsx_pci_write_register(pcr, RTS5264_CMD_OE_START_EARLY,
542 RTS5264_CMD_OE_EARLY_EN | RTS5264_CMD_OE_EARLY_CYCLE_MASK,
543 RTS5264_CMD_OE_EARLY_EN);
544 rtsx_pci_write_register(pcr, RTS5264_DAT_OE_START_EARLY,
545 RTS5264_DAT_OE_EARLY_EN | RTS5264_DAT_OE_EARLY_CYCLE_MASK,
546 RTS5264_DAT_OE_EARLY_EN);
547 rtsx_pci_write_register(pcr, SSC_DIV_N_0, 0xFF, 0x5D);
548
549 rtsx_pci_write_register(pcr, RTS5264_PWR_CUT,
550 RTS5264_CFG_MEM_PD, RTS5264_CFG_MEM_PD);
551 rtsx_pci_write_register(pcr, L1SUB_CONFIG1,
552 AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE);
553 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);
554 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG4,
555 RTS5264_AUX_CLK_16M_EN, 0);
556
557 /* Release PRSNT# */
558 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG4,
559 RTS5264_FORCE_PRSNT_LOW, 0);
560 rtsx_pci_write_register(pcr, PCLK_CTL,
561 PCLK_MODE_SEL, PCLK_MODE_SEL);
562
563 /* LED shine disabled, set initial shine cycle period */
564 rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);
565
566 /* Configure driving */
567 rts5264_fill_driving(pcr, OUTPUT_3V3);
568
569 if (pcr->flags & PCR_REVERSE_SOCKET)
570 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);
571 else
572 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
573
574 /*
575 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
576 * to drive low, and we forcibly request clock.
577 */
578 if (option->force_clkreq_0)
579 rtsx_pci_write_register(pcr, PETXCFG,
580 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
581 else
582 rtsx_pci_write_register(pcr, PETXCFG,
583 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
584
585 rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFF);
586 rtsx_pci_write_register(pcr, RBCTL, U_AUTO_DMA_EN_MASK, 0);
587 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG4,
588 RTS5264_F_HIGH_RC_MASK, RTS5264_F_HIGH_RC_400K);
589
590 if (pcr->rtd3_en) {
591 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
592 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL,
593 FORCE_PM_CONTROL | FORCE_PM_VALUE, 0);
594 } else {
595 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
596 rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL,
597 FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
598 }
599 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, D3_DELINK_MODE_EN, 0x00);
600
601 /* Clear Enter RTD3_cold Information*/
602 rtsx_pci_write_register(pcr, RTS5264_FW_CTL,
603 RTS5264_INFORM_RTD3_COLD, 0);
604
605 return 0;
606}
607
608static void rts5264_enable_aspm(struct rtsx_pcr *pcr, bool enable)
609{
610 u8 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
611 u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
612
613 if (pcr->aspm_enabled == enable)
614 return;
615
616 val |= (pcr->aspm_en & 0x02);
617 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
618 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
619 PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);
620 pcr->aspm_enabled = enable;
621}
622
623static void rts5264_disable_aspm(struct rtsx_pcr *pcr, bool enable)
624{
625 u8 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
626 u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
627
628 if (pcr->aspm_enabled == enable)
629 return;
630
631 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
632 PCI_EXP_LNKCTL_ASPMC, 0);
633 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
634 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
635 udelay(10);
636 pcr->aspm_enabled = enable;
637}
638
639static void rts5264_set_aspm(struct rtsx_pcr *pcr, bool enable)
640{
641 if (enable)
642 rts5264_enable_aspm(pcr, true);
643 else
644 rts5264_disable_aspm(pcr, false);
645}
646
647static void rts5264_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
648{
649 struct rtsx_cr_option *option = &(pcr->option);
650
651 u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
652 int card_exist = (interrupt & SD_EXIST);
653 int aspm_L1_1, aspm_L1_2;
654 u8 val = 0;
655
656 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
657 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
658
659 if (active) {
660 /* Run, latency: 60us */
661 if (aspm_L1_1)
662 val = option->ltr_l1off_snooze_sspwrgate;
663 } else {
664 /* L1off, latency: 300us */
665 if (aspm_L1_2)
666 val = option->ltr_l1off_sspwrgate;
667 }
668
669 if (aspm_L1_1 || aspm_L1_2) {
670 if (rtsx_check_dev_flag(pcr,
671 LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) {
672 if (card_exist)
673 val &= ~L1OFF_MBIAS2_EN_5250;
674 else
675 val |= L1OFF_MBIAS2_EN_5250;
676 }
677 }
678 rtsx_set_l1off_sub(pcr, val);
679}
680
681static const struct pcr_ops rts5264_pcr_ops = {
682 .turn_on_led = rts5264_turn_on_led,
683 .turn_off_led = rts5264_turn_off_led,
684 .extra_init_hw = rts5264_extra_init_hw,
685 .enable_auto_blink = rts5264_enable_auto_blink,
686 .disable_auto_blink = rts5264_disable_auto_blink,
687 .card_power_on = rts5264_card_power_on,
688 .card_power_off = rts5264_card_power_off,
689 .switch_output_voltage = rts5264_switch_output_voltage,
690 .force_power_down = rts5264_force_power_down,
691 .stop_cmd = rts5264_stop_cmd,
692 .set_aspm = rts5264_set_aspm,
693 .set_l1off_cfg_sub_d0 = rts5264_set_l1off_cfg_sub_d0,
694 .enable_ocp = rts5264_enable_ocp,
695 .disable_ocp = rts5264_disable_ocp,
696 .init_ocp = rts5264_init_ocp,
697 .process_ocp = rts5264_process_ocp,
698 .clear_ocpstat = rts5264_clear_ocpstat,
699};
700
701static inline u8 double_ssc_depth(u8 depth)
702{
703 return ((depth > 1) ? (depth - 1) : depth);
704}
705
706int rts5264_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
707 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
708{
709 int err, clk;
710 u16 n;
711 u8 clk_divider, mcu_cnt, div;
712 static const u8 depth[] = {
713 [RTSX_SSC_DEPTH_4M] = RTS5264_SSC_DEPTH_4M,
714 [RTSX_SSC_DEPTH_2M] = RTS5264_SSC_DEPTH_2M,
715 [RTSX_SSC_DEPTH_1M] = RTS5264_SSC_DEPTH_1M,
716 [RTSX_SSC_DEPTH_500K] = RTS5264_SSC_DEPTH_512K,
717 };
718
719 if (initial_mode) {
720 /* We use 250k(around) here, in initial stage */
721 clk_divider = SD_CLK_DIVIDE_128;
722 card_clock = 30000000;
723 } else {
724 clk_divider = SD_CLK_DIVIDE_0;
725 }
726 err = rtsx_pci_write_register(pcr, SD_CFG1,
727 SD_CLK_DIVIDE_MASK, clk_divider);
728 if (err < 0)
729 return err;
730
731 card_clock /= 1000000;
732 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
733
734 clk = card_clock;
735 if (!initial_mode && double_clk)
736 clk = card_clock * 2;
737 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
738 clk, pcr->cur_clock);
739
740 if (clk == pcr->cur_clock)
741 return 0;
742
743 if (pcr->ops->conv_clk_and_div_n)
744 n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
745 else
746 n = clk - 4;
747 if ((clk <= 4) || (n > 396))
748 return -EINVAL;
749
750 mcu_cnt = 125/clk + 3;
751 if (mcu_cnt > 15)
752 mcu_cnt = 15;
753
754 div = CLK_DIV_1;
755 while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) {
756 if (pcr->ops->conv_clk_and_div_n) {
757 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
758 DIV_N_TO_CLK) * 2;
759 n = pcr->ops->conv_clk_and_div_n(dbl_clk,
760 CLK_TO_DIV_N);
761 } else {
762 n = (n + 4) * 2 - 4;
763 }
764 div++;
765 }
766
767 n = (n / 2) - 1;
768 pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
769
770 ssc_depth = depth[ssc_depth];
771 if (double_clk)
772 ssc_depth = double_ssc_depth(ssc_depth);
773
774 if (ssc_depth) {
775 if (div == CLK_DIV_2) {
776 if (ssc_depth > 1)
777 ssc_depth -= 1;
778 else
779 ssc_depth = RTS5264_SSC_DEPTH_8M;
780 } else if (div == CLK_DIV_4) {
781 if (ssc_depth > 2)
782 ssc_depth -= 2;
783 else
784 ssc_depth = RTS5264_SSC_DEPTH_8M;
785 } else if (div == CLK_DIV_8) {
786 if (ssc_depth > 3)
787 ssc_depth -= 3;
788 else
789 ssc_depth = RTS5264_SSC_DEPTH_8M;
790 }
791 } else {
792 ssc_depth = 0;
793 }
794 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
795
796 rtsx_pci_init_cmd(pcr);
797 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
798 CHANGE_CLK, CHANGE_CLK);
799 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
800 0xFF, (div << 4) | mcu_cnt);
801 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
802 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
803 SSC_DEPTH_MASK, ssc_depth);
804 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
805
806 if (is_version(pcr, 0x5264, IC_VER_A)) {
807 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
808 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS5264_CARD_CLK_SRC2,
809 RTS5264_REG_BIG_KVCO_A, 0);
810 } else {
811 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
812 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS5264_SYS_DUMMY_1,
813 RTS5264_REG_BIG_KVCO, 0);
814 }
815
816 if (vpclk) {
817 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
818 PHASE_NOT_RESET, 0);
819 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
820 PHASE_NOT_RESET, 0);
821 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
822 PHASE_NOT_RESET, PHASE_NOT_RESET);
823 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
824 PHASE_NOT_RESET, PHASE_NOT_RESET);
825 }
826
827 err = rtsx_pci_send_cmd(pcr, 2000);
828 if (err < 0)
829 return err;
830
831 /* Wait SSC clock stable */
832 udelay(SSC_CLOCK_STABLE_WAIT);
833 err = rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0);
834 if (err < 0)
835 return err;
836
837 pcr->cur_clock = clk;
838 return 0;
839}
840
841void rts5264_init_params(struct rtsx_pcr *pcr)
842{
843 struct rtsx_cr_option *option = &pcr->option;
844 struct rtsx_hw_param *hw_param = &pcr->hw_param;
845 u8 val;
846
847 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
848 pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
849 rtsx_pci_read_register(pcr, RTS5264_FW_STATUS, &val);
850 if (!(val & RTS5264_EXPRESS_LINK_FAIL_MASK))
851 pcr->extra_caps |= EXTRA_CAPS_SD_EXPRESS;
852 pcr->num_slots = 1;
853 pcr->ops = &rts5264_pcr_ops;
854
855 pcr->flags = 0;
856 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
857 pcr->sd30_drive_sel_1v8 = 0x00;
858 pcr->sd30_drive_sel_3v3 = 0x00;
859 pcr->aspm_en = ASPM_L1_EN;
860 pcr->aspm_mode = ASPM_MODE_REG;
861 pcr->tx_initial_phase = SET_CLOCK_PHASE(24, 24, 11);
862 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
863
864 pcr->ic_version = rts5264_get_ic_version(pcr);
865 pcr->sd_pull_ctl_enable_tbl = rts5264_sd_pull_ctl_enable_tbl;
866 pcr->sd_pull_ctl_disable_tbl = rts5264_sd_pull_ctl_disable_tbl;
867
868 pcr->reg_pm_ctrl3 = RTS5264_AUTOLOAD_CFG3;
869
870 option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
871 | LTR_L1SS_PWR_GATE_EN);
872 option->ltr_en = true;
873
874 /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
875 option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
876 option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
877 option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
878 option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
879 option->ltr_l1off_sspwrgate = 0x7F;
880 option->ltr_l1off_snooze_sspwrgate = 0x78;
881
882 option->ocp_en = 1;
883 hw_param->interrupt_en |= (SD_OC_INT_EN | SD_OVP_INT_EN);
884 hw_param->ocp_glitch = SD_OCP_GLITCH_800U | SDVIO_OCP_GLITCH_800U;
885 option->sd_800mA_ocp_thd = RTS5264_LDO1_OCP_THD_1150;
886}