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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * twl_core.c - driver for TWL4030/TWL5030/TWL60X0/TPS659x0 PM
4 * and audio CODEC devices
5 *
6 * Copyright (C) 2005-2006 Texas Instruments, Inc.
7 *
8 * Modifications to defer interrupt handling to a kernel thread:
9 * Copyright (C) 2006 MontaVista Software, Inc.
10 *
11 * Based on tlv320aic23.c:
12 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
13 *
14 * Code cleanup and modifications to IRQ handler.
15 * by syed khasim <x0khasim@ti.com>
16 */
17
18#include <linux/init.h>
19#include <linux/mutex.h>
20#include <linux/platform_device.h>
21#include <linux/regmap.h>
22#include <linux/clk.h>
23#include <linux/err.h>
24#include <linux/device.h>
25#include <linux/of.h>
26#include <linux/of_irq.h>
27#include <linux/of_platform.h>
28#include <linux/irq.h>
29#include <linux/irqdomain.h>
30
31#include <linux/regulator/machine.h>
32
33#include <linux/i2c.h>
34
35#include <linux/mfd/core.h>
36#include <linux/mfd/twl.h>
37
38/* Register descriptions for audio */
39#include <linux/mfd/twl4030-audio.h>
40
41#include "twl-core.h"
42
43/*
44 * The TWL4030 "Triton 2" is one of a family of a multi-function "Power
45 * Management and System Companion Device" chips originally designed for
46 * use in OMAP2 and OMAP 3 based systems. Its control interfaces use I2C,
47 * often at around 3 Mbit/sec, including for interrupt handling.
48 *
49 * This driver core provides genirq support for the interrupts emitted,
50 * by the various modules, and exports register access primitives.
51 *
52 * FIXME this driver currently requires use of the first interrupt line
53 * (and associated registers).
54 */
55
56#define DRIVER_NAME "twl"
57
58/* Triton Core internal information (BEGIN) */
59
60/* Base Address defns for twl4030_map[] */
61
62/* subchip/slave 0 - USB ID */
63#define TWL4030_BASEADD_USB 0x0000
64
65/* subchip/slave 1 - AUD ID */
66#define TWL4030_BASEADD_AUDIO_VOICE 0x0000
67#define TWL4030_BASEADD_GPIO 0x0098
68#define TWL4030_BASEADD_INTBR 0x0085
69#define TWL4030_BASEADD_PIH 0x0080
70#define TWL4030_BASEADD_TEST 0x004C
71
72/* subchip/slave 2 - AUX ID */
73#define TWL4030_BASEADD_INTERRUPTS 0x00B9
74#define TWL4030_BASEADD_LED 0x00EE
75#define TWL4030_BASEADD_MADC 0x0000
76#define TWL4030_BASEADD_MAIN_CHARGE 0x0074
77#define TWL4030_BASEADD_PRECHARGE 0x00AA
78#define TWL4030_BASEADD_PWM 0x00F8
79#define TWL4030_BASEADD_KEYPAD 0x00D2
80
81#define TWL5031_BASEADD_ACCESSORY 0x0074 /* Replaces Main Charge */
82#define TWL5031_BASEADD_INTERRUPTS 0x00B9 /* Different than TWL4030's
83 one */
84
85/* subchip/slave 3 - POWER ID */
86#define TWL4030_BASEADD_BACKUP 0x0014
87#define TWL4030_BASEADD_INT 0x002E
88#define TWL4030_BASEADD_PM_MASTER 0x0036
89
90#define TWL4030_BASEADD_PM_RECEIVER 0x005B
91#define TWL4030_DCDC_GLOBAL_CFG 0x06
92#define SMARTREFLEX_ENABLE BIT(3)
93
94#define TWL4030_BASEADD_RTC 0x001C
95#define TWL4030_BASEADD_SECURED_REG 0x0000
96
97/* Triton Core internal information (END) */
98
99
100/* subchip/slave 0 0x48 - POWER */
101#define TWL6030_BASEADD_RTC 0x0000
102#define TWL6030_BASEADD_SECURED_REG 0x0017
103#define TWL6030_BASEADD_PM_MASTER 0x001F
104#define TWL6030_BASEADD_PM_SLAVE_MISC 0x0030 /* PM_RECEIVER */
105#define TWL6030_BASEADD_PM_MISC 0x00E2
106#define TWL6030_BASEADD_PM_PUPD 0x00F0
107
108/* subchip/slave 1 0x49 - FEATURE */
109#define TWL6030_BASEADD_USB 0x0000
110#define TWL6030_BASEADD_GPADC_CTRL 0x002E
111#define TWL6030_BASEADD_AUX 0x0090
112#define TWL6030_BASEADD_PWM 0x00BA
113#define TWL6030_BASEADD_GASGAUGE 0x00C0
114#define TWL6030_BASEADD_PIH 0x00D0
115#define TWL6032_BASEADD_CHARGER 0x00DA
116#define TWL6030_BASEADD_CHARGER 0x00E0
117#define TWL6030_BASEADD_LED 0x00F4
118
119/* subchip/slave 2 0x4A - DFT */
120#define TWL6030_BASEADD_DIEID 0x00C0
121
122/* subchip/slave 3 0x4B - AUDIO */
123#define TWL6030_BASEADD_AUDIO 0x0000
124#define TWL6030_BASEADD_RSV 0x0000
125#define TWL6030_BASEADD_ZERO 0x0000
126
127/* Few power values */
128#define R_CFG_BOOT 0x05
129
130/* some fields in R_CFG_BOOT */
131#define HFCLK_FREQ_19p2_MHZ (1 << 0)
132#define HFCLK_FREQ_26_MHZ (2 << 0)
133#define HFCLK_FREQ_38p4_MHZ (3 << 0)
134#define HIGH_PERF_SQ (1 << 3)
135#define CK32K_LOWPWR_EN (1 << 7)
136
137/*----------------------------------------------------------------------*/
138
139/* Structure for each TWL4030/TWL6030 Slave */
140struct twl_client {
141 struct i2c_client *client;
142 struct regmap *regmap;
143};
144
145/* mapping the module id to slave id and base address */
146struct twl_mapping {
147 unsigned char sid; /* Slave ID */
148 unsigned char base; /* base address */
149};
150
151struct twl_private {
152 bool ready; /* The core driver is ready to be used */
153 u32 twl_idcode; /* TWL IDCODE Register value */
154 unsigned int twl_id;
155
156 struct twl_mapping *twl_map;
157 struct twl_client *twl_modules;
158};
159
160static struct twl_private *twl_priv;
161
162static struct twl_mapping twl4030_map[] = {
163 /*
164 * NOTE: don't change this table without updating the
165 * <linux/mfd/twl.h> defines for TWL4030_MODULE_*
166 * so they continue to match the order in this table.
167 */
168
169 /* Common IPs */
170 { 0, TWL4030_BASEADD_USB },
171 { 1, TWL4030_BASEADD_PIH },
172 { 2, TWL4030_BASEADD_MAIN_CHARGE },
173 { 3, TWL4030_BASEADD_PM_MASTER },
174 { 3, TWL4030_BASEADD_PM_RECEIVER },
175
176 { 3, TWL4030_BASEADD_RTC },
177 { 2, TWL4030_BASEADD_PWM },
178 { 2, TWL4030_BASEADD_LED },
179 { 3, TWL4030_BASEADD_SECURED_REG },
180
181 /* TWL4030 specific IPs */
182 { 1, TWL4030_BASEADD_AUDIO_VOICE },
183 { 1, TWL4030_BASEADD_GPIO },
184 { 1, TWL4030_BASEADD_INTBR },
185 { 1, TWL4030_BASEADD_TEST },
186 { 2, TWL4030_BASEADD_KEYPAD },
187
188 { 2, TWL4030_BASEADD_MADC },
189 { 2, TWL4030_BASEADD_INTERRUPTS },
190 { 2, TWL4030_BASEADD_PRECHARGE },
191 { 3, TWL4030_BASEADD_BACKUP },
192 { 3, TWL4030_BASEADD_INT },
193
194 { 2, TWL5031_BASEADD_ACCESSORY },
195 { 2, TWL5031_BASEADD_INTERRUPTS },
196};
197
198static const struct reg_default twl4030_49_defaults[] = {
199 /* Audio Registers */
200 { 0x01, 0x00}, /* CODEC_MODE */
201 { 0x02, 0x00}, /* OPTION */
202 /* 0x03 Unused */
203 { 0x04, 0x00}, /* MICBIAS_CTL */
204 { 0x05, 0x00}, /* ANAMICL */
205 { 0x06, 0x00}, /* ANAMICR */
206 { 0x07, 0x00}, /* AVADC_CTL */
207 { 0x08, 0x00}, /* ADCMICSEL */
208 { 0x09, 0x00}, /* DIGMIXING */
209 { 0x0a, 0x0f}, /* ATXL1PGA */
210 { 0x0b, 0x0f}, /* ATXR1PGA */
211 { 0x0c, 0x0f}, /* AVTXL2PGA */
212 { 0x0d, 0x0f}, /* AVTXR2PGA */
213 { 0x0e, 0x00}, /* AUDIO_IF */
214 { 0x0f, 0x00}, /* VOICE_IF */
215 { 0x10, 0x3f}, /* ARXR1PGA */
216 { 0x11, 0x3f}, /* ARXL1PGA */
217 { 0x12, 0x3f}, /* ARXR2PGA */
218 { 0x13, 0x3f}, /* ARXL2PGA */
219 { 0x14, 0x25}, /* VRXPGA */
220 { 0x15, 0x00}, /* VSTPGA */
221 { 0x16, 0x00}, /* VRX2ARXPGA */
222 { 0x17, 0x00}, /* AVDAC_CTL */
223 { 0x18, 0x00}, /* ARX2VTXPGA */
224 { 0x19, 0x32}, /* ARXL1_APGA_CTL*/
225 { 0x1a, 0x32}, /* ARXR1_APGA_CTL*/
226 { 0x1b, 0x32}, /* ARXL2_APGA_CTL*/
227 { 0x1c, 0x32}, /* ARXR2_APGA_CTL*/
228 { 0x1d, 0x00}, /* ATX2ARXPGA */
229 { 0x1e, 0x00}, /* BT_IF */
230 { 0x1f, 0x55}, /* BTPGA */
231 { 0x20, 0x00}, /* BTSTPGA */
232 { 0x21, 0x00}, /* EAR_CTL */
233 { 0x22, 0x00}, /* HS_SEL */
234 { 0x23, 0x00}, /* HS_GAIN_SET */
235 { 0x24, 0x00}, /* HS_POPN_SET */
236 { 0x25, 0x00}, /* PREDL_CTL */
237 { 0x26, 0x00}, /* PREDR_CTL */
238 { 0x27, 0x00}, /* PRECKL_CTL */
239 { 0x28, 0x00}, /* PRECKR_CTL */
240 { 0x29, 0x00}, /* HFL_CTL */
241 { 0x2a, 0x00}, /* HFR_CTL */
242 { 0x2b, 0x05}, /* ALC_CTL */
243 { 0x2c, 0x00}, /* ALC_SET1 */
244 { 0x2d, 0x00}, /* ALC_SET2 */
245 { 0x2e, 0x00}, /* BOOST_CTL */
246 { 0x2f, 0x00}, /* SOFTVOL_CTL */
247 { 0x30, 0x13}, /* DTMF_FREQSEL */
248 { 0x31, 0x00}, /* DTMF_TONEXT1H */
249 { 0x32, 0x00}, /* DTMF_TONEXT1L */
250 { 0x33, 0x00}, /* DTMF_TONEXT2H */
251 { 0x34, 0x00}, /* DTMF_TONEXT2L */
252 { 0x35, 0x79}, /* DTMF_TONOFF */
253 { 0x36, 0x11}, /* DTMF_WANONOFF */
254 { 0x37, 0x00}, /* I2S_RX_SCRAMBLE_H */
255 { 0x38, 0x00}, /* I2S_RX_SCRAMBLE_M */
256 { 0x39, 0x00}, /* I2S_RX_SCRAMBLE_L */
257 { 0x3a, 0x06}, /* APLL_CTL */
258 { 0x3b, 0x00}, /* DTMF_CTL */
259 { 0x3c, 0x44}, /* DTMF_PGA_CTL2 (0x3C) */
260 { 0x3d, 0x69}, /* DTMF_PGA_CTL1 (0x3D) */
261 { 0x3e, 0x00}, /* MISC_SET_1 */
262 { 0x3f, 0x00}, /* PCMBTMUX */
263 /* 0x40 - 0x42 Unused */
264 { 0x43, 0x00}, /* RX_PATH_SEL */
265 { 0x44, 0x32}, /* VDL_APGA_CTL */
266 { 0x45, 0x00}, /* VIBRA_CTL */
267 { 0x46, 0x00}, /* VIBRA_SET */
268 { 0x47, 0x00}, /* VIBRA_PWM_SET */
269 { 0x48, 0x00}, /* ANAMIC_GAIN */
270 { 0x49, 0x00}, /* MISC_SET_2 */
271 /* End of Audio Registers */
272};
273
274static bool twl4030_49_nop_reg(struct device *dev, unsigned int reg)
275{
276 switch (reg) {
277 case 0x00:
278 case 0x03:
279 case 0x40:
280 case 0x41:
281 case 0x42:
282 return false;
283 default:
284 return true;
285 }
286}
287
288static const struct regmap_range twl4030_49_volatile_ranges[] = {
289 regmap_reg_range(TWL4030_BASEADD_TEST, 0xff),
290};
291
292static const struct regmap_access_table twl4030_49_volatile_table = {
293 .yes_ranges = twl4030_49_volatile_ranges,
294 .n_yes_ranges = ARRAY_SIZE(twl4030_49_volatile_ranges),
295};
296
297static const struct regmap_config twl4030_regmap_config[4] = {
298 {
299 /* Address 0x48 */
300 .reg_bits = 8,
301 .val_bits = 8,
302 .max_register = 0xff,
303 },
304 {
305 /* Address 0x49 */
306 .reg_bits = 8,
307 .val_bits = 8,
308 .max_register = 0xff,
309
310 .readable_reg = twl4030_49_nop_reg,
311 .writeable_reg = twl4030_49_nop_reg,
312
313 .volatile_table = &twl4030_49_volatile_table,
314
315 .reg_defaults = twl4030_49_defaults,
316 .num_reg_defaults = ARRAY_SIZE(twl4030_49_defaults),
317 .cache_type = REGCACHE_MAPLE,
318 },
319 {
320 /* Address 0x4a */
321 .reg_bits = 8,
322 .val_bits = 8,
323 .max_register = 0xff,
324 },
325 {
326 /* Address 0x4b */
327 .reg_bits = 8,
328 .val_bits = 8,
329 .max_register = 0xff,
330 },
331};
332
333static struct twl_mapping twl6030_map[] = {
334 /*
335 * NOTE: don't change this table without updating the
336 * <linux/mfd/twl.h> defines for TWL4030_MODULE_*
337 * so they continue to match the order in this table.
338 */
339
340 /* Common IPs */
341 { 1, TWL6030_BASEADD_USB },
342 { 1, TWL6030_BASEADD_PIH },
343 { 1, TWL6030_BASEADD_CHARGER },
344 { 0, TWL6030_BASEADD_PM_MASTER },
345 { 0, TWL6030_BASEADD_PM_SLAVE_MISC },
346
347 { 0, TWL6030_BASEADD_RTC },
348 { 1, TWL6030_BASEADD_PWM },
349 { 1, TWL6030_BASEADD_LED },
350 { 0, TWL6030_BASEADD_SECURED_REG },
351
352 /* TWL6030 specific IPs */
353 { 0, TWL6030_BASEADD_ZERO },
354 { 1, TWL6030_BASEADD_ZERO },
355 { 2, TWL6030_BASEADD_ZERO },
356 { 1, TWL6030_BASEADD_GPADC_CTRL },
357 { 1, TWL6030_BASEADD_GASGAUGE },
358
359 /* TWL6032 specific charger registers */
360 { 1, TWL6032_BASEADD_CHARGER },
361};
362
363static const struct regmap_config twl6030_regmap_config[3] = {
364 {
365 /* Address 0x48 */
366 .reg_bits = 8,
367 .val_bits = 8,
368 .max_register = 0xff,
369 },
370 {
371 /* Address 0x49 */
372 .reg_bits = 8,
373 .val_bits = 8,
374 .max_register = 0xff,
375 },
376 {
377 /* Address 0x4a */
378 .reg_bits = 8,
379 .val_bits = 8,
380 .max_register = 0xff,
381 },
382};
383
384/*----------------------------------------------------------------------*/
385
386static inline int twl_get_num_slaves(void)
387{
388 if (twl_class_is_4030())
389 return 4; /* TWL4030 class have four slave address */
390 else
391 return 3; /* TWL6030 class have three slave address */
392}
393
394static inline int twl_get_last_module(void)
395{
396 if (twl_class_is_4030())
397 return TWL4030_MODULE_LAST;
398 else
399 return TWL6030_MODULE_LAST;
400}
401
402/* Exported Functions */
403
404unsigned int twl_rev(void)
405{
406 return twl_priv ? twl_priv->twl_id : 0;
407}
408EXPORT_SYMBOL(twl_rev);
409
410/**
411 * twl_get_regmap - Get the regmap associated with the given module
412 * @mod_no: module number
413 *
414 * Returns the regmap pointer or NULL in case of failure.
415 */
416static struct regmap *twl_get_regmap(u8 mod_no)
417{
418 int sid;
419 struct twl_client *twl;
420
421 if (unlikely(!twl_priv || !twl_priv->ready)) {
422 pr_err("%s: not initialized\n", DRIVER_NAME);
423 return NULL;
424 }
425 if (unlikely(mod_no >= twl_get_last_module())) {
426 pr_err("%s: invalid module number %d\n", DRIVER_NAME, mod_no);
427 return NULL;
428 }
429
430 sid = twl_priv->twl_map[mod_no].sid;
431 twl = &twl_priv->twl_modules[sid];
432
433 return twl->regmap;
434}
435
436/**
437 * twl_i2c_write - Writes a n bit register in TWL4030/TWL5030/TWL60X0
438 * @mod_no: module number
439 * @value: an array of num_bytes+1 containing data to write
440 * @reg: register address (just offset will do)
441 * @num_bytes: number of bytes to transfer
442 *
443 * Returns 0 on success or else a negative error code.
444 */
445int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes)
446{
447 struct regmap *regmap = twl_get_regmap(mod_no);
448 int ret;
449
450 if (!regmap)
451 return -EPERM;
452
453 ret = regmap_bulk_write(regmap, twl_priv->twl_map[mod_no].base + reg,
454 value, num_bytes);
455
456 if (ret)
457 pr_err("%s: Write failed (mod %d, reg 0x%02x count %d)\n",
458 DRIVER_NAME, mod_no, reg, num_bytes);
459
460 return ret;
461}
462EXPORT_SYMBOL(twl_i2c_write);
463
464/**
465 * twl_i2c_read - Reads a n bit register in TWL4030/TWL5030/TWL60X0
466 * @mod_no: module number
467 * @value: an array of num_bytes containing data to be read
468 * @reg: register address (just offset will do)
469 * @num_bytes: number of bytes to transfer
470 *
471 * Returns 0 on success or else a negative error code.
472 */
473int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes)
474{
475 struct regmap *regmap = twl_get_regmap(mod_no);
476 int ret;
477
478 if (!regmap)
479 return -EPERM;
480
481 ret = regmap_bulk_read(regmap, twl_priv->twl_map[mod_no].base + reg,
482 value, num_bytes);
483
484 if (ret)
485 pr_err("%s: Read failed (mod %d, reg 0x%02x count %d)\n",
486 DRIVER_NAME, mod_no, reg, num_bytes);
487
488 return ret;
489}
490EXPORT_SYMBOL(twl_i2c_read);
491
492/**
493 * twl_set_regcache_bypass - Configure the regcache bypass for the regmap associated
494 * with the module
495 * @mod_no: module number
496 * @enable: Regcache bypass state
497 *
498 * Returns 0 else failure.
499 */
500int twl_set_regcache_bypass(u8 mod_no, bool enable)
501{
502 struct regmap *regmap = twl_get_regmap(mod_no);
503
504 if (!regmap)
505 return -EPERM;
506
507 regcache_cache_bypass(regmap, enable);
508
509 return 0;
510}
511EXPORT_SYMBOL(twl_set_regcache_bypass);
512
513/*----------------------------------------------------------------------*/
514
515/**
516 * twl_read_idcode_register - API to read the IDCODE register.
517 *
518 * Unlocks the IDCODE register and read the 32 bit value.
519 */
520static int twl_read_idcode_register(void)
521{
522 int err;
523
524 err = twl_i2c_write_u8(TWL4030_MODULE_INTBR, TWL_EEPROM_R_UNLOCK,
525 REG_UNLOCK_TEST_REG);
526 if (err) {
527 pr_err("TWL4030 Unable to unlock IDCODE registers -%d\n", err);
528 goto fail;
529 }
530
531 err = twl_i2c_read(TWL4030_MODULE_INTBR, (u8 *)(&twl_priv->twl_idcode),
532 REG_IDCODE_7_0, 4);
533 if (err) {
534 pr_err("TWL4030: unable to read IDCODE -%d\n", err);
535 goto fail;
536 }
537
538 err = twl_i2c_write_u8(TWL4030_MODULE_INTBR, 0x0, REG_UNLOCK_TEST_REG);
539 if (err)
540 pr_err("TWL4030 Unable to relock IDCODE registers -%d\n", err);
541fail:
542 return err;
543}
544
545/**
546 * twl_get_type - API to get TWL Si type.
547 *
548 * Api to get the TWL Si type from IDCODE value.
549 */
550int twl_get_type(void)
551{
552 return TWL_SIL_TYPE(twl_priv->twl_idcode);
553}
554EXPORT_SYMBOL_GPL(twl_get_type);
555
556/**
557 * twl_get_version - API to get TWL Si version.
558 *
559 * Api to get the TWL Si version from IDCODE value.
560 */
561int twl_get_version(void)
562{
563 return TWL_SIL_REV(twl_priv->twl_idcode);
564}
565EXPORT_SYMBOL_GPL(twl_get_version);
566
567/**
568 * twl_get_hfclk_rate - API to get TWL external HFCLK clock rate.
569 *
570 * Api to get the TWL HFCLK rate based on BOOT_CFG register.
571 */
572int twl_get_hfclk_rate(void)
573{
574 u8 ctrl;
575 int rate;
576
577 twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &ctrl, R_CFG_BOOT);
578
579 switch (ctrl & 0x3) {
580 case HFCLK_FREQ_19p2_MHZ:
581 rate = 19200000;
582 break;
583 case HFCLK_FREQ_26_MHZ:
584 rate = 26000000;
585 break;
586 case HFCLK_FREQ_38p4_MHZ:
587 rate = 38400000;
588 break;
589 default:
590 pr_err("TWL4030: HFCLK is not configured\n");
591 rate = -EINVAL;
592 break;
593 }
594
595 return rate;
596}
597EXPORT_SYMBOL_GPL(twl_get_hfclk_rate);
598
599/*----------------------------------------------------------------------*/
600
601/*
602 * These three functions initialize the on-chip clock framework,
603 * letting it generate the right frequencies for USB, MADC, and
604 * other purposes.
605 */
606static inline int protect_pm_master(void)
607{
608 int e = 0;
609
610 e = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
611 TWL4030_PM_MASTER_PROTECT_KEY);
612 return e;
613}
614
615static inline int unprotect_pm_master(void)
616{
617 int e = 0;
618
619 e |= twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
620 TWL4030_PM_MASTER_PROTECT_KEY);
621 e |= twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
622 TWL4030_PM_MASTER_PROTECT_KEY);
623
624 return e;
625}
626
627static void clocks_init(struct device *dev)
628{
629 int e = 0;
630 struct clk *osc;
631 u32 rate;
632 u8 ctrl = HFCLK_FREQ_26_MHZ;
633
634 osc = clk_get(dev, "fck");
635 if (IS_ERR(osc)) {
636 printk(KERN_WARNING "Skipping twl internal clock init and "
637 "using bootloader value (unknown osc rate)\n");
638 return;
639 }
640
641 rate = clk_get_rate(osc);
642 clk_put(osc);
643
644 switch (rate) {
645 case 19200000:
646 ctrl = HFCLK_FREQ_19p2_MHZ;
647 break;
648 case 26000000:
649 ctrl = HFCLK_FREQ_26_MHZ;
650 break;
651 case 38400000:
652 ctrl = HFCLK_FREQ_38p4_MHZ;
653 break;
654 }
655
656 ctrl |= HIGH_PERF_SQ;
657
658 e |= unprotect_pm_master();
659 /* effect->MADC+USB ck en */
660 e |= twl_i2c_write_u8(TWL_MODULE_PM_MASTER, ctrl, R_CFG_BOOT);
661 e |= protect_pm_master();
662
663 if (e < 0)
664 pr_err("%s: clock init err [%d]\n", DRIVER_NAME, e);
665}
666
667/*----------------------------------------------------------------------*/
668
669
670static void twl_remove(struct i2c_client *client)
671{
672 unsigned i, num_slaves;
673
674 if (twl_class_is_4030())
675 twl4030_exit_irq();
676 else
677 twl6030_exit_irq();
678
679 num_slaves = twl_get_num_slaves();
680 for (i = 0; i < num_slaves; i++) {
681 struct twl_client *twl = &twl_priv->twl_modules[i];
682
683 if (twl->client && twl->client != client)
684 i2c_unregister_device(twl->client);
685 twl->client = NULL;
686 }
687 twl_priv->ready = false;
688}
689
690static struct of_dev_auxdata twl_auxdata_lookup[] = {
691 OF_DEV_AUXDATA("ti,twl4030-gpio", 0, "twl4030-gpio", NULL),
692 { /* sentinel */ },
693};
694
695static const struct mfd_cell twl6032_cells[] = {
696 { .name = "twl6032-clk" },
697};
698
699/* NOTE: This driver only handles a single twl4030/tps659x0 chip */
700static int
701twl_probe(struct i2c_client *client)
702{
703 const struct i2c_device_id *id = i2c_client_get_device_id(client);
704 struct device_node *node = client->dev.of_node;
705 struct platform_device *pdev;
706 const struct regmap_config *twl_regmap_config;
707 int irq_base = 0;
708 int status;
709 unsigned i, num_slaves;
710
711 if (!node) {
712 dev_err(&client->dev, "no platform data\n");
713 return -EINVAL;
714 }
715
716 if (twl_priv) {
717 dev_dbg(&client->dev, "only one instance of %s allowed\n",
718 DRIVER_NAME);
719 return -EBUSY;
720 }
721
722 pdev = platform_device_alloc(DRIVER_NAME, -1);
723 if (!pdev) {
724 dev_err(&client->dev, "can't alloc pdev\n");
725 return -ENOMEM;
726 }
727
728 status = platform_device_add(pdev);
729 if (status) {
730 platform_device_put(pdev);
731 return status;
732 }
733
734 if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C) == 0) {
735 dev_dbg(&client->dev, "can't talk I2C?\n");
736 status = -EIO;
737 goto free;
738 }
739
740 twl_priv = devm_kzalloc(&client->dev, sizeof(struct twl_private),
741 GFP_KERNEL);
742 if (!twl_priv) {
743 status = -ENOMEM;
744 goto free;
745 }
746
747 if ((id->driver_data) & TWL6030_CLASS) {
748 twl_priv->twl_id = TWL6030_CLASS_ID;
749 twl_priv->twl_map = &twl6030_map[0];
750 twl_regmap_config = twl6030_regmap_config;
751 } else {
752 twl_priv->twl_id = TWL4030_CLASS_ID;
753 twl_priv->twl_map = &twl4030_map[0];
754 twl_regmap_config = twl4030_regmap_config;
755 }
756
757 num_slaves = twl_get_num_slaves();
758 twl_priv->twl_modules = devm_kcalloc(&client->dev,
759 num_slaves,
760 sizeof(struct twl_client),
761 GFP_KERNEL);
762 if (!twl_priv->twl_modules) {
763 status = -ENOMEM;
764 goto free;
765 }
766
767 for (i = 0; i < num_slaves; i++) {
768 struct twl_client *twl = &twl_priv->twl_modules[i];
769
770 if (i == 0) {
771 twl->client = client;
772 } else {
773 twl->client = i2c_new_dummy_device(client->adapter,
774 client->addr + i);
775 if (IS_ERR(twl->client)) {
776 dev_err(&client->dev,
777 "can't attach client %d\n", i);
778 status = PTR_ERR(twl->client);
779 goto fail;
780 }
781 }
782
783 twl->regmap = devm_regmap_init_i2c(twl->client,
784 &twl_regmap_config[i]);
785 if (IS_ERR(twl->regmap)) {
786 status = PTR_ERR(twl->regmap);
787 dev_err(&client->dev,
788 "Failed to allocate regmap %d, err: %d\n", i,
789 status);
790 goto fail;
791 }
792 }
793
794 twl_priv->ready = true;
795
796 /* setup clock framework */
797 clocks_init(&client->dev);
798
799 /* read TWL IDCODE Register */
800 if (twl_class_is_4030()) {
801 status = twl_read_idcode_register();
802 WARN(status < 0, "Error: reading twl_idcode register value\n");
803 }
804
805 /* Maybe init the T2 Interrupt subsystem */
806 if (client->irq) {
807 if (twl_class_is_4030()) {
808 twl4030_init_chip_irq(id->name);
809 irq_base = twl4030_init_irq(&client->dev, client->irq);
810 } else {
811 irq_base = twl6030_init_irq(&client->dev, client->irq);
812 }
813
814 if (irq_base < 0) {
815 status = irq_base;
816 goto fail;
817 }
818 }
819
820 /*
821 * Disable TWL4030/TWL5030 I2C Pull-up on I2C1 and I2C4(SR) interface.
822 * Program I2C_SCL_CTRL_PU(bit 0)=0, I2C_SDA_CTRL_PU (bit 2)=0,
823 * SR_I2C_SCL_CTRL_PU(bit 4)=0 and SR_I2C_SDA_CTRL_PU(bit 6)=0.
824 *
825 * Also, always enable SmartReflex bit as that's needed for omaps to
826 * do anything over I2C4 for voltage scaling even if SmartReflex
827 * is disabled. Without the SmartReflex bit omap sys_clkreq idle
828 * signal will never trigger for retention idle.
829 */
830 if (twl_class_is_4030()) {
831 u8 temp;
832
833 twl_i2c_read_u8(TWL4030_MODULE_INTBR, &temp, REG_GPPUPDCTR1);
834 temp &= ~(SR_I2C_SDA_CTRL_PU | SR_I2C_SCL_CTRL_PU | \
835 I2C_SDA_CTRL_PU | I2C_SCL_CTRL_PU);
836 twl_i2c_write_u8(TWL4030_MODULE_INTBR, temp, REG_GPPUPDCTR1);
837
838 twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp,
839 TWL4030_DCDC_GLOBAL_CFG);
840 temp |= SMARTREFLEX_ENABLE;
841 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp,
842 TWL4030_DCDC_GLOBAL_CFG);
843 }
844
845 if (id->driver_data == (TWL6030_CLASS | TWL6032_SUBCLASS)) {
846 status = devm_mfd_add_devices(&client->dev,
847 PLATFORM_DEVID_NONE,
848 twl6032_cells,
849 ARRAY_SIZE(twl6032_cells),
850 NULL, 0, NULL);
851 if (status < 0)
852 goto free;
853 }
854
855 status = of_platform_populate(node, NULL, twl_auxdata_lookup,
856 &client->dev);
857
858fail:
859 if (status < 0)
860 twl_remove(client);
861free:
862 if (status < 0)
863 platform_device_unregister(pdev);
864
865 return status;
866}
867
868static int __maybe_unused twl_suspend(struct device *dev)
869{
870 struct i2c_client *client = to_i2c_client(dev);
871
872 if (client->irq)
873 disable_irq(client->irq);
874
875 return 0;
876}
877
878static int __maybe_unused twl_resume(struct device *dev)
879{
880 struct i2c_client *client = to_i2c_client(dev);
881
882 if (client->irq)
883 enable_irq(client->irq);
884
885 return 0;
886}
887
888static SIMPLE_DEV_PM_OPS(twl_dev_pm_ops, twl_suspend, twl_resume);
889
890static const struct i2c_device_id twl_ids[] = {
891 { "twl4030", TWL4030_VAUX2 }, /* "Triton 2" */
892 { "twl5030", 0 }, /* T2 updated */
893 { "twl5031", TWL5031 }, /* TWL5030 updated */
894 { "tps65950", 0 }, /* catalog version of twl5030 */
895 { "tps65930", TPS_SUBSET }, /* fewer LDOs and DACs; no charger */
896 { "tps65920", TPS_SUBSET }, /* fewer LDOs; no codec or charger */
897 { "tps65921", TPS_SUBSET }, /* fewer LDOs; no codec, no LED
898 and vibrator. Charger in USB module*/
899 { "twl6030", TWL6030_CLASS }, /* "Phoenix power chip" */
900 { "twl6032", TWL6030_CLASS | TWL6032_SUBCLASS }, /* "Phoenix lite" */
901 { /* end of list */ },
902};
903
904/* One Client Driver , 4 Clients */
905static struct i2c_driver twl_driver = {
906 .driver.name = DRIVER_NAME,
907 .driver.pm = &twl_dev_pm_ops,
908 .id_table = twl_ids,
909 .probe = twl_probe,
910 .remove = twl_remove,
911};
912builtin_i2c_driver(twl_driver);
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * twl_core.c - driver for TWL4030/TWL5030/TWL60X0/TPS659x0 PM
4 * and audio CODEC devices
5 *
6 * Copyright (C) 2005-2006 Texas Instruments, Inc.
7 *
8 * Modifications to defer interrupt handling to a kernel thread:
9 * Copyright (C) 2006 MontaVista Software, Inc.
10 *
11 * Based on tlv320aic23.c:
12 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
13 *
14 * Code cleanup and modifications to IRQ handler.
15 * by syed khasim <x0khasim@ti.com>
16 */
17
18#include <linux/init.h>
19#include <linux/mutex.h>
20#include <linux/platform_device.h>
21#include <linux/regmap.h>
22#include <linux/clk.h>
23#include <linux/err.h>
24#include <linux/device.h>
25#include <linux/of.h>
26#include <linux/of_irq.h>
27#include <linux/of_platform.h>
28#include <linux/irq.h>
29#include <linux/irqdomain.h>
30
31#include <linux/regulator/machine.h>
32
33#include <linux/i2c.h>
34#include <linux/mfd/twl.h>
35
36/* Register descriptions for audio */
37#include <linux/mfd/twl4030-audio.h>
38
39#include "twl-core.h"
40
41/*
42 * The TWL4030 "Triton 2" is one of a family of a multi-function "Power
43 * Management and System Companion Device" chips originally designed for
44 * use in OMAP2 and OMAP 3 based systems. Its control interfaces use I2C,
45 * often at around 3 Mbit/sec, including for interrupt handling.
46 *
47 * This driver core provides genirq support for the interrupts emitted,
48 * by the various modules, and exports register access primitives.
49 *
50 * FIXME this driver currently requires use of the first interrupt line
51 * (and associated registers).
52 */
53
54#define DRIVER_NAME "twl"
55
56/* Triton Core internal information (BEGIN) */
57
58/* Base Address defns for twl4030_map[] */
59
60/* subchip/slave 0 - USB ID */
61#define TWL4030_BASEADD_USB 0x0000
62
63/* subchip/slave 1 - AUD ID */
64#define TWL4030_BASEADD_AUDIO_VOICE 0x0000
65#define TWL4030_BASEADD_GPIO 0x0098
66#define TWL4030_BASEADD_INTBR 0x0085
67#define TWL4030_BASEADD_PIH 0x0080
68#define TWL4030_BASEADD_TEST 0x004C
69
70/* subchip/slave 2 - AUX ID */
71#define TWL4030_BASEADD_INTERRUPTS 0x00B9
72#define TWL4030_BASEADD_LED 0x00EE
73#define TWL4030_BASEADD_MADC 0x0000
74#define TWL4030_BASEADD_MAIN_CHARGE 0x0074
75#define TWL4030_BASEADD_PRECHARGE 0x00AA
76#define TWL4030_BASEADD_PWM 0x00F8
77#define TWL4030_BASEADD_KEYPAD 0x00D2
78
79#define TWL5031_BASEADD_ACCESSORY 0x0074 /* Replaces Main Charge */
80#define TWL5031_BASEADD_INTERRUPTS 0x00B9 /* Different than TWL4030's
81 one */
82
83/* subchip/slave 3 - POWER ID */
84#define TWL4030_BASEADD_BACKUP 0x0014
85#define TWL4030_BASEADD_INT 0x002E
86#define TWL4030_BASEADD_PM_MASTER 0x0036
87
88#define TWL4030_BASEADD_PM_RECEIVER 0x005B
89#define TWL4030_DCDC_GLOBAL_CFG 0x06
90#define SMARTREFLEX_ENABLE BIT(3)
91
92#define TWL4030_BASEADD_RTC 0x001C
93#define TWL4030_BASEADD_SECURED_REG 0x0000
94
95/* Triton Core internal information (END) */
96
97
98/* subchip/slave 0 0x48 - POWER */
99#define TWL6030_BASEADD_RTC 0x0000
100#define TWL6030_BASEADD_SECURED_REG 0x0017
101#define TWL6030_BASEADD_PM_MASTER 0x001F
102#define TWL6030_BASEADD_PM_SLAVE_MISC 0x0030 /* PM_RECEIVER */
103#define TWL6030_BASEADD_PM_MISC 0x00E2
104#define TWL6030_BASEADD_PM_PUPD 0x00F0
105
106/* subchip/slave 1 0x49 - FEATURE */
107#define TWL6030_BASEADD_USB 0x0000
108#define TWL6030_BASEADD_GPADC_CTRL 0x002E
109#define TWL6030_BASEADD_AUX 0x0090
110#define TWL6030_BASEADD_PWM 0x00BA
111#define TWL6030_BASEADD_GASGAUGE 0x00C0
112#define TWL6030_BASEADD_PIH 0x00D0
113#define TWL6030_BASEADD_CHARGER 0x00E0
114#define TWL6032_BASEADD_CHARGER 0x00DA
115#define TWL6030_BASEADD_LED 0x00F4
116
117/* subchip/slave 2 0x4A - DFT */
118#define TWL6030_BASEADD_DIEID 0x00C0
119
120/* subchip/slave 3 0x4B - AUDIO */
121#define TWL6030_BASEADD_AUDIO 0x0000
122#define TWL6030_BASEADD_RSV 0x0000
123#define TWL6030_BASEADD_ZERO 0x0000
124
125/* Few power values */
126#define R_CFG_BOOT 0x05
127
128/* some fields in R_CFG_BOOT */
129#define HFCLK_FREQ_19p2_MHZ (1 << 0)
130#define HFCLK_FREQ_26_MHZ (2 << 0)
131#define HFCLK_FREQ_38p4_MHZ (3 << 0)
132#define HIGH_PERF_SQ (1 << 3)
133#define CK32K_LOWPWR_EN (1 << 7)
134
135/*----------------------------------------------------------------------*/
136
137/* Structure for each TWL4030/TWL6030 Slave */
138struct twl_client {
139 struct i2c_client *client;
140 struct regmap *regmap;
141};
142
143/* mapping the module id to slave id and base address */
144struct twl_mapping {
145 unsigned char sid; /* Slave ID */
146 unsigned char base; /* base address */
147};
148
149struct twl_private {
150 bool ready; /* The core driver is ready to be used */
151 u32 twl_idcode; /* TWL IDCODE Register value */
152 unsigned int twl_id;
153
154 struct twl_mapping *twl_map;
155 struct twl_client *twl_modules;
156};
157
158static struct twl_private *twl_priv;
159
160static struct twl_mapping twl4030_map[] = {
161 /*
162 * NOTE: don't change this table without updating the
163 * <linux/mfd/twl.h> defines for TWL4030_MODULE_*
164 * so they continue to match the order in this table.
165 */
166
167 /* Common IPs */
168 { 0, TWL4030_BASEADD_USB },
169 { 1, TWL4030_BASEADD_PIH },
170 { 2, TWL4030_BASEADD_MAIN_CHARGE },
171 { 3, TWL4030_BASEADD_PM_MASTER },
172 { 3, TWL4030_BASEADD_PM_RECEIVER },
173
174 { 3, TWL4030_BASEADD_RTC },
175 { 2, TWL4030_BASEADD_PWM },
176 { 2, TWL4030_BASEADD_LED },
177 { 3, TWL4030_BASEADD_SECURED_REG },
178
179 /* TWL4030 specific IPs */
180 { 1, TWL4030_BASEADD_AUDIO_VOICE },
181 { 1, TWL4030_BASEADD_GPIO },
182 { 1, TWL4030_BASEADD_INTBR },
183 { 1, TWL4030_BASEADD_TEST },
184 { 2, TWL4030_BASEADD_KEYPAD },
185
186 { 2, TWL4030_BASEADD_MADC },
187 { 2, TWL4030_BASEADD_INTERRUPTS },
188 { 2, TWL4030_BASEADD_PRECHARGE },
189 { 3, TWL4030_BASEADD_BACKUP },
190 { 3, TWL4030_BASEADD_INT },
191
192 { 2, TWL5031_BASEADD_ACCESSORY },
193 { 2, TWL5031_BASEADD_INTERRUPTS },
194};
195
196static const struct reg_default twl4030_49_defaults[] = {
197 /* Audio Registers */
198 { 0x01, 0x00}, /* CODEC_MODE */
199 { 0x02, 0x00}, /* OPTION */
200 /* 0x03 Unused */
201 { 0x04, 0x00}, /* MICBIAS_CTL */
202 { 0x05, 0x00}, /* ANAMICL */
203 { 0x06, 0x00}, /* ANAMICR */
204 { 0x07, 0x00}, /* AVADC_CTL */
205 { 0x08, 0x00}, /* ADCMICSEL */
206 { 0x09, 0x00}, /* DIGMIXING */
207 { 0x0a, 0x0f}, /* ATXL1PGA */
208 { 0x0b, 0x0f}, /* ATXR1PGA */
209 { 0x0c, 0x0f}, /* AVTXL2PGA */
210 { 0x0d, 0x0f}, /* AVTXR2PGA */
211 { 0x0e, 0x00}, /* AUDIO_IF */
212 { 0x0f, 0x00}, /* VOICE_IF */
213 { 0x10, 0x3f}, /* ARXR1PGA */
214 { 0x11, 0x3f}, /* ARXL1PGA */
215 { 0x12, 0x3f}, /* ARXR2PGA */
216 { 0x13, 0x3f}, /* ARXL2PGA */
217 { 0x14, 0x25}, /* VRXPGA */
218 { 0x15, 0x00}, /* VSTPGA */
219 { 0x16, 0x00}, /* VRX2ARXPGA */
220 { 0x17, 0x00}, /* AVDAC_CTL */
221 { 0x18, 0x00}, /* ARX2VTXPGA */
222 { 0x19, 0x32}, /* ARXL1_APGA_CTL*/
223 { 0x1a, 0x32}, /* ARXR1_APGA_CTL*/
224 { 0x1b, 0x32}, /* ARXL2_APGA_CTL*/
225 { 0x1c, 0x32}, /* ARXR2_APGA_CTL*/
226 { 0x1d, 0x00}, /* ATX2ARXPGA */
227 { 0x1e, 0x00}, /* BT_IF */
228 { 0x1f, 0x55}, /* BTPGA */
229 { 0x20, 0x00}, /* BTSTPGA */
230 { 0x21, 0x00}, /* EAR_CTL */
231 { 0x22, 0x00}, /* HS_SEL */
232 { 0x23, 0x00}, /* HS_GAIN_SET */
233 { 0x24, 0x00}, /* HS_POPN_SET */
234 { 0x25, 0x00}, /* PREDL_CTL */
235 { 0x26, 0x00}, /* PREDR_CTL */
236 { 0x27, 0x00}, /* PRECKL_CTL */
237 { 0x28, 0x00}, /* PRECKR_CTL */
238 { 0x29, 0x00}, /* HFL_CTL */
239 { 0x2a, 0x00}, /* HFR_CTL */
240 { 0x2b, 0x05}, /* ALC_CTL */
241 { 0x2c, 0x00}, /* ALC_SET1 */
242 { 0x2d, 0x00}, /* ALC_SET2 */
243 { 0x2e, 0x00}, /* BOOST_CTL */
244 { 0x2f, 0x00}, /* SOFTVOL_CTL */
245 { 0x30, 0x13}, /* DTMF_FREQSEL */
246 { 0x31, 0x00}, /* DTMF_TONEXT1H */
247 { 0x32, 0x00}, /* DTMF_TONEXT1L */
248 { 0x33, 0x00}, /* DTMF_TONEXT2H */
249 { 0x34, 0x00}, /* DTMF_TONEXT2L */
250 { 0x35, 0x79}, /* DTMF_TONOFF */
251 { 0x36, 0x11}, /* DTMF_WANONOFF */
252 { 0x37, 0x00}, /* I2S_RX_SCRAMBLE_H */
253 { 0x38, 0x00}, /* I2S_RX_SCRAMBLE_M */
254 { 0x39, 0x00}, /* I2S_RX_SCRAMBLE_L */
255 { 0x3a, 0x06}, /* APLL_CTL */
256 { 0x3b, 0x00}, /* DTMF_CTL */
257 { 0x3c, 0x44}, /* DTMF_PGA_CTL2 (0x3C) */
258 { 0x3d, 0x69}, /* DTMF_PGA_CTL1 (0x3D) */
259 { 0x3e, 0x00}, /* MISC_SET_1 */
260 { 0x3f, 0x00}, /* PCMBTMUX */
261 /* 0x40 - 0x42 Unused */
262 { 0x43, 0x00}, /* RX_PATH_SEL */
263 { 0x44, 0x32}, /* VDL_APGA_CTL */
264 { 0x45, 0x00}, /* VIBRA_CTL */
265 { 0x46, 0x00}, /* VIBRA_SET */
266 { 0x47, 0x00}, /* VIBRA_PWM_SET */
267 { 0x48, 0x00}, /* ANAMIC_GAIN */
268 { 0x49, 0x00}, /* MISC_SET_2 */
269 /* End of Audio Registers */
270};
271
272static bool twl4030_49_nop_reg(struct device *dev, unsigned int reg)
273{
274 switch (reg) {
275 case 0x00:
276 case 0x03:
277 case 0x40:
278 case 0x41:
279 case 0x42:
280 return false;
281 default:
282 return true;
283 }
284}
285
286static const struct regmap_range twl4030_49_volatile_ranges[] = {
287 regmap_reg_range(TWL4030_BASEADD_TEST, 0xff),
288};
289
290static const struct regmap_access_table twl4030_49_volatile_table = {
291 .yes_ranges = twl4030_49_volatile_ranges,
292 .n_yes_ranges = ARRAY_SIZE(twl4030_49_volatile_ranges),
293};
294
295static const struct regmap_config twl4030_regmap_config[4] = {
296 {
297 /* Address 0x48 */
298 .reg_bits = 8,
299 .val_bits = 8,
300 .max_register = 0xff,
301 },
302 {
303 /* Address 0x49 */
304 .reg_bits = 8,
305 .val_bits = 8,
306 .max_register = 0xff,
307
308 .readable_reg = twl4030_49_nop_reg,
309 .writeable_reg = twl4030_49_nop_reg,
310
311 .volatile_table = &twl4030_49_volatile_table,
312
313 .reg_defaults = twl4030_49_defaults,
314 .num_reg_defaults = ARRAY_SIZE(twl4030_49_defaults),
315 .cache_type = REGCACHE_RBTREE,
316 },
317 {
318 /* Address 0x4a */
319 .reg_bits = 8,
320 .val_bits = 8,
321 .max_register = 0xff,
322 },
323 {
324 /* Address 0x4b */
325 .reg_bits = 8,
326 .val_bits = 8,
327 .max_register = 0xff,
328 },
329};
330
331static struct twl_mapping twl6030_map[] = {
332 /*
333 * NOTE: don't change this table without updating the
334 * <linux/mfd/twl.h> defines for TWL4030_MODULE_*
335 * so they continue to match the order in this table.
336 */
337
338 /* Common IPs */
339 { 1, TWL6030_BASEADD_USB },
340 { 1, TWL6030_BASEADD_PIH },
341 { 1, TWL6030_BASEADD_CHARGER },
342 { 0, TWL6030_BASEADD_PM_MASTER },
343 { 0, TWL6030_BASEADD_PM_SLAVE_MISC },
344
345 { 0, TWL6030_BASEADD_RTC },
346 { 1, TWL6030_BASEADD_PWM },
347 { 1, TWL6030_BASEADD_LED },
348 { 0, TWL6030_BASEADD_SECURED_REG },
349
350 /* TWL6030 specific IPs */
351 { 0, TWL6030_BASEADD_ZERO },
352 { 1, TWL6030_BASEADD_ZERO },
353 { 2, TWL6030_BASEADD_ZERO },
354 { 1, TWL6030_BASEADD_GPADC_CTRL },
355 { 1, TWL6030_BASEADD_GASGAUGE },
356};
357
358static const struct regmap_config twl6030_regmap_config[3] = {
359 {
360 /* Address 0x48 */
361 .reg_bits = 8,
362 .val_bits = 8,
363 .max_register = 0xff,
364 },
365 {
366 /* Address 0x49 */
367 .reg_bits = 8,
368 .val_bits = 8,
369 .max_register = 0xff,
370 },
371 {
372 /* Address 0x4a */
373 .reg_bits = 8,
374 .val_bits = 8,
375 .max_register = 0xff,
376 },
377};
378
379/*----------------------------------------------------------------------*/
380
381static inline int twl_get_num_slaves(void)
382{
383 if (twl_class_is_4030())
384 return 4; /* TWL4030 class have four slave address */
385 else
386 return 3; /* TWL6030 class have three slave address */
387}
388
389static inline int twl_get_last_module(void)
390{
391 if (twl_class_is_4030())
392 return TWL4030_MODULE_LAST;
393 else
394 return TWL6030_MODULE_LAST;
395}
396
397/* Exported Functions */
398
399unsigned int twl_rev(void)
400{
401 return twl_priv ? twl_priv->twl_id : 0;
402}
403EXPORT_SYMBOL(twl_rev);
404
405/**
406 * twl_get_regmap - Get the regmap associated with the given module
407 * @mod_no: module number
408 *
409 * Returns the regmap pointer or NULL in case of failure.
410 */
411static struct regmap *twl_get_regmap(u8 mod_no)
412{
413 int sid;
414 struct twl_client *twl;
415
416 if (unlikely(!twl_priv || !twl_priv->ready)) {
417 pr_err("%s: not initialized\n", DRIVER_NAME);
418 return NULL;
419 }
420 if (unlikely(mod_no >= twl_get_last_module())) {
421 pr_err("%s: invalid module number %d\n", DRIVER_NAME, mod_no);
422 return NULL;
423 }
424
425 sid = twl_priv->twl_map[mod_no].sid;
426 twl = &twl_priv->twl_modules[sid];
427
428 return twl->regmap;
429}
430
431/**
432 * twl_i2c_write - Writes a n bit register in TWL4030/TWL5030/TWL60X0
433 * @mod_no: module number
434 * @value: an array of num_bytes+1 containing data to write
435 * @reg: register address (just offset will do)
436 * @num_bytes: number of bytes to transfer
437 *
438 * Returns 0 on success or else a negative error code.
439 */
440int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes)
441{
442 struct regmap *regmap = twl_get_regmap(mod_no);
443 int ret;
444
445 if (!regmap)
446 return -EPERM;
447
448 ret = regmap_bulk_write(regmap, twl_priv->twl_map[mod_no].base + reg,
449 value, num_bytes);
450
451 if (ret)
452 pr_err("%s: Write failed (mod %d, reg 0x%02x count %d)\n",
453 DRIVER_NAME, mod_no, reg, num_bytes);
454
455 return ret;
456}
457EXPORT_SYMBOL(twl_i2c_write);
458
459/**
460 * twl_i2c_read - Reads a n bit register in TWL4030/TWL5030/TWL60X0
461 * @mod_no: module number
462 * @value: an array of num_bytes containing data to be read
463 * @reg: register address (just offset will do)
464 * @num_bytes: number of bytes to transfer
465 *
466 * Returns 0 on success or else a negative error code.
467 */
468int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes)
469{
470 struct regmap *regmap = twl_get_regmap(mod_no);
471 int ret;
472
473 if (!regmap)
474 return -EPERM;
475
476 ret = regmap_bulk_read(regmap, twl_priv->twl_map[mod_no].base + reg,
477 value, num_bytes);
478
479 if (ret)
480 pr_err("%s: Read failed (mod %d, reg 0x%02x count %d)\n",
481 DRIVER_NAME, mod_no, reg, num_bytes);
482
483 return ret;
484}
485EXPORT_SYMBOL(twl_i2c_read);
486
487/**
488 * twl_set_regcache_bypass - Configure the regcache bypass for the regmap associated
489 * with the module
490 * @mod_no: module number
491 * @enable: Regcache bypass state
492 *
493 * Returns 0 else failure.
494 */
495int twl_set_regcache_bypass(u8 mod_no, bool enable)
496{
497 struct regmap *regmap = twl_get_regmap(mod_no);
498
499 if (!regmap)
500 return -EPERM;
501
502 regcache_cache_bypass(regmap, enable);
503
504 return 0;
505}
506EXPORT_SYMBOL(twl_set_regcache_bypass);
507
508/*----------------------------------------------------------------------*/
509
510/**
511 * twl_read_idcode_register - API to read the IDCODE register.
512 *
513 * Unlocks the IDCODE register and read the 32 bit value.
514 */
515static int twl_read_idcode_register(void)
516{
517 int err;
518
519 err = twl_i2c_write_u8(TWL4030_MODULE_INTBR, TWL_EEPROM_R_UNLOCK,
520 REG_UNLOCK_TEST_REG);
521 if (err) {
522 pr_err("TWL4030 Unable to unlock IDCODE registers -%d\n", err);
523 goto fail;
524 }
525
526 err = twl_i2c_read(TWL4030_MODULE_INTBR, (u8 *)(&twl_priv->twl_idcode),
527 REG_IDCODE_7_0, 4);
528 if (err) {
529 pr_err("TWL4030: unable to read IDCODE -%d\n", err);
530 goto fail;
531 }
532
533 err = twl_i2c_write_u8(TWL4030_MODULE_INTBR, 0x0, REG_UNLOCK_TEST_REG);
534 if (err)
535 pr_err("TWL4030 Unable to relock IDCODE registers -%d\n", err);
536fail:
537 return err;
538}
539
540/**
541 * twl_get_type - API to get TWL Si type.
542 *
543 * Api to get the TWL Si type from IDCODE value.
544 */
545int twl_get_type(void)
546{
547 return TWL_SIL_TYPE(twl_priv->twl_idcode);
548}
549EXPORT_SYMBOL_GPL(twl_get_type);
550
551/**
552 * twl_get_version - API to get TWL Si version.
553 *
554 * Api to get the TWL Si version from IDCODE value.
555 */
556int twl_get_version(void)
557{
558 return TWL_SIL_REV(twl_priv->twl_idcode);
559}
560EXPORT_SYMBOL_GPL(twl_get_version);
561
562/**
563 * twl_get_hfclk_rate - API to get TWL external HFCLK clock rate.
564 *
565 * Api to get the TWL HFCLK rate based on BOOT_CFG register.
566 */
567int twl_get_hfclk_rate(void)
568{
569 u8 ctrl;
570 int rate;
571
572 twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &ctrl, R_CFG_BOOT);
573
574 switch (ctrl & 0x3) {
575 case HFCLK_FREQ_19p2_MHZ:
576 rate = 19200000;
577 break;
578 case HFCLK_FREQ_26_MHZ:
579 rate = 26000000;
580 break;
581 case HFCLK_FREQ_38p4_MHZ:
582 rate = 38400000;
583 break;
584 default:
585 pr_err("TWL4030: HFCLK is not configured\n");
586 rate = -EINVAL;
587 break;
588 }
589
590 return rate;
591}
592EXPORT_SYMBOL_GPL(twl_get_hfclk_rate);
593
594static struct device *
595add_numbered_child(unsigned mod_no, const char *name, int num,
596 void *pdata, unsigned pdata_len,
597 bool can_wakeup, int irq0, int irq1)
598{
599 struct platform_device *pdev;
600 struct twl_client *twl;
601 int status, sid;
602
603 if (unlikely(mod_no >= twl_get_last_module())) {
604 pr_err("%s: invalid module number %d\n", DRIVER_NAME, mod_no);
605 return ERR_PTR(-EPERM);
606 }
607 sid = twl_priv->twl_map[mod_no].sid;
608 twl = &twl_priv->twl_modules[sid];
609
610 pdev = platform_device_alloc(name, num);
611 if (!pdev)
612 return ERR_PTR(-ENOMEM);
613
614 pdev->dev.parent = &twl->client->dev;
615
616 if (pdata) {
617 status = platform_device_add_data(pdev, pdata, pdata_len);
618 if (status < 0) {
619 dev_dbg(&pdev->dev, "can't add platform_data\n");
620 goto put_device;
621 }
622 }
623
624 if (irq0) {
625 struct resource r[2] = {
626 { .start = irq0, .flags = IORESOURCE_IRQ, },
627 { .start = irq1, .flags = IORESOURCE_IRQ, },
628 };
629
630 status = platform_device_add_resources(pdev, r, irq1 ? 2 : 1);
631 if (status < 0) {
632 dev_dbg(&pdev->dev, "can't add irqs\n");
633 goto put_device;
634 }
635 }
636
637 status = platform_device_add(pdev);
638 if (status)
639 goto put_device;
640
641 device_init_wakeup(&pdev->dev, can_wakeup);
642
643 return &pdev->dev;
644
645put_device:
646 platform_device_put(pdev);
647 dev_err(&twl->client->dev, "failed to add device %s\n", name);
648 return ERR_PTR(status);
649}
650
651static inline struct device *add_child(unsigned mod_no, const char *name,
652 void *pdata, unsigned pdata_len,
653 bool can_wakeup, int irq0, int irq1)
654{
655 return add_numbered_child(mod_no, name, -1, pdata, pdata_len,
656 can_wakeup, irq0, irq1);
657}
658
659/*----------------------------------------------------------------------*/
660
661/*
662 * These three functions initialize the on-chip clock framework,
663 * letting it generate the right frequencies for USB, MADC, and
664 * other purposes.
665 */
666static inline int protect_pm_master(void)
667{
668 int e = 0;
669
670 e = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
671 TWL4030_PM_MASTER_PROTECT_KEY);
672 return e;
673}
674
675static inline int unprotect_pm_master(void)
676{
677 int e = 0;
678
679 e |= twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
680 TWL4030_PM_MASTER_PROTECT_KEY);
681 e |= twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
682 TWL4030_PM_MASTER_PROTECT_KEY);
683
684 return e;
685}
686
687static void clocks_init(struct device *dev)
688{
689 int e = 0;
690 struct clk *osc;
691 u32 rate;
692 u8 ctrl = HFCLK_FREQ_26_MHZ;
693
694 osc = clk_get(dev, "fck");
695 if (IS_ERR(osc)) {
696 printk(KERN_WARNING "Skipping twl internal clock init and "
697 "using bootloader value (unknown osc rate)\n");
698 return;
699 }
700
701 rate = clk_get_rate(osc);
702 clk_put(osc);
703
704 switch (rate) {
705 case 19200000:
706 ctrl = HFCLK_FREQ_19p2_MHZ;
707 break;
708 case 26000000:
709 ctrl = HFCLK_FREQ_26_MHZ;
710 break;
711 case 38400000:
712 ctrl = HFCLK_FREQ_38p4_MHZ;
713 break;
714 }
715
716 ctrl |= HIGH_PERF_SQ;
717
718 e |= unprotect_pm_master();
719 /* effect->MADC+USB ck en */
720 e |= twl_i2c_write_u8(TWL_MODULE_PM_MASTER, ctrl, R_CFG_BOOT);
721 e |= protect_pm_master();
722
723 if (e < 0)
724 pr_err("%s: clock init err [%d]\n", DRIVER_NAME, e);
725}
726
727/*----------------------------------------------------------------------*/
728
729
730static void twl_remove(struct i2c_client *client)
731{
732 unsigned i, num_slaves;
733
734 if (twl_class_is_4030())
735 twl4030_exit_irq();
736 else
737 twl6030_exit_irq();
738
739 num_slaves = twl_get_num_slaves();
740 for (i = 0; i < num_slaves; i++) {
741 struct twl_client *twl = &twl_priv->twl_modules[i];
742
743 if (twl->client && twl->client != client)
744 i2c_unregister_device(twl->client);
745 twl->client = NULL;
746 }
747 twl_priv->ready = false;
748}
749
750static struct of_dev_auxdata twl_auxdata_lookup[] = {
751 OF_DEV_AUXDATA("ti,twl4030-gpio", 0, "twl4030-gpio", NULL),
752 { /* sentinel */ },
753};
754
755/* NOTE: This driver only handles a single twl4030/tps659x0 chip */
756static int
757twl_probe(struct i2c_client *client)
758{
759 const struct i2c_device_id *id = i2c_client_get_device_id(client);
760 struct device_node *node = client->dev.of_node;
761 struct platform_device *pdev;
762 const struct regmap_config *twl_regmap_config;
763 int irq_base = 0;
764 int status;
765 unsigned i, num_slaves;
766
767 if (!node) {
768 dev_err(&client->dev, "no platform data\n");
769 return -EINVAL;
770 }
771
772 if (twl_priv) {
773 dev_dbg(&client->dev, "only one instance of %s allowed\n",
774 DRIVER_NAME);
775 return -EBUSY;
776 }
777
778 pdev = platform_device_alloc(DRIVER_NAME, -1);
779 if (!pdev) {
780 dev_err(&client->dev, "can't alloc pdev\n");
781 return -ENOMEM;
782 }
783
784 status = platform_device_add(pdev);
785 if (status) {
786 platform_device_put(pdev);
787 return status;
788 }
789
790 if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C) == 0) {
791 dev_dbg(&client->dev, "can't talk I2C?\n");
792 status = -EIO;
793 goto free;
794 }
795
796 twl_priv = devm_kzalloc(&client->dev, sizeof(struct twl_private),
797 GFP_KERNEL);
798 if (!twl_priv) {
799 status = -ENOMEM;
800 goto free;
801 }
802
803 if ((id->driver_data) & TWL6030_CLASS) {
804 twl_priv->twl_id = TWL6030_CLASS_ID;
805 twl_priv->twl_map = &twl6030_map[0];
806 /* The charger base address is different in twl6032 */
807 if ((id->driver_data) & TWL6032_SUBCLASS)
808 twl_priv->twl_map[TWL_MODULE_MAIN_CHARGE].base =
809 TWL6032_BASEADD_CHARGER;
810 twl_regmap_config = twl6030_regmap_config;
811 } else {
812 twl_priv->twl_id = TWL4030_CLASS_ID;
813 twl_priv->twl_map = &twl4030_map[0];
814 twl_regmap_config = twl4030_regmap_config;
815 }
816
817 num_slaves = twl_get_num_slaves();
818 twl_priv->twl_modules = devm_kcalloc(&client->dev,
819 num_slaves,
820 sizeof(struct twl_client),
821 GFP_KERNEL);
822 if (!twl_priv->twl_modules) {
823 status = -ENOMEM;
824 goto free;
825 }
826
827 for (i = 0; i < num_slaves; i++) {
828 struct twl_client *twl = &twl_priv->twl_modules[i];
829
830 if (i == 0) {
831 twl->client = client;
832 } else {
833 twl->client = i2c_new_dummy_device(client->adapter,
834 client->addr + i);
835 if (IS_ERR(twl->client)) {
836 dev_err(&client->dev,
837 "can't attach client %d\n", i);
838 status = PTR_ERR(twl->client);
839 goto fail;
840 }
841 }
842
843 twl->regmap = devm_regmap_init_i2c(twl->client,
844 &twl_regmap_config[i]);
845 if (IS_ERR(twl->regmap)) {
846 status = PTR_ERR(twl->regmap);
847 dev_err(&client->dev,
848 "Failed to allocate regmap %d, err: %d\n", i,
849 status);
850 goto fail;
851 }
852 }
853
854 twl_priv->ready = true;
855
856 /* setup clock framework */
857 clocks_init(&client->dev);
858
859 /* read TWL IDCODE Register */
860 if (twl_class_is_4030()) {
861 status = twl_read_idcode_register();
862 WARN(status < 0, "Error: reading twl_idcode register value\n");
863 }
864
865 /* Maybe init the T2 Interrupt subsystem */
866 if (client->irq) {
867 if (twl_class_is_4030()) {
868 twl4030_init_chip_irq(id->name);
869 irq_base = twl4030_init_irq(&client->dev, client->irq);
870 } else {
871 irq_base = twl6030_init_irq(&client->dev, client->irq);
872 }
873
874 if (irq_base < 0) {
875 status = irq_base;
876 goto fail;
877 }
878 }
879
880 /*
881 * Disable TWL4030/TWL5030 I2C Pull-up on I2C1 and I2C4(SR) interface.
882 * Program I2C_SCL_CTRL_PU(bit 0)=0, I2C_SDA_CTRL_PU (bit 2)=0,
883 * SR_I2C_SCL_CTRL_PU(bit 4)=0 and SR_I2C_SDA_CTRL_PU(bit 6)=0.
884 *
885 * Also, always enable SmartReflex bit as that's needed for omaps to
886 * do anything over I2C4 for voltage scaling even if SmartReflex
887 * is disabled. Without the SmartReflex bit omap sys_clkreq idle
888 * signal will never trigger for retention idle.
889 */
890 if (twl_class_is_4030()) {
891 u8 temp;
892
893 twl_i2c_read_u8(TWL4030_MODULE_INTBR, &temp, REG_GPPUPDCTR1);
894 temp &= ~(SR_I2C_SDA_CTRL_PU | SR_I2C_SCL_CTRL_PU | \
895 I2C_SDA_CTRL_PU | I2C_SCL_CTRL_PU);
896 twl_i2c_write_u8(TWL4030_MODULE_INTBR, temp, REG_GPPUPDCTR1);
897
898 twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp,
899 TWL4030_DCDC_GLOBAL_CFG);
900 temp |= SMARTREFLEX_ENABLE;
901 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp,
902 TWL4030_DCDC_GLOBAL_CFG);
903 }
904
905 status = of_platform_populate(node, NULL, twl_auxdata_lookup,
906 &client->dev);
907
908fail:
909 if (status < 0)
910 twl_remove(client);
911free:
912 if (status < 0)
913 platform_device_unregister(pdev);
914
915 return status;
916}
917
918static int __maybe_unused twl_suspend(struct device *dev)
919{
920 struct i2c_client *client = to_i2c_client(dev);
921
922 if (client->irq)
923 disable_irq(client->irq);
924
925 return 0;
926}
927
928static int __maybe_unused twl_resume(struct device *dev)
929{
930 struct i2c_client *client = to_i2c_client(dev);
931
932 if (client->irq)
933 enable_irq(client->irq);
934
935 return 0;
936}
937
938static SIMPLE_DEV_PM_OPS(twl_dev_pm_ops, twl_suspend, twl_resume);
939
940static const struct i2c_device_id twl_ids[] = {
941 { "twl4030", TWL4030_VAUX2 }, /* "Triton 2" */
942 { "twl5030", 0 }, /* T2 updated */
943 { "twl5031", TWL5031 }, /* TWL5030 updated */
944 { "tps65950", 0 }, /* catalog version of twl5030 */
945 { "tps65930", TPS_SUBSET }, /* fewer LDOs and DACs; no charger */
946 { "tps65920", TPS_SUBSET }, /* fewer LDOs; no codec or charger */
947 { "tps65921", TPS_SUBSET }, /* fewer LDOs; no codec, no LED
948 and vibrator. Charger in USB module*/
949 { "twl6030", TWL6030_CLASS }, /* "Phoenix power chip" */
950 { "twl6032", TWL6030_CLASS | TWL6032_SUBCLASS }, /* "Phoenix lite" */
951 { /* end of list */ },
952};
953
954/* One Client Driver , 4 Clients */
955static struct i2c_driver twl_driver = {
956 .driver.name = DRIVER_NAME,
957 .driver.pm = &twl_dev_pm_ops,
958 .id_table = twl_ids,
959 .probe_new = twl_probe,
960 .remove = twl_remove,
961};
962builtin_i2c_driver(twl_driver);