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1/*
2 * SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation
4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/iopoll.h>
9
10#include "dsi_phy.h"
11#include "dsi.xml.h"
12#include "dsi_phy_7nm.xml.h"
13
14/*
15 * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram
16 *
17 * dsi0_pll_out_div_clk dsi0_pll_bit_clk
18 * | |
19 * | |
20 * +---------+ | +----------+ | +----+
21 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
22 * +---------+ | +----------+ | +----+
23 * | |
24 * | | dsi0_pll_by_2_bit_clk
25 * | | |
26 * | | +----+ | |\ dsi0_pclk_mux
27 * | |--| /2 |--o--| \ |
28 * | | +----+ | \ | +---------+
29 * | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_out_dsiclk
30 * |------------------------------| / +---------+
31 * | +-----+ | /
32 * -----------| /4? |--o----------|/
33 * +-----+ | |
34 * | |dsiclk_sel
35 * |
36 * dsi0_pll_post_out_div_clk
37 */
38
39#define VCO_REF_CLK_RATE 19200000
40#define FRAC_BITS 18
41
42/* Hardware is pre V4.1 */
43#define DSI_PHY_7NM_QUIRK_PRE_V4_1 BIT(0)
44/* Hardware is V4.1 */
45#define DSI_PHY_7NM_QUIRK_V4_1 BIT(1)
46/* Hardware is V4.2 */
47#define DSI_PHY_7NM_QUIRK_V4_2 BIT(2)
48/* Hardware is V4.3 */
49#define DSI_PHY_7NM_QUIRK_V4_3 BIT(3)
50/* Hardware is V5.2 */
51#define DSI_PHY_7NM_QUIRK_V5_2 BIT(4)
52
53struct dsi_pll_config {
54 bool enable_ssc;
55 bool ssc_center;
56 u32 ssc_freq;
57 u32 ssc_offset;
58 u32 ssc_adj_per;
59
60 /* out */
61 u32 decimal_div_start;
62 u32 frac_div_start;
63 u32 pll_clock_inverters;
64 u32 ssc_stepsize;
65 u32 ssc_div_per;
66};
67
68struct pll_7nm_cached_state {
69 unsigned long vco_rate;
70 u8 bit_clk_div;
71 u8 pix_clk_div;
72 u8 pll_out_div;
73 u8 pll_mux;
74};
75
76struct dsi_pll_7nm {
77 struct clk_hw clk_hw;
78
79 struct msm_dsi_phy *phy;
80
81 u64 vco_current_rate;
82
83 /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */
84 spinlock_t postdiv_lock;
85
86 struct pll_7nm_cached_state cached_state;
87
88 struct dsi_pll_7nm *slave;
89};
90
91#define to_pll_7nm(x) container_of(x, struct dsi_pll_7nm, clk_hw)
92
93/*
94 * Global list of private DSI PLL struct pointers. We need this for bonded DSI
95 * mode, where the master PLL's clk_ops needs access the slave's private data
96 */
97static struct dsi_pll_7nm *pll_7nm_list[DSI_MAX];
98
99static void dsi_pll_setup_config(struct dsi_pll_config *config)
100{
101 config->ssc_freq = 31500;
102 config->ssc_offset = 4800;
103 config->ssc_adj_per = 2;
104
105 /* TODO: ssc enable */
106 config->enable_ssc = false;
107 config->ssc_center = 0;
108}
109
110static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
111{
112 u64 fref = VCO_REF_CLK_RATE;
113 u64 pll_freq;
114 u64 divider;
115 u64 dec, dec_multiple;
116 u32 frac;
117 u64 multiplier;
118
119 pll_freq = pll->vco_current_rate;
120
121 divider = fref * 2;
122
123 multiplier = 1 << FRAC_BITS;
124 dec_multiple = div_u64(pll_freq * multiplier, divider);
125 dec = div_u64_rem(dec_multiple, multiplier, &frac);
126
127 if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)
128 config->pll_clock_inverters = 0x28;
129 else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
130 if (pll_freq <= 1300000000ULL)
131 config->pll_clock_inverters = 0xa0;
132 else if (pll_freq <= 2500000000ULL)
133 config->pll_clock_inverters = 0x20;
134 else if (pll_freq <= 4000000000ULL)
135 config->pll_clock_inverters = 0x00;
136 else
137 config->pll_clock_inverters = 0x40;
138 } else {
139 if (pll_freq <= 1000000000ULL)
140 config->pll_clock_inverters = 0xa0;
141 else if (pll_freq <= 2500000000ULL)
142 config->pll_clock_inverters = 0x20;
143 else if (pll_freq <= 3020000000ULL)
144 config->pll_clock_inverters = 0x00;
145 else
146 config->pll_clock_inverters = 0x40;
147 }
148
149 config->decimal_div_start = dec;
150 config->frac_div_start = frac;
151}
152
153#define SSC_CENTER BIT(0)
154#define SSC_EN BIT(1)
155
156static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
157{
158 u32 ssc_per;
159 u32 ssc_mod;
160 u64 ssc_step_size;
161 u64 frac;
162
163 if (!config->enable_ssc) {
164 DBG("SSC not enabled\n");
165 return;
166 }
167
168 ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) / 2 - 1;
169 ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1);
170 ssc_per -= ssc_mod;
171
172 frac = config->frac_div_start;
173 ssc_step_size = config->decimal_div_start;
174 ssc_step_size *= (1 << FRAC_BITS);
175 ssc_step_size += frac;
176 ssc_step_size *= config->ssc_offset;
177 ssc_step_size *= (config->ssc_adj_per + 1);
178 ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1));
179 ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000);
180
181 config->ssc_div_per = ssc_per;
182 config->ssc_stepsize = ssc_step_size;
183
184 pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n",
185 config->decimal_div_start, frac, FRAC_BITS);
186 pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n",
187 ssc_per, (u32)ssc_step_size, config->ssc_adj_per);
188}
189
190static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
191{
192 void __iomem *base = pll->phy->pll_base;
193
194 if (config->enable_ssc) {
195 pr_debug("SSC is enabled\n");
196
197 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
198 config->ssc_stepsize & 0xff);
199 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
200 config->ssc_stepsize >> 8);
201 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1,
202 config->ssc_div_per & 0xff);
203 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
204 config->ssc_div_per >> 8);
205 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1,
206 config->ssc_adj_per & 0xff);
207 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1,
208 config->ssc_adj_per >> 8);
209 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL,
210 SSC_EN | (config->ssc_center ? SSC_CENTER : 0));
211 }
212}
213
214static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
215{
216 void __iomem *base = pll->phy->pll_base;
217 u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00;
218
219 if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1))
220 if (pll->vco_current_rate >= 3100000000ULL)
221 analog_controls_five_1 = 0x03;
222
223 if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
224 if (pll->vco_current_rate < 1520000000ULL)
225 vco_config_1 = 0x08;
226 else if (pll->vco_current_rate < 2990000000ULL)
227 vco_config_1 = 0x01;
228 }
229
230 if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) ||
231 (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) {
232 if (pll->vco_current_rate < 1520000000ULL)
233 vco_config_1 = 0x08;
234 else if (pll->vco_current_rate >= 2990000000ULL)
235 vco_config_1 = 0x01;
236 }
237
238 if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
239 if (pll->vco_current_rate < 1557000000ULL)
240 vco_config_1 = 0x08;
241 else
242 vco_config_1 = 0x01;
243 }
244
245 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
246 analog_controls_five_1);
247 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1);
248 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE, 0x01);
249 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03);
250 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00);
251 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DSM_DIVIDER, 0x00);
252 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e);
253 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40);
254 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE, 0xba);
255 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c);
256 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_OUTDIV, 0x00);
257 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE, 0x00);
258 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08);
259 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x0a);
260 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1, 0xc0);
261 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x84);
262 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x82);
263 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x4c);
264 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80);
265 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x29);
266 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f);
267 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a);
268 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT,
269 !(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) ? 0x3f : 0x22);
270
271 if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) {
272 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
273 if (pll->slave)
274 dsi_phy_write(pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
275 }
276}
277
278static void dsi_pll_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
279{
280 void __iomem *base = pll->phy->pll_base;
281
282 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
283 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1,
284 config->decimal_div_start);
285 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1,
286 config->frac_div_start & 0xff);
287 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1,
288 (config->frac_div_start & 0xff00) >> 8);
289 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1,
290 (config->frac_div_start & 0x30000) >> 16);
291 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40);
292 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
293 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1,
294 pll->phy->cphy_mode ? 0x00 : 0x10);
295 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS,
296 config->pll_clock_inverters);
297}
298
299static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
300 unsigned long parent_rate)
301{
302 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
303 struct dsi_pll_config config;
304
305 DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->phy->id, rate,
306 parent_rate);
307
308 pll_7nm->vco_current_rate = rate;
309
310 dsi_pll_setup_config(&config);
311
312 dsi_pll_calc_dec_frac(pll_7nm, &config);
313
314 dsi_pll_calc_ssc(pll_7nm, &config);
315
316 dsi_pll_commit(pll_7nm, &config);
317
318 dsi_pll_config_hzindep_reg(pll_7nm);
319
320 dsi_pll_ssc_commit(pll_7nm, &config);
321
322 /* flush, ensure all register writes are done*/
323 wmb();
324
325 return 0;
326}
327
328static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll)
329{
330 int rc;
331 u32 status = 0;
332 u32 const delay_us = 100;
333 u32 const timeout_us = 5000;
334
335 rc = readl_poll_timeout_atomic(pll->phy->pll_base +
336 REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE,
337 status,
338 ((status & BIT(0)) > 0),
339 delay_us,
340 timeout_us);
341 if (rc)
342 pr_err("DSI PLL(%d) lock failed, status=0x%08x\n",
343 pll->phy->id, status);
344
345 return rc;
346}
347
348static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
349{
350 u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
351
352 dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0);
353 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data & ~BIT(5));
354 ndelay(250);
355}
356
357static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll)
358{
359 u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
360
361 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data | BIT(5));
362 dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
363 ndelay(250);
364}
365
366static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll)
367{
368 u32 data;
369
370 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
371 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data & ~BIT(5));
372}
373
374static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll)
375{
376 u32 data;
377
378 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04);
379
380 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
381 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1,
382 data | BIT(5) | BIT(4));
383}
384
385static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll)
386{
387 /*
388 * Reset the PHY digital domain. This would be needed when
389 * coming out of a CX or analog rail power collapse while
390 * ensuring that the pads maintain LP00 or LP11 state
391 */
392 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0));
393 wmb(); /* Ensure that the reset is deasserted */
394 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0);
395 wmb(); /* Ensure that the reset is deasserted */
396}
397
398static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw)
399{
400 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
401 int rc;
402
403 dsi_pll_enable_pll_bias(pll_7nm);
404 if (pll_7nm->slave)
405 dsi_pll_enable_pll_bias(pll_7nm->slave);
406
407 /* Start PLL */
408 dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x01);
409
410 /*
411 * ensure all PLL configurations are written prior to checking
412 * for PLL lock.
413 */
414 wmb();
415
416 /* Check for PLL lock */
417 rc = dsi_pll_7nm_lock_status(pll_7nm);
418 if (rc) {
419 pr_err("PLL(%d) lock failed\n", pll_7nm->phy->id);
420 goto error;
421 }
422
423 pll_7nm->phy->pll_on = true;
424
425 /*
426 * assert power on reset for PHY digital in case the PLL is
427 * enabled after CX of analog domain power collapse. This needs
428 * to be done before enabling the global clk.
429 */
430 dsi_pll_phy_dig_reset(pll_7nm);
431 if (pll_7nm->slave)
432 dsi_pll_phy_dig_reset(pll_7nm->slave);
433
434 dsi_pll_enable_global_clk(pll_7nm);
435 if (pll_7nm->slave)
436 dsi_pll_enable_global_clk(pll_7nm->slave);
437
438error:
439 return rc;
440}
441
442static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll)
443{
444 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0);
445 dsi_pll_disable_pll_bias(pll);
446}
447
448static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw)
449{
450 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
451
452 /*
453 * To avoid any stray glitches while abruptly powering down the PLL
454 * make sure to gate the clock using the clock enable bit before
455 * powering down the PLL
456 */
457 dsi_pll_disable_global_clk(pll_7nm);
458 dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0);
459 dsi_pll_disable_sub(pll_7nm);
460 if (pll_7nm->slave) {
461 dsi_pll_disable_global_clk(pll_7nm->slave);
462 dsi_pll_disable_sub(pll_7nm->slave);
463 }
464 /* flush, ensure all register writes are done */
465 wmb();
466 pll_7nm->phy->pll_on = false;
467}
468
469static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
470 unsigned long parent_rate)
471{
472 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
473 void __iomem *base = pll_7nm->phy->pll_base;
474 u64 ref_clk = VCO_REF_CLK_RATE;
475 u64 vco_rate = 0x0;
476 u64 multiplier;
477 u32 frac;
478 u32 dec;
479 u64 pll_freq, tmp64;
480
481 dec = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1);
482 dec &= 0xff;
483
484 frac = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1);
485 frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1) &
486 0xff) << 8);
487 frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1) &
488 0x3) << 16);
489
490 /*
491 * TODO:
492 * 1. Assumes prescaler is disabled
493 */
494 multiplier = 1 << FRAC_BITS;
495 pll_freq = dec * (ref_clk * 2);
496 tmp64 = (ref_clk * 2 * frac);
497 pll_freq += div_u64(tmp64, multiplier);
498
499 vco_rate = pll_freq;
500 pll_7nm->vco_current_rate = vco_rate;
501
502 DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x",
503 pll_7nm->phy->id, (unsigned long)vco_rate, dec, frac);
504
505 return (unsigned long)vco_rate;
506}
507
508static long dsi_pll_7nm_clk_round_rate(struct clk_hw *hw,
509 unsigned long rate, unsigned long *parent_rate)
510{
511 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
512
513 if (rate < pll_7nm->phy->cfg->min_pll_rate)
514 return pll_7nm->phy->cfg->min_pll_rate;
515 else if (rate > pll_7nm->phy->cfg->max_pll_rate)
516 return pll_7nm->phy->cfg->max_pll_rate;
517 else
518 return rate;
519}
520
521static const struct clk_ops clk_ops_dsi_pll_7nm_vco = {
522 .round_rate = dsi_pll_7nm_clk_round_rate,
523 .set_rate = dsi_pll_7nm_vco_set_rate,
524 .recalc_rate = dsi_pll_7nm_vco_recalc_rate,
525 .prepare = dsi_pll_7nm_vco_prepare,
526 .unprepare = dsi_pll_7nm_vco_unprepare,
527};
528
529/*
530 * PLL Callbacks
531 */
532
533static void dsi_7nm_pll_save_state(struct msm_dsi_phy *phy)
534{
535 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
536 struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
537 void __iomem *phy_base = pll_7nm->phy->base;
538 u32 cmn_clk_cfg0, cmn_clk_cfg1;
539
540 cached->pll_out_div = dsi_phy_read(pll_7nm->phy->pll_base +
541 REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
542 cached->pll_out_div &= 0x3;
543
544 cmn_clk_cfg0 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);
545 cached->bit_clk_div = cmn_clk_cfg0 & 0xf;
546 cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4;
547
548 cmn_clk_cfg1 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
549 cached->pll_mux = cmn_clk_cfg1 & 0x3;
550
551 DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x",
552 pll_7nm->phy->id, cached->pll_out_div, cached->bit_clk_div,
553 cached->pix_clk_div, cached->pll_mux);
554}
555
556static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy)
557{
558 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
559 struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
560 void __iomem *phy_base = pll_7nm->phy->base;
561 u32 val;
562 int ret;
563
564 val = dsi_phy_read(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
565 val &= ~0x3;
566 val |= cached->pll_out_div;
567 dsi_phy_write(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, val);
568
569 dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0,
570 cached->bit_clk_div | (cached->pix_clk_div << 4));
571
572 val = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
573 val &= ~0x3;
574 val |= cached->pll_mux;
575 dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val);
576
577 ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw,
578 pll_7nm->vco_current_rate,
579 VCO_REF_CLK_RATE);
580 if (ret) {
581 DRM_DEV_ERROR(&pll_7nm->phy->pdev->dev,
582 "restore vco rate failed. ret=%d\n", ret);
583 return ret;
584 }
585
586 DBG("DSI PLL%d", pll_7nm->phy->id);
587
588 return 0;
589}
590
591static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
592{
593 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
594 void __iomem *base = phy->base;
595 u32 data = 0x0; /* internal PLL */
596
597 DBG("DSI PLL%d", pll_7nm->phy->id);
598
599 switch (phy->usecase) {
600 case MSM_DSI_PHY_STANDALONE:
601 break;
602 case MSM_DSI_PHY_MASTER:
603 pll_7nm->slave = pll_7nm_list[(pll_7nm->phy->id + 1) % DSI_MAX];
604 break;
605 case MSM_DSI_PHY_SLAVE:
606 data = 0x1; /* external PLL */
607 break;
608 default:
609 return -EINVAL;
610 }
611
612 /* set PLL src */
613 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2));
614
615 return 0;
616}
617
618/*
619 * The post dividers and mux clocks are created using the standard divider and
620 * mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux
621 * state to follow the master PLL's divider/mux state. Therefore, we don't
622 * require special clock ops that also configure the slave PLL registers
623 */
624static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provided_clocks)
625{
626 char clk_name[32];
627 struct clk_init_data vco_init = {
628 .parent_data = &(const struct clk_parent_data) {
629 .fw_name = "ref",
630 },
631 .num_parents = 1,
632 .name = clk_name,
633 .flags = CLK_IGNORE_UNUSED,
634 .ops = &clk_ops_dsi_pll_7nm_vco,
635 };
636 struct device *dev = &pll_7nm->phy->pdev->dev;
637 struct clk_hw *hw, *pll_out_div, *pll_bit, *pll_by_2_bit;
638 struct clk_hw *pll_post_out_div, *phy_pll_out_dsi_parent;
639 int ret;
640
641 DBG("DSI%d", pll_7nm->phy->id);
642
643 snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_7nm->phy->id);
644 pll_7nm->clk_hw.init = &vco_init;
645
646 ret = devm_clk_hw_register(dev, &pll_7nm->clk_hw);
647 if (ret)
648 return ret;
649
650 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
651
652 pll_out_div = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
653 &pll_7nm->clk_hw, CLK_SET_RATE_PARENT,
654 pll_7nm->phy->pll_base +
655 REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE,
656 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
657 if (IS_ERR(pll_out_div)) {
658 ret = PTR_ERR(pll_out_div);
659 goto fail;
660 }
661
662 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_bit_clk", pll_7nm->phy->id);
663
664 /* BIT CLK: DIV_CTRL_3_0 */
665 pll_bit = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
666 pll_out_div, CLK_SET_RATE_PARENT,
667 pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0,
668 0, 4, CLK_DIVIDER_ONE_BASED, &pll_7nm->postdiv_lock);
669 if (IS_ERR(pll_bit)) {
670 ret = PTR_ERR(pll_bit);
671 goto fail;
672 }
673
674 snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_byteclk", pll_7nm->phy->id);
675
676 /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
677 hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, clk_name,
678 pll_bit, CLK_SET_RATE_PARENT, 1,
679 pll_7nm->phy->cphy_mode ? 7 : 8);
680 if (IS_ERR(hw)) {
681 ret = PTR_ERR(hw);
682 goto fail;
683 }
684
685 provided_clocks[DSI_BYTE_PLL_CLK] = hw;
686
687 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id);
688
689 pll_by_2_bit = devm_clk_hw_register_fixed_factor_parent_hw(dev,
690 clk_name, pll_bit, 0, 1, 2);
691 if (IS_ERR(pll_by_2_bit)) {
692 ret = PTR_ERR(pll_by_2_bit);
693 goto fail;
694 }
695
696 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id);
697
698 if (pll_7nm->phy->cphy_mode)
699 pll_post_out_div = devm_clk_hw_register_fixed_factor_parent_hw(
700 dev, clk_name, pll_out_div, 0, 2, 7);
701 else
702 pll_post_out_div = devm_clk_hw_register_fixed_factor_parent_hw(
703 dev, clk_name, pll_out_div, 0, 1, 4);
704 if (IS_ERR(pll_post_out_div)) {
705 ret = PTR_ERR(pll_post_out_div);
706 goto fail;
707 }
708
709 /* in CPHY mode, pclk_mux will always have post_out_div as parent
710 * don't register a pclk_mux clock and just use post_out_div instead
711 */
712 if (pll_7nm->phy->cphy_mode) {
713 u32 data;
714
715 data = dsi_phy_read(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
716 dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data | 3);
717
718 phy_pll_out_dsi_parent = pll_post_out_div;
719 } else {
720 snprintf(clk_name, sizeof(clk_name), "dsi%d_pclk_mux", pll_7nm->phy->id);
721
722 hw = devm_clk_hw_register_mux_parent_hws(dev, clk_name,
723 ((const struct clk_hw *[]){
724 pll_bit,
725 pll_by_2_bit,
726 }), 2, 0, pll_7nm->phy->base +
727 REG_DSI_7nm_PHY_CMN_CLK_CFG1,
728 0, 1, 0, NULL);
729 if (IS_ERR(hw)) {
730 ret = PTR_ERR(hw);
731 goto fail;
732 }
733
734 phy_pll_out_dsi_parent = hw;
735 }
736
737 snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_dsiclk", pll_7nm->phy->id);
738
739 /* PIX CLK DIV : DIV_CTRL_7_4*/
740 hw = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
741 phy_pll_out_dsi_parent, 0,
742 pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0,
743 4, 4, CLK_DIVIDER_ONE_BASED, &pll_7nm->postdiv_lock);
744 if (IS_ERR(hw)) {
745 ret = PTR_ERR(hw);
746 goto fail;
747 }
748
749 provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
750
751 return 0;
752
753fail:
754
755 return ret;
756}
757
758static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
759{
760 struct platform_device *pdev = phy->pdev;
761 struct dsi_pll_7nm *pll_7nm;
762 int ret;
763
764 pll_7nm = devm_kzalloc(&pdev->dev, sizeof(*pll_7nm), GFP_KERNEL);
765 if (!pll_7nm)
766 return -ENOMEM;
767
768 DBG("DSI PLL%d", phy->id);
769
770 pll_7nm_list[phy->id] = pll_7nm;
771
772 spin_lock_init(&pll_7nm->postdiv_lock);
773
774 pll_7nm->phy = phy;
775
776 ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws);
777 if (ret) {
778 DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
779 return ret;
780 }
781
782 phy->vco_hw = &pll_7nm->clk_hw;
783
784 /* TODO: Remove this when we have proper display handover support */
785 msm_dsi_phy_pll_save_state(phy);
786
787 return 0;
788}
789
790static int dsi_phy_hw_v4_0_is_pll_on(struct msm_dsi_phy *phy)
791{
792 void __iomem *base = phy->base;
793 u32 data = 0;
794
795 data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL);
796 mb(); /* make sure read happened */
797
798 return (data & BIT(0));
799}
800
801static void dsi_phy_hw_v4_0_config_lpcdrx(struct msm_dsi_phy *phy, bool enable)
802{
803 void __iomem *lane_base = phy->lane_base;
804 int phy_lane_0 = 0; /* TODO: Support all lane swap configs */
805
806 /*
807 * LPRX and CDRX need to enabled only for physical data lane
808 * corresponding to the logical data lane 0
809 */
810 if (enable)
811 dsi_phy_write(lane_base +
812 REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0x3);
813 else
814 dsi_phy_write(lane_base +
815 REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0);
816}
817
818static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy)
819{
820 int i;
821 const u8 tx_dctrl_0[] = { 0x00, 0x00, 0x00, 0x04, 0x01 };
822 const u8 tx_dctrl_1[] = { 0x40, 0x40, 0x40, 0x46, 0x41 };
823 const u8 *tx_dctrl = tx_dctrl_0;
824 void __iomem *lane_base = phy->lane_base;
825
826 if (!(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1))
827 tx_dctrl = tx_dctrl_1;
828
829 /* Strength ctrl settings */
830 for (i = 0; i < 5; i++) {
831 /*
832 * Disable LPRX and CDRX for all lanes. And later on, it will
833 * be only enabled for the physical data lane corresponding
834 * to the logical data lane 0
835 */
836 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(i), 0);
837 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_PIN_SWAP(i), 0x0);
838 }
839
840 dsi_phy_hw_v4_0_config_lpcdrx(phy, true);
841
842 /* other settings */
843 for (i = 0; i < 5; i++) {
844 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG0(i), 0x0);
845 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG1(i), 0x0);
846 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG2(i), i == 4 ? 0x8a : 0xa);
847 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_TX_DCTRL(i), tx_dctrl[i]);
848 }
849}
850
851static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
852 struct msm_dsi_phy_clk_request *clk_req)
853{
854 int ret;
855 u32 status;
856 u32 const delay_us = 5;
857 u32 const timeout_us = 1000;
858 struct msm_dsi_dphy_timing *timing = &phy->timing;
859 void __iomem *base = phy->base;
860 bool less_than_1500_mhz;
861 u32 vreg_ctrl_0, vreg_ctrl_1, lane_ctrl0;
862 u32 glbl_pemph_ctrl_0;
863 u32 glbl_str_swi_cal_sel_ctrl, glbl_hstx_str_ctrl_0;
864 u32 glbl_rescode_top_ctrl, glbl_rescode_bot_ctrl;
865 u32 data;
866
867 DBG("");
868
869 if (phy->cphy_mode)
870 ret = msm_dsi_cphy_timing_calc_v4(timing, clk_req);
871 else
872 ret = msm_dsi_dphy_timing_calc_v4(timing, clk_req);
873 if (ret) {
874 DRM_DEV_ERROR(&phy->pdev->dev,
875 "%s: PHY timing calculation failed\n", __func__);
876 return -EINVAL;
877 }
878
879 if (dsi_phy_hw_v4_0_is_pll_on(phy))
880 pr_warn("PLL turned on before configuring PHY\n");
881
882 /* Request for REFGEN READY */
883 if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) ||
884 (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
885 dsi_phy_write(phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x1);
886 udelay(500);
887 }
888
889 /* wait for REFGEN READY */
890 ret = readl_poll_timeout_atomic(base + REG_DSI_7nm_PHY_CMN_PHY_STATUS,
891 status, (status & BIT(0)),
892 delay_us, timeout_us);
893 if (ret) {
894 pr_err("Ref gen not ready. Aborting\n");
895 return -EINVAL;
896 }
897
898 /* TODO: CPHY enable path (this is for DPHY only) */
899
900 /* Alter PHY configurations if data rate less than 1.5GHZ*/
901 less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000);
902
903 glbl_str_swi_cal_sel_ctrl = 0x00;
904 if (phy->cphy_mode) {
905 vreg_ctrl_0 = 0x51;
906 vreg_ctrl_1 = 0x55;
907 glbl_hstx_str_ctrl_0 = 0x00;
908 glbl_pemph_ctrl_0 = 0x11;
909 lane_ctrl0 = 0x17;
910 } else {
911 vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
912 vreg_ctrl_1 = 0x5c;
913 glbl_hstx_str_ctrl_0 = 0x88;
914 glbl_pemph_ctrl_0 = 0x00;
915 lane_ctrl0 = 0x1f;
916 }
917
918 if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
919 if (phy->cphy_mode) {
920 vreg_ctrl_0 = 0x45;
921 vreg_ctrl_1 = 0x41;
922 glbl_rescode_top_ctrl = 0x00;
923 glbl_rescode_bot_ctrl = 0x00;
924 } else {
925 vreg_ctrl_0 = 0x44;
926 vreg_ctrl_1 = 0x19;
927 glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x03;
928 glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3c;
929 }
930 } else if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) {
931 if (phy->cphy_mode) {
932 glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01;
933 glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b;
934 } else {
935 glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01;
936 glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39;
937 }
938 } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) {
939 if (phy->cphy_mode) {
940 glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01;
941 glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b;
942 } else {
943 glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x00;
944 glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39;
945 }
946 } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
947 if (phy->cphy_mode) {
948 glbl_hstx_str_ctrl_0 = 0x88;
949 glbl_rescode_top_ctrl = 0x00;
950 glbl_rescode_bot_ctrl = 0x3c;
951 } else {
952 glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00;
953 glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c;
954 }
955 } else {
956 if (phy->cphy_mode) {
957 glbl_str_swi_cal_sel_ctrl = 0x03;
958 glbl_hstx_str_ctrl_0 = 0x66;
959 } else {
960 vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;
961 glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00;
962 glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88;
963 }
964 glbl_rescode_top_ctrl = 0x03;
965 glbl_rescode_bot_ctrl = 0x3c;
966 }
967
968 /* de-assert digital and pll power down */
969 data = BIT(6) | BIT(5);
970 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data);
971
972 /* Assert PLL core reset */
973 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x00);
974
975 /* turn off resync FIFO */
976 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0x00);
977
978 /* program CMN_CTRL_4 for minor_ver 2 chipsets*/
979 if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) ||
980 (dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0) & (0xf0)) == 0x20)
981 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_4, 0x04);
982
983 /* Configure PHY lane swap (TODO: we need to calculate this) */
984 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CFG0, 0x21);
985 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CFG1, 0x84);
986
987 if (phy->cphy_mode)
988 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_CTRL, BIT(6));
989
990 /* Enable LDO */
991 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_0, vreg_ctrl_0);
992 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_1, vreg_ctrl_1);
993
994 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x00);
995 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL,
996 glbl_str_swi_cal_sel_ctrl);
997 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0,
998 glbl_hstx_str_ctrl_0);
999 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0,
1000 glbl_pemph_ctrl_0);
1001 if (phy->cphy_mode)
1002 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1, 0x01);
1003 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL,
1004 glbl_rescode_top_ctrl);
1005 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL,
1006 glbl_rescode_bot_ctrl);
1007 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL, 0x55);
1008
1009 /* Remove power down from all blocks */
1010 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, 0x7f);
1011
1012 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0, lane_ctrl0);
1013
1014 /* Select full-rate mode */
1015 if (!phy->cphy_mode)
1016 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_2, 0x40);
1017
1018 ret = dsi_7nm_set_usecase(phy);
1019 if (ret) {
1020 DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
1021 __func__, ret);
1022 return ret;
1023 }
1024
1025 /* DSI PHY timings */
1026 if (phy->cphy_mode) {
1027 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0, 0x00);
1028 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4, timing->hs_exit);
1029 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5,
1030 timing->shared_timings.clk_pre);
1031 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6, timing->clk_prepare);
1032 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7,
1033 timing->shared_timings.clk_post);
1034 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8, timing->hs_rqst);
1035 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9, 0x02);
1036 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10, 0x04);
1037 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11, 0x00);
1038 } else {
1039 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0, 0x00);
1040 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1, timing->clk_zero);
1041 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2, timing->clk_prepare);
1042 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3, timing->clk_trail);
1043 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4, timing->hs_exit);
1044 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5, timing->hs_zero);
1045 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6, timing->hs_prepare);
1046 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7, timing->hs_trail);
1047 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8, timing->hs_rqst);
1048 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9, 0x02);
1049 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10, 0x04);
1050 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11, 0x00);
1051 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12,
1052 timing->shared_timings.clk_pre);
1053 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13,
1054 timing->shared_timings.clk_post);
1055 }
1056
1057 /* DSI lane settings */
1058 dsi_phy_hw_v4_0_lane_settings(phy);
1059
1060 DBG("DSI%d PHY enabled", phy->id);
1061
1062 return 0;
1063}
1064
1065static bool dsi_7nm_set_continuous_clock(struct msm_dsi_phy *phy, bool enable)
1066{
1067 void __iomem *base = phy->base;
1068 u32 data;
1069
1070 data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL1);
1071 if (enable)
1072 data |= BIT(5) | BIT(6);
1073 else
1074 data &= ~(BIT(5) | BIT(6));
1075 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL1, data);
1076
1077 return enable;
1078}
1079
1080static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
1081{
1082 void __iomem *base = phy->base;
1083 u32 data;
1084
1085 DBG("");
1086
1087 if (dsi_phy_hw_v4_0_is_pll_on(phy))
1088 pr_warn("Turning OFF PHY while PLL is on\n");
1089
1090 dsi_phy_hw_v4_0_config_lpcdrx(phy, false);
1091
1092 /* Turn off REFGEN Vote */
1093 if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) ||
1094 (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
1095 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x0);
1096 wmb();
1097 /* Delay to ensure HW removes vote before PHY shut down */
1098 udelay(2);
1099 }
1100
1101 data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_CTRL_0);
1102
1103 /* disable all lanes */
1104 data &= ~0x1F;
1105 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data);
1106 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0, 0);
1107
1108 /* Turn off all PHY blocks */
1109 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, 0x00);
1110 /* make sure phy is turned off */
1111 wmb();
1112
1113 DBG("DSI%d PHY disabled", phy->id);
1114}
1115
1116static const struct regulator_bulk_data dsi_phy_7nm_36mA_regulators[] = {
1117 { .supply = "vdds", .init_load_uA = 36000 },
1118};
1119
1120static const struct regulator_bulk_data dsi_phy_7nm_37750uA_regulators[] = {
1121 { .supply = "vdds", .init_load_uA = 37550 },
1122};
1123
1124static const struct regulator_bulk_data dsi_phy_7nm_98000uA_regulators[] = {
1125 { .supply = "vdds", .init_load_uA = 98000 },
1126};
1127
1128static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = {
1129 { .supply = "vdds", .init_load_uA = 97800 },
1130};
1131
1132static const struct regulator_bulk_data dsi_phy_7nm_98400uA_regulators[] = {
1133 { .supply = "vdds", .init_load_uA = 98400 },
1134};
1135
1136const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
1137 .has_phy_lane = true,
1138 .regulator_data = dsi_phy_7nm_36mA_regulators,
1139 .num_regulators = ARRAY_SIZE(dsi_phy_7nm_36mA_regulators),
1140 .ops = {
1141 .enable = dsi_7nm_phy_enable,
1142 .disable = dsi_7nm_phy_disable,
1143 .pll_init = dsi_pll_7nm_init,
1144 .save_pll_state = dsi_7nm_pll_save_state,
1145 .restore_pll_state = dsi_7nm_pll_restore_state,
1146 .set_continuous_clock = dsi_7nm_set_continuous_clock,
1147 },
1148 .min_pll_rate = 600000000UL,
1149#ifdef CONFIG_64BIT
1150 .max_pll_rate = 5000000000UL,
1151#else
1152 .max_pll_rate = ULONG_MAX,
1153#endif
1154 .io_start = { 0xae94400, 0xae96400 },
1155 .num_dsi_phy = 2,
1156 .quirks = DSI_PHY_7NM_QUIRK_V4_1,
1157};
1158
1159const struct msm_dsi_phy_cfg dsi_phy_7nm_6375_cfgs = {
1160 .has_phy_lane = true,
1161 .ops = {
1162 .enable = dsi_7nm_phy_enable,
1163 .disable = dsi_7nm_phy_disable,
1164 .pll_init = dsi_pll_7nm_init,
1165 .save_pll_state = dsi_7nm_pll_save_state,
1166 .restore_pll_state = dsi_7nm_pll_restore_state,
1167 },
1168 .min_pll_rate = 600000000UL,
1169#ifdef CONFIG_64BIT
1170 .max_pll_rate = 5000000000ULL,
1171#else
1172 .max_pll_rate = ULONG_MAX,
1173#endif
1174 .io_start = { 0x5e94400 },
1175 .num_dsi_phy = 1,
1176 .quirks = DSI_PHY_7NM_QUIRK_V4_1,
1177};
1178
1179const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
1180 .has_phy_lane = true,
1181 .regulator_data = dsi_phy_7nm_36mA_regulators,
1182 .num_regulators = ARRAY_SIZE(dsi_phy_7nm_36mA_regulators),
1183 .ops = {
1184 .enable = dsi_7nm_phy_enable,
1185 .disable = dsi_7nm_phy_disable,
1186 .pll_init = dsi_pll_7nm_init,
1187 .save_pll_state = dsi_7nm_pll_save_state,
1188 .restore_pll_state = dsi_7nm_pll_restore_state,
1189 .set_continuous_clock = dsi_7nm_set_continuous_clock,
1190 },
1191 .min_pll_rate = 1000000000UL,
1192 .max_pll_rate = 3500000000UL,
1193 .io_start = { 0xae94400, 0xae96400 },
1194 .num_dsi_phy = 2,
1195 .quirks = DSI_PHY_7NM_QUIRK_PRE_V4_1,
1196};
1197
1198const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = {
1199 .has_phy_lane = true,
1200 .regulator_data = dsi_phy_7nm_37750uA_regulators,
1201 .num_regulators = ARRAY_SIZE(dsi_phy_7nm_37750uA_regulators),
1202 .ops = {
1203 .enable = dsi_7nm_phy_enable,
1204 .disable = dsi_7nm_phy_disable,
1205 .pll_init = dsi_pll_7nm_init,
1206 .save_pll_state = dsi_7nm_pll_save_state,
1207 .restore_pll_state = dsi_7nm_pll_restore_state,
1208 },
1209 .min_pll_rate = 600000000UL,
1210#ifdef CONFIG_64BIT
1211 .max_pll_rate = 5000000000ULL,
1212#else
1213 .max_pll_rate = ULONG_MAX,
1214#endif
1215 .io_start = { 0xae94400 },
1216 .num_dsi_phy = 1,
1217 .quirks = DSI_PHY_7NM_QUIRK_V4_1,
1218};
1219
1220const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs = {
1221 .has_phy_lane = true,
1222 .regulator_data = dsi_phy_7nm_37750uA_regulators,
1223 .num_regulators = ARRAY_SIZE(dsi_phy_7nm_37750uA_regulators),
1224 .ops = {
1225 .enable = dsi_7nm_phy_enable,
1226 .disable = dsi_7nm_phy_disable,
1227 .pll_init = dsi_pll_7nm_init,
1228 .save_pll_state = dsi_7nm_pll_save_state,
1229 .restore_pll_state = dsi_7nm_pll_restore_state,
1230 .set_continuous_clock = dsi_7nm_set_continuous_clock,
1231 },
1232 .min_pll_rate = 600000000UL,
1233#ifdef CONFIG_64BIT
1234 .max_pll_rate = 5000000000UL,
1235#else
1236 .max_pll_rate = ULONG_MAX,
1237#endif
1238 .io_start = { 0xae94400, 0xae96400 },
1239 .num_dsi_phy = 2,
1240 .quirks = DSI_PHY_7NM_QUIRK_V4_2,
1241};
1242
1243const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = {
1244 .has_phy_lane = true,
1245 .regulator_data = dsi_phy_7nm_97800uA_regulators,
1246 .num_regulators = ARRAY_SIZE(dsi_phy_7nm_97800uA_regulators),
1247 .ops = {
1248 .enable = dsi_7nm_phy_enable,
1249 .disable = dsi_7nm_phy_disable,
1250 .pll_init = dsi_pll_7nm_init,
1251 .save_pll_state = dsi_7nm_pll_save_state,
1252 .restore_pll_state = dsi_7nm_pll_restore_state,
1253 .set_continuous_clock = dsi_7nm_set_continuous_clock,
1254 },
1255 .min_pll_rate = 600000000UL,
1256#ifdef CONFIG_64BIT
1257 .max_pll_rate = 5000000000UL,
1258#else
1259 .max_pll_rate = ULONG_MAX,
1260#endif
1261 .io_start = { 0xae94400, 0xae96400 },
1262 .num_dsi_phy = 2,
1263 .quirks = DSI_PHY_7NM_QUIRK_V4_3,
1264};
1265
1266const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = {
1267 .has_phy_lane = true,
1268 .regulator_data = dsi_phy_7nm_98400uA_regulators,
1269 .num_regulators = ARRAY_SIZE(dsi_phy_7nm_98400uA_regulators),
1270 .ops = {
1271 .enable = dsi_7nm_phy_enable,
1272 .disable = dsi_7nm_phy_disable,
1273 .pll_init = dsi_pll_7nm_init,
1274 .save_pll_state = dsi_7nm_pll_save_state,
1275 .restore_pll_state = dsi_7nm_pll_restore_state,
1276 .set_continuous_clock = dsi_7nm_set_continuous_clock,
1277 },
1278 .min_pll_rate = 600000000UL,
1279#ifdef CONFIG_64BIT
1280 .max_pll_rate = 5000000000UL,
1281#else
1282 .max_pll_rate = ULONG_MAX,
1283#endif
1284 .io_start = { 0xae95000, 0xae97000 },
1285 .num_dsi_phy = 2,
1286 .quirks = DSI_PHY_7NM_QUIRK_V5_2,
1287};
1288
1289const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs = {
1290 .has_phy_lane = true,
1291 .regulator_data = dsi_phy_7nm_98000uA_regulators,
1292 .num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators),
1293 .ops = {
1294 .enable = dsi_7nm_phy_enable,
1295 .disable = dsi_7nm_phy_disable,
1296 .pll_init = dsi_pll_7nm_init,
1297 .save_pll_state = dsi_7nm_pll_save_state,
1298 .restore_pll_state = dsi_7nm_pll_restore_state,
1299 .set_continuous_clock = dsi_7nm_set_continuous_clock,
1300 },
1301 .min_pll_rate = 600000000UL,
1302#ifdef CONFIG_64BIT
1303 .max_pll_rate = 5000000000UL,
1304#else
1305 .max_pll_rate = ULONG_MAX,
1306#endif
1307 .io_start = { 0xae95000, 0xae97000 },
1308 .num_dsi_phy = 2,
1309 .quirks = DSI_PHY_7NM_QUIRK_V5_2,
1310};
1/*
2 * SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation
4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/iopoll.h>
9
10#include "dsi_phy.h"
11#include "dsi.xml.h"
12#include "dsi_phy_7nm.xml.h"
13
14/*
15 * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram
16 *
17 * dsi0_pll_out_div_clk dsi0_pll_bit_clk
18 * | |
19 * | |
20 * +---------+ | +----------+ | +----+
21 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
22 * +---------+ | +----------+ | +----+
23 * | |
24 * | | dsi0_pll_by_2_bit_clk
25 * | | |
26 * | | +----+ | |\ dsi0_pclk_mux
27 * | |--| /2 |--o--| \ |
28 * | | +----+ | \ | +---------+
29 * | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_out_dsiclk
30 * |------------------------------| / +---------+
31 * | +-----+ | /
32 * -----------| /4? |--o----------|/
33 * +-----+ | |
34 * | |dsiclk_sel
35 * |
36 * dsi0_pll_post_out_div_clk
37 */
38
39#define VCO_REF_CLK_RATE 19200000
40#define FRAC_BITS 18
41
42/* Hardware is V4.1 */
43#define DSI_PHY_7NM_QUIRK_V4_1 BIT(0)
44
45struct dsi_pll_config {
46 bool enable_ssc;
47 bool ssc_center;
48 u32 ssc_freq;
49 u32 ssc_offset;
50 u32 ssc_adj_per;
51
52 /* out */
53 u32 decimal_div_start;
54 u32 frac_div_start;
55 u32 pll_clock_inverters;
56 u32 ssc_stepsize;
57 u32 ssc_div_per;
58};
59
60struct pll_7nm_cached_state {
61 unsigned long vco_rate;
62 u8 bit_clk_div;
63 u8 pix_clk_div;
64 u8 pll_out_div;
65 u8 pll_mux;
66};
67
68struct dsi_pll_7nm {
69 struct clk_hw clk_hw;
70
71 struct msm_dsi_phy *phy;
72
73 u64 vco_current_rate;
74
75 /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */
76 spinlock_t postdiv_lock;
77
78 struct pll_7nm_cached_state cached_state;
79
80 struct dsi_pll_7nm *slave;
81};
82
83#define to_pll_7nm(x) container_of(x, struct dsi_pll_7nm, clk_hw)
84
85/*
86 * Global list of private DSI PLL struct pointers. We need this for bonded DSI
87 * mode, where the master PLL's clk_ops needs access the slave's private data
88 */
89static struct dsi_pll_7nm *pll_7nm_list[DSI_MAX];
90
91static void dsi_pll_setup_config(struct dsi_pll_config *config)
92{
93 config->ssc_freq = 31500;
94 config->ssc_offset = 4800;
95 config->ssc_adj_per = 2;
96
97 /* TODO: ssc enable */
98 config->enable_ssc = false;
99 config->ssc_center = 0;
100}
101
102static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
103{
104 u64 fref = VCO_REF_CLK_RATE;
105 u64 pll_freq;
106 u64 divider;
107 u64 dec, dec_multiple;
108 u32 frac;
109 u64 multiplier;
110
111 pll_freq = pll->vco_current_rate;
112
113 divider = fref * 2;
114
115 multiplier = 1 << FRAC_BITS;
116 dec_multiple = div_u64(pll_freq * multiplier, divider);
117 dec = div_u64_rem(dec_multiple, multiplier, &frac);
118
119 if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1))
120 config->pll_clock_inverters = 0x28;
121 else if (pll_freq <= 1000000000ULL)
122 config->pll_clock_inverters = 0xa0;
123 else if (pll_freq <= 2500000000ULL)
124 config->pll_clock_inverters = 0x20;
125 else if (pll_freq <= 3020000000ULL)
126 config->pll_clock_inverters = 0x00;
127 else
128 config->pll_clock_inverters = 0x40;
129
130 config->decimal_div_start = dec;
131 config->frac_div_start = frac;
132}
133
134#define SSC_CENTER BIT(0)
135#define SSC_EN BIT(1)
136
137static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
138{
139 u32 ssc_per;
140 u32 ssc_mod;
141 u64 ssc_step_size;
142 u64 frac;
143
144 if (!config->enable_ssc) {
145 DBG("SSC not enabled\n");
146 return;
147 }
148
149 ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) / 2 - 1;
150 ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1);
151 ssc_per -= ssc_mod;
152
153 frac = config->frac_div_start;
154 ssc_step_size = config->decimal_div_start;
155 ssc_step_size *= (1 << FRAC_BITS);
156 ssc_step_size += frac;
157 ssc_step_size *= config->ssc_offset;
158 ssc_step_size *= (config->ssc_adj_per + 1);
159 ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1));
160 ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000);
161
162 config->ssc_div_per = ssc_per;
163 config->ssc_stepsize = ssc_step_size;
164
165 pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n",
166 config->decimal_div_start, frac, FRAC_BITS);
167 pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n",
168 ssc_per, (u32)ssc_step_size, config->ssc_adj_per);
169}
170
171static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
172{
173 void __iomem *base = pll->phy->pll_base;
174
175 if (config->enable_ssc) {
176 pr_debug("SSC is enabled\n");
177
178 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
179 config->ssc_stepsize & 0xff);
180 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
181 config->ssc_stepsize >> 8);
182 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1,
183 config->ssc_div_per & 0xff);
184 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
185 config->ssc_div_per >> 8);
186 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1,
187 config->ssc_adj_per & 0xff);
188 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1,
189 config->ssc_adj_per >> 8);
190 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL,
191 SSC_EN | (config->ssc_center ? SSC_CENTER : 0));
192 }
193}
194
195static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
196{
197 void __iomem *base = pll->phy->pll_base;
198 u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00;
199
200 if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
201 if (pll->vco_current_rate >= 3100000000ULL)
202 analog_controls_five_1 = 0x03;
203
204 if (pll->vco_current_rate < 1520000000ULL)
205 vco_config_1 = 0x08;
206 else if (pll->vco_current_rate < 2990000000ULL)
207 vco_config_1 = 0x01;
208 }
209
210 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
211 analog_controls_five_1);
212 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1);
213 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE, 0x01);
214 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03);
215 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00);
216 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DSM_DIVIDER, 0x00);
217 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e);
218 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40);
219 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE, 0xba);
220 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c);
221 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_OUTDIV, 0x00);
222 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE, 0x00);
223 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08);
224 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x0a);
225 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1, 0xc0);
226 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x84);
227 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x82);
228 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x4c);
229 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80);
230 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x29);
231 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f);
232 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a);
233 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT,
234 pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22);
235
236 if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
237 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
238 if (pll->slave)
239 dsi_phy_write(pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
240 }
241}
242
243static void dsi_pll_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
244{
245 void __iomem *base = pll->phy->pll_base;
246
247 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
248 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1,
249 config->decimal_div_start);
250 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1,
251 config->frac_div_start & 0xff);
252 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1,
253 (config->frac_div_start & 0xff00) >> 8);
254 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1,
255 (config->frac_div_start & 0x30000) >> 16);
256 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40);
257 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
258 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1,
259 pll->phy->cphy_mode ? 0x00 : 0x10);
260 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS,
261 config->pll_clock_inverters);
262}
263
264static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
265 unsigned long parent_rate)
266{
267 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
268 struct dsi_pll_config config;
269
270 DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->phy->id, rate,
271 parent_rate);
272
273 pll_7nm->vco_current_rate = rate;
274
275 dsi_pll_setup_config(&config);
276
277 dsi_pll_calc_dec_frac(pll_7nm, &config);
278
279 dsi_pll_calc_ssc(pll_7nm, &config);
280
281 dsi_pll_commit(pll_7nm, &config);
282
283 dsi_pll_config_hzindep_reg(pll_7nm);
284
285 dsi_pll_ssc_commit(pll_7nm, &config);
286
287 /* flush, ensure all register writes are done*/
288 wmb();
289
290 return 0;
291}
292
293static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll)
294{
295 int rc;
296 u32 status = 0;
297 u32 const delay_us = 100;
298 u32 const timeout_us = 5000;
299
300 rc = readl_poll_timeout_atomic(pll->phy->pll_base +
301 REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE,
302 status,
303 ((status & BIT(0)) > 0),
304 delay_us,
305 timeout_us);
306 if (rc)
307 pr_err("DSI PLL(%d) lock failed, status=0x%08x\n",
308 pll->phy->id, status);
309
310 return rc;
311}
312
313static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
314{
315 u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
316
317 dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0);
318 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data & ~BIT(5));
319 ndelay(250);
320}
321
322static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll)
323{
324 u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
325
326 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data | BIT(5));
327 dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
328 ndelay(250);
329}
330
331static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll)
332{
333 u32 data;
334
335 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
336 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data & ~BIT(5));
337}
338
339static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll)
340{
341 u32 data;
342
343 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04);
344
345 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
346 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1,
347 data | BIT(5) | BIT(4));
348}
349
350static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll)
351{
352 /*
353 * Reset the PHY digital domain. This would be needed when
354 * coming out of a CX or analog rail power collapse while
355 * ensuring that the pads maintain LP00 or LP11 state
356 */
357 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0));
358 wmb(); /* Ensure that the reset is deasserted */
359 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0);
360 wmb(); /* Ensure that the reset is deasserted */
361}
362
363static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw)
364{
365 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
366 int rc;
367
368 dsi_pll_enable_pll_bias(pll_7nm);
369 if (pll_7nm->slave)
370 dsi_pll_enable_pll_bias(pll_7nm->slave);
371
372 /* Start PLL */
373 dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x01);
374
375 /*
376 * ensure all PLL configurations are written prior to checking
377 * for PLL lock.
378 */
379 wmb();
380
381 /* Check for PLL lock */
382 rc = dsi_pll_7nm_lock_status(pll_7nm);
383 if (rc) {
384 pr_err("PLL(%d) lock failed\n", pll_7nm->phy->id);
385 goto error;
386 }
387
388 pll_7nm->phy->pll_on = true;
389
390 /*
391 * assert power on reset for PHY digital in case the PLL is
392 * enabled after CX of analog domain power collapse. This needs
393 * to be done before enabling the global clk.
394 */
395 dsi_pll_phy_dig_reset(pll_7nm);
396 if (pll_7nm->slave)
397 dsi_pll_phy_dig_reset(pll_7nm->slave);
398
399 dsi_pll_enable_global_clk(pll_7nm);
400 if (pll_7nm->slave)
401 dsi_pll_enable_global_clk(pll_7nm->slave);
402
403error:
404 return rc;
405}
406
407static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll)
408{
409 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0);
410 dsi_pll_disable_pll_bias(pll);
411}
412
413static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw)
414{
415 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
416
417 /*
418 * To avoid any stray glitches while abruptly powering down the PLL
419 * make sure to gate the clock using the clock enable bit before
420 * powering down the PLL
421 */
422 dsi_pll_disable_global_clk(pll_7nm);
423 dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0);
424 dsi_pll_disable_sub(pll_7nm);
425 if (pll_7nm->slave) {
426 dsi_pll_disable_global_clk(pll_7nm->slave);
427 dsi_pll_disable_sub(pll_7nm->slave);
428 }
429 /* flush, ensure all register writes are done */
430 wmb();
431 pll_7nm->phy->pll_on = false;
432}
433
434static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
435 unsigned long parent_rate)
436{
437 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
438 void __iomem *base = pll_7nm->phy->pll_base;
439 u64 ref_clk = VCO_REF_CLK_RATE;
440 u64 vco_rate = 0x0;
441 u64 multiplier;
442 u32 frac;
443 u32 dec;
444 u64 pll_freq, tmp64;
445
446 dec = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1);
447 dec &= 0xff;
448
449 frac = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1);
450 frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1) &
451 0xff) << 8);
452 frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1) &
453 0x3) << 16);
454
455 /*
456 * TODO:
457 * 1. Assumes prescaler is disabled
458 */
459 multiplier = 1 << FRAC_BITS;
460 pll_freq = dec * (ref_clk * 2);
461 tmp64 = (ref_clk * 2 * frac);
462 pll_freq += div_u64(tmp64, multiplier);
463
464 vco_rate = pll_freq;
465 pll_7nm->vco_current_rate = vco_rate;
466
467 DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x",
468 pll_7nm->phy->id, (unsigned long)vco_rate, dec, frac);
469
470 return (unsigned long)vco_rate;
471}
472
473static long dsi_pll_7nm_clk_round_rate(struct clk_hw *hw,
474 unsigned long rate, unsigned long *parent_rate)
475{
476 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
477
478 if (rate < pll_7nm->phy->cfg->min_pll_rate)
479 return pll_7nm->phy->cfg->min_pll_rate;
480 else if (rate > pll_7nm->phy->cfg->max_pll_rate)
481 return pll_7nm->phy->cfg->max_pll_rate;
482 else
483 return rate;
484}
485
486static const struct clk_ops clk_ops_dsi_pll_7nm_vco = {
487 .round_rate = dsi_pll_7nm_clk_round_rate,
488 .set_rate = dsi_pll_7nm_vco_set_rate,
489 .recalc_rate = dsi_pll_7nm_vco_recalc_rate,
490 .prepare = dsi_pll_7nm_vco_prepare,
491 .unprepare = dsi_pll_7nm_vco_unprepare,
492};
493
494/*
495 * PLL Callbacks
496 */
497
498static void dsi_7nm_pll_save_state(struct msm_dsi_phy *phy)
499{
500 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
501 struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
502 void __iomem *phy_base = pll_7nm->phy->base;
503 u32 cmn_clk_cfg0, cmn_clk_cfg1;
504
505 cached->pll_out_div = dsi_phy_read(pll_7nm->phy->pll_base +
506 REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
507 cached->pll_out_div &= 0x3;
508
509 cmn_clk_cfg0 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);
510 cached->bit_clk_div = cmn_clk_cfg0 & 0xf;
511 cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4;
512
513 cmn_clk_cfg1 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
514 cached->pll_mux = cmn_clk_cfg1 & 0x3;
515
516 DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x",
517 pll_7nm->phy->id, cached->pll_out_div, cached->bit_clk_div,
518 cached->pix_clk_div, cached->pll_mux);
519}
520
521static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy)
522{
523 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
524 struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
525 void __iomem *phy_base = pll_7nm->phy->base;
526 u32 val;
527 int ret;
528
529 val = dsi_phy_read(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
530 val &= ~0x3;
531 val |= cached->pll_out_div;
532 dsi_phy_write(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, val);
533
534 dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0,
535 cached->bit_clk_div | (cached->pix_clk_div << 4));
536
537 val = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
538 val &= ~0x3;
539 val |= cached->pll_mux;
540 dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val);
541
542 ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw,
543 pll_7nm->vco_current_rate,
544 VCO_REF_CLK_RATE);
545 if (ret) {
546 DRM_DEV_ERROR(&pll_7nm->phy->pdev->dev,
547 "restore vco rate failed. ret=%d\n", ret);
548 return ret;
549 }
550
551 DBG("DSI PLL%d", pll_7nm->phy->id);
552
553 return 0;
554}
555
556static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
557{
558 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
559 void __iomem *base = phy->base;
560 u32 data = 0x0; /* internal PLL */
561
562 DBG("DSI PLL%d", pll_7nm->phy->id);
563
564 switch (phy->usecase) {
565 case MSM_DSI_PHY_STANDALONE:
566 break;
567 case MSM_DSI_PHY_MASTER:
568 pll_7nm->slave = pll_7nm_list[(pll_7nm->phy->id + 1) % DSI_MAX];
569 break;
570 case MSM_DSI_PHY_SLAVE:
571 data = 0x1; /* external PLL */
572 break;
573 default:
574 return -EINVAL;
575 }
576
577 /* set PLL src */
578 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2));
579
580 return 0;
581}
582
583/*
584 * The post dividers and mux clocks are created using the standard divider and
585 * mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux
586 * state to follow the master PLL's divider/mux state. Therefore, we don't
587 * require special clock ops that also configure the slave PLL registers
588 */
589static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provided_clocks)
590{
591 char clk_name[32];
592 struct clk_init_data vco_init = {
593 .parent_data = &(const struct clk_parent_data) {
594 .fw_name = "ref",
595 },
596 .num_parents = 1,
597 .name = clk_name,
598 .flags = CLK_IGNORE_UNUSED,
599 .ops = &clk_ops_dsi_pll_7nm_vco,
600 };
601 struct device *dev = &pll_7nm->phy->pdev->dev;
602 struct clk_hw *hw, *pll_out_div, *pll_bit, *pll_by_2_bit;
603 struct clk_hw *pll_post_out_div, *phy_pll_out_dsi_parent;
604 int ret;
605
606 DBG("DSI%d", pll_7nm->phy->id);
607
608 snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_7nm->phy->id);
609 pll_7nm->clk_hw.init = &vco_init;
610
611 ret = devm_clk_hw_register(dev, &pll_7nm->clk_hw);
612 if (ret)
613 return ret;
614
615 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
616
617 pll_out_div = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
618 &pll_7nm->clk_hw, CLK_SET_RATE_PARENT,
619 pll_7nm->phy->pll_base +
620 REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE,
621 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
622 if (IS_ERR(pll_out_div)) {
623 ret = PTR_ERR(pll_out_div);
624 goto fail;
625 }
626
627 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_bit_clk", pll_7nm->phy->id);
628
629 /* BIT CLK: DIV_CTRL_3_0 */
630 pll_bit = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
631 pll_out_div, CLK_SET_RATE_PARENT,
632 pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0,
633 0, 4, CLK_DIVIDER_ONE_BASED, &pll_7nm->postdiv_lock);
634 if (IS_ERR(pll_bit)) {
635 ret = PTR_ERR(pll_bit);
636 goto fail;
637 }
638
639 snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_byteclk", pll_7nm->phy->id);
640
641 /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
642 hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, clk_name,
643 pll_bit, CLK_SET_RATE_PARENT, 1,
644 pll_7nm->phy->cphy_mode ? 7 : 8);
645 if (IS_ERR(hw)) {
646 ret = PTR_ERR(hw);
647 goto fail;
648 }
649
650 provided_clocks[DSI_BYTE_PLL_CLK] = hw;
651
652 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id);
653
654 pll_by_2_bit = devm_clk_hw_register_fixed_factor_parent_hw(dev,
655 clk_name, pll_bit, 0, 1, 2);
656 if (IS_ERR(pll_by_2_bit)) {
657 ret = PTR_ERR(pll_by_2_bit);
658 goto fail;
659 }
660
661 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id);
662
663 if (pll_7nm->phy->cphy_mode)
664 pll_post_out_div = devm_clk_hw_register_fixed_factor_parent_hw(
665 dev, clk_name, pll_out_div, 0, 2, 7);
666 else
667 pll_post_out_div = devm_clk_hw_register_fixed_factor_parent_hw(
668 dev, clk_name, pll_out_div, 0, 1, 4);
669 if (IS_ERR(pll_post_out_div)) {
670 ret = PTR_ERR(pll_post_out_div);
671 goto fail;
672 }
673
674 /* in CPHY mode, pclk_mux will always have post_out_div as parent
675 * don't register a pclk_mux clock and just use post_out_div instead
676 */
677 if (pll_7nm->phy->cphy_mode) {
678 u32 data;
679
680 data = dsi_phy_read(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
681 dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data | 3);
682
683 phy_pll_out_dsi_parent = pll_post_out_div;
684 } else {
685 snprintf(clk_name, sizeof(clk_name), "dsi%d_pclk_mux", pll_7nm->phy->id);
686
687 hw = devm_clk_hw_register_mux_parent_hws(dev, clk_name,
688 ((const struct clk_hw *[]){
689 pll_bit,
690 pll_by_2_bit,
691 }), 2, 0, pll_7nm->phy->base +
692 REG_DSI_7nm_PHY_CMN_CLK_CFG1,
693 0, 1, 0, NULL);
694 if (IS_ERR(hw)) {
695 ret = PTR_ERR(hw);
696 goto fail;
697 }
698
699 phy_pll_out_dsi_parent = hw;
700 }
701
702 snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_dsiclk", pll_7nm->phy->id);
703
704 /* PIX CLK DIV : DIV_CTRL_7_4*/
705 hw = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
706 phy_pll_out_dsi_parent, 0,
707 pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0,
708 4, 4, CLK_DIVIDER_ONE_BASED, &pll_7nm->postdiv_lock);
709 if (IS_ERR(hw)) {
710 ret = PTR_ERR(hw);
711 goto fail;
712 }
713
714 provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
715
716 return 0;
717
718fail:
719
720 return ret;
721}
722
723static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
724{
725 struct platform_device *pdev = phy->pdev;
726 struct dsi_pll_7nm *pll_7nm;
727 int ret;
728
729 pll_7nm = devm_kzalloc(&pdev->dev, sizeof(*pll_7nm), GFP_KERNEL);
730 if (!pll_7nm)
731 return -ENOMEM;
732
733 DBG("DSI PLL%d", phy->id);
734
735 pll_7nm_list[phy->id] = pll_7nm;
736
737 spin_lock_init(&pll_7nm->postdiv_lock);
738
739 pll_7nm->phy = phy;
740
741 ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws);
742 if (ret) {
743 DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
744 return ret;
745 }
746
747 phy->vco_hw = &pll_7nm->clk_hw;
748
749 /* TODO: Remove this when we have proper display handover support */
750 msm_dsi_phy_pll_save_state(phy);
751
752 return 0;
753}
754
755static int dsi_phy_hw_v4_0_is_pll_on(struct msm_dsi_phy *phy)
756{
757 void __iomem *base = phy->base;
758 u32 data = 0;
759
760 data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL);
761 mb(); /* make sure read happened */
762
763 return (data & BIT(0));
764}
765
766static void dsi_phy_hw_v4_0_config_lpcdrx(struct msm_dsi_phy *phy, bool enable)
767{
768 void __iomem *lane_base = phy->lane_base;
769 int phy_lane_0 = 0; /* TODO: Support all lane swap configs */
770
771 /*
772 * LPRX and CDRX need to enabled only for physical data lane
773 * corresponding to the logical data lane 0
774 */
775 if (enable)
776 dsi_phy_write(lane_base +
777 REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0x3);
778 else
779 dsi_phy_write(lane_base +
780 REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0);
781}
782
783static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy)
784{
785 int i;
786 const u8 tx_dctrl_0[] = { 0x00, 0x00, 0x00, 0x04, 0x01 };
787 const u8 tx_dctrl_1[] = { 0x40, 0x40, 0x40, 0x46, 0x41 };
788 const u8 *tx_dctrl = tx_dctrl_0;
789 void __iomem *lane_base = phy->lane_base;
790
791 if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)
792 tx_dctrl = tx_dctrl_1;
793
794 /* Strength ctrl settings */
795 for (i = 0; i < 5; i++) {
796 /*
797 * Disable LPRX and CDRX for all lanes. And later on, it will
798 * be only enabled for the physical data lane corresponding
799 * to the logical data lane 0
800 */
801 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(i), 0);
802 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_PIN_SWAP(i), 0x0);
803 }
804
805 dsi_phy_hw_v4_0_config_lpcdrx(phy, true);
806
807 /* other settings */
808 for (i = 0; i < 5; i++) {
809 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG0(i), 0x0);
810 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG1(i), 0x0);
811 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG2(i), i == 4 ? 0x8a : 0xa);
812 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_TX_DCTRL(i), tx_dctrl[i]);
813 }
814}
815
816static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
817 struct msm_dsi_phy_clk_request *clk_req)
818{
819 int ret;
820 u32 status;
821 u32 const delay_us = 5;
822 u32 const timeout_us = 1000;
823 struct msm_dsi_dphy_timing *timing = &phy->timing;
824 void __iomem *base = phy->base;
825 bool less_than_1500_mhz;
826 u32 vreg_ctrl_0, vreg_ctrl_1, lane_ctrl0;
827 u32 glbl_pemph_ctrl_0;
828 u32 glbl_str_swi_cal_sel_ctrl, glbl_hstx_str_ctrl_0;
829 u32 glbl_rescode_top_ctrl, glbl_rescode_bot_ctrl;
830 u32 data;
831
832 DBG("");
833
834 if (phy->cphy_mode)
835 ret = msm_dsi_cphy_timing_calc_v4(timing, clk_req);
836 else
837 ret = msm_dsi_dphy_timing_calc_v4(timing, clk_req);
838 if (ret) {
839 DRM_DEV_ERROR(&phy->pdev->dev,
840 "%s: PHY timing calculation failed\n", __func__);
841 return -EINVAL;
842 }
843
844 if (dsi_phy_hw_v4_0_is_pll_on(phy))
845 pr_warn("PLL turned on before configuring PHY\n");
846
847 /* wait for REFGEN READY */
848 ret = readl_poll_timeout_atomic(base + REG_DSI_7nm_PHY_CMN_PHY_STATUS,
849 status, (status & BIT(0)),
850 delay_us, timeout_us);
851 if (ret) {
852 pr_err("Ref gen not ready. Aborting\n");
853 return -EINVAL;
854 }
855
856 /* TODO: CPHY enable path (this is for DPHY only) */
857
858 /* Alter PHY configurations if data rate less than 1.5GHZ*/
859 less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000);
860
861 if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
862 vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
863 if (phy->cphy_mode) {
864 glbl_rescode_top_ctrl = 0x00;
865 glbl_rescode_bot_ctrl = 0x3c;
866 } else {
867 glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00;
868 glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c;
869 }
870 glbl_str_swi_cal_sel_ctrl = 0x00;
871 glbl_hstx_str_ctrl_0 = 0x88;
872 } else {
873 vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;
874 if (phy->cphy_mode) {
875 glbl_str_swi_cal_sel_ctrl = 0x03;
876 glbl_hstx_str_ctrl_0 = 0x66;
877 } else {
878 glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00;
879 glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88;
880 }
881 glbl_rescode_top_ctrl = 0x03;
882 glbl_rescode_bot_ctrl = 0x3c;
883 }
884
885 if (phy->cphy_mode) {
886 vreg_ctrl_0 = 0x51;
887 vreg_ctrl_1 = 0x55;
888 glbl_pemph_ctrl_0 = 0x11;
889 lane_ctrl0 = 0x17;
890 } else {
891 vreg_ctrl_1 = 0x5c;
892 glbl_pemph_ctrl_0 = 0x00;
893 lane_ctrl0 = 0x1f;
894 }
895
896 /* de-assert digital and pll power down */
897 data = BIT(6) | BIT(5);
898 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data);
899
900 /* Assert PLL core reset */
901 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x00);
902
903 /* turn off resync FIFO */
904 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0x00);
905
906 /* program CMN_CTRL_4 for minor_ver 2 chipsets*/
907 data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0);
908 data = data & (0xf0);
909 if (data == 0x20)
910 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_4, 0x04);
911
912 /* Configure PHY lane swap (TODO: we need to calculate this) */
913 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CFG0, 0x21);
914 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CFG1, 0x84);
915
916 if (phy->cphy_mode)
917 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_CTRL, BIT(6));
918
919 /* Enable LDO */
920 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_0, vreg_ctrl_0);
921 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_1, vreg_ctrl_1);
922
923 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x00);
924 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL,
925 glbl_str_swi_cal_sel_ctrl);
926 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0,
927 glbl_hstx_str_ctrl_0);
928 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0,
929 glbl_pemph_ctrl_0);
930 if (phy->cphy_mode)
931 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1, 0x01);
932 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL,
933 glbl_rescode_top_ctrl);
934 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL,
935 glbl_rescode_bot_ctrl);
936 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL, 0x55);
937
938 /* Remove power down from all blocks */
939 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, 0x7f);
940
941 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0, lane_ctrl0);
942
943 /* Select full-rate mode */
944 if (!phy->cphy_mode)
945 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_2, 0x40);
946
947 ret = dsi_7nm_set_usecase(phy);
948 if (ret) {
949 DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
950 __func__, ret);
951 return ret;
952 }
953
954 /* DSI PHY timings */
955 if (phy->cphy_mode) {
956 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0, 0x00);
957 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4, timing->hs_exit);
958 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5,
959 timing->shared_timings.clk_pre);
960 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6, timing->clk_prepare);
961 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7,
962 timing->shared_timings.clk_post);
963 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8, timing->hs_rqst);
964 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9, 0x02);
965 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10, 0x04);
966 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11, 0x00);
967 } else {
968 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0, 0x00);
969 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1, timing->clk_zero);
970 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2, timing->clk_prepare);
971 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3, timing->clk_trail);
972 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4, timing->hs_exit);
973 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5, timing->hs_zero);
974 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6, timing->hs_prepare);
975 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7, timing->hs_trail);
976 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8, timing->hs_rqst);
977 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9, 0x02);
978 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10, 0x04);
979 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11, 0x00);
980 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12,
981 timing->shared_timings.clk_pre);
982 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13,
983 timing->shared_timings.clk_post);
984 }
985
986 /* DSI lane settings */
987 dsi_phy_hw_v4_0_lane_settings(phy);
988
989 DBG("DSI%d PHY enabled", phy->id);
990
991 return 0;
992}
993
994static bool dsi_7nm_set_continuous_clock(struct msm_dsi_phy *phy, bool enable)
995{
996 void __iomem *base = phy->base;
997 u32 data;
998
999 data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL1);
1000 if (enable)
1001 data |= BIT(5) | BIT(6);
1002 else
1003 data &= ~(BIT(5) | BIT(6));
1004 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL1, data);
1005
1006 return enable;
1007}
1008
1009static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
1010{
1011 void __iomem *base = phy->base;
1012 u32 data;
1013
1014 DBG("");
1015
1016 if (dsi_phy_hw_v4_0_is_pll_on(phy))
1017 pr_warn("Turning OFF PHY while PLL is on\n");
1018
1019 dsi_phy_hw_v4_0_config_lpcdrx(phy, false);
1020 data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_CTRL_0);
1021
1022 /* disable all lanes */
1023 data &= ~0x1F;
1024 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data);
1025 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0, 0);
1026
1027 /* Turn off all PHY blocks */
1028 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, 0x00);
1029 /* make sure phy is turned off */
1030 wmb();
1031
1032 DBG("DSI%d PHY disabled", phy->id);
1033}
1034
1035static const struct regulator_bulk_data dsi_phy_7nm_36mA_regulators[] = {
1036 { .supply = "vdds", .init_load_uA = 36000 },
1037};
1038
1039static const struct regulator_bulk_data dsi_phy_7nm_37750uA_regulators[] = {
1040 { .supply = "vdds", .init_load_uA = 37550 },
1041};
1042
1043const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
1044 .has_phy_lane = true,
1045 .regulator_data = dsi_phy_7nm_36mA_regulators,
1046 .num_regulators = ARRAY_SIZE(dsi_phy_7nm_36mA_regulators),
1047 .ops = {
1048 .enable = dsi_7nm_phy_enable,
1049 .disable = dsi_7nm_phy_disable,
1050 .pll_init = dsi_pll_7nm_init,
1051 .save_pll_state = dsi_7nm_pll_save_state,
1052 .restore_pll_state = dsi_7nm_pll_restore_state,
1053 .set_continuous_clock = dsi_7nm_set_continuous_clock,
1054 },
1055 .min_pll_rate = 600000000UL,
1056#ifdef CONFIG_64BIT
1057 .max_pll_rate = 5000000000UL,
1058#else
1059 .max_pll_rate = ULONG_MAX,
1060#endif
1061 .io_start = { 0xae94400, 0xae96400 },
1062 .num_dsi_phy = 2,
1063 .quirks = DSI_PHY_7NM_QUIRK_V4_1,
1064};
1065
1066const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
1067 .has_phy_lane = true,
1068 .regulator_data = dsi_phy_7nm_36mA_regulators,
1069 .num_regulators = ARRAY_SIZE(dsi_phy_7nm_36mA_regulators),
1070 .ops = {
1071 .enable = dsi_7nm_phy_enable,
1072 .disable = dsi_7nm_phy_disable,
1073 .pll_init = dsi_pll_7nm_init,
1074 .save_pll_state = dsi_7nm_pll_save_state,
1075 .restore_pll_state = dsi_7nm_pll_restore_state,
1076 .set_continuous_clock = dsi_7nm_set_continuous_clock,
1077 },
1078 .min_pll_rate = 1000000000UL,
1079 .max_pll_rate = 3500000000UL,
1080 .io_start = { 0xae94400, 0xae96400 },
1081 .num_dsi_phy = 2,
1082};
1083
1084const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = {
1085 .has_phy_lane = true,
1086 .regulator_data = dsi_phy_7nm_37750uA_regulators,
1087 .num_regulators = ARRAY_SIZE(dsi_phy_7nm_37750uA_regulators),
1088 .ops = {
1089 .enable = dsi_7nm_phy_enable,
1090 .disable = dsi_7nm_phy_disable,
1091 .pll_init = dsi_pll_7nm_init,
1092 .save_pll_state = dsi_7nm_pll_save_state,
1093 .restore_pll_state = dsi_7nm_pll_restore_state,
1094 },
1095 .min_pll_rate = 600000000UL,
1096#ifdef CONFIG_64BIT
1097 .max_pll_rate = 5000000000ULL,
1098#else
1099 .max_pll_rate = ULONG_MAX,
1100#endif
1101 .io_start = { 0xae94400 },
1102 .num_dsi_phy = 1,
1103 .quirks = DSI_PHY_7NM_QUIRK_V4_1,
1104};