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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2020 Intel Corporation
4 */
5#include <linux/kernel.h>
6
7#include <drm/drm_atomic_helper.h>
8#include <drm/drm_atomic_uapi.h>
9#include <drm/drm_blend.h>
10#include <drm/drm_damage_helper.h>
11#include <drm/drm_fourcc.h>
12
13#include "i915_reg.h"
14#include "intel_atomic.h"
15#include "intel_atomic_plane.h"
16#include "intel_cursor.h"
17#include "intel_de.h"
18#include "intel_display.h"
19#include "intel_display_types.h"
20#include "intel_fb.h"
21#include "intel_fb_pin.h"
22#include "intel_frontbuffer.h"
23#include "intel_psr.h"
24#include "intel_psr_regs.h"
25#include "skl_watermark.h"
26
27#include "gem/i915_gem_object.h"
28
29/* Cursor formats */
30static const u32 intel_cursor_formats[] = {
31 DRM_FORMAT_ARGB8888,
32};
33
34static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
35{
36 struct drm_i915_private *dev_priv =
37 to_i915(plane_state->uapi.plane->dev);
38 const struct drm_framebuffer *fb = plane_state->hw.fb;
39 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
40 u32 base;
41
42 if (DISPLAY_INFO(dev_priv)->cursor_needs_physical)
43 base = i915_gem_object_get_dma_address(obj, 0);
44 else
45 base = intel_plane_ggtt_offset(plane_state);
46
47 return base + plane_state->view.color_plane[0].offset;
48}
49
50static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
51{
52 int x = plane_state->uapi.dst.x1;
53 int y = plane_state->uapi.dst.y1;
54 u32 pos = 0;
55
56 if (x < 0) {
57 pos |= CURSOR_POS_X_SIGN;
58 x = -x;
59 }
60 pos |= CURSOR_POS_X(x);
61
62 if (y < 0) {
63 pos |= CURSOR_POS_Y_SIGN;
64 y = -y;
65 }
66 pos |= CURSOR_POS_Y(y);
67
68 return pos;
69}
70
71static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
72{
73 const struct drm_mode_config *config =
74 &plane_state->uapi.plane->dev->mode_config;
75 int width = drm_rect_width(&plane_state->uapi.dst);
76 int height = drm_rect_height(&plane_state->uapi.dst);
77
78 return width > 0 && width <= config->cursor_width &&
79 height > 0 && height <= config->cursor_height;
80}
81
82static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
83{
84 struct drm_i915_private *dev_priv =
85 to_i915(plane_state->uapi.plane->dev);
86 unsigned int rotation = plane_state->hw.rotation;
87 int src_x, src_y;
88 u32 offset;
89 int ret;
90
91 ret = intel_plane_compute_gtt(plane_state);
92 if (ret)
93 return ret;
94
95 if (!plane_state->uapi.visible)
96 return 0;
97
98 src_x = plane_state->uapi.src.x1 >> 16;
99 src_y = plane_state->uapi.src.y1 >> 16;
100
101 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
102 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
103 plane_state, 0);
104
105 if (src_x != 0 || src_y != 0) {
106 drm_dbg_kms(&dev_priv->drm,
107 "Arbitrary cursor panning not supported\n");
108 return -EINVAL;
109 }
110
111 /*
112 * Put the final coordinates back so that the src
113 * coordinate checks will see the right values.
114 */
115 drm_rect_translate_to(&plane_state->uapi.src,
116 src_x << 16, src_y << 16);
117
118 /* ILK+ do this automagically in hardware */
119 if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
120 const struct drm_framebuffer *fb = plane_state->hw.fb;
121 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
122 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
123
124 offset += (src_h * src_w - 1) * fb->format->cpp[0];
125 }
126
127 plane_state->view.color_plane[0].offset = offset;
128 plane_state->view.color_plane[0].x = src_x;
129 plane_state->view.color_plane[0].y = src_y;
130
131 return 0;
132}
133
134static int intel_check_cursor(struct intel_crtc_state *crtc_state,
135 struct intel_plane_state *plane_state)
136{
137 const struct drm_framebuffer *fb = plane_state->hw.fb;
138 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
139 const struct drm_rect src = plane_state->uapi.src;
140 const struct drm_rect dst = plane_state->uapi.dst;
141 int ret;
142
143 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
144 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n");
145 return -EINVAL;
146 }
147
148 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
149 DRM_PLANE_NO_SCALING,
150 DRM_PLANE_NO_SCALING,
151 true);
152 if (ret)
153 return ret;
154
155 /* Use the unclipped src/dst rectangles, which we program to hw */
156 plane_state->uapi.src = src;
157 plane_state->uapi.dst = dst;
158
159 /* final plane coordinates will be relative to the plane's pipe */
160 drm_rect_translate(&plane_state->uapi.dst,
161 -crtc_state->pipe_src.x1,
162 -crtc_state->pipe_src.y1);
163
164 ret = intel_cursor_check_surface(plane_state);
165 if (ret)
166 return ret;
167
168 if (!plane_state->uapi.visible)
169 return 0;
170
171 ret = intel_plane_check_src_coordinates(plane_state);
172 if (ret)
173 return ret;
174
175 return 0;
176}
177
178static unsigned int
179i845_cursor_max_stride(struct intel_plane *plane,
180 u32 pixel_format, u64 modifier,
181 unsigned int rotation)
182{
183 return 2048;
184}
185
186static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
187{
188 u32 cntl = 0;
189
190 if (crtc_state->gamma_enable)
191 cntl |= CURSOR_PIPE_GAMMA_ENABLE;
192
193 return cntl;
194}
195
196static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
197 const struct intel_plane_state *plane_state)
198{
199 return CURSOR_ENABLE |
200 CURSOR_FORMAT_ARGB |
201 CURSOR_STRIDE(plane_state->view.color_plane[0].mapping_stride);
202}
203
204static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
205{
206 int width = drm_rect_width(&plane_state->uapi.dst);
207
208 /*
209 * 845g/865g are only limited by the width of their cursors,
210 * the height is arbitrary up to the precision of the register.
211 */
212 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
213}
214
215static int i845_check_cursor(struct intel_crtc_state *crtc_state,
216 struct intel_plane_state *plane_state)
217{
218 const struct drm_framebuffer *fb = plane_state->hw.fb;
219 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
220 int ret;
221
222 ret = intel_check_cursor(crtc_state, plane_state);
223 if (ret)
224 return ret;
225
226 /* if we want to turn off the cursor ignore width and height */
227 if (!fb)
228 return 0;
229
230 /* Check for which cursor types we support */
231 if (!i845_cursor_size_ok(plane_state)) {
232 drm_dbg_kms(&i915->drm,
233 "Cursor dimension %dx%d not supported\n",
234 drm_rect_width(&plane_state->uapi.dst),
235 drm_rect_height(&plane_state->uapi.dst));
236 return -EINVAL;
237 }
238
239 drm_WARN_ON(&i915->drm, plane_state->uapi.visible &&
240 plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]);
241
242 switch (fb->pitches[0]) {
243 case 256:
244 case 512:
245 case 1024:
246 case 2048:
247 break;
248 default:
249 drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n",
250 fb->pitches[0]);
251 return -EINVAL;
252 }
253
254 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
255
256 return 0;
257}
258
259/* TODO: split into noarm+arm pair */
260static void i845_cursor_update_arm(struct intel_plane *plane,
261 const struct intel_crtc_state *crtc_state,
262 const struct intel_plane_state *plane_state)
263{
264 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
265 u32 cntl = 0, base = 0, pos = 0, size = 0;
266
267 if (plane_state && plane_state->uapi.visible) {
268 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
269 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
270
271 cntl = plane_state->ctl |
272 i845_cursor_ctl_crtc(crtc_state);
273
274 size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width);
275
276 base = intel_cursor_base(plane_state);
277 pos = intel_cursor_position(plane_state);
278 }
279
280 /* On these chipsets we can only modify the base/size/stride
281 * whilst the cursor is disabled.
282 */
283 if (plane->cursor.base != base ||
284 plane->cursor.size != size ||
285 plane->cursor.cntl != cntl) {
286 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
287 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
288 intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size);
289 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
290 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
291
292 plane->cursor.base = base;
293 plane->cursor.size = size;
294 plane->cursor.cntl = cntl;
295 } else {
296 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
297 }
298}
299
300static void i845_cursor_disable_arm(struct intel_plane *plane,
301 const struct intel_crtc_state *crtc_state)
302{
303 i845_cursor_update_arm(plane, crtc_state, NULL);
304}
305
306static bool i845_cursor_get_hw_state(struct intel_plane *plane,
307 enum pipe *pipe)
308{
309 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
310 enum intel_display_power_domain power_domain;
311 intel_wakeref_t wakeref;
312 bool ret;
313
314 power_domain = POWER_DOMAIN_PIPE(PIPE_A);
315 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
316 if (!wakeref)
317 return false;
318
319 ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE;
320
321 *pipe = PIPE_A;
322
323 intel_display_power_put(dev_priv, power_domain, wakeref);
324
325 return ret;
326}
327
328static unsigned int
329i9xx_cursor_max_stride(struct intel_plane *plane,
330 u32 pixel_format, u64 modifier,
331 unsigned int rotation)
332{
333 return plane->base.dev->mode_config.cursor_width * 4;
334}
335
336static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
337{
338 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
339 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
340 u32 cntl = 0;
341
342 if (DISPLAY_VER(dev_priv) >= 11)
343 return cntl;
344
345 if (crtc_state->gamma_enable)
346 cntl = MCURSOR_PIPE_GAMMA_ENABLE;
347
348 if (crtc_state->csc_enable)
349 cntl |= MCURSOR_PIPE_CSC_ENABLE;
350
351 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
352 cntl |= MCURSOR_PIPE_SEL(crtc->pipe);
353
354 return cntl;
355}
356
357static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
358 const struct intel_plane_state *plane_state)
359{
360 struct drm_i915_private *dev_priv =
361 to_i915(plane_state->uapi.plane->dev);
362 u32 cntl = 0;
363
364 if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
365 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
366
367 switch (drm_rect_width(&plane_state->uapi.dst)) {
368 case 64:
369 cntl |= MCURSOR_MODE_64_ARGB_AX;
370 break;
371 case 128:
372 cntl |= MCURSOR_MODE_128_ARGB_AX;
373 break;
374 case 256:
375 cntl |= MCURSOR_MODE_256_ARGB_AX;
376 break;
377 default:
378 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
379 return 0;
380 }
381
382 if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
383 cntl |= MCURSOR_ROTATE_180;
384
385 /* Wa_22012358565:adl-p */
386 if (DISPLAY_VER(dev_priv) == 13)
387 cntl |= MCURSOR_ARB_SLOTS(1);
388
389 return cntl;
390}
391
392static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
393{
394 struct drm_i915_private *dev_priv =
395 to_i915(plane_state->uapi.plane->dev);
396 int width = drm_rect_width(&plane_state->uapi.dst);
397 int height = drm_rect_height(&plane_state->uapi.dst);
398
399 if (!intel_cursor_size_ok(plane_state))
400 return false;
401
402 /* Cursor width is limited to a few power-of-two sizes */
403 switch (width) {
404 case 256:
405 case 128:
406 case 64:
407 break;
408 default:
409 return false;
410 }
411
412 /*
413 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
414 * height from 8 lines up to the cursor width, when the
415 * cursor is not rotated. Everything else requires square
416 * cursors.
417 */
418 if (HAS_CUR_FBC(dev_priv) &&
419 plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
420 if (height < 8 || height > width)
421 return false;
422 } else {
423 if (height != width)
424 return false;
425 }
426
427 return true;
428}
429
430static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
431 struct intel_plane_state *plane_state)
432{
433 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
434 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
435 const struct drm_framebuffer *fb = plane_state->hw.fb;
436 enum pipe pipe = plane->pipe;
437 int ret;
438
439 ret = intel_check_cursor(crtc_state, plane_state);
440 if (ret)
441 return ret;
442
443 /* if we want to turn off the cursor ignore width and height */
444 if (!fb)
445 return 0;
446
447 /* Check for which cursor types we support */
448 if (!i9xx_cursor_size_ok(plane_state)) {
449 drm_dbg(&dev_priv->drm,
450 "Cursor dimension %dx%d not supported\n",
451 drm_rect_width(&plane_state->uapi.dst),
452 drm_rect_height(&plane_state->uapi.dst));
453 return -EINVAL;
454 }
455
456 drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible &&
457 plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]);
458
459 if (fb->pitches[0] !=
460 drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
461 drm_dbg_kms(&dev_priv->drm,
462 "Invalid cursor stride (%u) (cursor width %d)\n",
463 fb->pitches[0],
464 drm_rect_width(&plane_state->uapi.dst));
465 return -EINVAL;
466 }
467
468 /*
469 * There's something wrong with the cursor on CHV pipe C.
470 * If it straddles the left edge of the screen then
471 * moving it away from the edge or disabling it often
472 * results in a pipe underrun, and often that can lead to
473 * dead pipe (constant underrun reported, and it scans
474 * out just a solid color). To recover from that, the
475 * display power well must be turned off and on again.
476 * Refuse the put the cursor into that compromised position.
477 */
478 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
479 plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
480 drm_dbg_kms(&dev_priv->drm,
481 "CHV cursor C not allowed to straddle the left screen edge\n");
482 return -EINVAL;
483 }
484
485 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
486
487 return 0;
488}
489
490static void i9xx_cursor_disable_sel_fetch_arm(struct intel_plane *plane,
491 const struct intel_crtc_state *crtc_state)
492{
493 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
494 enum pipe pipe = plane->pipe;
495
496 if (!crtc_state->enable_psr2_sel_fetch)
497 return;
498
499 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
500}
501
502static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane,
503 const struct intel_crtc_state *crtc_state,
504 const struct intel_plane_state *plane_state)
505{
506 struct drm_i915_private *i915 = to_i915(plane->base.dev);
507 enum pipe pipe = plane->pipe;
508
509 if (!crtc_state->enable_psr2_sel_fetch)
510 return;
511
512 if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0)
513 intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id),
514 plane_state->ctl);
515 else
516 i9xx_cursor_disable_sel_fetch_arm(plane, crtc_state);
517}
518
519/* TODO: split into noarm+arm pair */
520static void i9xx_cursor_update_arm(struct intel_plane *plane,
521 const struct intel_crtc_state *crtc_state,
522 const struct intel_plane_state *plane_state)
523{
524 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
525 enum pipe pipe = plane->pipe;
526 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
527
528 if (plane_state && plane_state->uapi.visible) {
529 int width = drm_rect_width(&plane_state->uapi.dst);
530 int height = drm_rect_height(&plane_state->uapi.dst);
531
532 cntl = plane_state->ctl |
533 i9xx_cursor_ctl_crtc(crtc_state);
534
535 if (width != height)
536 fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1);
537
538 base = intel_cursor_base(plane_state);
539 pos = intel_cursor_position(plane_state);
540 }
541
542 /*
543 * On some platforms writing CURCNTR first will also
544 * cause CURPOS to be armed by the CURBASE write.
545 * Without the CURCNTR write the CURPOS write would
546 * arm itself. Thus we always update CURCNTR before
547 * CURPOS.
548 *
549 * On other platforms CURPOS always requires the
550 * CURBASE write to arm the update. Additonally
551 * a write to any of the cursor register will cancel
552 * an already armed cursor update. Thus leaving out
553 * the CURBASE write after CURPOS could lead to a
554 * cursor that doesn't appear to move, or even change
555 * shape. Thus we always write CURBASE.
556 *
557 * The other registers are armed by the CURBASE write
558 * except when the plane is getting enabled at which time
559 * the CURCNTR write arms the update.
560 */
561
562 if (DISPLAY_VER(dev_priv) >= 9)
563 skl_write_cursor_wm(plane, crtc_state);
564
565 if (plane_state)
566 i9xx_cursor_update_sel_fetch_arm(plane, crtc_state,
567 plane_state);
568 else
569 i9xx_cursor_disable_sel_fetch_arm(plane, crtc_state);
570
571 if (plane->cursor.base != base ||
572 plane->cursor.size != fbc_ctl ||
573 plane->cursor.cntl != cntl) {
574 if (HAS_CUR_FBC(dev_priv))
575 intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
576 fbc_ctl);
577 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl);
578 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
579 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
580
581 plane->cursor.base = base;
582 plane->cursor.size = fbc_ctl;
583 plane->cursor.cntl = cntl;
584 } else {
585 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
586 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
587 }
588}
589
590static void i9xx_cursor_disable_arm(struct intel_plane *plane,
591 const struct intel_crtc_state *crtc_state)
592{
593 i9xx_cursor_update_arm(plane, crtc_state, NULL);
594}
595
596static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
597 enum pipe *pipe)
598{
599 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
600 enum intel_display_power_domain power_domain;
601 intel_wakeref_t wakeref;
602 bool ret;
603 u32 val;
604
605 /*
606 * Not 100% correct for planes that can move between pipes,
607 * but that's only the case for gen2-3 which don't have any
608 * display power wells.
609 */
610 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
611 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
612 if (!wakeref)
613 return false;
614
615 val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
616
617 ret = val & MCURSOR_MODE_MASK;
618
619 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
620 *pipe = plane->pipe;
621 else
622 *pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val);
623
624 intel_display_power_put(dev_priv, power_domain, wakeref);
625
626 return ret;
627}
628
629static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
630 u32 format, u64 modifier)
631{
632 if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
633 return false;
634
635 return format == DRM_FORMAT_ARGB8888;
636}
637
638static int
639intel_legacy_cursor_update(struct drm_plane *_plane,
640 struct drm_crtc *_crtc,
641 struct drm_framebuffer *fb,
642 int crtc_x, int crtc_y,
643 unsigned int crtc_w, unsigned int crtc_h,
644 u32 src_x, u32 src_y,
645 u32 src_w, u32 src_h,
646 struct drm_modeset_acquire_ctx *ctx)
647{
648 struct intel_plane *plane = to_intel_plane(_plane);
649 struct intel_crtc *crtc = to_intel_crtc(_crtc);
650 struct intel_plane_state *old_plane_state =
651 to_intel_plane_state(plane->base.state);
652 struct intel_plane_state *new_plane_state;
653 struct intel_crtc_state *crtc_state =
654 to_intel_crtc_state(crtc->base.state);
655 struct intel_crtc_state *new_crtc_state;
656 int ret;
657
658 /*
659 * When crtc is inactive or there is a modeset pending,
660 * wait for it to complete in the slowpath.
661 * PSR2 selective fetch also requires the slow path as
662 * PSR2 plane and transcoder registers can only be updated during
663 * vblank.
664 *
665 * FIXME bigjoiner fastpath would be good
666 */
667 if (!crtc_state->hw.active ||
668 intel_crtc_needs_modeset(crtc_state) ||
669 intel_crtc_needs_fastset(crtc_state) ||
670 crtc_state->bigjoiner_pipes)
671 goto slow;
672
673 /*
674 * Don't do an async update if there is an outstanding commit modifying
675 * the plane. This prevents our async update's changes from getting
676 * overridden by a previous synchronous update's state.
677 */
678 if (old_plane_state->uapi.commit &&
679 !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
680 goto slow;
681
682 /*
683 * If any parameters change that may affect watermarks,
684 * take the slowpath. Only changing fb or position should be
685 * in the fastpath.
686 */
687 if (old_plane_state->uapi.crtc != &crtc->base ||
688 old_plane_state->uapi.src_w != src_w ||
689 old_plane_state->uapi.src_h != src_h ||
690 old_plane_state->uapi.crtc_w != crtc_w ||
691 old_plane_state->uapi.crtc_h != crtc_h ||
692 !old_plane_state->uapi.fb != !fb)
693 goto slow;
694
695 new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
696 if (!new_plane_state)
697 return -ENOMEM;
698
699 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
700 if (!new_crtc_state) {
701 ret = -ENOMEM;
702 goto out_free;
703 }
704
705 drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
706
707 new_plane_state->uapi.src_x = src_x;
708 new_plane_state->uapi.src_y = src_y;
709 new_plane_state->uapi.src_w = src_w;
710 new_plane_state->uapi.src_h = src_h;
711 new_plane_state->uapi.crtc_x = crtc_x;
712 new_plane_state->uapi.crtc_y = crtc_y;
713 new_plane_state->uapi.crtc_w = crtc_w;
714 new_plane_state->uapi.crtc_h = crtc_h;
715
716 intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state, crtc);
717
718 ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
719 old_plane_state, new_plane_state);
720 if (ret)
721 goto out_free;
722
723 ret = intel_plane_pin_fb(new_plane_state);
724 if (ret)
725 goto out_free;
726
727 intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
728 ORIGIN_CURSOR_UPDATE);
729 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
730 to_intel_frontbuffer(new_plane_state->hw.fb),
731 plane->frontbuffer_bit);
732
733 /* Swap plane state */
734 plane->base.state = &new_plane_state->uapi;
735
736 /*
737 * We cannot swap crtc_state as it may be in use by an atomic commit or
738 * page flip that's running simultaneously. If we swap crtc_state and
739 * destroy the old state, we will cause a use-after-free there.
740 *
741 * Only update active_planes, which is needed for our internal
742 * bookkeeping. Either value will do the right thing when updating
743 * planes atomically. If the cursor was part of the atomic update then
744 * we would have taken the slowpath.
745 */
746 crtc_state->active_planes = new_crtc_state->active_planes;
747
748 /*
749 * Technically we should do a vblank evasion here to make
750 * sure all the cursor registers update on the same frame.
751 * For now just make sure the register writes happen as
752 * quickly as possible to minimize the race window.
753 */
754 local_irq_disable();
755
756 if (new_plane_state->uapi.visible) {
757 intel_plane_update_noarm(plane, crtc_state, new_plane_state);
758 intel_plane_update_arm(plane, crtc_state, new_plane_state);
759 } else {
760 intel_plane_disable_arm(plane, crtc_state);
761 }
762
763 local_irq_enable();
764
765 intel_plane_unpin_fb(old_plane_state);
766
767out_free:
768 if (new_crtc_state)
769 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
770 if (ret)
771 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
772 else
773 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
774 return ret;
775
776slow:
777 return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
778 crtc_x, crtc_y, crtc_w, crtc_h,
779 src_x, src_y, src_w, src_h, ctx);
780}
781
782static const struct drm_plane_funcs intel_cursor_plane_funcs = {
783 .update_plane = intel_legacy_cursor_update,
784 .disable_plane = drm_atomic_helper_disable_plane,
785 .destroy = intel_plane_destroy,
786 .atomic_duplicate_state = intel_plane_duplicate_state,
787 .atomic_destroy_state = intel_plane_destroy_state,
788 .format_mod_supported = intel_cursor_format_mod_supported,
789};
790
791struct intel_plane *
792intel_cursor_plane_create(struct drm_i915_private *dev_priv,
793 enum pipe pipe)
794{
795 struct intel_plane *cursor;
796 int ret, zpos;
797 u64 *modifiers;
798
799 cursor = intel_plane_alloc();
800 if (IS_ERR(cursor))
801 return cursor;
802
803 cursor->pipe = pipe;
804 cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
805 cursor->id = PLANE_CURSOR;
806 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
807
808 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
809 cursor->max_stride = i845_cursor_max_stride;
810 cursor->update_arm = i845_cursor_update_arm;
811 cursor->disable_arm = i845_cursor_disable_arm;
812 cursor->get_hw_state = i845_cursor_get_hw_state;
813 cursor->check_plane = i845_check_cursor;
814 } else {
815 cursor->max_stride = i9xx_cursor_max_stride;
816 cursor->update_arm = i9xx_cursor_update_arm;
817 cursor->disable_arm = i9xx_cursor_disable_arm;
818 cursor->get_hw_state = i9xx_cursor_get_hw_state;
819 cursor->check_plane = i9xx_check_cursor;
820 }
821
822 cursor->cursor.base = ~0;
823 cursor->cursor.cntl = ~0;
824
825 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
826 cursor->cursor.size = ~0;
827
828 modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_NONE);
829
830 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
831 0, &intel_cursor_plane_funcs,
832 intel_cursor_formats,
833 ARRAY_SIZE(intel_cursor_formats),
834 modifiers,
835 DRM_PLANE_TYPE_CURSOR,
836 "cursor %c", pipe_name(pipe));
837
838 kfree(modifiers);
839
840 if (ret)
841 goto fail;
842
843 if (DISPLAY_VER(dev_priv) >= 4)
844 drm_plane_create_rotation_property(&cursor->base,
845 DRM_MODE_ROTATE_0,
846 DRM_MODE_ROTATE_0 |
847 DRM_MODE_ROTATE_180);
848
849 zpos = DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
850 drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
851
852 if (DISPLAY_VER(dev_priv) >= 12)
853 drm_plane_enable_fb_damage_clips(&cursor->base);
854
855 intel_plane_helper_add(cursor);
856
857 return cursor;
858
859fail:
860 intel_plane_free(cursor);
861
862 return ERR_PTR(ret);
863}
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2020 Intel Corporation
4 */
5#include <linux/kernel.h>
6
7#include <drm/drm_atomic_helper.h>
8#include <drm/drm_atomic_uapi.h>
9#include <drm/drm_blend.h>
10#include <drm/drm_damage_helper.h>
11#include <drm/drm_fourcc.h>
12
13#include "i915_reg.h"
14#include "intel_atomic.h"
15#include "intel_atomic_plane.h"
16#include "intel_cursor.h"
17#include "intel_de.h"
18#include "intel_display.h"
19#include "intel_display_types.h"
20#include "intel_fb.h"
21#include "intel_fb_pin.h"
22#include "intel_frontbuffer.h"
23#include "intel_psr.h"
24#include "intel_sprite.h"
25#include "skl_watermark.h"
26
27/* Cursor formats */
28static const u32 intel_cursor_formats[] = {
29 DRM_FORMAT_ARGB8888,
30};
31
32static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
33{
34 struct drm_i915_private *dev_priv =
35 to_i915(plane_state->uapi.plane->dev);
36 const struct drm_framebuffer *fb = plane_state->hw.fb;
37 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
38 u32 base;
39
40 if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
41 base = sg_dma_address(obj->mm.pages->sgl);
42 else
43 base = intel_plane_ggtt_offset(plane_state);
44
45 return base + plane_state->view.color_plane[0].offset;
46}
47
48static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
49{
50 int x = plane_state->uapi.dst.x1;
51 int y = plane_state->uapi.dst.y1;
52 u32 pos = 0;
53
54 if (x < 0) {
55 pos |= CURSOR_POS_X_SIGN;
56 x = -x;
57 }
58 pos |= CURSOR_POS_X(x);
59
60 if (y < 0) {
61 pos |= CURSOR_POS_Y_SIGN;
62 y = -y;
63 }
64 pos |= CURSOR_POS_Y(y);
65
66 return pos;
67}
68
69static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
70{
71 const struct drm_mode_config *config =
72 &plane_state->uapi.plane->dev->mode_config;
73 int width = drm_rect_width(&plane_state->uapi.dst);
74 int height = drm_rect_height(&plane_state->uapi.dst);
75
76 return width > 0 && width <= config->cursor_width &&
77 height > 0 && height <= config->cursor_height;
78}
79
80static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
81{
82 struct drm_i915_private *dev_priv =
83 to_i915(plane_state->uapi.plane->dev);
84 unsigned int rotation = plane_state->hw.rotation;
85 int src_x, src_y;
86 u32 offset;
87 int ret;
88
89 ret = intel_plane_compute_gtt(plane_state);
90 if (ret)
91 return ret;
92
93 if (!plane_state->uapi.visible)
94 return 0;
95
96 src_x = plane_state->uapi.src.x1 >> 16;
97 src_y = plane_state->uapi.src.y1 >> 16;
98
99 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
100 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
101 plane_state, 0);
102
103 if (src_x != 0 || src_y != 0) {
104 drm_dbg_kms(&dev_priv->drm,
105 "Arbitrary cursor panning not supported\n");
106 return -EINVAL;
107 }
108
109 /*
110 * Put the final coordinates back so that the src
111 * coordinate checks will see the right values.
112 */
113 drm_rect_translate_to(&plane_state->uapi.src,
114 src_x << 16, src_y << 16);
115
116 /* ILK+ do this automagically in hardware */
117 if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
118 const struct drm_framebuffer *fb = plane_state->hw.fb;
119 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
120 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
121
122 offset += (src_h * src_w - 1) * fb->format->cpp[0];
123 }
124
125 plane_state->view.color_plane[0].offset = offset;
126 plane_state->view.color_plane[0].x = src_x;
127 plane_state->view.color_plane[0].y = src_y;
128
129 return 0;
130}
131
132static int intel_check_cursor(struct intel_crtc_state *crtc_state,
133 struct intel_plane_state *plane_state)
134{
135 const struct drm_framebuffer *fb = plane_state->hw.fb;
136 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
137 const struct drm_rect src = plane_state->uapi.src;
138 const struct drm_rect dst = plane_state->uapi.dst;
139 int ret;
140
141 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
142 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n");
143 return -EINVAL;
144 }
145
146 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
147 DRM_PLANE_NO_SCALING,
148 DRM_PLANE_NO_SCALING,
149 true);
150 if (ret)
151 return ret;
152
153 /* Use the unclipped src/dst rectangles, which we program to hw */
154 plane_state->uapi.src = src;
155 plane_state->uapi.dst = dst;
156
157 /* final plane coordinates will be relative to the plane's pipe */
158 drm_rect_translate(&plane_state->uapi.dst,
159 -crtc_state->pipe_src.x1,
160 -crtc_state->pipe_src.y1);
161
162 ret = intel_cursor_check_surface(plane_state);
163 if (ret)
164 return ret;
165
166 if (!plane_state->uapi.visible)
167 return 0;
168
169 ret = intel_plane_check_src_coordinates(plane_state);
170 if (ret)
171 return ret;
172
173 return 0;
174}
175
176static unsigned int
177i845_cursor_max_stride(struct intel_plane *plane,
178 u32 pixel_format, u64 modifier,
179 unsigned int rotation)
180{
181 return 2048;
182}
183
184static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
185{
186 u32 cntl = 0;
187
188 if (crtc_state->gamma_enable)
189 cntl |= CURSOR_PIPE_GAMMA_ENABLE;
190
191 return cntl;
192}
193
194static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
195 const struct intel_plane_state *plane_state)
196{
197 return CURSOR_ENABLE |
198 CURSOR_FORMAT_ARGB |
199 CURSOR_STRIDE(plane_state->view.color_plane[0].mapping_stride);
200}
201
202static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
203{
204 int width = drm_rect_width(&plane_state->uapi.dst);
205
206 /*
207 * 845g/865g are only limited by the width of their cursors,
208 * the height is arbitrary up to the precision of the register.
209 */
210 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
211}
212
213static int i845_check_cursor(struct intel_crtc_state *crtc_state,
214 struct intel_plane_state *plane_state)
215{
216 const struct drm_framebuffer *fb = plane_state->hw.fb;
217 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
218 int ret;
219
220 ret = intel_check_cursor(crtc_state, plane_state);
221 if (ret)
222 return ret;
223
224 /* if we want to turn off the cursor ignore width and height */
225 if (!fb)
226 return 0;
227
228 /* Check for which cursor types we support */
229 if (!i845_cursor_size_ok(plane_state)) {
230 drm_dbg_kms(&i915->drm,
231 "Cursor dimension %dx%d not supported\n",
232 drm_rect_width(&plane_state->uapi.dst),
233 drm_rect_height(&plane_state->uapi.dst));
234 return -EINVAL;
235 }
236
237 drm_WARN_ON(&i915->drm, plane_state->uapi.visible &&
238 plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]);
239
240 switch (fb->pitches[0]) {
241 case 256:
242 case 512:
243 case 1024:
244 case 2048:
245 break;
246 default:
247 drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n",
248 fb->pitches[0]);
249 return -EINVAL;
250 }
251
252 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
253
254 return 0;
255}
256
257/* TODO: split into noarm+arm pair */
258static void i845_cursor_update_arm(struct intel_plane *plane,
259 const struct intel_crtc_state *crtc_state,
260 const struct intel_plane_state *plane_state)
261{
262 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
263 u32 cntl = 0, base = 0, pos = 0, size = 0;
264
265 if (plane_state && plane_state->uapi.visible) {
266 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
267 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
268
269 cntl = plane_state->ctl |
270 i845_cursor_ctl_crtc(crtc_state);
271
272 size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width);
273
274 base = intel_cursor_base(plane_state);
275 pos = intel_cursor_position(plane_state);
276 }
277
278 /* On these chipsets we can only modify the base/size/stride
279 * whilst the cursor is disabled.
280 */
281 if (plane->cursor.base != base ||
282 plane->cursor.size != size ||
283 plane->cursor.cntl != cntl) {
284 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
285 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
286 intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size);
287 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
288 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
289
290 plane->cursor.base = base;
291 plane->cursor.size = size;
292 plane->cursor.cntl = cntl;
293 } else {
294 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
295 }
296}
297
298static void i845_cursor_disable_arm(struct intel_plane *plane,
299 const struct intel_crtc_state *crtc_state)
300{
301 i845_cursor_update_arm(plane, crtc_state, NULL);
302}
303
304static bool i845_cursor_get_hw_state(struct intel_plane *plane,
305 enum pipe *pipe)
306{
307 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
308 enum intel_display_power_domain power_domain;
309 intel_wakeref_t wakeref;
310 bool ret;
311
312 power_domain = POWER_DOMAIN_PIPE(PIPE_A);
313 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
314 if (!wakeref)
315 return false;
316
317 ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE;
318
319 *pipe = PIPE_A;
320
321 intel_display_power_put(dev_priv, power_domain, wakeref);
322
323 return ret;
324}
325
326static unsigned int
327i9xx_cursor_max_stride(struct intel_plane *plane,
328 u32 pixel_format, u64 modifier,
329 unsigned int rotation)
330{
331 return plane->base.dev->mode_config.cursor_width * 4;
332}
333
334static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
335{
336 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
337 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
338 u32 cntl = 0;
339
340 if (DISPLAY_VER(dev_priv) >= 11)
341 return cntl;
342
343 if (crtc_state->gamma_enable)
344 cntl = MCURSOR_PIPE_GAMMA_ENABLE;
345
346 if (crtc_state->csc_enable)
347 cntl |= MCURSOR_PIPE_CSC_ENABLE;
348
349 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
350 cntl |= MCURSOR_PIPE_SEL(crtc->pipe);
351
352 return cntl;
353}
354
355static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
356 const struct intel_plane_state *plane_state)
357{
358 struct drm_i915_private *dev_priv =
359 to_i915(plane_state->uapi.plane->dev);
360 u32 cntl = 0;
361
362 if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
363 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
364
365 switch (drm_rect_width(&plane_state->uapi.dst)) {
366 case 64:
367 cntl |= MCURSOR_MODE_64_ARGB_AX;
368 break;
369 case 128:
370 cntl |= MCURSOR_MODE_128_ARGB_AX;
371 break;
372 case 256:
373 cntl |= MCURSOR_MODE_256_ARGB_AX;
374 break;
375 default:
376 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
377 return 0;
378 }
379
380 if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
381 cntl |= MCURSOR_ROTATE_180;
382
383 /* Wa_22012358565:adl-p */
384 if (DISPLAY_VER(dev_priv) == 13)
385 cntl |= MCURSOR_ARB_SLOTS(1);
386
387 return cntl;
388}
389
390static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
391{
392 struct drm_i915_private *dev_priv =
393 to_i915(plane_state->uapi.plane->dev);
394 int width = drm_rect_width(&plane_state->uapi.dst);
395 int height = drm_rect_height(&plane_state->uapi.dst);
396
397 if (!intel_cursor_size_ok(plane_state))
398 return false;
399
400 /* Cursor width is limited to a few power-of-two sizes */
401 switch (width) {
402 case 256:
403 case 128:
404 case 64:
405 break;
406 default:
407 return false;
408 }
409
410 /*
411 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
412 * height from 8 lines up to the cursor width, when the
413 * cursor is not rotated. Everything else requires square
414 * cursors.
415 */
416 if (HAS_CUR_FBC(dev_priv) &&
417 plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
418 if (height < 8 || height > width)
419 return false;
420 } else {
421 if (height != width)
422 return false;
423 }
424
425 return true;
426}
427
428static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
429 struct intel_plane_state *plane_state)
430{
431 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
432 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
433 const struct drm_framebuffer *fb = plane_state->hw.fb;
434 enum pipe pipe = plane->pipe;
435 int ret;
436
437 ret = intel_check_cursor(crtc_state, plane_state);
438 if (ret)
439 return ret;
440
441 /* if we want to turn off the cursor ignore width and height */
442 if (!fb)
443 return 0;
444
445 /* Check for which cursor types we support */
446 if (!i9xx_cursor_size_ok(plane_state)) {
447 drm_dbg(&dev_priv->drm,
448 "Cursor dimension %dx%d not supported\n",
449 drm_rect_width(&plane_state->uapi.dst),
450 drm_rect_height(&plane_state->uapi.dst));
451 return -EINVAL;
452 }
453
454 drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible &&
455 plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]);
456
457 if (fb->pitches[0] !=
458 drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
459 drm_dbg_kms(&dev_priv->drm,
460 "Invalid cursor stride (%u) (cursor width %d)\n",
461 fb->pitches[0],
462 drm_rect_width(&plane_state->uapi.dst));
463 return -EINVAL;
464 }
465
466 /*
467 * There's something wrong with the cursor on CHV pipe C.
468 * If it straddles the left edge of the screen then
469 * moving it away from the edge or disabling it often
470 * results in a pipe underrun, and often that can lead to
471 * dead pipe (constant underrun reported, and it scans
472 * out just a solid color). To recover from that, the
473 * display power well must be turned off and on again.
474 * Refuse the put the cursor into that compromised position.
475 */
476 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
477 plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
478 drm_dbg_kms(&dev_priv->drm,
479 "CHV cursor C not allowed to straddle the left screen edge\n");
480 return -EINVAL;
481 }
482
483 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
484
485 return 0;
486}
487
488/* TODO: split into noarm+arm pair */
489static void i9xx_cursor_update_arm(struct intel_plane *plane,
490 const struct intel_crtc_state *crtc_state,
491 const struct intel_plane_state *plane_state)
492{
493 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
494 enum pipe pipe = plane->pipe;
495 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
496
497 if (plane_state && plane_state->uapi.visible) {
498 int width = drm_rect_width(&plane_state->uapi.dst);
499 int height = drm_rect_height(&plane_state->uapi.dst);
500
501 cntl = plane_state->ctl |
502 i9xx_cursor_ctl_crtc(crtc_state);
503
504 if (width != height)
505 fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1);
506
507 base = intel_cursor_base(plane_state);
508 pos = intel_cursor_position(plane_state);
509 }
510
511 /*
512 * On some platforms writing CURCNTR first will also
513 * cause CURPOS to be armed by the CURBASE write.
514 * Without the CURCNTR write the CURPOS write would
515 * arm itself. Thus we always update CURCNTR before
516 * CURPOS.
517 *
518 * On other platforms CURPOS always requires the
519 * CURBASE write to arm the update. Additonally
520 * a write to any of the cursor register will cancel
521 * an already armed cursor update. Thus leaving out
522 * the CURBASE write after CURPOS could lead to a
523 * cursor that doesn't appear to move, or even change
524 * shape. Thus we always write CURBASE.
525 *
526 * The other registers are armed by the CURBASE write
527 * except when the plane is getting enabled at which time
528 * the CURCNTR write arms the update.
529 */
530
531 if (DISPLAY_VER(dev_priv) >= 9)
532 skl_write_cursor_wm(plane, crtc_state);
533
534 if (plane_state)
535 intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, 0);
536 else
537 intel_psr2_disable_plane_sel_fetch(plane, crtc_state);
538
539 if (plane->cursor.base != base ||
540 plane->cursor.size != fbc_ctl ||
541 plane->cursor.cntl != cntl) {
542 if (HAS_CUR_FBC(dev_priv))
543 intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
544 fbc_ctl);
545 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl);
546 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
547 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
548
549 plane->cursor.base = base;
550 plane->cursor.size = fbc_ctl;
551 plane->cursor.cntl = cntl;
552 } else {
553 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
554 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
555 }
556}
557
558static void i9xx_cursor_disable_arm(struct intel_plane *plane,
559 const struct intel_crtc_state *crtc_state)
560{
561 i9xx_cursor_update_arm(plane, crtc_state, NULL);
562}
563
564static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
565 enum pipe *pipe)
566{
567 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
568 enum intel_display_power_domain power_domain;
569 intel_wakeref_t wakeref;
570 bool ret;
571 u32 val;
572
573 /*
574 * Not 100% correct for planes that can move between pipes,
575 * but that's only the case for gen2-3 which don't have any
576 * display power wells.
577 */
578 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
579 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
580 if (!wakeref)
581 return false;
582
583 val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
584
585 ret = val & MCURSOR_MODE_MASK;
586
587 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
588 *pipe = plane->pipe;
589 else
590 *pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val);
591
592 intel_display_power_put(dev_priv, power_domain, wakeref);
593
594 return ret;
595}
596
597static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
598 u32 format, u64 modifier)
599{
600 if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
601 return false;
602
603 return format == DRM_FORMAT_ARGB8888;
604}
605
606static int
607intel_legacy_cursor_update(struct drm_plane *_plane,
608 struct drm_crtc *_crtc,
609 struct drm_framebuffer *fb,
610 int crtc_x, int crtc_y,
611 unsigned int crtc_w, unsigned int crtc_h,
612 u32 src_x, u32 src_y,
613 u32 src_w, u32 src_h,
614 struct drm_modeset_acquire_ctx *ctx)
615{
616 struct intel_plane *plane = to_intel_plane(_plane);
617 struct intel_crtc *crtc = to_intel_crtc(_crtc);
618 struct intel_plane_state *old_plane_state =
619 to_intel_plane_state(plane->base.state);
620 struct intel_plane_state *new_plane_state;
621 struct intel_crtc_state *crtc_state =
622 to_intel_crtc_state(crtc->base.state);
623 struct intel_crtc_state *new_crtc_state;
624 int ret;
625
626 /*
627 * When crtc is inactive or there is a modeset pending,
628 * wait for it to complete in the slowpath.
629 * PSR2 selective fetch also requires the slow path as
630 * PSR2 plane and transcoder registers can only be updated during
631 * vblank.
632 *
633 * FIXME bigjoiner fastpath would be good
634 */
635 if (!crtc_state->hw.active ||
636 intel_crtc_needs_modeset(crtc_state) ||
637 intel_crtc_needs_fastset(crtc_state) ||
638 crtc_state->bigjoiner_pipes)
639 goto slow;
640
641 /*
642 * Don't do an async update if there is an outstanding commit modifying
643 * the plane. This prevents our async update's changes from getting
644 * overridden by a previous synchronous update's state.
645 */
646 if (old_plane_state->uapi.commit &&
647 !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
648 goto slow;
649
650 /*
651 * If any parameters change that may affect watermarks,
652 * take the slowpath. Only changing fb or position should be
653 * in the fastpath.
654 */
655 if (old_plane_state->uapi.crtc != &crtc->base ||
656 old_plane_state->uapi.src_w != src_w ||
657 old_plane_state->uapi.src_h != src_h ||
658 old_plane_state->uapi.crtc_w != crtc_w ||
659 old_plane_state->uapi.crtc_h != crtc_h ||
660 !old_plane_state->uapi.fb != !fb)
661 goto slow;
662
663 new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
664 if (!new_plane_state)
665 return -ENOMEM;
666
667 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
668 if (!new_crtc_state) {
669 ret = -ENOMEM;
670 goto out_free;
671 }
672
673 drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
674
675 new_plane_state->uapi.src_x = src_x;
676 new_plane_state->uapi.src_y = src_y;
677 new_plane_state->uapi.src_w = src_w;
678 new_plane_state->uapi.src_h = src_h;
679 new_plane_state->uapi.crtc_x = crtc_x;
680 new_plane_state->uapi.crtc_y = crtc_y;
681 new_plane_state->uapi.crtc_w = crtc_w;
682 new_plane_state->uapi.crtc_h = crtc_h;
683
684 intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state, crtc);
685
686 ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
687 old_plane_state, new_plane_state);
688 if (ret)
689 goto out_free;
690
691 ret = intel_plane_pin_fb(new_plane_state);
692 if (ret)
693 goto out_free;
694
695 intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
696 ORIGIN_CURSOR_UPDATE);
697 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
698 to_intel_frontbuffer(new_plane_state->hw.fb),
699 plane->frontbuffer_bit);
700
701 /* Swap plane state */
702 plane->base.state = &new_plane_state->uapi;
703
704 /*
705 * We cannot swap crtc_state as it may be in use by an atomic commit or
706 * page flip that's running simultaneously. If we swap crtc_state and
707 * destroy the old state, we will cause a use-after-free there.
708 *
709 * Only update active_planes, which is needed for our internal
710 * bookkeeping. Either value will do the right thing when updating
711 * planes atomically. If the cursor was part of the atomic update then
712 * we would have taken the slowpath.
713 */
714 crtc_state->active_planes = new_crtc_state->active_planes;
715
716 /*
717 * Technically we should do a vblank evasion here to make
718 * sure all the cursor registers update on the same frame.
719 * For now just make sure the register writes happen as
720 * quickly as possible to minimize the race window.
721 */
722 local_irq_disable();
723
724 if (new_plane_state->uapi.visible) {
725 intel_plane_update_noarm(plane, crtc_state, new_plane_state);
726 intel_plane_update_arm(plane, crtc_state, new_plane_state);
727 } else {
728 intel_plane_disable_arm(plane, crtc_state);
729 }
730
731 local_irq_enable();
732
733 intel_plane_unpin_fb(old_plane_state);
734
735out_free:
736 if (new_crtc_state)
737 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
738 if (ret)
739 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
740 else
741 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
742 return ret;
743
744slow:
745 return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
746 crtc_x, crtc_y, crtc_w, crtc_h,
747 src_x, src_y, src_w, src_h, ctx);
748}
749
750static const struct drm_plane_funcs intel_cursor_plane_funcs = {
751 .update_plane = intel_legacy_cursor_update,
752 .disable_plane = drm_atomic_helper_disable_plane,
753 .destroy = intel_plane_destroy,
754 .atomic_duplicate_state = intel_plane_duplicate_state,
755 .atomic_destroy_state = intel_plane_destroy_state,
756 .format_mod_supported = intel_cursor_format_mod_supported,
757};
758
759struct intel_plane *
760intel_cursor_plane_create(struct drm_i915_private *dev_priv,
761 enum pipe pipe)
762{
763 struct intel_plane *cursor;
764 int ret, zpos;
765 u64 *modifiers;
766
767 cursor = intel_plane_alloc();
768 if (IS_ERR(cursor))
769 return cursor;
770
771 cursor->pipe = pipe;
772 cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
773 cursor->id = PLANE_CURSOR;
774 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
775
776 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
777 cursor->max_stride = i845_cursor_max_stride;
778 cursor->update_arm = i845_cursor_update_arm;
779 cursor->disable_arm = i845_cursor_disable_arm;
780 cursor->get_hw_state = i845_cursor_get_hw_state;
781 cursor->check_plane = i845_check_cursor;
782 } else {
783 cursor->max_stride = i9xx_cursor_max_stride;
784 cursor->update_arm = i9xx_cursor_update_arm;
785 cursor->disable_arm = i9xx_cursor_disable_arm;
786 cursor->get_hw_state = i9xx_cursor_get_hw_state;
787 cursor->check_plane = i9xx_check_cursor;
788 }
789
790 cursor->cursor.base = ~0;
791 cursor->cursor.cntl = ~0;
792
793 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
794 cursor->cursor.size = ~0;
795
796 modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_NONE);
797
798 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
799 0, &intel_cursor_plane_funcs,
800 intel_cursor_formats,
801 ARRAY_SIZE(intel_cursor_formats),
802 modifiers,
803 DRM_PLANE_TYPE_CURSOR,
804 "cursor %c", pipe_name(pipe));
805
806 kfree(modifiers);
807
808 if (ret)
809 goto fail;
810
811 if (DISPLAY_VER(dev_priv) >= 4)
812 drm_plane_create_rotation_property(&cursor->base,
813 DRM_MODE_ROTATE_0,
814 DRM_MODE_ROTATE_0 |
815 DRM_MODE_ROTATE_180);
816
817 zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
818 drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
819
820 if (DISPLAY_VER(dev_priv) >= 12)
821 drm_plane_enable_fb_damage_clips(&cursor->base);
822
823 intel_plane_helper_add(cursor);
824
825 return cursor;
826
827fail:
828 intel_plane_free(cursor);
829
830 return ERR_PTR(ret);
831}