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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2019 Intel Corporation
4 */
5
6#include <drm/drm_atomic_state_helper.h>
7
8#include "i915_drv.h"
9#include "i915_reg.h"
10#include "i915_utils.h"
11#include "intel_atomic.h"
12#include "intel_bw.h"
13#include "intel_cdclk.h"
14#include "intel_display_core.h"
15#include "intel_display_types.h"
16#include "skl_watermark.h"
17#include "intel_mchbar_regs.h"
18#include "intel_pcode.h"
19
20/* Parameters for Qclk Geyserville (QGV) */
21struct intel_qgv_point {
22 u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
23};
24
25struct intel_psf_gv_point {
26 u8 clk; /* clock in multiples of 16.6666 MHz */
27};
28
29struct intel_qgv_info {
30 struct intel_qgv_point points[I915_NUM_QGV_POINTS];
31 struct intel_psf_gv_point psf_points[I915_NUM_PSF_GV_POINTS];
32 u8 num_points;
33 u8 num_psf_points;
34 u8 t_bl;
35 u8 max_numchannels;
36 u8 channel_width;
37 u8 deinterleave;
38};
39
40static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
41 struct intel_qgv_point *sp,
42 int point)
43{
44 u32 dclk_ratio, dclk_reference;
45 u32 val;
46
47 val = intel_uncore_read(&dev_priv->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC);
48 dclk_ratio = REG_FIELD_GET(DG1_QCLK_RATIO_MASK, val);
49 if (val & DG1_QCLK_REFERENCE)
50 dclk_reference = 6; /* 6 * 16.666 MHz = 100 MHz */
51 else
52 dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */
53 sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + 500, 1000);
54
55 val = intel_uncore_read(&dev_priv->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
56 if (val & DG1_GEAR_TYPE)
57 sp->dclk *= 2;
58
59 if (sp->dclk == 0)
60 return -EINVAL;
61
62 val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
63 sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val);
64 sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val);
65
66 val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH);
67 sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val);
68 sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val);
69
70 sp->t_rc = sp->t_rp + sp->t_ras;
71
72 return 0;
73}
74
75static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
76 struct intel_qgv_point *sp,
77 int point)
78{
79 u32 val = 0, val2 = 0;
80 u16 dclk;
81 int ret;
82
83 ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
84 ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
85 &val, &val2);
86 if (ret)
87 return ret;
88
89 dclk = val & 0xffff;
90 sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) >= 12 ? 500 : 0),
91 1000);
92 sp->t_rp = (val & 0xff0000) >> 16;
93 sp->t_rcd = (val & 0xff000000) >> 24;
94
95 sp->t_rdpre = val2 & 0xff;
96 sp->t_ras = (val2 & 0xff00) >> 8;
97
98 sp->t_rc = sp->t_rp + sp->t_ras;
99
100 return 0;
101}
102
103static int adls_pcode_read_psf_gv_point_info(struct drm_i915_private *dev_priv,
104 struct intel_psf_gv_point *points)
105{
106 u32 val = 0;
107 int ret;
108 int i;
109
110 ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
111 ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
112 if (ret)
113 return ret;
114
115 for (i = 0; i < I915_NUM_PSF_GV_POINTS; i++) {
116 points[i].clk = val & 0xff;
117 val >>= 8;
118 }
119
120 return 0;
121}
122
123static u16 icl_qgv_points_mask(struct drm_i915_private *i915)
124{
125 unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
126 unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
127 u16 qgv_points = 0, psf_points = 0;
128
129 /*
130 * We can _not_ use the whole ADLS_QGV_PT_MASK here, as PCode rejects
131 * it with failure if we try masking any unadvertised points.
132 * So need to operate only with those returned from PCode.
133 */
134 if (num_qgv_points > 0)
135 qgv_points = GENMASK(num_qgv_points - 1, 0);
136
137 if (num_psf_gv_points > 0)
138 psf_points = GENMASK(num_psf_gv_points - 1, 0);
139
140 return ICL_PCODE_REQ_QGV_PT(qgv_points) | ADLS_PCODE_REQ_PSF_PT(psf_points);
141}
142
143static bool is_sagv_enabled(struct drm_i915_private *i915, u16 points_mask)
144{
145 return !is_power_of_2(~points_mask & icl_qgv_points_mask(i915) &
146 ICL_PCODE_REQ_QGV_PT_MASK);
147}
148
149int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
150 u32 points_mask)
151{
152 int ret;
153
154 if (DISPLAY_VER(dev_priv) >= 14)
155 return 0;
156
157 /* bspec says to keep retrying for at least 1 ms */
158 ret = skl_pcode_request(&dev_priv->uncore, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
159 points_mask,
160 ICL_PCODE_REP_QGV_MASK | ADLS_PCODE_REP_PSF_MASK,
161 ICL_PCODE_REP_QGV_SAFE | ADLS_PCODE_REP_PSF_SAFE,
162 1);
163
164 if (ret < 0) {
165 drm_err(&dev_priv->drm, "Failed to disable qgv points (%d) points: 0x%x\n", ret, points_mask);
166 return ret;
167 }
168
169 dev_priv->display.sagv.status = is_sagv_enabled(dev_priv, points_mask) ?
170 I915_SAGV_ENABLED : I915_SAGV_DISABLED;
171
172 return 0;
173}
174
175static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv,
176 struct intel_qgv_point *sp, int point)
177{
178 u32 val, val2;
179 u16 dclk;
180
181 val = intel_uncore_read(&dev_priv->uncore,
182 MTL_MEM_SS_INFO_QGV_POINT_LOW(point));
183 val2 = intel_uncore_read(&dev_priv->uncore,
184 MTL_MEM_SS_INFO_QGV_POINT_HIGH(point));
185 dclk = REG_FIELD_GET(MTL_DCLK_MASK, val);
186 sp->dclk = DIV_ROUND_CLOSEST(16667 * dclk, 1000);
187 sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val);
188 sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val);
189
190 sp->t_rdpre = REG_FIELD_GET(MTL_TRDPRE_MASK, val2);
191 sp->t_ras = REG_FIELD_GET(MTL_TRAS_MASK, val2);
192
193 sp->t_rc = sp->t_rp + sp->t_ras;
194
195 return 0;
196}
197
198static int
199intel_read_qgv_point_info(struct drm_i915_private *dev_priv,
200 struct intel_qgv_point *sp,
201 int point)
202{
203 if (DISPLAY_VER(dev_priv) >= 14)
204 return mtl_read_qgv_point_info(dev_priv, sp, point);
205 else if (IS_DG1(dev_priv))
206 return dg1_mchbar_read_qgv_point_info(dev_priv, sp, point);
207 else
208 return icl_pcode_read_qgv_point_info(dev_priv, sp, point);
209}
210
211static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
212 struct intel_qgv_info *qi,
213 bool is_y_tile)
214{
215 const struct dram_info *dram_info = &dev_priv->dram_info;
216 int i, ret;
217
218 qi->num_points = dram_info->num_qgv_points;
219 qi->num_psf_points = dram_info->num_psf_gv_points;
220
221 if (DISPLAY_VER(dev_priv) >= 14) {
222 switch (dram_info->type) {
223 case INTEL_DRAM_DDR4:
224 qi->t_bl = 4;
225 qi->max_numchannels = 2;
226 qi->channel_width = 64;
227 qi->deinterleave = 2;
228 break;
229 case INTEL_DRAM_DDR5:
230 qi->t_bl = 8;
231 qi->max_numchannels = 4;
232 qi->channel_width = 32;
233 qi->deinterleave = 2;
234 break;
235 case INTEL_DRAM_LPDDR4:
236 case INTEL_DRAM_LPDDR5:
237 qi->t_bl = 16;
238 qi->max_numchannels = 8;
239 qi->channel_width = 16;
240 qi->deinterleave = 4;
241 break;
242 default:
243 MISSING_CASE(dram_info->type);
244 return -EINVAL;
245 }
246 } else if (DISPLAY_VER(dev_priv) >= 12) {
247 switch (dram_info->type) {
248 case INTEL_DRAM_DDR4:
249 qi->t_bl = is_y_tile ? 8 : 4;
250 qi->max_numchannels = 2;
251 qi->channel_width = 64;
252 qi->deinterleave = is_y_tile ? 1 : 2;
253 break;
254 case INTEL_DRAM_DDR5:
255 qi->t_bl = is_y_tile ? 16 : 8;
256 qi->max_numchannels = 4;
257 qi->channel_width = 32;
258 qi->deinterleave = is_y_tile ? 1 : 2;
259 break;
260 case INTEL_DRAM_LPDDR4:
261 if (IS_ROCKETLAKE(dev_priv)) {
262 qi->t_bl = 8;
263 qi->max_numchannels = 4;
264 qi->channel_width = 32;
265 qi->deinterleave = 2;
266 break;
267 }
268 fallthrough;
269 case INTEL_DRAM_LPDDR5:
270 qi->t_bl = 16;
271 qi->max_numchannels = 8;
272 qi->channel_width = 16;
273 qi->deinterleave = is_y_tile ? 2 : 4;
274 break;
275 default:
276 qi->t_bl = 16;
277 qi->max_numchannels = 1;
278 break;
279 }
280 } else if (DISPLAY_VER(dev_priv) == 11) {
281 qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
282 qi->max_numchannels = 1;
283 }
284
285 if (drm_WARN_ON(&dev_priv->drm,
286 qi->num_points > ARRAY_SIZE(qi->points)))
287 qi->num_points = ARRAY_SIZE(qi->points);
288
289 for (i = 0; i < qi->num_points; i++) {
290 struct intel_qgv_point *sp = &qi->points[i];
291
292 ret = intel_read_qgv_point_info(dev_priv, sp, i);
293 if (ret)
294 return ret;
295
296 drm_dbg_kms(&dev_priv->drm,
297 "QGV %d: DCLK=%d tRP=%d tRDPRE=%d tRAS=%d tRCD=%d tRC=%d\n",
298 i, sp->dclk, sp->t_rp, sp->t_rdpre, sp->t_ras,
299 sp->t_rcd, sp->t_rc);
300 }
301
302 if (qi->num_psf_points > 0) {
303 ret = adls_pcode_read_psf_gv_point_info(dev_priv, qi->psf_points);
304 if (ret) {
305 drm_err(&dev_priv->drm, "Failed to read PSF point data; PSF points will not be considered in bandwidth calculations.\n");
306 qi->num_psf_points = 0;
307 }
308
309 for (i = 0; i < qi->num_psf_points; i++)
310 drm_dbg_kms(&dev_priv->drm,
311 "PSF GV %d: CLK=%d \n",
312 i, qi->psf_points[i].clk);
313 }
314
315 return 0;
316}
317
318static int adl_calc_psf_bw(int clk)
319{
320 /*
321 * clk is multiples of 16.666MHz (100/6)
322 * According to BSpec PSF GV bandwidth is
323 * calculated as BW = 64 * clk * 16.666Mhz
324 */
325 return DIV_ROUND_CLOSEST(64 * clk * 100, 6);
326}
327
328static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
329{
330 u16 dclk = 0;
331 int i;
332
333 for (i = 0; i < qi->num_points; i++)
334 dclk = max(dclk, qi->points[i].dclk);
335
336 return dclk;
337}
338
339struct intel_sa_info {
340 u16 displayrtids;
341 u8 deburst, deprogbwlimit, derating;
342};
343
344static const struct intel_sa_info icl_sa_info = {
345 .deburst = 8,
346 .deprogbwlimit = 25, /* GB/s */
347 .displayrtids = 128,
348 .derating = 10,
349};
350
351static const struct intel_sa_info tgl_sa_info = {
352 .deburst = 16,
353 .deprogbwlimit = 34, /* GB/s */
354 .displayrtids = 256,
355 .derating = 10,
356};
357
358static const struct intel_sa_info rkl_sa_info = {
359 .deburst = 8,
360 .deprogbwlimit = 20, /* GB/s */
361 .displayrtids = 128,
362 .derating = 10,
363};
364
365static const struct intel_sa_info adls_sa_info = {
366 .deburst = 16,
367 .deprogbwlimit = 38, /* GB/s */
368 .displayrtids = 256,
369 .derating = 10,
370};
371
372static const struct intel_sa_info adlp_sa_info = {
373 .deburst = 16,
374 .deprogbwlimit = 38, /* GB/s */
375 .displayrtids = 256,
376 .derating = 20,
377};
378
379static const struct intel_sa_info mtl_sa_info = {
380 .deburst = 32,
381 .deprogbwlimit = 38, /* GB/s */
382 .displayrtids = 256,
383 .derating = 10,
384};
385
386static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
387{
388 struct intel_qgv_info qi = {};
389 bool is_y_tile = true; /* assume y tile may be used */
390 int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels);
391 int ipqdepth, ipqdepthpch = 16;
392 int dclk_max;
393 int maxdebw;
394 int num_groups = ARRAY_SIZE(dev_priv->display.bw.max);
395 int i, ret;
396
397 ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile);
398 if (ret) {
399 drm_dbg_kms(&dev_priv->drm,
400 "Failed to get memory subsystem information, ignoring bandwidth limits");
401 return ret;
402 }
403
404 dclk_max = icl_sagv_max_dclk(&qi);
405 maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
406 ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
407 qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
408
409 for (i = 0; i < num_groups; i++) {
410 struct intel_bw_info *bi = &dev_priv->display.bw.max[i];
411 int clpchgroup;
412 int j;
413
414 clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
415 bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
416
417 bi->num_qgv_points = qi.num_points;
418 bi->num_psf_gv_points = qi.num_psf_points;
419
420 for (j = 0; j < qi.num_points; j++) {
421 const struct intel_qgv_point *sp = &qi.points[j];
422 int ct, bw;
423
424 /*
425 * Max row cycle time
426 *
427 * FIXME what is the logic behind the
428 * assumed burst length?
429 */
430 ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd +
431 (clpchgroup - 1) * qi.t_bl + sp->t_rdpre);
432 bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
433
434 bi->deratedbw[j] = min(maxdebw,
435 bw * (100 - sa->derating) / 100);
436
437 drm_dbg_kms(&dev_priv->drm,
438 "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
439 i, j, bi->num_planes, bi->deratedbw[j]);
440 }
441 }
442 /*
443 * In case if SAGV is disabled in BIOS, we always get 1
444 * SAGV point, but we can't send PCode commands to restrict it
445 * as it will fail and pointless anyway.
446 */
447 if (qi.num_points == 1)
448 dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
449 else
450 dev_priv->display.sagv.status = I915_SAGV_ENABLED;
451
452 return 0;
453}
454
455static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
456{
457 struct intel_qgv_info qi = {};
458 const struct dram_info *dram_info = &dev_priv->dram_info;
459 bool is_y_tile = true; /* assume y tile may be used */
460 int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels);
461 int ipqdepth, ipqdepthpch = 16;
462 int dclk_max;
463 int maxdebw, peakbw;
464 int clperchgroup;
465 int num_groups = ARRAY_SIZE(dev_priv->display.bw.max);
466 int i, ret;
467
468 ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile);
469 if (ret) {
470 drm_dbg_kms(&dev_priv->drm,
471 "Failed to get memory subsystem information, ignoring bandwidth limits");
472 return ret;
473 }
474
475 if (DISPLAY_VER(dev_priv) < 14 &&
476 (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == INTEL_DRAM_LPDDR5))
477 num_channels *= 2;
478
479 qi.deinterleave = qi.deinterleave ? : DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
480
481 if (num_channels < qi.max_numchannels && DISPLAY_VER(dev_priv) >= 12)
482 qi.deinterleave = max(DIV_ROUND_UP(qi.deinterleave, 2), 1);
483
484 if (DISPLAY_VER(dev_priv) >= 12 && num_channels > qi.max_numchannels)
485 drm_warn(&dev_priv->drm, "Number of channels exceeds max number of channels.");
486 if (qi.max_numchannels != 0)
487 num_channels = min_t(u8, num_channels, qi.max_numchannels);
488
489 dclk_max = icl_sagv_max_dclk(&qi);
490
491 peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
492 maxdebw = min(sa->deprogbwlimit * 1000, peakbw * 6 / 10); /* 60% */
493
494 ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
495 /*
496 * clperchgroup = 4kpagespermempage * clperchperblock,
497 * clperchperblock = 8 / num_channels * interleave
498 */
499 clperchgroup = 4 * DIV_ROUND_UP(8, num_channels) * qi.deinterleave;
500
501 for (i = 0; i < num_groups; i++) {
502 struct intel_bw_info *bi = &dev_priv->display.bw.max[i];
503 struct intel_bw_info *bi_next;
504 int clpchgroup;
505 int j;
506
507 clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
508
509 if (i < num_groups - 1) {
510 bi_next = &dev_priv->display.bw.max[i + 1];
511
512 if (clpchgroup < clperchgroup)
513 bi_next->num_planes = (ipqdepth - clpchgroup) /
514 clpchgroup + 1;
515 else
516 bi_next->num_planes = 0;
517 }
518
519 bi->num_qgv_points = qi.num_points;
520 bi->num_psf_gv_points = qi.num_psf_points;
521
522 for (j = 0; j < qi.num_points; j++) {
523 const struct intel_qgv_point *sp = &qi.points[j];
524 int ct, bw;
525
526 /*
527 * Max row cycle time
528 *
529 * FIXME what is the logic behind the
530 * assumed burst length?
531 */
532 ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd +
533 (clpchgroup - 1) * qi.t_bl + sp->t_rdpre);
534 bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
535
536 bi->deratedbw[j] = min(maxdebw,
537 bw * (100 - sa->derating) / 100);
538 bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk *
539 num_channels *
540 qi.channel_width, 8);
541
542 drm_dbg_kms(&dev_priv->drm,
543 "BW%d / QGV %d: num_planes=%d deratedbw=%u peakbw: %u\n",
544 i, j, bi->num_planes, bi->deratedbw[j],
545 bi->peakbw[j]);
546 }
547
548 for (j = 0; j < qi.num_psf_points; j++) {
549 const struct intel_psf_gv_point *sp = &qi.psf_points[j];
550
551 bi->psf_bw[j] = adl_calc_psf_bw(sp->clk);
552
553 drm_dbg_kms(&dev_priv->drm,
554 "BW%d / PSF GV %d: num_planes=%d bw=%u\n",
555 i, j, bi->num_planes, bi->psf_bw[j]);
556 }
557 }
558
559 /*
560 * In case if SAGV is disabled in BIOS, we always get 1
561 * SAGV point, but we can't send PCode commands to restrict it
562 * as it will fail and pointless anyway.
563 */
564 if (qi.num_points == 1)
565 dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
566 else
567 dev_priv->display.sagv.status = I915_SAGV_ENABLED;
568
569 return 0;
570}
571
572static void dg2_get_bw_info(struct drm_i915_private *i915)
573{
574 unsigned int deratedbw = IS_DG2_G11(i915) ? 38000 : 50000;
575 int num_groups = ARRAY_SIZE(i915->display.bw.max);
576 int i;
577
578 /*
579 * DG2 doesn't have SAGV or QGV points, just a constant max bandwidth
580 * that doesn't depend on the number of planes enabled. So fill all the
581 * plane group with constant bw information for uniformity with other
582 * platforms. DG2-G10 platforms have a constant 50 GB/s bandwidth,
583 * whereas DG2-G11 platforms have 38 GB/s.
584 */
585 for (i = 0; i < num_groups; i++) {
586 struct intel_bw_info *bi = &i915->display.bw.max[i];
587
588 bi->num_planes = 1;
589 /* Need only one dummy QGV point per group */
590 bi->num_qgv_points = 1;
591 bi->deratedbw[0] = deratedbw;
592 }
593
594 i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
595}
596
597static unsigned int icl_max_bw_index(struct drm_i915_private *dev_priv,
598 int num_planes, int qgv_point)
599{
600 int i;
601
602 /*
603 * Let's return max bw for 0 planes
604 */
605 num_planes = max(1, num_planes);
606
607 for (i = 0; i < ARRAY_SIZE(dev_priv->display.bw.max); i++) {
608 const struct intel_bw_info *bi =
609 &dev_priv->display.bw.max[i];
610
611 /*
612 * Pcode will not expose all QGV points when
613 * SAGV is forced to off/min/med/max.
614 */
615 if (qgv_point >= bi->num_qgv_points)
616 return UINT_MAX;
617
618 if (num_planes >= bi->num_planes)
619 return i;
620 }
621
622 return UINT_MAX;
623}
624
625static unsigned int tgl_max_bw_index(struct drm_i915_private *dev_priv,
626 int num_planes, int qgv_point)
627{
628 int i;
629
630 /*
631 * Let's return max bw for 0 planes
632 */
633 num_planes = max(1, num_planes);
634
635 for (i = ARRAY_SIZE(dev_priv->display.bw.max) - 1; i >= 0; i--) {
636 const struct intel_bw_info *bi =
637 &dev_priv->display.bw.max[i];
638
639 /*
640 * Pcode will not expose all QGV points when
641 * SAGV is forced to off/min/med/max.
642 */
643 if (qgv_point >= bi->num_qgv_points)
644 return UINT_MAX;
645
646 if (num_planes <= bi->num_planes)
647 return i;
648 }
649
650 return 0;
651}
652
653static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv,
654 int psf_gv_point)
655{
656 const struct intel_bw_info *bi =
657 &dev_priv->display.bw.max[0];
658
659 return bi->psf_bw[psf_gv_point];
660}
661
662void intel_bw_init_hw(struct drm_i915_private *dev_priv)
663{
664 if (!HAS_DISPLAY(dev_priv))
665 return;
666
667 if (DISPLAY_VER(dev_priv) >= 14)
668 tgl_get_bw_info(dev_priv, &mtl_sa_info);
669 else if (IS_DG2(dev_priv))
670 dg2_get_bw_info(dev_priv);
671 else if (IS_ALDERLAKE_P(dev_priv))
672 tgl_get_bw_info(dev_priv, &adlp_sa_info);
673 else if (IS_ALDERLAKE_S(dev_priv))
674 tgl_get_bw_info(dev_priv, &adls_sa_info);
675 else if (IS_ROCKETLAKE(dev_priv))
676 tgl_get_bw_info(dev_priv, &rkl_sa_info);
677 else if (DISPLAY_VER(dev_priv) == 12)
678 tgl_get_bw_info(dev_priv, &tgl_sa_info);
679 else if (DISPLAY_VER(dev_priv) == 11)
680 icl_get_bw_info(dev_priv, &icl_sa_info);
681}
682
683static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
684{
685 /*
686 * We assume cursors are small enough
687 * to not not cause bandwidth problems.
688 */
689 return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR));
690}
691
692static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state)
693{
694 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
695 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
696 unsigned int data_rate = 0;
697 enum plane_id plane_id;
698
699 for_each_plane_id_on_crtc(crtc, plane_id) {
700 /*
701 * We assume cursors are small enough
702 * to not not cause bandwidth problems.
703 */
704 if (plane_id == PLANE_CURSOR)
705 continue;
706
707 data_rate += crtc_state->data_rate[plane_id];
708
709 if (DISPLAY_VER(i915) < 11)
710 data_rate += crtc_state->data_rate_y[plane_id];
711 }
712
713 return data_rate;
714}
715
716/* "Maximum Pipe Read Bandwidth" */
717static int intel_bw_crtc_min_cdclk(const struct intel_crtc_state *crtc_state)
718{
719 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
720 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
721
722 if (DISPLAY_VER(i915) < 12)
723 return 0;
724
725 return DIV_ROUND_UP_ULL(mul_u32_u32(intel_bw_crtc_data_rate(crtc_state), 10), 512);
726}
727
728void intel_bw_crtc_update(struct intel_bw_state *bw_state,
729 const struct intel_crtc_state *crtc_state)
730{
731 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
732 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
733
734 bw_state->data_rate[crtc->pipe] =
735 intel_bw_crtc_data_rate(crtc_state);
736 bw_state->num_active_planes[crtc->pipe] =
737 intel_bw_crtc_num_active_planes(crtc_state);
738
739 drm_dbg_kms(&i915->drm, "pipe %c data rate %u num active planes %u\n",
740 pipe_name(crtc->pipe),
741 bw_state->data_rate[crtc->pipe],
742 bw_state->num_active_planes[crtc->pipe]);
743}
744
745static unsigned int intel_bw_num_active_planes(struct drm_i915_private *dev_priv,
746 const struct intel_bw_state *bw_state)
747{
748 unsigned int num_active_planes = 0;
749 enum pipe pipe;
750
751 for_each_pipe(dev_priv, pipe)
752 num_active_planes += bw_state->num_active_planes[pipe];
753
754 return num_active_planes;
755}
756
757static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
758 const struct intel_bw_state *bw_state)
759{
760 unsigned int data_rate = 0;
761 enum pipe pipe;
762
763 for_each_pipe(dev_priv, pipe)
764 data_rate += bw_state->data_rate[pipe];
765
766 if (DISPLAY_VER(dev_priv) >= 13 && i915_vtd_active(dev_priv))
767 data_rate = DIV_ROUND_UP(data_rate * 105, 100);
768
769 return data_rate;
770}
771
772struct intel_bw_state *
773intel_atomic_get_old_bw_state(struct intel_atomic_state *state)
774{
775 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
776 struct intel_global_state *bw_state;
777
778 bw_state = intel_atomic_get_old_global_obj_state(state, &dev_priv->display.bw.obj);
779
780 return to_intel_bw_state(bw_state);
781}
782
783struct intel_bw_state *
784intel_atomic_get_new_bw_state(struct intel_atomic_state *state)
785{
786 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
787 struct intel_global_state *bw_state;
788
789 bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->display.bw.obj);
790
791 return to_intel_bw_state(bw_state);
792}
793
794struct intel_bw_state *
795intel_atomic_get_bw_state(struct intel_atomic_state *state)
796{
797 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
798 struct intel_global_state *bw_state;
799
800 bw_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.bw.obj);
801 if (IS_ERR(bw_state))
802 return ERR_CAST(bw_state);
803
804 return to_intel_bw_state(bw_state);
805}
806
807static int mtl_find_qgv_points(struct drm_i915_private *i915,
808 unsigned int data_rate,
809 unsigned int num_active_planes,
810 struct intel_bw_state *new_bw_state)
811{
812 unsigned int best_rate = UINT_MAX;
813 unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
814 unsigned int qgv_peak_bw = 0;
815 int i;
816 int ret;
817
818 ret = intel_atomic_lock_global_state(&new_bw_state->base);
819 if (ret)
820 return ret;
821
822 /*
823 * If SAGV cannot be enabled, disable the pcode SAGV by passing all 1's
824 * for qgv peak bw in PM Demand request. So assign UINT_MAX if SAGV is
825 * not enabled. PM Demand code will clamp the value for the register
826 */
827 if (!intel_can_enable_sagv(i915, new_bw_state)) {
828 new_bw_state->qgv_point_peakbw = U16_MAX;
829 drm_dbg_kms(&i915->drm, "No SAGV, use UINT_MAX as peak bw.");
830 return 0;
831 }
832
833 /*
834 * Find the best QGV point by comparing the data_rate with max data rate
835 * offered per plane group
836 */
837 for (i = 0; i < num_qgv_points; i++) {
838 unsigned int bw_index =
839 tgl_max_bw_index(i915, num_active_planes, i);
840 unsigned int max_data_rate;
841
842 if (bw_index >= ARRAY_SIZE(i915->display.bw.max))
843 continue;
844
845 max_data_rate = i915->display.bw.max[bw_index].deratedbw[i];
846
847 if (max_data_rate < data_rate)
848 continue;
849
850 if (max_data_rate - data_rate < best_rate) {
851 best_rate = max_data_rate - data_rate;
852 qgv_peak_bw = i915->display.bw.max[bw_index].peakbw[i];
853 }
854
855 drm_dbg_kms(&i915->drm, "QGV point %d: max bw %d required %d qgv_peak_bw: %d\n",
856 i, max_data_rate, data_rate, qgv_peak_bw);
857 }
858
859 drm_dbg_kms(&i915->drm, "Matching peaks QGV bw: %d for required data rate: %d\n",
860 qgv_peak_bw, data_rate);
861
862 /*
863 * The display configuration cannot be supported if no QGV point
864 * satisfying the required data rate is found
865 */
866 if (qgv_peak_bw == 0) {
867 drm_dbg_kms(&i915->drm, "No QGV points for bw %d for display configuration(%d active planes).\n",
868 data_rate, num_active_planes);
869 return -EINVAL;
870 }
871
872 /* MTL PM DEMAND expects QGV BW parameter in multiples of 100 mbps */
873 new_bw_state->qgv_point_peakbw = DIV_ROUND_CLOSEST(qgv_peak_bw, 100);
874
875 return 0;
876}
877
878static int icl_find_qgv_points(struct drm_i915_private *i915,
879 unsigned int data_rate,
880 unsigned int num_active_planes,
881 const struct intel_bw_state *old_bw_state,
882 struct intel_bw_state *new_bw_state)
883{
884 unsigned int max_bw_point = 0;
885 unsigned int max_bw = 0;
886 unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
887 unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
888 u16 psf_points = 0;
889 u16 qgv_points = 0;
890 int i;
891 int ret;
892
893 ret = intel_atomic_lock_global_state(&new_bw_state->base);
894 if (ret)
895 return ret;
896
897 for (i = 0; i < num_qgv_points; i++) {
898 unsigned int idx;
899 unsigned int max_data_rate;
900
901 if (DISPLAY_VER(i915) >= 12)
902 idx = tgl_max_bw_index(i915, num_active_planes, i);
903 else
904 idx = icl_max_bw_index(i915, num_active_planes, i);
905
906 if (idx >= ARRAY_SIZE(i915->display.bw.max))
907 continue;
908
909 max_data_rate = i915->display.bw.max[idx].deratedbw[i];
910
911 /*
912 * We need to know which qgv point gives us
913 * maximum bandwidth in order to disable SAGV
914 * if we find that we exceed SAGV block time
915 * with watermarks. By that moment we already
916 * have those, as it is calculated earlier in
917 * intel_atomic_check,
918 */
919 if (max_data_rate > max_bw) {
920 max_bw_point = i;
921 max_bw = max_data_rate;
922 }
923 if (max_data_rate >= data_rate)
924 qgv_points |= BIT(i);
925
926 drm_dbg_kms(&i915->drm, "QGV point %d: max bw %d required %d\n",
927 i, max_data_rate, data_rate);
928 }
929
930 for (i = 0; i < num_psf_gv_points; i++) {
931 unsigned int max_data_rate = adl_psf_bw(i915, i);
932
933 if (max_data_rate >= data_rate)
934 psf_points |= BIT(i);
935
936 drm_dbg_kms(&i915->drm, "PSF GV point %d: max bw %d"
937 " required %d\n",
938 i, max_data_rate, data_rate);
939 }
940
941 /*
942 * BSpec states that we always should have at least one allowed point
943 * left, so if we couldn't - simply reject the configuration for obvious
944 * reasons.
945 */
946 if (qgv_points == 0) {
947 drm_dbg_kms(&i915->drm, "No QGV points provide sufficient memory"
948 " bandwidth %d for display configuration(%d active planes).\n",
949 data_rate, num_active_planes);
950 return -EINVAL;
951 }
952
953 if (num_psf_gv_points > 0 && psf_points == 0) {
954 drm_dbg_kms(&i915->drm, "No PSF GV points provide sufficient memory"
955 " bandwidth %d for display configuration(%d active planes).\n",
956 data_rate, num_active_planes);
957 return -EINVAL;
958 }
959
960 /*
961 * Leave only single point with highest bandwidth, if
962 * we can't enable SAGV due to the increased memory latency it may
963 * cause.
964 */
965 if (!intel_can_enable_sagv(i915, new_bw_state)) {
966 qgv_points = BIT(max_bw_point);
967 drm_dbg_kms(&i915->drm, "No SAGV, using single QGV point %d\n",
968 max_bw_point);
969 }
970
971 /*
972 * We store the ones which need to be masked as that is what PCode
973 * actually accepts as a parameter.
974 */
975 new_bw_state->qgv_points_mask =
976 ~(ICL_PCODE_REQ_QGV_PT(qgv_points) |
977 ADLS_PCODE_REQ_PSF_PT(psf_points)) &
978 icl_qgv_points_mask(i915);
979
980 /*
981 * If the actual mask had changed we need to make sure that
982 * the commits are serialized(in case this is a nomodeset, nonblocking)
983 */
984 if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
985 ret = intel_atomic_serialize_global_state(&new_bw_state->base);
986 if (ret)
987 return ret;
988 }
989
990 return 0;
991}
992
993static int intel_bw_check_qgv_points(struct drm_i915_private *i915,
994 const struct intel_bw_state *old_bw_state,
995 struct intel_bw_state *new_bw_state)
996{
997 unsigned int data_rate = intel_bw_data_rate(i915, new_bw_state);
998 unsigned int num_active_planes =
999 intel_bw_num_active_planes(i915, new_bw_state);
1000
1001 data_rate = DIV_ROUND_UP(data_rate, 1000);
1002
1003 if (DISPLAY_VER(i915) >= 14)
1004 return mtl_find_qgv_points(i915, data_rate, num_active_planes,
1005 new_bw_state);
1006 else
1007 return icl_find_qgv_points(i915, data_rate, num_active_planes,
1008 old_bw_state, new_bw_state);
1009}
1010
1011static bool intel_bw_state_changed(struct drm_i915_private *i915,
1012 const struct intel_bw_state *old_bw_state,
1013 const struct intel_bw_state *new_bw_state)
1014{
1015 enum pipe pipe;
1016
1017 for_each_pipe(i915, pipe) {
1018 const struct intel_dbuf_bw *old_crtc_bw =
1019 &old_bw_state->dbuf_bw[pipe];
1020 const struct intel_dbuf_bw *new_crtc_bw =
1021 &new_bw_state->dbuf_bw[pipe];
1022 enum dbuf_slice slice;
1023
1024 for_each_dbuf_slice(i915, slice) {
1025 if (old_crtc_bw->max_bw[slice] != new_crtc_bw->max_bw[slice] ||
1026 old_crtc_bw->active_planes[slice] != new_crtc_bw->active_planes[slice])
1027 return true;
1028 }
1029
1030 if (old_bw_state->min_cdclk[pipe] != new_bw_state->min_cdclk[pipe])
1031 return true;
1032 }
1033
1034 return false;
1035}
1036
1037static void skl_plane_calc_dbuf_bw(struct intel_bw_state *bw_state,
1038 struct intel_crtc *crtc,
1039 enum plane_id plane_id,
1040 const struct skl_ddb_entry *ddb,
1041 unsigned int data_rate)
1042{
1043 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1044 struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
1045 unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
1046 enum dbuf_slice slice;
1047
1048 /*
1049 * The arbiter can only really guarantee an
1050 * equal share of the total bw to each plane.
1051 */
1052 for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask) {
1053 crtc_bw->max_bw[slice] = max(crtc_bw->max_bw[slice], data_rate);
1054 crtc_bw->active_planes[slice] |= BIT(plane_id);
1055 }
1056}
1057
1058static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
1059 const struct intel_crtc_state *crtc_state)
1060{
1061 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1062 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1063 struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
1064 enum plane_id plane_id;
1065
1066 memset(crtc_bw, 0, sizeof(*crtc_bw));
1067
1068 if (!crtc_state->hw.active)
1069 return;
1070
1071 for_each_plane_id_on_crtc(crtc, plane_id) {
1072 /*
1073 * We assume cursors are small enough
1074 * to not cause bandwidth problems.
1075 */
1076 if (plane_id == PLANE_CURSOR)
1077 continue;
1078
1079 skl_plane_calc_dbuf_bw(bw_state, crtc, plane_id,
1080 &crtc_state->wm.skl.plane_ddb[plane_id],
1081 crtc_state->data_rate[plane_id]);
1082
1083 if (DISPLAY_VER(i915) < 11)
1084 skl_plane_calc_dbuf_bw(bw_state, crtc, plane_id,
1085 &crtc_state->wm.skl.plane_ddb_y[plane_id],
1086 crtc_state->data_rate[plane_id]);
1087 }
1088}
1089
1090/* "Maximum Data Buffer Bandwidth" */
1091static int
1092intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915,
1093 const struct intel_bw_state *bw_state)
1094{
1095 unsigned int total_max_bw = 0;
1096 enum dbuf_slice slice;
1097
1098 for_each_dbuf_slice(i915, slice) {
1099 int num_active_planes = 0;
1100 unsigned int max_bw = 0;
1101 enum pipe pipe;
1102
1103 /*
1104 * The arbiter can only really guarantee an
1105 * equal share of the total bw to each plane.
1106 */
1107 for_each_pipe(i915, pipe) {
1108 const struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[pipe];
1109
1110 max_bw = max(crtc_bw->max_bw[slice], max_bw);
1111 num_active_planes += hweight8(crtc_bw->active_planes[slice]);
1112 }
1113 max_bw *= num_active_planes;
1114
1115 total_max_bw = max(total_max_bw, max_bw);
1116 }
1117
1118 return DIV_ROUND_UP(total_max_bw, 64);
1119}
1120
1121int intel_bw_min_cdclk(struct drm_i915_private *i915,
1122 const struct intel_bw_state *bw_state)
1123{
1124 enum pipe pipe;
1125 int min_cdclk;
1126
1127 min_cdclk = intel_bw_dbuf_min_cdclk(i915, bw_state);
1128
1129 for_each_pipe(i915, pipe)
1130 min_cdclk = max(bw_state->min_cdclk[pipe], min_cdclk);
1131
1132 return min_cdclk;
1133}
1134
1135int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
1136 bool *need_cdclk_calc)
1137{
1138 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1139 struct intel_bw_state *new_bw_state = NULL;
1140 const struct intel_bw_state *old_bw_state = NULL;
1141 const struct intel_cdclk_state *cdclk_state;
1142 const struct intel_crtc_state *crtc_state;
1143 int old_min_cdclk, new_min_cdclk;
1144 struct intel_crtc *crtc;
1145 int i;
1146
1147 if (DISPLAY_VER(dev_priv) < 9)
1148 return 0;
1149
1150 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
1151 new_bw_state = intel_atomic_get_bw_state(state);
1152 if (IS_ERR(new_bw_state))
1153 return PTR_ERR(new_bw_state);
1154
1155 old_bw_state = intel_atomic_get_old_bw_state(state);
1156
1157 skl_crtc_calc_dbuf_bw(new_bw_state, crtc_state);
1158
1159 new_bw_state->min_cdclk[crtc->pipe] =
1160 intel_bw_crtc_min_cdclk(crtc_state);
1161 }
1162
1163 if (!old_bw_state)
1164 return 0;
1165
1166 if (intel_bw_state_changed(dev_priv, old_bw_state, new_bw_state)) {
1167 int ret = intel_atomic_lock_global_state(&new_bw_state->base);
1168 if (ret)
1169 return ret;
1170 }
1171
1172 old_min_cdclk = intel_bw_min_cdclk(dev_priv, old_bw_state);
1173 new_min_cdclk = intel_bw_min_cdclk(dev_priv, new_bw_state);
1174
1175 /*
1176 * No need to check against the cdclk state if
1177 * the min cdclk doesn't increase.
1178 *
1179 * Ie. we only ever increase the cdclk due to bandwidth
1180 * requirements. This can reduce back and forth
1181 * display blinking due to constant cdclk changes.
1182 */
1183 if (new_min_cdclk <= old_min_cdclk)
1184 return 0;
1185
1186 cdclk_state = intel_atomic_get_cdclk_state(state);
1187 if (IS_ERR(cdclk_state))
1188 return PTR_ERR(cdclk_state);
1189
1190 /*
1191 * No need to recalculate the cdclk state if
1192 * the min cdclk doesn't increase.
1193 *
1194 * Ie. we only ever increase the cdclk due to bandwidth
1195 * requirements. This can reduce back and forth
1196 * display blinking due to constant cdclk changes.
1197 */
1198 if (new_min_cdclk <= cdclk_state->bw_min_cdclk)
1199 return 0;
1200
1201 drm_dbg_kms(&dev_priv->drm,
1202 "new bandwidth min cdclk (%d kHz) > old min cdclk (%d kHz)\n",
1203 new_min_cdclk, cdclk_state->bw_min_cdclk);
1204 *need_cdclk_calc = true;
1205
1206 return 0;
1207}
1208
1209static int intel_bw_check_data_rate(struct intel_atomic_state *state, bool *changed)
1210{
1211 struct drm_i915_private *i915 = to_i915(state->base.dev);
1212 const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
1213 struct intel_crtc *crtc;
1214 int i;
1215
1216 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
1217 new_crtc_state, i) {
1218 unsigned int old_data_rate =
1219 intel_bw_crtc_data_rate(old_crtc_state);
1220 unsigned int new_data_rate =
1221 intel_bw_crtc_data_rate(new_crtc_state);
1222 unsigned int old_active_planes =
1223 intel_bw_crtc_num_active_planes(old_crtc_state);
1224 unsigned int new_active_planes =
1225 intel_bw_crtc_num_active_planes(new_crtc_state);
1226 struct intel_bw_state *new_bw_state;
1227
1228 /*
1229 * Avoid locking the bw state when
1230 * nothing significant has changed.
1231 */
1232 if (old_data_rate == new_data_rate &&
1233 old_active_planes == new_active_planes)
1234 continue;
1235
1236 new_bw_state = intel_atomic_get_bw_state(state);
1237 if (IS_ERR(new_bw_state))
1238 return PTR_ERR(new_bw_state);
1239
1240 new_bw_state->data_rate[crtc->pipe] = new_data_rate;
1241 new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
1242
1243 *changed = true;
1244
1245 drm_dbg_kms(&i915->drm,
1246 "[CRTC:%d:%s] data rate %u num active planes %u\n",
1247 crtc->base.base.id, crtc->base.name,
1248 new_bw_state->data_rate[crtc->pipe],
1249 new_bw_state->num_active_planes[crtc->pipe]);
1250 }
1251
1252 return 0;
1253}
1254
1255int intel_bw_atomic_check(struct intel_atomic_state *state)
1256{
1257 bool changed = false;
1258 struct drm_i915_private *i915 = to_i915(state->base.dev);
1259 struct intel_bw_state *new_bw_state;
1260 const struct intel_bw_state *old_bw_state;
1261 int ret;
1262
1263 /* FIXME earlier gens need some checks too */
1264 if (DISPLAY_VER(i915) < 11)
1265 return 0;
1266
1267 ret = intel_bw_check_data_rate(state, &changed);
1268 if (ret)
1269 return ret;
1270
1271 old_bw_state = intel_atomic_get_old_bw_state(state);
1272 new_bw_state = intel_atomic_get_new_bw_state(state);
1273
1274 if (new_bw_state &&
1275 intel_can_enable_sagv(i915, old_bw_state) !=
1276 intel_can_enable_sagv(i915, new_bw_state))
1277 changed = true;
1278
1279 /*
1280 * If none of our inputs (data rates, number of active
1281 * planes, SAGV yes/no) changed then nothing to do here.
1282 */
1283 if (!changed)
1284 return 0;
1285
1286 ret = intel_bw_check_qgv_points(i915, old_bw_state, new_bw_state);
1287 if (ret)
1288 return ret;
1289
1290 return 0;
1291}
1292
1293static struct intel_global_state *
1294intel_bw_duplicate_state(struct intel_global_obj *obj)
1295{
1296 struct intel_bw_state *state;
1297
1298 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
1299 if (!state)
1300 return NULL;
1301
1302 return &state->base;
1303}
1304
1305static void intel_bw_destroy_state(struct intel_global_obj *obj,
1306 struct intel_global_state *state)
1307{
1308 kfree(state);
1309}
1310
1311static const struct intel_global_state_funcs intel_bw_funcs = {
1312 .atomic_duplicate_state = intel_bw_duplicate_state,
1313 .atomic_destroy_state = intel_bw_destroy_state,
1314};
1315
1316int intel_bw_init(struct drm_i915_private *dev_priv)
1317{
1318 struct intel_bw_state *state;
1319
1320 state = kzalloc(sizeof(*state), GFP_KERNEL);
1321 if (!state)
1322 return -ENOMEM;
1323
1324 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.bw.obj,
1325 &state->base, &intel_bw_funcs);
1326
1327 return 0;
1328}
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2019 Intel Corporation
4 */
5
6#include <drm/drm_atomic_state_helper.h>
7
8#include "i915_drv.h"
9#include "i915_reg.h"
10#include "i915_utils.h"
11#include "intel_atomic.h"
12#include "intel_bw.h"
13#include "intel_cdclk.h"
14#include "intel_display_core.h"
15#include "intel_display_types.h"
16#include "skl_watermark.h"
17#include "intel_mchbar_regs.h"
18#include "intel_pcode.h"
19
20/* Parameters for Qclk Geyserville (QGV) */
21struct intel_qgv_point {
22 u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
23};
24
25struct intel_psf_gv_point {
26 u8 clk; /* clock in multiples of 16.6666 MHz */
27};
28
29struct intel_qgv_info {
30 struct intel_qgv_point points[I915_NUM_QGV_POINTS];
31 struct intel_psf_gv_point psf_points[I915_NUM_PSF_GV_POINTS];
32 u8 num_points;
33 u8 num_psf_points;
34 u8 t_bl;
35 u8 max_numchannels;
36 u8 channel_width;
37 u8 deinterleave;
38};
39
40static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
41 struct intel_qgv_point *sp,
42 int point)
43{
44 u32 dclk_ratio, dclk_reference;
45 u32 val;
46
47 val = intel_uncore_read(&dev_priv->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC);
48 dclk_ratio = REG_FIELD_GET(DG1_QCLK_RATIO_MASK, val);
49 if (val & DG1_QCLK_REFERENCE)
50 dclk_reference = 6; /* 6 * 16.666 MHz = 100 MHz */
51 else
52 dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */
53 sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + 500, 1000);
54
55 val = intel_uncore_read(&dev_priv->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
56 if (val & DG1_GEAR_TYPE)
57 sp->dclk *= 2;
58
59 if (sp->dclk == 0)
60 return -EINVAL;
61
62 val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
63 sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val);
64 sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val);
65
66 val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH);
67 sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val);
68 sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val);
69
70 sp->t_rc = sp->t_rp + sp->t_ras;
71
72 return 0;
73}
74
75static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
76 struct intel_qgv_point *sp,
77 int point)
78{
79 u32 val = 0, val2 = 0;
80 u16 dclk;
81 int ret;
82
83 ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
84 ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
85 &val, &val2);
86 if (ret)
87 return ret;
88
89 dclk = val & 0xffff;
90 sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) > 11 ? 500 : 0), 1000);
91 sp->t_rp = (val & 0xff0000) >> 16;
92 sp->t_rcd = (val & 0xff000000) >> 24;
93
94 sp->t_rdpre = val2 & 0xff;
95 sp->t_ras = (val2 & 0xff00) >> 8;
96
97 sp->t_rc = sp->t_rp + sp->t_ras;
98
99 return 0;
100}
101
102static int adls_pcode_read_psf_gv_point_info(struct drm_i915_private *dev_priv,
103 struct intel_psf_gv_point *points)
104{
105 u32 val = 0;
106 int ret;
107 int i;
108
109 ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
110 ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
111 if (ret)
112 return ret;
113
114 for (i = 0; i < I915_NUM_PSF_GV_POINTS; i++) {
115 points[i].clk = val & 0xff;
116 val >>= 8;
117 }
118
119 return 0;
120}
121
122int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
123 u32 points_mask)
124{
125 int ret;
126
127 /* bspec says to keep retrying for at least 1 ms */
128 ret = skl_pcode_request(&dev_priv->uncore, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
129 points_mask,
130 ICL_PCODE_REP_QGV_MASK | ADLS_PCODE_REP_PSF_MASK,
131 ICL_PCODE_REP_QGV_SAFE | ADLS_PCODE_REP_PSF_SAFE,
132 1);
133
134 if (ret < 0) {
135 drm_err(&dev_priv->drm, "Failed to disable qgv points (%d) points: 0x%x\n", ret, points_mask);
136 return ret;
137 }
138
139 return 0;
140}
141
142static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv,
143 struct intel_qgv_point *sp, int point)
144{
145 u32 val, val2;
146 u16 dclk;
147
148 val = intel_uncore_read(&dev_priv->uncore,
149 MTL_MEM_SS_INFO_QGV_POINT_LOW(point));
150 val2 = intel_uncore_read(&dev_priv->uncore,
151 MTL_MEM_SS_INFO_QGV_POINT_HIGH(point));
152 dclk = REG_FIELD_GET(MTL_DCLK_MASK, val);
153 sp->dclk = DIV_ROUND_UP((16667 * dclk), 1000);
154 sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val);
155 sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val);
156
157 sp->t_rdpre = REG_FIELD_GET(MTL_TRDPRE_MASK, val2);
158 sp->t_ras = REG_FIELD_GET(MTL_TRAS_MASK, val2);
159
160 sp->t_rc = sp->t_rp + sp->t_ras;
161
162 return 0;
163}
164
165static int
166intel_read_qgv_point_info(struct drm_i915_private *dev_priv,
167 struct intel_qgv_point *sp,
168 int point)
169{
170 if (DISPLAY_VER(dev_priv) >= 14)
171 return mtl_read_qgv_point_info(dev_priv, sp, point);
172 else if (IS_DG1(dev_priv))
173 return dg1_mchbar_read_qgv_point_info(dev_priv, sp, point);
174 else
175 return icl_pcode_read_qgv_point_info(dev_priv, sp, point);
176}
177
178static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
179 struct intel_qgv_info *qi,
180 bool is_y_tile)
181{
182 const struct dram_info *dram_info = &dev_priv->dram_info;
183 int i, ret;
184
185 qi->num_points = dram_info->num_qgv_points;
186 qi->num_psf_points = dram_info->num_psf_gv_points;
187
188 if (DISPLAY_VER(dev_priv) >= 14) {
189 switch (dram_info->type) {
190 case INTEL_DRAM_DDR4:
191 qi->t_bl = 4;
192 qi->max_numchannels = 2;
193 qi->channel_width = 64;
194 qi->deinterleave = 2;
195 break;
196 case INTEL_DRAM_DDR5:
197 qi->t_bl = 8;
198 qi->max_numchannels = 4;
199 qi->channel_width = 32;
200 qi->deinterleave = 2;
201 break;
202 case INTEL_DRAM_LPDDR4:
203 case INTEL_DRAM_LPDDR5:
204 qi->t_bl = 16;
205 qi->max_numchannels = 8;
206 qi->channel_width = 16;
207 qi->deinterleave = 4;
208 break;
209 default:
210 MISSING_CASE(dram_info->type);
211 return -EINVAL;
212 }
213 } else if (DISPLAY_VER(dev_priv) >= 12) {
214 switch (dram_info->type) {
215 case INTEL_DRAM_DDR4:
216 qi->t_bl = is_y_tile ? 8 : 4;
217 qi->max_numchannels = 2;
218 qi->channel_width = 64;
219 qi->deinterleave = is_y_tile ? 1 : 2;
220 break;
221 case INTEL_DRAM_DDR5:
222 qi->t_bl = is_y_tile ? 16 : 8;
223 qi->max_numchannels = 4;
224 qi->channel_width = 32;
225 qi->deinterleave = is_y_tile ? 1 : 2;
226 break;
227 case INTEL_DRAM_LPDDR4:
228 if (IS_ROCKETLAKE(dev_priv)) {
229 qi->t_bl = 8;
230 qi->max_numchannels = 4;
231 qi->channel_width = 32;
232 qi->deinterleave = 2;
233 break;
234 }
235 fallthrough;
236 case INTEL_DRAM_LPDDR5:
237 qi->t_bl = 16;
238 qi->max_numchannels = 8;
239 qi->channel_width = 16;
240 qi->deinterleave = is_y_tile ? 2 : 4;
241 break;
242 default:
243 qi->t_bl = 16;
244 qi->max_numchannels = 1;
245 break;
246 }
247 } else if (DISPLAY_VER(dev_priv) == 11) {
248 qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
249 qi->max_numchannels = 1;
250 }
251
252 if (drm_WARN_ON(&dev_priv->drm,
253 qi->num_points > ARRAY_SIZE(qi->points)))
254 qi->num_points = ARRAY_SIZE(qi->points);
255
256 for (i = 0; i < qi->num_points; i++) {
257 struct intel_qgv_point *sp = &qi->points[i];
258
259 ret = intel_read_qgv_point_info(dev_priv, sp, i);
260 if (ret)
261 return ret;
262
263 drm_dbg_kms(&dev_priv->drm,
264 "QGV %d: DCLK=%d tRP=%d tRDPRE=%d tRAS=%d tRCD=%d tRC=%d\n",
265 i, sp->dclk, sp->t_rp, sp->t_rdpre, sp->t_ras,
266 sp->t_rcd, sp->t_rc);
267 }
268
269 if (qi->num_psf_points > 0) {
270 ret = adls_pcode_read_psf_gv_point_info(dev_priv, qi->psf_points);
271 if (ret) {
272 drm_err(&dev_priv->drm, "Failed to read PSF point data; PSF points will not be considered in bandwidth calculations.\n");
273 qi->num_psf_points = 0;
274 }
275
276 for (i = 0; i < qi->num_psf_points; i++)
277 drm_dbg_kms(&dev_priv->drm,
278 "PSF GV %d: CLK=%d \n",
279 i, qi->psf_points[i].clk);
280 }
281
282 return 0;
283}
284
285static int adl_calc_psf_bw(int clk)
286{
287 /*
288 * clk is multiples of 16.666MHz (100/6)
289 * According to BSpec PSF GV bandwidth is
290 * calculated as BW = 64 * clk * 16.666Mhz
291 */
292 return DIV_ROUND_CLOSEST(64 * clk * 100, 6);
293}
294
295static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
296{
297 u16 dclk = 0;
298 int i;
299
300 for (i = 0; i < qi->num_points; i++)
301 dclk = max(dclk, qi->points[i].dclk);
302
303 return dclk;
304}
305
306struct intel_sa_info {
307 u16 displayrtids;
308 u8 deburst, deprogbwlimit, derating;
309};
310
311static const struct intel_sa_info icl_sa_info = {
312 .deburst = 8,
313 .deprogbwlimit = 25, /* GB/s */
314 .displayrtids = 128,
315 .derating = 10,
316};
317
318static const struct intel_sa_info tgl_sa_info = {
319 .deburst = 16,
320 .deprogbwlimit = 34, /* GB/s */
321 .displayrtids = 256,
322 .derating = 10,
323};
324
325static const struct intel_sa_info rkl_sa_info = {
326 .deburst = 8,
327 .deprogbwlimit = 20, /* GB/s */
328 .displayrtids = 128,
329 .derating = 10,
330};
331
332static const struct intel_sa_info adls_sa_info = {
333 .deburst = 16,
334 .deprogbwlimit = 38, /* GB/s */
335 .displayrtids = 256,
336 .derating = 10,
337};
338
339static const struct intel_sa_info adlp_sa_info = {
340 .deburst = 16,
341 .deprogbwlimit = 38, /* GB/s */
342 .displayrtids = 256,
343 .derating = 20,
344};
345
346static const struct intel_sa_info mtl_sa_info = {
347 .deburst = 32,
348 .deprogbwlimit = 38, /* GB/s */
349 .displayrtids = 256,
350 .derating = 20,
351};
352
353static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
354{
355 struct intel_qgv_info qi = {};
356 bool is_y_tile = true; /* assume y tile may be used */
357 int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels);
358 int ipqdepth, ipqdepthpch = 16;
359 int dclk_max;
360 int maxdebw;
361 int num_groups = ARRAY_SIZE(dev_priv->display.bw.max);
362 int i, ret;
363
364 ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile);
365 if (ret) {
366 drm_dbg_kms(&dev_priv->drm,
367 "Failed to get memory subsystem information, ignoring bandwidth limits");
368 return ret;
369 }
370
371 dclk_max = icl_sagv_max_dclk(&qi);
372 maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
373 ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
374 qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
375
376 for (i = 0; i < num_groups; i++) {
377 struct intel_bw_info *bi = &dev_priv->display.bw.max[i];
378 int clpchgroup;
379 int j;
380
381 clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
382 bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
383
384 bi->num_qgv_points = qi.num_points;
385 bi->num_psf_gv_points = qi.num_psf_points;
386
387 for (j = 0; j < qi.num_points; j++) {
388 const struct intel_qgv_point *sp = &qi.points[j];
389 int ct, bw;
390
391 /*
392 * Max row cycle time
393 *
394 * FIXME what is the logic behind the
395 * assumed burst length?
396 */
397 ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd +
398 (clpchgroup - 1) * qi.t_bl + sp->t_rdpre);
399 bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
400
401 bi->deratedbw[j] = min(maxdebw,
402 bw * (100 - sa->derating) / 100);
403
404 drm_dbg_kms(&dev_priv->drm,
405 "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
406 i, j, bi->num_planes, bi->deratedbw[j]);
407 }
408 }
409 /*
410 * In case if SAGV is disabled in BIOS, we always get 1
411 * SAGV point, but we can't send PCode commands to restrict it
412 * as it will fail and pointless anyway.
413 */
414 if (qi.num_points == 1)
415 dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
416 else
417 dev_priv->display.sagv.status = I915_SAGV_ENABLED;
418
419 return 0;
420}
421
422static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
423{
424 struct intel_qgv_info qi = {};
425 const struct dram_info *dram_info = &dev_priv->dram_info;
426 bool is_y_tile = true; /* assume y tile may be used */
427 int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels);
428 int ipqdepth, ipqdepthpch = 16;
429 int dclk_max;
430 int maxdebw, peakbw;
431 int clperchgroup;
432 int num_groups = ARRAY_SIZE(dev_priv->display.bw.max);
433 int i, ret;
434
435 ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile);
436 if (ret) {
437 drm_dbg_kms(&dev_priv->drm,
438 "Failed to get memory subsystem information, ignoring bandwidth limits");
439 return ret;
440 }
441
442 if (DISPLAY_VER(dev_priv) < 14 &&
443 (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == INTEL_DRAM_LPDDR5))
444 num_channels *= 2;
445
446 qi.deinterleave = qi.deinterleave ? : DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
447
448 if (num_channels < qi.max_numchannels && DISPLAY_VER(dev_priv) >= 12)
449 qi.deinterleave = max(DIV_ROUND_UP(qi.deinterleave, 2), 1);
450
451 if (DISPLAY_VER(dev_priv) > 11 && num_channels > qi.max_numchannels)
452 drm_warn(&dev_priv->drm, "Number of channels exceeds max number of channels.");
453 if (qi.max_numchannels != 0)
454 num_channels = min_t(u8, num_channels, qi.max_numchannels);
455
456 dclk_max = icl_sagv_max_dclk(&qi);
457
458 peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
459 maxdebw = min(sa->deprogbwlimit * 1000, peakbw * 6 / 10); /* 60% */
460
461 ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
462 /*
463 * clperchgroup = 4kpagespermempage * clperchperblock,
464 * clperchperblock = 8 / num_channels * interleave
465 */
466 clperchgroup = 4 * DIV_ROUND_UP(8, num_channels) * qi.deinterleave;
467
468 for (i = 0; i < num_groups; i++) {
469 struct intel_bw_info *bi = &dev_priv->display.bw.max[i];
470 struct intel_bw_info *bi_next;
471 int clpchgroup;
472 int j;
473
474 clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
475
476 if (i < num_groups - 1) {
477 bi_next = &dev_priv->display.bw.max[i + 1];
478
479 if (clpchgroup < clperchgroup)
480 bi_next->num_planes = (ipqdepth - clpchgroup) /
481 clpchgroup + 1;
482 else
483 bi_next->num_planes = 0;
484 }
485
486 bi->num_qgv_points = qi.num_points;
487 bi->num_psf_gv_points = qi.num_psf_points;
488
489 for (j = 0; j < qi.num_points; j++) {
490 const struct intel_qgv_point *sp = &qi.points[j];
491 int ct, bw;
492
493 /*
494 * Max row cycle time
495 *
496 * FIXME what is the logic behind the
497 * assumed burst length?
498 */
499 ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd +
500 (clpchgroup - 1) * qi.t_bl + sp->t_rdpre);
501 bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
502
503 bi->deratedbw[j] = min(maxdebw,
504 bw * (100 - sa->derating) / 100);
505
506 drm_dbg_kms(&dev_priv->drm,
507 "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
508 i, j, bi->num_planes, bi->deratedbw[j]);
509 }
510
511 for (j = 0; j < qi.num_psf_points; j++) {
512 const struct intel_psf_gv_point *sp = &qi.psf_points[j];
513
514 bi->psf_bw[j] = adl_calc_psf_bw(sp->clk);
515
516 drm_dbg_kms(&dev_priv->drm,
517 "BW%d / PSF GV %d: num_planes=%d bw=%u\n",
518 i, j, bi->num_planes, bi->psf_bw[j]);
519 }
520 }
521
522 /*
523 * In case if SAGV is disabled in BIOS, we always get 1
524 * SAGV point, but we can't send PCode commands to restrict it
525 * as it will fail and pointless anyway.
526 */
527 if (qi.num_points == 1)
528 dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
529 else
530 dev_priv->display.sagv.status = I915_SAGV_ENABLED;
531
532 return 0;
533}
534
535static void dg2_get_bw_info(struct drm_i915_private *i915)
536{
537 unsigned int deratedbw = IS_DG2_G11(i915) ? 38000 : 50000;
538 int num_groups = ARRAY_SIZE(i915->display.bw.max);
539 int i;
540
541 /*
542 * DG2 doesn't have SAGV or QGV points, just a constant max bandwidth
543 * that doesn't depend on the number of planes enabled. So fill all the
544 * plane group with constant bw information for uniformity with other
545 * platforms. DG2-G10 platforms have a constant 50 GB/s bandwidth,
546 * whereas DG2-G11 platforms have 38 GB/s.
547 */
548 for (i = 0; i < num_groups; i++) {
549 struct intel_bw_info *bi = &i915->display.bw.max[i];
550
551 bi->num_planes = 1;
552 /* Need only one dummy QGV point per group */
553 bi->num_qgv_points = 1;
554 bi->deratedbw[0] = deratedbw;
555 }
556
557 i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
558}
559
560static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
561 int num_planes, int qgv_point)
562{
563 int i;
564
565 /*
566 * Let's return max bw for 0 planes
567 */
568 num_planes = max(1, num_planes);
569
570 for (i = 0; i < ARRAY_SIZE(dev_priv->display.bw.max); i++) {
571 const struct intel_bw_info *bi =
572 &dev_priv->display.bw.max[i];
573
574 /*
575 * Pcode will not expose all QGV points when
576 * SAGV is forced to off/min/med/max.
577 */
578 if (qgv_point >= bi->num_qgv_points)
579 return UINT_MAX;
580
581 if (num_planes >= bi->num_planes)
582 return bi->deratedbw[qgv_point];
583 }
584
585 return 0;
586}
587
588static unsigned int tgl_max_bw(struct drm_i915_private *dev_priv,
589 int num_planes, int qgv_point)
590{
591 int i;
592
593 /*
594 * Let's return max bw for 0 planes
595 */
596 num_planes = max(1, num_planes);
597
598 for (i = ARRAY_SIZE(dev_priv->display.bw.max) - 1; i >= 0; i--) {
599 const struct intel_bw_info *bi =
600 &dev_priv->display.bw.max[i];
601
602 /*
603 * Pcode will not expose all QGV points when
604 * SAGV is forced to off/min/med/max.
605 */
606 if (qgv_point >= bi->num_qgv_points)
607 return UINT_MAX;
608
609 if (num_planes <= bi->num_planes)
610 return bi->deratedbw[qgv_point];
611 }
612
613 return dev_priv->display.bw.max[0].deratedbw[qgv_point];
614}
615
616static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv,
617 int psf_gv_point)
618{
619 const struct intel_bw_info *bi =
620 &dev_priv->display.bw.max[0];
621
622 return bi->psf_bw[psf_gv_point];
623}
624
625void intel_bw_init_hw(struct drm_i915_private *dev_priv)
626{
627 if (!HAS_DISPLAY(dev_priv))
628 return;
629
630 if (DISPLAY_VER(dev_priv) >= 14)
631 tgl_get_bw_info(dev_priv, &mtl_sa_info);
632 else if (IS_DG2(dev_priv))
633 dg2_get_bw_info(dev_priv);
634 else if (IS_ALDERLAKE_P(dev_priv))
635 tgl_get_bw_info(dev_priv, &adlp_sa_info);
636 else if (IS_ALDERLAKE_S(dev_priv))
637 tgl_get_bw_info(dev_priv, &adls_sa_info);
638 else if (IS_ROCKETLAKE(dev_priv))
639 tgl_get_bw_info(dev_priv, &rkl_sa_info);
640 else if (DISPLAY_VER(dev_priv) == 12)
641 tgl_get_bw_info(dev_priv, &tgl_sa_info);
642 else if (DISPLAY_VER(dev_priv) == 11)
643 icl_get_bw_info(dev_priv, &icl_sa_info);
644}
645
646static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
647{
648 /*
649 * We assume cursors are small enough
650 * to not not cause bandwidth problems.
651 */
652 return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR));
653}
654
655static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state)
656{
657 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
658 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
659 unsigned int data_rate = 0;
660 enum plane_id plane_id;
661
662 for_each_plane_id_on_crtc(crtc, plane_id) {
663 /*
664 * We assume cursors are small enough
665 * to not not cause bandwidth problems.
666 */
667 if (plane_id == PLANE_CURSOR)
668 continue;
669
670 data_rate += crtc_state->data_rate[plane_id];
671
672 if (DISPLAY_VER(i915) < 11)
673 data_rate += crtc_state->data_rate_y[plane_id];
674 }
675
676 return data_rate;
677}
678
679/* "Maximum Pipe Read Bandwidth" */
680static int intel_bw_crtc_min_cdclk(const struct intel_crtc_state *crtc_state)
681{
682 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
683 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
684
685 if (DISPLAY_VER(i915) < 12)
686 return 0;
687
688 return DIV_ROUND_UP_ULL(mul_u32_u32(intel_bw_crtc_data_rate(crtc_state), 10), 512);
689}
690
691void intel_bw_crtc_update(struct intel_bw_state *bw_state,
692 const struct intel_crtc_state *crtc_state)
693{
694 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
695 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
696
697 bw_state->data_rate[crtc->pipe] =
698 intel_bw_crtc_data_rate(crtc_state);
699 bw_state->num_active_planes[crtc->pipe] =
700 intel_bw_crtc_num_active_planes(crtc_state);
701
702 drm_dbg_kms(&i915->drm, "pipe %c data rate %u num active planes %u\n",
703 pipe_name(crtc->pipe),
704 bw_state->data_rate[crtc->pipe],
705 bw_state->num_active_planes[crtc->pipe]);
706}
707
708static unsigned int intel_bw_num_active_planes(struct drm_i915_private *dev_priv,
709 const struct intel_bw_state *bw_state)
710{
711 unsigned int num_active_planes = 0;
712 enum pipe pipe;
713
714 for_each_pipe(dev_priv, pipe)
715 num_active_planes += bw_state->num_active_planes[pipe];
716
717 return num_active_planes;
718}
719
720static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
721 const struct intel_bw_state *bw_state)
722{
723 unsigned int data_rate = 0;
724 enum pipe pipe;
725
726 for_each_pipe(dev_priv, pipe)
727 data_rate += bw_state->data_rate[pipe];
728
729 if (DISPLAY_VER(dev_priv) >= 13 && i915_vtd_active(dev_priv))
730 data_rate = DIV_ROUND_UP(data_rate * 105, 100);
731
732 return data_rate;
733}
734
735struct intel_bw_state *
736intel_atomic_get_old_bw_state(struct intel_atomic_state *state)
737{
738 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
739 struct intel_global_state *bw_state;
740
741 bw_state = intel_atomic_get_old_global_obj_state(state, &dev_priv->display.bw.obj);
742
743 return to_intel_bw_state(bw_state);
744}
745
746struct intel_bw_state *
747intel_atomic_get_new_bw_state(struct intel_atomic_state *state)
748{
749 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
750 struct intel_global_state *bw_state;
751
752 bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->display.bw.obj);
753
754 return to_intel_bw_state(bw_state);
755}
756
757struct intel_bw_state *
758intel_atomic_get_bw_state(struct intel_atomic_state *state)
759{
760 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
761 struct intel_global_state *bw_state;
762
763 bw_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.bw.obj);
764 if (IS_ERR(bw_state))
765 return ERR_CAST(bw_state);
766
767 return to_intel_bw_state(bw_state);
768}
769
770static bool intel_bw_state_changed(struct drm_i915_private *i915,
771 const struct intel_bw_state *old_bw_state,
772 const struct intel_bw_state *new_bw_state)
773{
774 enum pipe pipe;
775
776 for_each_pipe(i915, pipe) {
777 const struct intel_dbuf_bw *old_crtc_bw =
778 &old_bw_state->dbuf_bw[pipe];
779 const struct intel_dbuf_bw *new_crtc_bw =
780 &new_bw_state->dbuf_bw[pipe];
781 enum dbuf_slice slice;
782
783 for_each_dbuf_slice(i915, slice) {
784 if (old_crtc_bw->max_bw[slice] != new_crtc_bw->max_bw[slice] ||
785 old_crtc_bw->active_planes[slice] != new_crtc_bw->active_planes[slice])
786 return true;
787 }
788
789 if (old_bw_state->min_cdclk[pipe] != new_bw_state->min_cdclk[pipe])
790 return true;
791 }
792
793 return false;
794}
795
796static void skl_plane_calc_dbuf_bw(struct intel_bw_state *bw_state,
797 struct intel_crtc *crtc,
798 enum plane_id plane_id,
799 const struct skl_ddb_entry *ddb,
800 unsigned int data_rate)
801{
802 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
803 struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
804 unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
805 enum dbuf_slice slice;
806
807 /*
808 * The arbiter can only really guarantee an
809 * equal share of the total bw to each plane.
810 */
811 for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask) {
812 crtc_bw->max_bw[slice] = max(crtc_bw->max_bw[slice], data_rate);
813 crtc_bw->active_planes[slice] |= BIT(plane_id);
814 }
815}
816
817static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
818 const struct intel_crtc_state *crtc_state)
819{
820 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
821 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
822 struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
823 enum plane_id plane_id;
824
825 memset(crtc_bw, 0, sizeof(*crtc_bw));
826
827 if (!crtc_state->hw.active)
828 return;
829
830 for_each_plane_id_on_crtc(crtc, plane_id) {
831 /*
832 * We assume cursors are small enough
833 * to not cause bandwidth problems.
834 */
835 if (plane_id == PLANE_CURSOR)
836 continue;
837
838 skl_plane_calc_dbuf_bw(bw_state, crtc, plane_id,
839 &crtc_state->wm.skl.plane_ddb[plane_id],
840 crtc_state->data_rate[plane_id]);
841
842 if (DISPLAY_VER(i915) < 11)
843 skl_plane_calc_dbuf_bw(bw_state, crtc, plane_id,
844 &crtc_state->wm.skl.plane_ddb_y[plane_id],
845 crtc_state->data_rate[plane_id]);
846 }
847}
848
849/* "Maximum Data Buffer Bandwidth" */
850static int
851intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915,
852 const struct intel_bw_state *bw_state)
853{
854 unsigned int total_max_bw = 0;
855 enum dbuf_slice slice;
856
857 for_each_dbuf_slice(i915, slice) {
858 int num_active_planes = 0;
859 unsigned int max_bw = 0;
860 enum pipe pipe;
861
862 /*
863 * The arbiter can only really guarantee an
864 * equal share of the total bw to each plane.
865 */
866 for_each_pipe(i915, pipe) {
867 const struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[pipe];
868
869 max_bw = max(crtc_bw->max_bw[slice], max_bw);
870 num_active_planes += hweight8(crtc_bw->active_planes[slice]);
871 }
872 max_bw *= num_active_planes;
873
874 total_max_bw = max(total_max_bw, max_bw);
875 }
876
877 return DIV_ROUND_UP(total_max_bw, 64);
878}
879
880int intel_bw_min_cdclk(struct drm_i915_private *i915,
881 const struct intel_bw_state *bw_state)
882{
883 enum pipe pipe;
884 int min_cdclk;
885
886 min_cdclk = intel_bw_dbuf_min_cdclk(i915, bw_state);
887
888 for_each_pipe(i915, pipe)
889 min_cdclk = max(bw_state->min_cdclk[pipe], min_cdclk);
890
891 return min_cdclk;
892}
893
894int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
895 bool *need_cdclk_calc)
896{
897 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
898 struct intel_bw_state *new_bw_state = NULL;
899 const struct intel_bw_state *old_bw_state = NULL;
900 const struct intel_cdclk_state *cdclk_state;
901 const struct intel_crtc_state *crtc_state;
902 int old_min_cdclk, new_min_cdclk;
903 struct intel_crtc *crtc;
904 int i;
905
906 if (DISPLAY_VER(dev_priv) < 9)
907 return 0;
908
909 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
910 new_bw_state = intel_atomic_get_bw_state(state);
911 if (IS_ERR(new_bw_state))
912 return PTR_ERR(new_bw_state);
913
914 old_bw_state = intel_atomic_get_old_bw_state(state);
915
916 skl_crtc_calc_dbuf_bw(new_bw_state, crtc_state);
917
918 new_bw_state->min_cdclk[crtc->pipe] =
919 intel_bw_crtc_min_cdclk(crtc_state);
920 }
921
922 if (!old_bw_state)
923 return 0;
924
925 if (intel_bw_state_changed(dev_priv, old_bw_state, new_bw_state)) {
926 int ret = intel_atomic_lock_global_state(&new_bw_state->base);
927 if (ret)
928 return ret;
929 }
930
931 old_min_cdclk = intel_bw_min_cdclk(dev_priv, old_bw_state);
932 new_min_cdclk = intel_bw_min_cdclk(dev_priv, new_bw_state);
933
934 /*
935 * No need to check against the cdclk state if
936 * the min cdclk doesn't increase.
937 *
938 * Ie. we only ever increase the cdclk due to bandwidth
939 * requirements. This can reduce back and forth
940 * display blinking due to constant cdclk changes.
941 */
942 if (new_min_cdclk <= old_min_cdclk)
943 return 0;
944
945 cdclk_state = intel_atomic_get_cdclk_state(state);
946 if (IS_ERR(cdclk_state))
947 return PTR_ERR(cdclk_state);
948
949 /*
950 * No need to recalculate the cdclk state if
951 * the min cdclk doesn't increase.
952 *
953 * Ie. we only ever increase the cdclk due to bandwidth
954 * requirements. This can reduce back and forth
955 * display blinking due to constant cdclk changes.
956 */
957 if (new_min_cdclk <= cdclk_state->bw_min_cdclk)
958 return 0;
959
960 drm_dbg_kms(&dev_priv->drm,
961 "new bandwidth min cdclk (%d kHz) > old min cdclk (%d kHz)\n",
962 new_min_cdclk, cdclk_state->bw_min_cdclk);
963 *need_cdclk_calc = true;
964
965 return 0;
966}
967
968static u16 icl_qgv_points_mask(struct drm_i915_private *i915)
969{
970 unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
971 unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
972 u16 qgv_points = 0, psf_points = 0;
973
974 /*
975 * We can _not_ use the whole ADLS_QGV_PT_MASK here, as PCode rejects
976 * it with failure if we try masking any unadvertised points.
977 * So need to operate only with those returned from PCode.
978 */
979 if (num_qgv_points > 0)
980 qgv_points = GENMASK(num_qgv_points - 1, 0);
981
982 if (num_psf_gv_points > 0)
983 psf_points = GENMASK(num_psf_gv_points - 1, 0);
984
985 return ICL_PCODE_REQ_QGV_PT(qgv_points) | ADLS_PCODE_REQ_PSF_PT(psf_points);
986}
987
988static int intel_bw_check_data_rate(struct intel_atomic_state *state, bool *changed)
989{
990 struct drm_i915_private *i915 = to_i915(state->base.dev);
991 const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
992 struct intel_crtc *crtc;
993 int i;
994
995 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
996 new_crtc_state, i) {
997 unsigned int old_data_rate =
998 intel_bw_crtc_data_rate(old_crtc_state);
999 unsigned int new_data_rate =
1000 intel_bw_crtc_data_rate(new_crtc_state);
1001 unsigned int old_active_planes =
1002 intel_bw_crtc_num_active_planes(old_crtc_state);
1003 unsigned int new_active_planes =
1004 intel_bw_crtc_num_active_planes(new_crtc_state);
1005 struct intel_bw_state *new_bw_state;
1006
1007 /*
1008 * Avoid locking the bw state when
1009 * nothing significant has changed.
1010 */
1011 if (old_data_rate == new_data_rate &&
1012 old_active_planes == new_active_planes)
1013 continue;
1014
1015 new_bw_state = intel_atomic_get_bw_state(state);
1016 if (IS_ERR(new_bw_state))
1017 return PTR_ERR(new_bw_state);
1018
1019 new_bw_state->data_rate[crtc->pipe] = new_data_rate;
1020 new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
1021
1022 *changed = true;
1023
1024 drm_dbg_kms(&i915->drm,
1025 "[CRTC:%d:%s] data rate %u num active planes %u\n",
1026 crtc->base.base.id, crtc->base.name,
1027 new_bw_state->data_rate[crtc->pipe],
1028 new_bw_state->num_active_planes[crtc->pipe]);
1029 }
1030
1031 return 0;
1032}
1033
1034int intel_bw_atomic_check(struct intel_atomic_state *state)
1035{
1036 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1037 const struct intel_bw_state *old_bw_state;
1038 struct intel_bw_state *new_bw_state;
1039 unsigned int data_rate;
1040 unsigned int num_active_planes;
1041 int i, ret;
1042 u16 qgv_points = 0, psf_points = 0;
1043 unsigned int max_bw_point = 0, max_bw = 0;
1044 unsigned int num_qgv_points = dev_priv->display.bw.max[0].num_qgv_points;
1045 unsigned int num_psf_gv_points = dev_priv->display.bw.max[0].num_psf_gv_points;
1046 bool changed = false;
1047
1048 /* FIXME earlier gens need some checks too */
1049 if (DISPLAY_VER(dev_priv) < 11)
1050 return 0;
1051
1052 ret = intel_bw_check_data_rate(state, &changed);
1053 if (ret)
1054 return ret;
1055
1056 old_bw_state = intel_atomic_get_old_bw_state(state);
1057 new_bw_state = intel_atomic_get_new_bw_state(state);
1058
1059 if (new_bw_state &&
1060 intel_can_enable_sagv(dev_priv, old_bw_state) !=
1061 intel_can_enable_sagv(dev_priv, new_bw_state))
1062 changed = true;
1063
1064 /*
1065 * If none of our inputs (data rates, number of active
1066 * planes, SAGV yes/no) changed then nothing to do here.
1067 */
1068 if (!changed)
1069 return 0;
1070
1071 ret = intel_atomic_lock_global_state(&new_bw_state->base);
1072 if (ret)
1073 return ret;
1074
1075 data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
1076 data_rate = DIV_ROUND_UP(data_rate, 1000);
1077
1078 num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
1079
1080 for (i = 0; i < num_qgv_points; i++) {
1081 unsigned int max_data_rate;
1082
1083 if (DISPLAY_VER(dev_priv) > 11)
1084 max_data_rate = tgl_max_bw(dev_priv, num_active_planes, i);
1085 else
1086 max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
1087 /*
1088 * We need to know which qgv point gives us
1089 * maximum bandwidth in order to disable SAGV
1090 * if we find that we exceed SAGV block time
1091 * with watermarks. By that moment we already
1092 * have those, as it is calculated earlier in
1093 * intel_atomic_check,
1094 */
1095 if (max_data_rate > max_bw) {
1096 max_bw_point = i;
1097 max_bw = max_data_rate;
1098 }
1099 if (max_data_rate >= data_rate)
1100 qgv_points |= BIT(i);
1101
1102 drm_dbg_kms(&dev_priv->drm, "QGV point %d: max bw %d required %d\n",
1103 i, max_data_rate, data_rate);
1104 }
1105
1106 for (i = 0; i < num_psf_gv_points; i++) {
1107 unsigned int max_data_rate = adl_psf_bw(dev_priv, i);
1108
1109 if (max_data_rate >= data_rate)
1110 psf_points |= BIT(i);
1111
1112 drm_dbg_kms(&dev_priv->drm, "PSF GV point %d: max bw %d"
1113 " required %d\n",
1114 i, max_data_rate, data_rate);
1115 }
1116
1117 /*
1118 * BSpec states that we always should have at least one allowed point
1119 * left, so if we couldn't - simply reject the configuration for obvious
1120 * reasons.
1121 */
1122 if (qgv_points == 0) {
1123 drm_dbg_kms(&dev_priv->drm, "No QGV points provide sufficient memory"
1124 " bandwidth %d for display configuration(%d active planes).\n",
1125 data_rate, num_active_planes);
1126 return -EINVAL;
1127 }
1128
1129 if (num_psf_gv_points > 0 && psf_points == 0) {
1130 drm_dbg_kms(&dev_priv->drm, "No PSF GV points provide sufficient memory"
1131 " bandwidth %d for display configuration(%d active planes).\n",
1132 data_rate, num_active_planes);
1133 return -EINVAL;
1134 }
1135
1136 /*
1137 * Leave only single point with highest bandwidth, if
1138 * we can't enable SAGV due to the increased memory latency it may
1139 * cause.
1140 */
1141 if (!intel_can_enable_sagv(dev_priv, new_bw_state)) {
1142 qgv_points = BIT(max_bw_point);
1143 drm_dbg_kms(&dev_priv->drm, "No SAGV, using single QGV point %d\n",
1144 max_bw_point);
1145 }
1146
1147 /*
1148 * We store the ones which need to be masked as that is what PCode
1149 * actually accepts as a parameter.
1150 */
1151 new_bw_state->qgv_points_mask =
1152 ~(ICL_PCODE_REQ_QGV_PT(qgv_points) |
1153 ADLS_PCODE_REQ_PSF_PT(psf_points)) &
1154 icl_qgv_points_mask(dev_priv);
1155
1156 /*
1157 * If the actual mask had changed we need to make sure that
1158 * the commits are serialized(in case this is a nomodeset, nonblocking)
1159 */
1160 if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
1161 ret = intel_atomic_serialize_global_state(&new_bw_state->base);
1162 if (ret)
1163 return ret;
1164 }
1165
1166 return 0;
1167}
1168
1169static struct intel_global_state *
1170intel_bw_duplicate_state(struct intel_global_obj *obj)
1171{
1172 struct intel_bw_state *state;
1173
1174 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
1175 if (!state)
1176 return NULL;
1177
1178 return &state->base;
1179}
1180
1181static void intel_bw_destroy_state(struct intel_global_obj *obj,
1182 struct intel_global_state *state)
1183{
1184 kfree(state);
1185}
1186
1187static const struct intel_global_state_funcs intel_bw_funcs = {
1188 .atomic_duplicate_state = intel_bw_duplicate_state,
1189 .atomic_destroy_state = intel_bw_destroy_state,
1190};
1191
1192int intel_bw_init(struct drm_i915_private *dev_priv)
1193{
1194 struct intel_bw_state *state;
1195
1196 state = kzalloc(sizeof(*state), GFP_KERNEL);
1197 if (!state)
1198 return -ENOMEM;
1199
1200 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.bw.obj,
1201 &state->base, &intel_bw_funcs);
1202
1203 return 0;
1204}