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1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/pci.h>
25
26#include "amdgpu.h"
27#include "amdgpu_ih.h"
28#include "soc15.h"
29
30#include "oss/osssys_4_2_0_offset.h"
31#include "oss/osssys_4_2_0_sh_mask.h"
32
33#include "soc15_common.h"
34#include "vega20_ih.h"
35
36#define MAX_REARM_RETRY 10
37
38#define mmIH_CHICKEN_ALDEBARAN 0x18d
39#define mmIH_CHICKEN_ALDEBARAN_BASE_IDX 0
40
41#define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN 0x00ea
42#define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN_BASE_IDX 0
43#define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE__SHIFT 0x10
44#define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE_MASK 0x00010000L
45
46static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev);
47
48/**
49 * vega20_ih_init_register_offset - Initialize register offset for ih rings
50 *
51 * @adev: amdgpu_device pointer
52 *
53 * Initialize register offset ih rings (VEGA20).
54 */
55static void vega20_ih_init_register_offset(struct amdgpu_device *adev)
56{
57 struct amdgpu_ih_regs *ih_regs;
58
59 if (adev->irq.ih.ring_size) {
60 ih_regs = &adev->irq.ih.ih_regs;
61 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
62 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);
63 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
64 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
65 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
66 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);
67 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
68 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);
69 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
70 }
71
72 if (adev->irq.ih1.ring_size) {
73 ih_regs = &adev->irq.ih1.ih_regs;
74 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);
75 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);
76 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
77 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
78 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
79 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);
80 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
81 }
82
83 if (adev->irq.ih2.ring_size) {
84 ih_regs = &adev->irq.ih2.ih_regs;
85 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);
86 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);
87 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
88 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
89 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
90 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);
91 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2;
92 }
93}
94
95/**
96 * vega20_ih_toggle_ring_interrupts - toggle the interrupt ring buffer
97 *
98 * @adev: amdgpu_device pointer
99 * @ih: amdgpu_ih_ring pointer
100 * @enable: true - enable the interrupts, false - disable the interrupts
101 *
102 * Toggle the interrupt ring buffer (VEGA20)
103 */
104static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
105 struct amdgpu_ih_ring *ih,
106 bool enable)
107{
108 struct amdgpu_ih_regs *ih_regs;
109 uint32_t tmp;
110
111 ih_regs = &ih->ih_regs;
112
113 tmp = RREG32(ih_regs->ih_rb_cntl);
114 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
115 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);
116
117 /* enable_intr field is only valid in ring0 */
118 if (ih == &adev->irq.ih)
119 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
120 if (amdgpu_sriov_vf(adev)) {
121 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
122 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
123 return -ETIMEDOUT;
124 }
125 } else {
126 WREG32(ih_regs->ih_rb_cntl, tmp);
127 }
128
129 if (enable) {
130 ih->enabled = true;
131 } else {
132 /* set rptr, wptr to 0 */
133 WREG32(ih_regs->ih_rb_rptr, 0);
134 WREG32(ih_regs->ih_rb_wptr, 0);
135 ih->enabled = false;
136 ih->rptr = 0;
137 }
138
139 return 0;
140}
141
142/**
143 * vega20_ih_toggle_interrupts - Toggle all the available interrupt ring buffers
144 *
145 * @adev: amdgpu_device pointer
146 * @enable: enable or disable interrupt ring buffers
147 *
148 * Toggle all the available interrupt ring buffers (VEGA20).
149 */
150static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable)
151{
152 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
153 int i;
154 int r;
155
156 for (i = 0; i < ARRAY_SIZE(ih); i++) {
157 if (ih[i]->ring_size) {
158 r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable);
159 if (r)
160 return r;
161 }
162 }
163
164 return 0;
165}
166
167static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
168{
169 int rb_bufsz = order_base_2(ih->ring_size / 4);
170
171 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
172 MC_SPACE, ih->use_bus_addr ? 1 : 4);
173 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
174 WPTR_OVERFLOW_CLEAR, 1);
175 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
176 WPTR_OVERFLOW_ENABLE, 1);
177 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
178 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
179 * value is written to memory
180 */
181 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
182 WPTR_WRITEBACK_ENABLE, 1);
183 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
184 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
185 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
186
187 return ih_rb_cntl;
188}
189
190static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
191{
192 u32 ih_doorbell_rtpr = 0;
193
194 if (ih->use_doorbell) {
195 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
196 IH_DOORBELL_RPTR, OFFSET,
197 ih->doorbell_index);
198 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
199 IH_DOORBELL_RPTR,
200 ENABLE, 1);
201 } else {
202 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
203 IH_DOORBELL_RPTR,
204 ENABLE, 0);
205 }
206 return ih_doorbell_rtpr;
207}
208
209/**
210 * vega20_ih_enable_ring - enable an ih ring buffer
211 *
212 * @adev: amdgpu_device pointer
213 * @ih: amdgpu_ih_ring pointer
214 *
215 * Enable an ih ring buffer (VEGA20)
216 */
217static int vega20_ih_enable_ring(struct amdgpu_device *adev,
218 struct amdgpu_ih_ring *ih)
219{
220 struct amdgpu_ih_regs *ih_regs;
221 uint32_t tmp;
222
223 ih_regs = &ih->ih_regs;
224
225 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
226 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
227 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
228
229 tmp = RREG32(ih_regs->ih_rb_cntl);
230 tmp = vega20_ih_rb_cntl(ih, tmp);
231 if (ih == &adev->irq.ih)
232 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
233 if (ih == &adev->irq.ih1)
234 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
235 if (amdgpu_sriov_vf(adev)) {
236 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
237 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
238 return -ETIMEDOUT;
239 }
240 } else {
241 WREG32(ih_regs->ih_rb_cntl, tmp);
242 }
243
244 if (ih == &adev->irq.ih) {
245 /* set the ih ring 0 writeback address whether it's enabled or not */
246 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
247 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
248 }
249
250 /* set rptr, wptr to 0 */
251 WREG32(ih_regs->ih_rb_wptr, 0);
252 WREG32(ih_regs->ih_rb_rptr, 0);
253
254 WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih));
255
256 return 0;
257}
258
259static uint32_t vega20_setup_retry_doorbell(u32 doorbell_index)
260{
261 u32 val = 0;
262
263 val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, OFFSET, doorbell_index);
264 val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, ENABLE, 1);
265
266 return val;
267}
268
269/**
270 * vega20_ih_irq_init - init and enable the interrupt ring
271 *
272 * @adev: amdgpu_device pointer
273 *
274 * Allocate a ring buffer for the interrupt controller,
275 * enable the RLC, disable interrupts, enable the IH
276 * ring buffer and enable it (VI).
277 * Called at device load and reume.
278 * Returns 0 for success, errors for failure.
279 */
280static int vega20_ih_irq_init(struct amdgpu_device *adev)
281{
282 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
283 u32 ih_chicken;
284 int ret;
285 int i;
286
287 /* disable irqs */
288 ret = vega20_ih_toggle_interrupts(adev, false);
289 if (ret)
290 return ret;
291
292 adev->nbio.funcs->ih_control(adev);
293
294 if ((amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 2, 1)) &&
295 adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
296 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
297 if (adev->irq.ih.use_bus_addr) {
298 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
299 MC_SPACE_GPA_ENABLE, 1);
300 }
301 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
302 }
303
304 /* psp firmware won't program IH_CHICKEN for aldebaran
305 * driver needs to program it properly according to
306 * MC_SPACE type in IH_RB_CNTL */
307 if ((amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 0)) ||
308 (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2))) {
309 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN);
310 if (adev->irq.ih.use_bus_addr) {
311 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
312 MC_SPACE_GPA_ENABLE, 1);
313 }
314 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN, ih_chicken);
315 }
316
317 for (i = 0; i < ARRAY_SIZE(ih); i++) {
318 if (ih[i]->ring_size) {
319 ret = vega20_ih_enable_ring(adev, ih[i]);
320 if (ret)
321 return ret;
322 }
323 }
324
325 if (!amdgpu_sriov_vf(adev))
326 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
327 adev->irq.ih.doorbell_index);
328
329 pci_set_master(adev->pdev);
330
331 /* Allocate the doorbell for IH Retry CAM */
332 adev->irq.retry_cam_doorbell_index = (adev->doorbell_index.ih + 3) << 1;
333 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RETRY_CAM,
334 vega20_setup_retry_doorbell(adev->irq.retry_cam_doorbell_index));
335
336 /* Enable IH Retry CAM */
337 if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 0) ||
338 amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2))
339 WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL_ALDEBARAN,
340 ENABLE, 1);
341 else
342 WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL, ENABLE, 1);
343
344 adev->irq.retry_cam_enabled = true;
345
346 /* enable interrupts */
347 ret = vega20_ih_toggle_interrupts(adev, true);
348 if (ret)
349 return ret;
350
351 if (adev->irq.ih_soft.ring_size)
352 adev->irq.ih_soft.enabled = true;
353
354 return 0;
355}
356
357/**
358 * vega20_ih_irq_disable - disable interrupts
359 *
360 * @adev: amdgpu_device pointer
361 *
362 * Disable interrupts on the hw (VEGA20).
363 */
364static void vega20_ih_irq_disable(struct amdgpu_device *adev)
365{
366 vega20_ih_toggle_interrupts(adev, false);
367
368 /* Wait and acknowledge irq */
369 mdelay(1);
370}
371
372/**
373 * vega20_ih_get_wptr - get the IH ring buffer wptr
374 *
375 * @adev: amdgpu_device pointer
376 * @ih: amdgpu_ih_ring pointer
377 *
378 * Get the IH ring buffer wptr from either the register
379 * or the writeback memory buffer (VEGA20). Also check for
380 * ring buffer overflow and deal with it.
381 * Returns the value of the wptr.
382 */
383static u32 vega20_ih_get_wptr(struct amdgpu_device *adev,
384 struct amdgpu_ih_ring *ih)
385{
386 u32 wptr, tmp;
387 struct amdgpu_ih_regs *ih_regs;
388
389 if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) {
390 /* Only ring0 supports writeback. On other rings fall back
391 * to register-based code with overflow checking below.
392 * ih_soft ring doesn't have any backing hardware registers,
393 * update wptr and return.
394 */
395 wptr = le32_to_cpu(*ih->wptr_cpu);
396
397 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
398 goto out;
399 }
400
401 ih_regs = &ih->ih_regs;
402
403 /* Double check that the overflow wasn't already cleared. */
404 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
405 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
406 goto out;
407
408 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
409
410 /* When a ring buffer overflow happen start parsing interrupt
411 * from the last not overwritten vector (wptr + 32). Hopefully
412 * this should allow us to catchup.
413 */
414 tmp = (wptr + 32) & ih->ptr_mask;
415 dev_warn(adev->dev, "IH ring buffer overflow "
416 "(0x%08X, 0x%08X, 0x%08X)\n",
417 wptr, ih->rptr, tmp);
418 ih->rptr = tmp;
419
420 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
421 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
422 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
423
424 /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
425 * can be detected.
426 */
427 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
428 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
429
430out:
431 return (wptr & ih->ptr_mask);
432}
433
434/**
435 * vega20_ih_irq_rearm - rearm IRQ if lost
436 *
437 * @adev: amdgpu_device pointer
438 * @ih: amdgpu_ih_ring pointer
439 *
440 */
441static void vega20_ih_irq_rearm(struct amdgpu_device *adev,
442 struct amdgpu_ih_ring *ih)
443{
444 uint32_t v = 0;
445 uint32_t i = 0;
446 struct amdgpu_ih_regs *ih_regs;
447
448 ih_regs = &ih->ih_regs;
449
450 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */
451 for (i = 0; i < MAX_REARM_RETRY; i++) {
452 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
453 if ((v < ih->ring_size) && (v != ih->rptr))
454 WDOORBELL32(ih->doorbell_index, ih->rptr);
455 else
456 break;
457 }
458}
459
460/**
461 * vega20_ih_set_rptr - set the IH ring buffer rptr
462 *
463 * @adev: amdgpu_device pointer
464 * @ih: amdgpu_ih_ring pointer
465 *
466 * Set the IH ring buffer rptr.
467 */
468static void vega20_ih_set_rptr(struct amdgpu_device *adev,
469 struct amdgpu_ih_ring *ih)
470{
471 struct amdgpu_ih_regs *ih_regs;
472
473 if (ih == &adev->irq.ih_soft)
474 return;
475
476 if (ih->use_doorbell) {
477 /* XXX check if swapping is necessary on BE */
478 *ih->rptr_cpu = ih->rptr;
479 WDOORBELL32(ih->doorbell_index, ih->rptr);
480
481 if (amdgpu_sriov_vf(adev))
482 vega20_ih_irq_rearm(adev, ih);
483 } else {
484 ih_regs = &ih->ih_regs;
485 WREG32(ih_regs->ih_rb_rptr, ih->rptr);
486 }
487}
488
489/**
490 * vega20_ih_self_irq - dispatch work for ring 1 and 2
491 *
492 * @adev: amdgpu_device pointer
493 * @source: irq source
494 * @entry: IV with WPTR update
495 *
496 * Update the WPTR from the IV and schedule work to handle the entries.
497 */
498static int vega20_ih_self_irq(struct amdgpu_device *adev,
499 struct amdgpu_irq_src *source,
500 struct amdgpu_iv_entry *entry)
501{
502 switch (entry->ring_id) {
503 case 1:
504 schedule_work(&adev->irq.ih1_work);
505 break;
506 case 2:
507 schedule_work(&adev->irq.ih2_work);
508 break;
509 default:
510 break;
511 }
512 return 0;
513}
514
515static const struct amdgpu_irq_src_funcs vega20_ih_self_irq_funcs = {
516 .process = vega20_ih_self_irq,
517};
518
519static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev)
520{
521 adev->irq.self_irq.num_types = 0;
522 adev->irq.self_irq.funcs = &vega20_ih_self_irq_funcs;
523}
524
525static int vega20_ih_early_init(void *handle)
526{
527 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
528
529 vega20_ih_set_interrupt_funcs(adev);
530 vega20_ih_set_self_irq_funcs(adev);
531 return 0;
532}
533
534static int vega20_ih_sw_init(void *handle)
535{
536 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
537 bool use_bus_addr = true;
538 int r;
539
540 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0,
541 &adev->irq.self_irq);
542 if (r)
543 return r;
544
545 if ((adev->flags & AMD_IS_APU) &&
546 (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2)))
547 use_bus_addr = false;
548
549 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr);
550 if (r)
551 return r;
552
553 adev->irq.ih.use_doorbell = true;
554 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
555
556 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, use_bus_addr);
557 if (r)
558 return r;
559
560 adev->irq.ih1.use_doorbell = true;
561 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
562
563 if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) != IP_VERSION(4, 4, 2)) {
564 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);
565 if (r)
566 return r;
567
568 adev->irq.ih2.use_doorbell = true;
569 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;
570 }
571
572 /* initialize ih control registers offset */
573 vega20_ih_init_register_offset(adev);
574
575 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, use_bus_addr);
576 if (r)
577 return r;
578
579 r = amdgpu_irq_init(adev);
580
581 return r;
582}
583
584static int vega20_ih_sw_fini(void *handle)
585{
586 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
587
588 amdgpu_irq_fini_sw(adev);
589
590 return 0;
591}
592
593static int vega20_ih_hw_init(void *handle)
594{
595 int r;
596 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
597
598 r = vega20_ih_irq_init(adev);
599 if (r)
600 return r;
601
602 return 0;
603}
604
605static int vega20_ih_hw_fini(void *handle)
606{
607 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
608
609 vega20_ih_irq_disable(adev);
610
611 return 0;
612}
613
614static int vega20_ih_suspend(void *handle)
615{
616 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
617
618 return vega20_ih_hw_fini(adev);
619}
620
621static int vega20_ih_resume(void *handle)
622{
623 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
624
625 return vega20_ih_hw_init(adev);
626}
627
628static bool vega20_ih_is_idle(void *handle)
629{
630 /* todo */
631 return true;
632}
633
634static int vega20_ih_wait_for_idle(void *handle)
635{
636 /* todo */
637 return -ETIMEDOUT;
638}
639
640static int vega20_ih_soft_reset(void *handle)
641{
642 /* todo */
643
644 return 0;
645}
646
647static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev,
648 bool enable)
649{
650 uint32_t data, def, field_val;
651
652 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
653 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
654 field_val = enable ? 0 : 1;
655 data = REG_SET_FIELD(data, IH_CLK_CTRL,
656 IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val);
657 data = REG_SET_FIELD(data, IH_CLK_CTRL,
658 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val);
659 data = REG_SET_FIELD(data, IH_CLK_CTRL,
660 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
661 data = REG_SET_FIELD(data, IH_CLK_CTRL,
662 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
663 data = REG_SET_FIELD(data, IH_CLK_CTRL,
664 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
665 data = REG_SET_FIELD(data, IH_CLK_CTRL,
666 DYN_CLK_SOFT_OVERRIDE, field_val);
667 data = REG_SET_FIELD(data, IH_CLK_CTRL,
668 REG_CLK_SOFT_OVERRIDE, field_val);
669 if (def != data)
670 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);
671 }
672}
673
674static int vega20_ih_set_clockgating_state(void *handle,
675 enum amd_clockgating_state state)
676{
677 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
678
679 vega20_ih_update_clockgating_state(adev,
680 state == AMD_CG_STATE_GATE);
681 return 0;
682
683}
684
685static int vega20_ih_set_powergating_state(void *handle,
686 enum amd_powergating_state state)
687{
688 return 0;
689}
690
691const struct amd_ip_funcs vega20_ih_ip_funcs = {
692 .name = "vega20_ih",
693 .early_init = vega20_ih_early_init,
694 .late_init = NULL,
695 .sw_init = vega20_ih_sw_init,
696 .sw_fini = vega20_ih_sw_fini,
697 .hw_init = vega20_ih_hw_init,
698 .hw_fini = vega20_ih_hw_fini,
699 .suspend = vega20_ih_suspend,
700 .resume = vega20_ih_resume,
701 .is_idle = vega20_ih_is_idle,
702 .wait_for_idle = vega20_ih_wait_for_idle,
703 .soft_reset = vega20_ih_soft_reset,
704 .set_clockgating_state = vega20_ih_set_clockgating_state,
705 .set_powergating_state = vega20_ih_set_powergating_state,
706};
707
708static const struct amdgpu_ih_funcs vega20_ih_funcs = {
709 .get_wptr = vega20_ih_get_wptr,
710 .decode_iv = amdgpu_ih_decode_iv_helper,
711 .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper,
712 .set_rptr = vega20_ih_set_rptr
713};
714
715static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev)
716{
717 adev->irq.ih_funcs = &vega20_ih_funcs;
718}
719
720const struct amdgpu_ip_block_version vega20_ih_ip_block = {
721 .type = AMD_IP_BLOCK_TYPE_IH,
722 .major = 4,
723 .minor = 2,
724 .rev = 0,
725 .funcs = &vega20_ih_ip_funcs,
726};
1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/pci.h>
25
26#include "amdgpu.h"
27#include "amdgpu_ih.h"
28#include "soc15.h"
29
30#include "oss/osssys_4_2_0_offset.h"
31#include "oss/osssys_4_2_0_sh_mask.h"
32
33#include "soc15_common.h"
34#include "vega20_ih.h"
35
36#define MAX_REARM_RETRY 10
37
38#define mmIH_CHICKEN_ALDEBARAN 0x18d
39#define mmIH_CHICKEN_ALDEBARAN_BASE_IDX 0
40
41static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev);
42
43/**
44 * vega20_ih_init_register_offset - Initialize register offset for ih rings
45 *
46 * @adev: amdgpu_device pointer
47 *
48 * Initialize register offset ih rings (VEGA20).
49 */
50static void vega20_ih_init_register_offset(struct amdgpu_device *adev)
51{
52 struct amdgpu_ih_regs *ih_regs;
53
54 if (adev->irq.ih.ring_size) {
55 ih_regs = &adev->irq.ih.ih_regs;
56 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
57 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);
58 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
59 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
60 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
61 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);
62 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
63 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);
64 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
65 }
66
67 if (adev->irq.ih1.ring_size) {
68 ih_regs = &adev->irq.ih1.ih_regs;
69 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);
70 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);
71 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
72 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
73 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
74 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);
75 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
76 }
77
78 if (adev->irq.ih2.ring_size) {
79 ih_regs = &adev->irq.ih2.ih_regs;
80 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);
81 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);
82 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
83 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
84 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
85 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);
86 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2;
87 }
88}
89
90/**
91 * vega20_ih_toggle_ring_interrupts - toggle the interrupt ring buffer
92 *
93 * @adev: amdgpu_device pointer
94 * @ih: amdgpu_ih_ring pointer
95 * @enable: true - enable the interrupts, false - disable the interrupts
96 *
97 * Toggle the interrupt ring buffer (VEGA20)
98 */
99static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
100 struct amdgpu_ih_ring *ih,
101 bool enable)
102{
103 struct amdgpu_ih_regs *ih_regs;
104 uint32_t tmp;
105
106 ih_regs = &ih->ih_regs;
107
108 tmp = RREG32(ih_regs->ih_rb_cntl);
109 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
110 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);
111
112 /* enable_intr field is only valid in ring0 */
113 if (ih == &adev->irq.ih)
114 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
115 if (amdgpu_sriov_vf(adev)) {
116 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
117 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
118 return -ETIMEDOUT;
119 }
120 } else {
121 WREG32(ih_regs->ih_rb_cntl, tmp);
122 }
123
124 if (enable) {
125 ih->enabled = true;
126 } else {
127 /* set rptr, wptr to 0 */
128 WREG32(ih_regs->ih_rb_rptr, 0);
129 WREG32(ih_regs->ih_rb_wptr, 0);
130 ih->enabled = false;
131 ih->rptr = 0;
132 }
133
134 return 0;
135}
136
137/**
138 * vega20_ih_toggle_interrupts - Toggle all the available interrupt ring buffers
139 *
140 * @adev: amdgpu_device pointer
141 * @enable: enable or disable interrupt ring buffers
142 *
143 * Toggle all the available interrupt ring buffers (VEGA20).
144 */
145static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable)
146{
147 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
148 int i;
149 int r;
150
151 for (i = 0; i < ARRAY_SIZE(ih); i++) {
152 if (ih[i]->ring_size) {
153 r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable);
154 if (r)
155 return r;
156 }
157 }
158
159 return 0;
160}
161
162static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
163{
164 int rb_bufsz = order_base_2(ih->ring_size / 4);
165
166 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
167 MC_SPACE, ih->use_bus_addr ? 1 : 4);
168 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
169 WPTR_OVERFLOW_CLEAR, 1);
170 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
171 WPTR_OVERFLOW_ENABLE, 1);
172 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
173 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
174 * value is written to memory
175 */
176 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
177 WPTR_WRITEBACK_ENABLE, 1);
178 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
179 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
180 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
181
182 return ih_rb_cntl;
183}
184
185static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
186{
187 u32 ih_doorbell_rtpr = 0;
188
189 if (ih->use_doorbell) {
190 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
191 IH_DOORBELL_RPTR, OFFSET,
192 ih->doorbell_index);
193 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
194 IH_DOORBELL_RPTR,
195 ENABLE, 1);
196 } else {
197 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
198 IH_DOORBELL_RPTR,
199 ENABLE, 0);
200 }
201 return ih_doorbell_rtpr;
202}
203
204/**
205 * vega20_ih_enable_ring - enable an ih ring buffer
206 *
207 * @adev: amdgpu_device pointer
208 * @ih: amdgpu_ih_ring pointer
209 *
210 * Enable an ih ring buffer (VEGA20)
211 */
212static int vega20_ih_enable_ring(struct amdgpu_device *adev,
213 struct amdgpu_ih_ring *ih)
214{
215 struct amdgpu_ih_regs *ih_regs;
216 uint32_t tmp;
217
218 ih_regs = &ih->ih_regs;
219
220 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
221 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
222 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
223
224 tmp = RREG32(ih_regs->ih_rb_cntl);
225 tmp = vega20_ih_rb_cntl(ih, tmp);
226 if (ih == &adev->irq.ih)
227 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
228 if (ih == &adev->irq.ih1)
229 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
230 if (amdgpu_sriov_vf(adev)) {
231 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
232 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
233 return -ETIMEDOUT;
234 }
235 } else {
236 WREG32(ih_regs->ih_rb_cntl, tmp);
237 }
238
239 if (ih == &adev->irq.ih) {
240 /* set the ih ring 0 writeback address whether it's enabled or not */
241 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
242 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
243 }
244
245 /* set rptr, wptr to 0 */
246 WREG32(ih_regs->ih_rb_wptr, 0);
247 WREG32(ih_regs->ih_rb_rptr, 0);
248
249 WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih));
250
251 return 0;
252}
253
254/**
255 * vega20_ih_reroute_ih - reroute VMC/UTCL2 ih to an ih ring
256 *
257 * @adev: amdgpu_device pointer
258 *
259 * Reroute VMC and UMC interrupts on primary ih ring to
260 * ih ring 1 so they won't lose when bunches of page faults
261 * interrupts overwhelms the interrupt handler(VEGA20)
262 */
263static void vega20_ih_reroute_ih(struct amdgpu_device *adev)
264{
265 uint32_t tmp;
266
267 /* vega20 ih reroute will go through psp this
268 * function is used for newer asics starting arcturus
269 */
270 if (adev->ip_versions[OSSSYS_HWIP][0] >= IP_VERSION(4, 2, 1)) {
271 /* Reroute to IH ring 1 for VMC */
272 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12);
273 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);
274 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
275 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
276 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);
277
278 /* Reroute IH ring 1 for UTCL2 */
279 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B);
280 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);
281 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
282 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);
283 }
284}
285
286/**
287 * vega20_ih_irq_init - init and enable the interrupt ring
288 *
289 * @adev: amdgpu_device pointer
290 *
291 * Allocate a ring buffer for the interrupt controller,
292 * enable the RLC, disable interrupts, enable the IH
293 * ring buffer and enable it (VI).
294 * Called at device load and reume.
295 * Returns 0 for success, errors for failure.
296 */
297static int vega20_ih_irq_init(struct amdgpu_device *adev)
298{
299 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
300 u32 ih_chicken;
301 int ret;
302 int i;
303
304 /* disable irqs */
305 ret = vega20_ih_toggle_interrupts(adev, false);
306 if (ret)
307 return ret;
308
309 adev->nbio.funcs->ih_control(adev);
310
311 if ((adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 2, 1)) &&
312 adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
313 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
314 if (adev->irq.ih.use_bus_addr) {
315 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
316 MC_SPACE_GPA_ENABLE, 1);
317 }
318 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
319 }
320
321 /* psp firmware won't program IH_CHICKEN for aldebaran
322 * driver needs to program it properly according to
323 * MC_SPACE type in IH_RB_CNTL */
324 if (adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 0)) {
325 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN);
326 if (adev->irq.ih.use_bus_addr) {
327 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
328 MC_SPACE_GPA_ENABLE, 1);
329 }
330 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN, ih_chicken);
331 }
332
333 for (i = 0; i < ARRAY_SIZE(ih); i++) {
334 if (ih[i]->ring_size) {
335 if (i == 1)
336 vega20_ih_reroute_ih(adev);
337 ret = vega20_ih_enable_ring(adev, ih[i]);
338 if (ret)
339 return ret;
340 }
341 }
342
343 if (!amdgpu_sriov_vf(adev))
344 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
345 adev->irq.ih.doorbell_index);
346
347 pci_set_master(adev->pdev);
348
349 /* enable interrupts */
350 ret = vega20_ih_toggle_interrupts(adev, true);
351 if (ret)
352 return ret;
353
354 if (adev->irq.ih_soft.ring_size)
355 adev->irq.ih_soft.enabled = true;
356
357 return 0;
358}
359
360/**
361 * vega20_ih_irq_disable - disable interrupts
362 *
363 * @adev: amdgpu_device pointer
364 *
365 * Disable interrupts on the hw (VEGA20).
366 */
367static void vega20_ih_irq_disable(struct amdgpu_device *adev)
368{
369 vega20_ih_toggle_interrupts(adev, false);
370
371 /* Wait and acknowledge irq */
372 mdelay(1);
373}
374
375/**
376 * vega20_ih_get_wptr - get the IH ring buffer wptr
377 *
378 * @adev: amdgpu_device pointer
379 * @ih: amdgpu_ih_ring pointer
380 *
381 * Get the IH ring buffer wptr from either the register
382 * or the writeback memory buffer (VEGA20). Also check for
383 * ring buffer overflow and deal with it.
384 * Returns the value of the wptr.
385 */
386static u32 vega20_ih_get_wptr(struct amdgpu_device *adev,
387 struct amdgpu_ih_ring *ih)
388{
389 u32 wptr, tmp;
390 struct amdgpu_ih_regs *ih_regs;
391
392 if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) {
393 /* Only ring0 supports writeback. On other rings fall back
394 * to register-based code with overflow checking below.
395 * ih_soft ring doesn't have any backing hardware registers,
396 * update wptr and return.
397 */
398 wptr = le32_to_cpu(*ih->wptr_cpu);
399
400 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
401 goto out;
402 }
403
404 ih_regs = &ih->ih_regs;
405
406 /* Double check that the overflow wasn't already cleared. */
407 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
408 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
409 goto out;
410
411 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
412
413 /* When a ring buffer overflow happen start parsing interrupt
414 * from the last not overwritten vector (wptr + 32). Hopefully
415 * this should allow us to catchup.
416 */
417 tmp = (wptr + 32) & ih->ptr_mask;
418 dev_warn(adev->dev, "IH ring buffer overflow "
419 "(0x%08X, 0x%08X, 0x%08X)\n",
420 wptr, ih->rptr, tmp);
421 ih->rptr = tmp;
422
423 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
424 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
425 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
426
427out:
428 return (wptr & ih->ptr_mask);
429}
430
431/**
432 * vega20_ih_irq_rearm - rearm IRQ if lost
433 *
434 * @adev: amdgpu_device pointer
435 * @ih: amdgpu_ih_ring pointer
436 *
437 */
438static void vega20_ih_irq_rearm(struct amdgpu_device *adev,
439 struct amdgpu_ih_ring *ih)
440{
441 uint32_t v = 0;
442 uint32_t i = 0;
443 struct amdgpu_ih_regs *ih_regs;
444
445 ih_regs = &ih->ih_regs;
446
447 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */
448 for (i = 0; i < MAX_REARM_RETRY; i++) {
449 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
450 if ((v < ih->ring_size) && (v != ih->rptr))
451 WDOORBELL32(ih->doorbell_index, ih->rptr);
452 else
453 break;
454 }
455}
456
457/**
458 * vega20_ih_set_rptr - set the IH ring buffer rptr
459 *
460 * @adev: amdgpu_device pointer
461 * @ih: amdgpu_ih_ring pointer
462 *
463 * Set the IH ring buffer rptr.
464 */
465static void vega20_ih_set_rptr(struct amdgpu_device *adev,
466 struct amdgpu_ih_ring *ih)
467{
468 struct amdgpu_ih_regs *ih_regs;
469
470 if (ih == &adev->irq.ih_soft)
471 return;
472
473 if (ih->use_doorbell) {
474 /* XXX check if swapping is necessary on BE */
475 *ih->rptr_cpu = ih->rptr;
476 WDOORBELL32(ih->doorbell_index, ih->rptr);
477
478 if (amdgpu_sriov_vf(adev))
479 vega20_ih_irq_rearm(adev, ih);
480 } else {
481 ih_regs = &ih->ih_regs;
482 WREG32(ih_regs->ih_rb_rptr, ih->rptr);
483 }
484}
485
486/**
487 * vega20_ih_self_irq - dispatch work for ring 1 and 2
488 *
489 * @adev: amdgpu_device pointer
490 * @source: irq source
491 * @entry: IV with WPTR update
492 *
493 * Update the WPTR from the IV and schedule work to handle the entries.
494 */
495static int vega20_ih_self_irq(struct amdgpu_device *adev,
496 struct amdgpu_irq_src *source,
497 struct amdgpu_iv_entry *entry)
498{
499 switch (entry->ring_id) {
500 case 1:
501 schedule_work(&adev->irq.ih1_work);
502 break;
503 case 2:
504 schedule_work(&adev->irq.ih2_work);
505 break;
506 default: break;
507 }
508 return 0;
509}
510
511static const struct amdgpu_irq_src_funcs vega20_ih_self_irq_funcs = {
512 .process = vega20_ih_self_irq,
513};
514
515static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev)
516{
517 adev->irq.self_irq.num_types = 0;
518 adev->irq.self_irq.funcs = &vega20_ih_self_irq_funcs;
519}
520
521static int vega20_ih_early_init(void *handle)
522{
523 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
524
525 vega20_ih_set_interrupt_funcs(adev);
526 vega20_ih_set_self_irq_funcs(adev);
527 return 0;
528}
529
530static int vega20_ih_sw_init(void *handle)
531{
532 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
533 int r;
534
535 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0,
536 &adev->irq.self_irq);
537 if (r)
538 return r;
539
540 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true);
541 if (r)
542 return r;
543
544 adev->irq.ih.use_doorbell = true;
545 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
546
547 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true);
548 if (r)
549 return r;
550
551 adev->irq.ih1.use_doorbell = true;
552 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
553
554 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);
555 if (r)
556 return r;
557
558 adev->irq.ih2.use_doorbell = true;
559 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;
560
561 /* initialize ih control registers offset */
562 vega20_ih_init_register_offset(adev);
563
564 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true);
565 if (r)
566 return r;
567
568 r = amdgpu_irq_init(adev);
569
570 return r;
571}
572
573static int vega20_ih_sw_fini(void *handle)
574{
575 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
576
577 amdgpu_irq_fini_sw(adev);
578
579 return 0;
580}
581
582static int vega20_ih_hw_init(void *handle)
583{
584 int r;
585 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
586
587 r = vega20_ih_irq_init(adev);
588 if (r)
589 return r;
590
591 return 0;
592}
593
594static int vega20_ih_hw_fini(void *handle)
595{
596 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
597
598 vega20_ih_irq_disable(adev);
599
600 return 0;
601}
602
603static int vega20_ih_suspend(void *handle)
604{
605 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
606
607 return vega20_ih_hw_fini(adev);
608}
609
610static int vega20_ih_resume(void *handle)
611{
612 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
613
614 return vega20_ih_hw_init(adev);
615}
616
617static bool vega20_ih_is_idle(void *handle)
618{
619 /* todo */
620 return true;
621}
622
623static int vega20_ih_wait_for_idle(void *handle)
624{
625 /* todo */
626 return -ETIMEDOUT;
627}
628
629static int vega20_ih_soft_reset(void *handle)
630{
631 /* todo */
632
633 return 0;
634}
635
636static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev,
637 bool enable)
638{
639 uint32_t data, def, field_val;
640
641 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
642 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
643 field_val = enable ? 0 : 1;
644 data = REG_SET_FIELD(data, IH_CLK_CTRL,
645 IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val);
646 data = REG_SET_FIELD(data, IH_CLK_CTRL,
647 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val);
648 data = REG_SET_FIELD(data, IH_CLK_CTRL,
649 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
650 data = REG_SET_FIELD(data, IH_CLK_CTRL,
651 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
652 data = REG_SET_FIELD(data, IH_CLK_CTRL,
653 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
654 data = REG_SET_FIELD(data, IH_CLK_CTRL,
655 DYN_CLK_SOFT_OVERRIDE, field_val);
656 data = REG_SET_FIELD(data, IH_CLK_CTRL,
657 REG_CLK_SOFT_OVERRIDE, field_val);
658 if (def != data)
659 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);
660 }
661}
662
663static int vega20_ih_set_clockgating_state(void *handle,
664 enum amd_clockgating_state state)
665{
666 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
667
668 vega20_ih_update_clockgating_state(adev,
669 state == AMD_CG_STATE_GATE);
670 return 0;
671
672}
673
674static int vega20_ih_set_powergating_state(void *handle,
675 enum amd_powergating_state state)
676{
677 return 0;
678}
679
680const struct amd_ip_funcs vega20_ih_ip_funcs = {
681 .name = "vega20_ih",
682 .early_init = vega20_ih_early_init,
683 .late_init = NULL,
684 .sw_init = vega20_ih_sw_init,
685 .sw_fini = vega20_ih_sw_fini,
686 .hw_init = vega20_ih_hw_init,
687 .hw_fini = vega20_ih_hw_fini,
688 .suspend = vega20_ih_suspend,
689 .resume = vega20_ih_resume,
690 .is_idle = vega20_ih_is_idle,
691 .wait_for_idle = vega20_ih_wait_for_idle,
692 .soft_reset = vega20_ih_soft_reset,
693 .set_clockgating_state = vega20_ih_set_clockgating_state,
694 .set_powergating_state = vega20_ih_set_powergating_state,
695};
696
697static const struct amdgpu_ih_funcs vega20_ih_funcs = {
698 .get_wptr = vega20_ih_get_wptr,
699 .decode_iv = amdgpu_ih_decode_iv_helper,
700 .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper,
701 .set_rptr = vega20_ih_set_rptr
702};
703
704static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev)
705{
706 adev->irq.ih_funcs = &vega20_ih_funcs;
707}
708
709const struct amdgpu_ip_block_version vega20_ih_ip_block =
710{
711 .type = AMD_IP_BLOCK_TYPE_IH,
712 .major = 4,
713 .minor = 2,
714 .rev = 0,
715 .funcs = &vega20_ih_ip_funcs,
716};