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1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/delay.h>
25#include <linux/firmware.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28
29#include "amdgpu.h"
30#include "amdgpu_ucode.h"
31#include "amdgpu_trace.h"
32
33#include "gc/gc_11_0_0_offset.h"
34#include "gc/gc_11_0_0_sh_mask.h"
35#include "gc/gc_11_0_0_default.h"
36#include "hdp/hdp_6_0_0_offset.h"
37#include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
38
39#include "soc15_common.h"
40#include "soc15.h"
41#include "sdma_v6_0_0_pkt_open.h"
42#include "nbio_v4_3.h"
43#include "sdma_common.h"
44#include "sdma_v6_0.h"
45#include "v11_structs.h"
46
47MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin");
48MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin");
49MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin");
50MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin");
51MODULE_FIRMWARE("amdgpu/sdma_6_1_0.bin");
52
53#define SDMA1_REG_OFFSET 0x600
54#define SDMA0_HYP_DEC_REG_START 0x5880
55#define SDMA0_HYP_DEC_REG_END 0x589a
56#define SDMA1_HYP_DEC_REG_OFFSET 0x20
57
58static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev);
59static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev);
60static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev);
61static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev);
62static int sdma_v6_0_start(struct amdgpu_device *adev);
63
64static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
65{
66 u32 base;
67
68 if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
69 internal_offset <= SDMA0_HYP_DEC_REG_END) {
70 base = adev->reg_offset[GC_HWIP][0][1];
71 if (instance != 0)
72 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
73 } else {
74 base = adev->reg_offset[GC_HWIP][0][0];
75 if (instance == 1)
76 internal_offset += SDMA1_REG_OFFSET;
77 }
78
79 return base + internal_offset;
80}
81
82static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring)
83{
84 unsigned ret;
85
86 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE));
87 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
88 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
89 amdgpu_ring_write(ring, 1);
90 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
91 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
92
93 return ret;
94}
95
96static void sdma_v6_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
97 unsigned offset)
98{
99 unsigned cur;
100
101 BUG_ON(offset > ring->buf_mask);
102 BUG_ON(ring->ring[offset] != 0x55aa55aa);
103
104 cur = (ring->wptr - 1) & ring->buf_mask;
105 if (cur > offset)
106 ring->ring[offset] = cur - offset;
107 else
108 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
109}
110
111/**
112 * sdma_v6_0_ring_get_rptr - get the current read pointer
113 *
114 * @ring: amdgpu ring pointer
115 *
116 * Get the current rptr from the hardware.
117 */
118static uint64_t sdma_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
119{
120 u64 *rptr;
121
122 /* XXX check if swapping is necessary on BE */
123 rptr = (u64 *)ring->rptr_cpu_addr;
124
125 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
126 return ((*rptr) >> 2);
127}
128
129/**
130 * sdma_v6_0_ring_get_wptr - get the current write pointer
131 *
132 * @ring: amdgpu ring pointer
133 *
134 * Get the current wptr from the hardware.
135 */
136static uint64_t sdma_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
137{
138 u64 wptr = 0;
139
140 if (ring->use_doorbell) {
141 /* XXX check if swapping is necessary on BE */
142 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
143 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
144 }
145
146 return wptr >> 2;
147}
148
149/**
150 * sdma_v6_0_ring_set_wptr - commit the write pointer
151 *
152 * @ring: amdgpu ring pointer
153 *
154 * Write the wptr back to the hardware.
155 */
156static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
157{
158 struct amdgpu_device *adev = ring->adev;
159
160 if (ring->use_doorbell) {
161 DRM_DEBUG("Using doorbell -- "
162 "wptr_offs == 0x%08x "
163 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
164 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
165 ring->wptr_offs,
166 lower_32_bits(ring->wptr << 2),
167 upper_32_bits(ring->wptr << 2));
168 /* XXX check if swapping is necessary on BE */
169 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
170 ring->wptr << 2);
171 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
172 ring->doorbell_index, ring->wptr << 2);
173 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
174 } else {
175 DRM_DEBUG("Not using doorbell -- "
176 "regSDMA%i_GFX_RB_WPTR == 0x%08x "
177 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
178 ring->me,
179 lower_32_bits(ring->wptr << 2),
180 ring->me,
181 upper_32_bits(ring->wptr << 2));
182 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,
183 ring->me, regSDMA0_QUEUE0_RB_WPTR),
184 lower_32_bits(ring->wptr << 2));
185 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,
186 ring->me, regSDMA0_QUEUE0_RB_WPTR_HI),
187 upper_32_bits(ring->wptr << 2));
188 }
189}
190
191static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
192{
193 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
194 int i;
195
196 for (i = 0; i < count; i++)
197 if (sdma && sdma->burst_nop && (i == 0))
198 amdgpu_ring_write(ring, ring->funcs->nop |
199 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
200 else
201 amdgpu_ring_write(ring, ring->funcs->nop);
202}
203
204/*
205 * sdma_v6_0_ring_emit_ib - Schedule an IB on the DMA engine
206 *
207 * @ring: amdgpu ring pointer
208 * @ib: IB object to schedule
209 * @flags: unused
210 * @job: job to retrieve vmid from
211 *
212 * Schedule an IB in the DMA ring.
213 */
214static void sdma_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
215 struct amdgpu_job *job,
216 struct amdgpu_ib *ib,
217 uint32_t flags)
218{
219 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
220 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
221
222 /* An IB packet must end on a 8 DW boundary--the next dword
223 * must be on a 8-dword boundary. Our IB packet below is 6
224 * dwords long, thus add x number of NOPs, such that, in
225 * modular arithmetic,
226 * wptr + 6 + x = 8k, k >= 0, which in C is,
227 * (wptr + 6 + x) % 8 = 0.
228 * The expression below, is a solution of x.
229 */
230 sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
231
232 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) |
233 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
234 /* base must be 32 byte aligned */
235 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
236 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
237 amdgpu_ring_write(ring, ib->length_dw);
238 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
239 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
240}
241
242/**
243 * sdma_v6_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
244 *
245 * @ring: amdgpu ring pointer
246 *
247 * flush the IB by graphics cache rinse.
248 */
249static void sdma_v6_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
250{
251 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
252 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
253 SDMA_GCR_GLI_INV(1);
254
255 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
256 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ));
257 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
258 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
259 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
260 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
261 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
262 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
263 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
264}
265
266
267/**
268 * sdma_v6_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
269 *
270 * @ring: amdgpu ring pointer
271 *
272 * Emit an hdp flush packet on the requested DMA ring.
273 */
274static void sdma_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
275{
276 struct amdgpu_device *adev = ring->adev;
277 u32 ref_and_mask = 0;
278 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
279
280 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
281
282 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
283 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
284 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
285 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
286 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
287 amdgpu_ring_write(ring, ref_and_mask); /* reference */
288 amdgpu_ring_write(ring, ref_and_mask); /* mask */
289 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
290 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
291}
292
293/**
294 * sdma_v6_0_ring_emit_fence - emit a fence on the DMA ring
295 *
296 * @ring: amdgpu ring pointer
297 * @addr: address
298 * @seq: fence seq number
299 * @flags: fence flags
300 *
301 * Add a DMA fence packet to the ring to write
302 * the fence seq number and DMA trap packet to generate
303 * an interrupt if needed.
304 */
305static void sdma_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
306 unsigned flags)
307{
308 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
309 /* write the fence */
310 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
311 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
312 /* zero in first two bits */
313 BUG_ON(addr & 0x3);
314 amdgpu_ring_write(ring, lower_32_bits(addr));
315 amdgpu_ring_write(ring, upper_32_bits(addr));
316 amdgpu_ring_write(ring, lower_32_bits(seq));
317
318 /* optionally write high bits as well */
319 if (write64bit) {
320 addr += 4;
321 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
322 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
323 /* zero in first two bits */
324 BUG_ON(addr & 0x3);
325 amdgpu_ring_write(ring, lower_32_bits(addr));
326 amdgpu_ring_write(ring, upper_32_bits(addr));
327 amdgpu_ring_write(ring, upper_32_bits(seq));
328 }
329
330 if (flags & AMDGPU_FENCE_FLAG_INT) {
331 uint32_t ctx = ring->is_mes_queue ?
332 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
333 /* generate an interrupt */
334 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP));
335 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
336 }
337}
338
339/**
340 * sdma_v6_0_gfx_stop - stop the gfx async dma engines
341 *
342 * @adev: amdgpu_device pointer
343 *
344 * Stop the gfx async dma ring buffers.
345 */
346static void sdma_v6_0_gfx_stop(struct amdgpu_device *adev)
347{
348 u32 rb_cntl, ib_cntl;
349 int i;
350
351 for (i = 0; i < adev->sdma.num_instances; i++) {
352 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
353 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0);
354 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
355 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
356 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0);
357 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
358 }
359}
360
361/**
362 * sdma_v6_0_rlc_stop - stop the compute async dma engines
363 *
364 * @adev: amdgpu_device pointer
365 *
366 * Stop the compute async dma queues.
367 */
368static void sdma_v6_0_rlc_stop(struct amdgpu_device *adev)
369{
370 /* XXX todo */
371}
372
373/**
374 * sdma_v6_0_ctxempty_int_enable - enable or disable context empty interrupts
375 *
376 * @adev: amdgpu_device pointer
377 * @enable: enable/disable context switching due to queue empty conditions
378 *
379 * Enable or disable the async dma engines queue empty context switch.
380 */
381static void sdma_v6_0_ctxempty_int_enable(struct amdgpu_device *adev, bool enable)
382{
383 u32 f32_cntl;
384 int i;
385
386 if (!amdgpu_sriov_vf(adev)) {
387 for (i = 0; i < adev->sdma.num_instances; i++) {
388 f32_cntl = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL));
389 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
390 CTXEMPTY_INT_ENABLE, enable ? 1 : 0);
391 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL), f32_cntl);
392 }
393 }
394}
395
396/**
397 * sdma_v6_0_enable - stop the async dma engines
398 *
399 * @adev: amdgpu_device pointer
400 * @enable: enable/disable the DMA MEs.
401 *
402 * Halt or unhalt the async dma engines.
403 */
404static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable)
405{
406 u32 f32_cntl;
407 int i;
408
409 if (!enable) {
410 sdma_v6_0_gfx_stop(adev);
411 sdma_v6_0_rlc_stop(adev);
412 }
413
414 if (amdgpu_sriov_vf(adev))
415 return;
416
417 for (i = 0; i < adev->sdma.num_instances; i++) {
418 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
419 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
420 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl);
421 }
422}
423
424/**
425 * sdma_v6_0_gfx_resume - setup and start the async dma engines
426 *
427 * @adev: amdgpu_device pointer
428 *
429 * Set up the gfx DMA ring buffers and enable them.
430 * Returns 0 for success, error for failure.
431 */
432static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)
433{
434 struct amdgpu_ring *ring;
435 u32 rb_cntl, ib_cntl;
436 u32 rb_bufsz;
437 u32 doorbell;
438 u32 doorbell_offset;
439 u32 temp;
440 u64 wptr_gpu_addr;
441 int i, r;
442
443 for (i = 0; i < adev->sdma.num_instances; i++) {
444 ring = &adev->sdma.instance[i].ring;
445
446 if (!amdgpu_sriov_vf(adev))
447 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
448
449 /* Set ring buffer size in dwords */
450 rb_bufsz = order_base_2(ring->ring_size / 4);
451 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
452 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);
453#ifdef __BIG_ENDIAN
454 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1);
455 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL,
456 RPTR_WRITEBACK_SWAP_ENABLE, 1);
457#endif
458 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1);
459 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
460
461 /* Initialize the ring buffer's read and write pointers */
462 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);
463 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);
464 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);
465 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);
466
467 /* setup the wptr shadow polling */
468 wptr_gpu_addr = ring->wptr_gpu_addr;
469 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),
470 lower_32_bits(wptr_gpu_addr));
471 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),
472 upper_32_bits(wptr_gpu_addr));
473
474 /* set the wb address whether it's enabled or not */
475 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),
476 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
477 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),
478 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
479
480 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
481 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);
482 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1);
483
484 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
485 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);
486
487 ring->wptr = 0;
488
489 /* before programing wptr to a less value, need set minor_ptr_update first */
490 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);
491
492 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
493 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);
494 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
495 }
496
497 doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));
498 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET));
499
500 if (ring->use_doorbell) {
501 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
502 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET,
503 OFFSET, ring->doorbell_index);
504 } else {
505 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);
506 }
507 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);
508 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);
509
510 if (i == 0)
511 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
512 ring->doorbell_index,
513 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances);
514
515 if (amdgpu_sriov_vf(adev))
516 sdma_v6_0_ring_set_wptr(ring);
517
518 /* set minor_ptr_update to 0 after wptr programed */
519 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);
520
521 /* Set up RESP_MODE to non-copy addresses */
522 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));
523 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
524 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
525 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);
526
527 /* program default cache read and write policy */
528 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));
529 /* clean read policy and write policy bits */
530 temp &= 0xFF0FFF;
531 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
532 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
533 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
534 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);
535
536 if (!amdgpu_sriov_vf(adev)) {
537 /* unhalt engine */
538 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
539 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
540 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0);
541 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp);
542 }
543
544 /* enable DMA RB */
545 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1);
546 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
547
548 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
549 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1);
550#ifdef __BIG_ENDIAN
551 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1);
552#endif
553 /* enable DMA IBs */
554 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
555
556 if (amdgpu_sriov_vf(adev))
557 sdma_v6_0_enable(adev, true);
558
559 r = amdgpu_ring_test_helper(ring);
560 if (r)
561 return r;
562 }
563
564 return 0;
565}
566
567/**
568 * sdma_v6_0_rlc_resume - setup and start the async dma engines
569 *
570 * @adev: amdgpu_device pointer
571 *
572 * Set up the compute DMA queues and enable them.
573 * Returns 0 for success, error for failure.
574 */
575static int sdma_v6_0_rlc_resume(struct amdgpu_device *adev)
576{
577 return 0;
578}
579
580/**
581 * sdma_v6_0_load_microcode - load the sDMA ME ucode
582 *
583 * @adev: amdgpu_device pointer
584 *
585 * Loads the sDMA0/1 ucode.
586 * Returns 0 for success, -EINVAL if the ucode is not available.
587 */
588static int sdma_v6_0_load_microcode(struct amdgpu_device *adev)
589{
590 const struct sdma_firmware_header_v2_0 *hdr;
591 const __le32 *fw_data;
592 u32 fw_size;
593 int i, j;
594 bool use_broadcast;
595
596 /* halt the MEs */
597 sdma_v6_0_enable(adev, false);
598
599 if (!adev->sdma.instance[0].fw)
600 return -EINVAL;
601
602 /* use broadcast mode to load SDMA microcode by default */
603 use_broadcast = true;
604
605 if (use_broadcast) {
606 dev_info(adev->dev, "Use broadcast method to load SDMA firmware\n");
607 /* load Control Thread microcode */
608 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;
609 amdgpu_ucode_print_sdma_hdr(&hdr->header);
610 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4;
611
612 fw_data = (const __le32 *)
613 (adev->sdma.instance[0].fw->data +
614 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
615
616 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0);
617
618 for (j = 0; j < fw_size; j++) {
619 if (amdgpu_emu_mode == 1 && j % 500 == 0)
620 msleep(1);
621 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));
622 }
623
624 /* load Context Switch microcode */
625 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4;
626
627 fw_data = (const __le32 *)
628 (adev->sdma.instance[0].fw->data +
629 le32_to_cpu(hdr->ctl_ucode_offset));
630
631 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000);
632
633 for (j = 0; j < fw_size; j++) {
634 if (amdgpu_emu_mode == 1 && j % 500 == 0)
635 msleep(1);
636 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));
637 }
638 } else {
639 dev_info(adev->dev, "Use legacy method to load SDMA firmware\n");
640 for (i = 0; i < adev->sdma.num_instances; i++) {
641 /* load Control Thread microcode */
642 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;
643 amdgpu_ucode_print_sdma_hdr(&hdr->header);
644 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4;
645
646 fw_data = (const __le32 *)
647 (adev->sdma.instance[0].fw->data +
648 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
649
650 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0);
651
652 for (j = 0; j < fw_size; j++) {
653 if (amdgpu_emu_mode == 1 && j % 500 == 0)
654 msleep(1);
655 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
656 }
657
658 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
659
660 /* load Context Switch microcode */
661 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4;
662
663 fw_data = (const __le32 *)
664 (adev->sdma.instance[0].fw->data +
665 le32_to_cpu(hdr->ctl_ucode_offset));
666
667 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000);
668
669 for (j = 0; j < fw_size; j++) {
670 if (amdgpu_emu_mode == 1 && j % 500 == 0)
671 msleep(1);
672 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
673 }
674
675 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
676 }
677 }
678
679 return 0;
680}
681
682static int sdma_v6_0_soft_reset(void *handle)
683{
684 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
685 u32 tmp;
686 int i;
687
688 sdma_v6_0_gfx_stop(adev);
689
690 for (i = 0; i < adev->sdma.num_instances; i++) {
691 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE));
692 tmp |= SDMA0_FREEZE__FREEZE_MASK;
693 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp);
694 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
695 tmp |= SDMA0_F32_CNTL__HALT_MASK;
696 tmp |= SDMA0_F32_CNTL__TH1_RESET_MASK;
697 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp);
698
699 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0);
700
701 udelay(100);
702
703 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i;
704 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
705 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
706
707 udelay(100);
708
709 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0);
710 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
711
712 udelay(100);
713 }
714
715 return sdma_v6_0_start(adev);
716}
717
718static bool sdma_v6_0_check_soft_reset(void *handle)
719{
720 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
721 struct amdgpu_ring *ring;
722 int i, r;
723 long tmo = msecs_to_jiffies(1000);
724
725 for (i = 0; i < adev->sdma.num_instances; i++) {
726 ring = &adev->sdma.instance[i].ring;
727 r = amdgpu_ring_test_ib(ring, tmo);
728 if (r)
729 return true;
730 }
731
732 return false;
733}
734
735/**
736 * sdma_v6_0_start - setup and start the async dma engines
737 *
738 * @adev: amdgpu_device pointer
739 *
740 * Set up the DMA engines and enable them.
741 * Returns 0 for success, error for failure.
742 */
743static int sdma_v6_0_start(struct amdgpu_device *adev)
744{
745 int r = 0;
746
747 if (amdgpu_sriov_vf(adev)) {
748 sdma_v6_0_enable(adev, false);
749
750 /* set RB registers */
751 r = sdma_v6_0_gfx_resume(adev);
752 return r;
753 }
754
755 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
756 r = sdma_v6_0_load_microcode(adev);
757 if (r)
758 return r;
759
760 /* The value of regSDMA_F32_CNTL is invalid the moment after loading fw */
761 if (amdgpu_emu_mode == 1)
762 msleep(1000);
763 }
764
765 /* unhalt the MEs */
766 sdma_v6_0_enable(adev, true);
767 /* enable sdma ring preemption */
768 sdma_v6_0_ctxempty_int_enable(adev, true);
769
770 /* start the gfx rings and rlc compute queues */
771 r = sdma_v6_0_gfx_resume(adev);
772 if (r)
773 return r;
774 r = sdma_v6_0_rlc_resume(adev);
775
776 return r;
777}
778
779static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, void *mqd,
780 struct amdgpu_mqd_prop *prop)
781{
782 struct v11_sdma_mqd *m = mqd;
783 uint64_t wb_gpu_addr;
784
785 m->sdmax_rlcx_rb_cntl =
786 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT |
787 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
788 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
789 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT;
790
791 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
792 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
793
794 wb_gpu_addr = prop->wptr_gpu_addr;
795 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
796 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
797
798 wb_gpu_addr = prop->rptr_gpu_addr;
799 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
800 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
801
802 m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0,
803 regSDMA0_QUEUE0_IB_CNTL));
804
805 m->sdmax_rlcx_doorbell_offset =
806 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT;
807
808 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
809
810 m->sdmax_rlcx_skip_cntl = 0;
811 m->sdmax_rlcx_context_status = 0;
812 m->sdmax_rlcx_doorbell_log = 0;
813
814 m->sdmax_rlcx_rb_aql_cntl = regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT;
815 m->sdmax_rlcx_dummy_reg = regSDMA0_QUEUE0_DUMMY_REG_DEFAULT;
816
817 return 0;
818}
819
820static void sdma_v6_0_set_mqd_funcs(struct amdgpu_device *adev)
821{
822 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v11_sdma_mqd);
823 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v6_0_mqd_init;
824}
825
826/**
827 * sdma_v6_0_ring_test_ring - simple async dma engine test
828 *
829 * @ring: amdgpu_ring structure holding ring information
830 *
831 * Test the DMA engine by writing using it to write an
832 * value to memory.
833 * Returns 0 for success, error for failure.
834 */
835static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring)
836{
837 struct amdgpu_device *adev = ring->adev;
838 unsigned i;
839 unsigned index;
840 int r;
841 u32 tmp;
842 u64 gpu_addr;
843 volatile uint32_t *cpu_ptr = NULL;
844
845 tmp = 0xCAFEDEAD;
846
847 if (ring->is_mes_queue) {
848 uint32_t offset = 0;
849 offset = amdgpu_mes_ctx_get_offs(ring,
850 AMDGPU_MES_CTX_PADDING_OFFS);
851 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
852 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
853 *cpu_ptr = tmp;
854 } else {
855 r = amdgpu_device_wb_get(adev, &index);
856 if (r) {
857 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
858 return r;
859 }
860
861 gpu_addr = adev->wb.gpu_addr + (index * 4);
862 adev->wb.wb[index] = cpu_to_le32(tmp);
863 }
864
865 r = amdgpu_ring_alloc(ring, 5);
866 if (r) {
867 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
868 amdgpu_device_wb_free(adev, index);
869 return r;
870 }
871
872 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
873 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
874 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
875 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
876 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
877 amdgpu_ring_write(ring, 0xDEADBEEF);
878 amdgpu_ring_commit(ring);
879
880 for (i = 0; i < adev->usec_timeout; i++) {
881 if (ring->is_mes_queue)
882 tmp = le32_to_cpu(*cpu_ptr);
883 else
884 tmp = le32_to_cpu(adev->wb.wb[index]);
885 if (tmp == 0xDEADBEEF)
886 break;
887 if (amdgpu_emu_mode == 1)
888 msleep(1);
889 else
890 udelay(1);
891 }
892
893 if (i >= adev->usec_timeout)
894 r = -ETIMEDOUT;
895
896 if (!ring->is_mes_queue)
897 amdgpu_device_wb_free(adev, index);
898
899 return r;
900}
901
902/*
903 * sdma_v6_0_ring_test_ib - test an IB on the DMA engine
904 *
905 * @ring: amdgpu_ring structure holding ring information
906 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
907 *
908 * Test a simple IB in the DMA ring.
909 * Returns 0 on success, error on failure.
910 */
911static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
912{
913 struct amdgpu_device *adev = ring->adev;
914 struct amdgpu_ib ib;
915 struct dma_fence *f = NULL;
916 unsigned index;
917 long r;
918 u32 tmp = 0;
919 u64 gpu_addr;
920 volatile uint32_t *cpu_ptr = NULL;
921
922 tmp = 0xCAFEDEAD;
923 memset(&ib, 0, sizeof(ib));
924
925 if (ring->is_mes_queue) {
926 uint32_t offset = 0;
927 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
928 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
929 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
930
931 offset = amdgpu_mes_ctx_get_offs(ring,
932 AMDGPU_MES_CTX_PADDING_OFFS);
933 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
934 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
935 *cpu_ptr = tmp;
936 } else {
937 r = amdgpu_device_wb_get(adev, &index);
938 if (r) {
939 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
940 return r;
941 }
942
943 gpu_addr = adev->wb.gpu_addr + (index * 4);
944 adev->wb.wb[index] = cpu_to_le32(tmp);
945
946 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
947 if (r) {
948 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
949 goto err0;
950 }
951 }
952
953 ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
954 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
955 ib.ptr[1] = lower_32_bits(gpu_addr);
956 ib.ptr[2] = upper_32_bits(gpu_addr);
957 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
958 ib.ptr[4] = 0xDEADBEEF;
959 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
960 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
961 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
962 ib.length_dw = 8;
963
964 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
965 if (r)
966 goto err1;
967
968 r = dma_fence_wait_timeout(f, false, timeout);
969 if (r == 0) {
970 DRM_ERROR("amdgpu: IB test timed out\n");
971 r = -ETIMEDOUT;
972 goto err1;
973 } else if (r < 0) {
974 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
975 goto err1;
976 }
977
978 if (ring->is_mes_queue)
979 tmp = le32_to_cpu(*cpu_ptr);
980 else
981 tmp = le32_to_cpu(adev->wb.wb[index]);
982
983 if (tmp == 0xDEADBEEF)
984 r = 0;
985 else
986 r = -EINVAL;
987
988err1:
989 amdgpu_ib_free(adev, &ib, NULL);
990 dma_fence_put(f);
991err0:
992 if (!ring->is_mes_queue)
993 amdgpu_device_wb_free(adev, index);
994 return r;
995}
996
997
998/**
999 * sdma_v6_0_vm_copy_pte - update PTEs by copying them from the GART
1000 *
1001 * @ib: indirect buffer to fill with commands
1002 * @pe: addr of the page entry
1003 * @src: src addr to copy from
1004 * @count: number of page entries to update
1005 *
1006 * Update PTEs by copying them from the GART using sDMA.
1007 */
1008static void sdma_v6_0_vm_copy_pte(struct amdgpu_ib *ib,
1009 uint64_t pe, uint64_t src,
1010 unsigned count)
1011{
1012 unsigned bytes = count * 8;
1013
1014 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1015 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1016 ib->ptr[ib->length_dw++] = bytes - 1;
1017 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1018 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1019 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1020 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1021 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1022
1023}
1024
1025/**
1026 * sdma_v6_0_vm_write_pte - update PTEs by writing them manually
1027 *
1028 * @ib: indirect buffer to fill with commands
1029 * @pe: addr of the page entry
1030 * @value: dst addr to write into pe
1031 * @count: number of page entries to update
1032 * @incr: increase next addr by incr bytes
1033 *
1034 * Update PTEs by writing them manually using sDMA.
1035 */
1036static void sdma_v6_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1037 uint64_t value, unsigned count,
1038 uint32_t incr)
1039{
1040 unsigned ndw = count * 2;
1041
1042 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
1043 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1044 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1045 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1046 ib->ptr[ib->length_dw++] = ndw - 1;
1047 for (; ndw > 0; ndw -= 2) {
1048 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1049 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1050 value += incr;
1051 }
1052}
1053
1054/**
1055 * sdma_v6_0_vm_set_pte_pde - update the page tables using sDMA
1056 *
1057 * @ib: indirect buffer to fill with commands
1058 * @pe: addr of the page entry
1059 * @addr: dst addr to write into pe
1060 * @count: number of page entries to update
1061 * @incr: increase next addr by incr bytes
1062 * @flags: access flags
1063 *
1064 * Update the page tables using sDMA.
1065 */
1066static void sdma_v6_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1067 uint64_t pe,
1068 uint64_t addr, unsigned count,
1069 uint32_t incr, uint64_t flags)
1070{
1071 /* for physically contiguous pages (vram) */
1072 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE);
1073 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1074 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1075 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1076 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1077 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1078 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1079 ib->ptr[ib->length_dw++] = incr; /* increment size */
1080 ib->ptr[ib->length_dw++] = 0;
1081 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1082}
1083
1084/*
1085 * sdma_v6_0_ring_pad_ib - pad the IB
1086 * @ib: indirect buffer to fill with padding
1087 * @ring: amdgpu ring pointer
1088 *
1089 * Pad the IB with NOPs to a boundary multiple of 8.
1090 */
1091static void sdma_v6_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1092{
1093 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1094 u32 pad_count;
1095 int i;
1096
1097 pad_count = (-ib->length_dw) & 0x7;
1098 for (i = 0; i < pad_count; i++)
1099 if (sdma && sdma->burst_nop && (i == 0))
1100 ib->ptr[ib->length_dw++] =
1101 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) |
1102 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1103 else
1104 ib->ptr[ib->length_dw++] =
1105 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP);
1106}
1107
1108/**
1109 * sdma_v6_0_ring_emit_pipeline_sync - sync the pipeline
1110 *
1111 * @ring: amdgpu_ring pointer
1112 *
1113 * Make sure all previous operations are completed (CIK).
1114 */
1115static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1116{
1117 uint32_t seq = ring->fence_drv.sync_seq;
1118 uint64_t addr = ring->fence_drv.gpu_addr;
1119
1120 /* wait for idle */
1121 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1122 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1123 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1124 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1125 amdgpu_ring_write(ring, addr & 0xfffffffc);
1126 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1127 amdgpu_ring_write(ring, seq); /* reference */
1128 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1129 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1130 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1131}
1132
1133/*
1134 * sdma_v6_0_ring_emit_vm_flush - vm flush using sDMA
1135 *
1136 * @ring: amdgpu_ring pointer
1137 * @vmid: vmid number to use
1138 * @pd_addr: address
1139 *
1140 * Update the page table base and flush the VM TLB
1141 * using sDMA.
1142 */
1143static void sdma_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1144 unsigned vmid, uint64_t pd_addr)
1145{
1146 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
1147 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
1148
1149 /* Update the PD address for this VMID. */
1150 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
1151 (hub->ctx_addr_distance * vmid),
1152 lower_32_bits(pd_addr));
1153 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
1154 (hub->ctx_addr_distance * vmid),
1155 upper_32_bits(pd_addr));
1156
1157 /* Trigger invalidation. */
1158 amdgpu_ring_write(ring,
1159 SDMA_PKT_VM_INVALIDATION_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1160 SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(SDMA_SUBOP_VM_INVALIDATION) |
1161 SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(ring->vm_inv_eng) |
1162 SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(0x1f));
1163 amdgpu_ring_write(ring, req);
1164 amdgpu_ring_write(ring, 0xFFFFFFFF);
1165 amdgpu_ring_write(ring,
1166 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(1 << vmid) |
1167 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(0x1F));
1168}
1169
1170static void sdma_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
1171 uint32_t reg, uint32_t val)
1172{
1173 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1174 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1175 amdgpu_ring_write(ring, reg);
1176 amdgpu_ring_write(ring, val);
1177}
1178
1179static void sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1180 uint32_t val, uint32_t mask)
1181{
1182 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1183 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1184 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1185 amdgpu_ring_write(ring, reg << 2);
1186 amdgpu_ring_write(ring, 0);
1187 amdgpu_ring_write(ring, val); /* reference */
1188 amdgpu_ring_write(ring, mask); /* mask */
1189 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1190 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1191}
1192
1193static void sdma_v6_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1194 uint32_t reg0, uint32_t reg1,
1195 uint32_t ref, uint32_t mask)
1196{
1197 amdgpu_ring_emit_wreg(ring, reg0, ref);
1198 /* wait for a cycle to reset vm_inv_eng*_ack */
1199 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1200 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1201}
1202
1203static struct amdgpu_sdma_ras sdma_v6_0_3_ras = {
1204 .ras_block = {
1205 .ras_late_init = amdgpu_ras_block_late_init,
1206 },
1207};
1208
1209static void sdma_v6_0_set_ras_funcs(struct amdgpu_device *adev)
1210{
1211 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1212 case IP_VERSION(6, 0, 3):
1213 adev->sdma.ras = &sdma_v6_0_3_ras;
1214 break;
1215 default:
1216 break;
1217 }
1218}
1219
1220static int sdma_v6_0_early_init(void *handle)
1221{
1222 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1223 int r;
1224
1225 r = amdgpu_sdma_init_microcode(adev, 0, true);
1226 if (r)
1227 return r;
1228
1229 sdma_v6_0_set_ring_funcs(adev);
1230 sdma_v6_0_set_buffer_funcs(adev);
1231 sdma_v6_0_set_vm_pte_funcs(adev);
1232 sdma_v6_0_set_irq_funcs(adev);
1233 sdma_v6_0_set_mqd_funcs(adev);
1234 sdma_v6_0_set_ras_funcs(adev);
1235
1236 return 0;
1237}
1238
1239static int sdma_v6_0_sw_init(void *handle)
1240{
1241 struct amdgpu_ring *ring;
1242 int r, i;
1243 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1244
1245 /* SDMA trap event */
1246 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
1247 GFX_11_0_0__SRCID__SDMA_TRAP,
1248 &adev->sdma.trap_irq);
1249 if (r)
1250 return r;
1251
1252 for (i = 0; i < adev->sdma.num_instances; i++) {
1253 ring = &adev->sdma.instance[i].ring;
1254 ring->ring_obj = NULL;
1255 ring->use_doorbell = true;
1256 ring->me = i;
1257
1258 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1259 ring->use_doorbell?"true":"false");
1260
1261 ring->doorbell_index =
1262 (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset
1263
1264 ring->vm_hub = AMDGPU_GFXHUB(0);
1265 sprintf(ring->name, "sdma%d", i);
1266 r = amdgpu_ring_init(adev, ring, 1024,
1267 &adev->sdma.trap_irq,
1268 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1269 AMDGPU_RING_PRIO_DEFAULT, NULL);
1270 if (r)
1271 return r;
1272 }
1273
1274 if (amdgpu_sdma_ras_sw_init(adev)) {
1275 dev_err(adev->dev, "Failed to initialize sdma ras block!\n");
1276 return -EINVAL;
1277 }
1278
1279 return r;
1280}
1281
1282static int sdma_v6_0_sw_fini(void *handle)
1283{
1284 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1285 int i;
1286
1287 for (i = 0; i < adev->sdma.num_instances; i++)
1288 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1289
1290 amdgpu_sdma_destroy_inst_ctx(adev, true);
1291
1292 return 0;
1293}
1294
1295static int sdma_v6_0_hw_init(void *handle)
1296{
1297 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1298
1299 return sdma_v6_0_start(adev);
1300}
1301
1302static int sdma_v6_0_hw_fini(void *handle)
1303{
1304 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1305
1306 if (amdgpu_sriov_vf(adev))
1307 return 0;
1308
1309 sdma_v6_0_ctxempty_int_enable(adev, false);
1310 sdma_v6_0_enable(adev, false);
1311
1312 return 0;
1313}
1314
1315static int sdma_v6_0_suspend(void *handle)
1316{
1317 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1318
1319 return sdma_v6_0_hw_fini(adev);
1320}
1321
1322static int sdma_v6_0_resume(void *handle)
1323{
1324 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1325
1326 return sdma_v6_0_hw_init(adev);
1327}
1328
1329static bool sdma_v6_0_is_idle(void *handle)
1330{
1331 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1332 u32 i;
1333
1334 for (i = 0; i < adev->sdma.num_instances; i++) {
1335 u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));
1336
1337 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1338 return false;
1339 }
1340
1341 return true;
1342}
1343
1344static int sdma_v6_0_wait_for_idle(void *handle)
1345{
1346 unsigned i;
1347 u32 sdma0, sdma1;
1348 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1349
1350 for (i = 0; i < adev->usec_timeout; i++) {
1351 sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG));
1352 sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG));
1353
1354 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1355 return 0;
1356 udelay(1);
1357 }
1358 return -ETIMEDOUT;
1359}
1360
1361static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring)
1362{
1363 int i, r = 0;
1364 struct amdgpu_device *adev = ring->adev;
1365 u32 index = 0;
1366 u64 sdma_gfx_preempt;
1367
1368 amdgpu_sdma_get_index_from_ring(ring, &index);
1369 sdma_gfx_preempt =
1370 sdma_v6_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT);
1371
1372 /* assert preemption condition */
1373 amdgpu_ring_set_preempt_cond_exec(ring, false);
1374
1375 /* emit the trailing fence */
1376 ring->trail_seq += 1;
1377 amdgpu_ring_alloc(ring, 10);
1378 sdma_v6_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1379 ring->trail_seq, 0);
1380 amdgpu_ring_commit(ring);
1381
1382 /* assert IB preemption */
1383 WREG32(sdma_gfx_preempt, 1);
1384
1385 /* poll the trailing fence */
1386 for (i = 0; i < adev->usec_timeout; i++) {
1387 if (ring->trail_seq ==
1388 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1389 break;
1390 udelay(1);
1391 }
1392
1393 if (i >= adev->usec_timeout) {
1394 r = -EINVAL;
1395 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1396 }
1397
1398 /* deassert IB preemption */
1399 WREG32(sdma_gfx_preempt, 0);
1400
1401 /* deassert the preemption condition */
1402 amdgpu_ring_set_preempt_cond_exec(ring, true);
1403 return r;
1404}
1405
1406static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev,
1407 struct amdgpu_irq_src *source,
1408 unsigned type,
1409 enum amdgpu_interrupt_state state)
1410{
1411 u32 sdma_cntl;
1412
1413 u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL);
1414
1415 if (!amdgpu_sriov_vf(adev)) {
1416 sdma_cntl = RREG32(reg_offset);
1417 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1418 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1419 WREG32(reg_offset, sdma_cntl);
1420 }
1421
1422 return 0;
1423}
1424
1425static int sdma_v6_0_process_trap_irq(struct amdgpu_device *adev,
1426 struct amdgpu_irq_src *source,
1427 struct amdgpu_iv_entry *entry)
1428{
1429 int instances, queue;
1430 uint32_t mes_queue_id = entry->src_data[0];
1431
1432 DRM_DEBUG("IH: SDMA trap\n");
1433
1434 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1435 struct amdgpu_mes_queue *queue;
1436
1437 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1438
1439 spin_lock(&adev->mes.queue_id_lock);
1440 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1441 if (queue) {
1442 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1443 amdgpu_fence_process(queue->ring);
1444 }
1445 spin_unlock(&adev->mes.queue_id_lock);
1446 return 0;
1447 }
1448
1449 queue = entry->ring_id & 0xf;
1450 instances = (entry->ring_id & 0xf0) >> 4;
1451 if (instances > 1) {
1452 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n");
1453 return -EINVAL;
1454 }
1455
1456 switch (entry->client_id) {
1457 case SOC21_IH_CLIENTID_GFX:
1458 switch (queue) {
1459 case 0:
1460 amdgpu_fence_process(&adev->sdma.instance[instances].ring);
1461 break;
1462 default:
1463 break;
1464 }
1465 break;
1466 }
1467 return 0;
1468}
1469
1470static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1471 struct amdgpu_irq_src *source,
1472 struct amdgpu_iv_entry *entry)
1473{
1474 return 0;
1475}
1476
1477static int sdma_v6_0_set_clockgating_state(void *handle,
1478 enum amd_clockgating_state state)
1479{
1480 return 0;
1481}
1482
1483static int sdma_v6_0_set_powergating_state(void *handle,
1484 enum amd_powergating_state state)
1485{
1486 return 0;
1487}
1488
1489static void sdma_v6_0_get_clockgating_state(void *handle, u64 *flags)
1490{
1491}
1492
1493const struct amd_ip_funcs sdma_v6_0_ip_funcs = {
1494 .name = "sdma_v6_0",
1495 .early_init = sdma_v6_0_early_init,
1496 .late_init = NULL,
1497 .sw_init = sdma_v6_0_sw_init,
1498 .sw_fini = sdma_v6_0_sw_fini,
1499 .hw_init = sdma_v6_0_hw_init,
1500 .hw_fini = sdma_v6_0_hw_fini,
1501 .suspend = sdma_v6_0_suspend,
1502 .resume = sdma_v6_0_resume,
1503 .is_idle = sdma_v6_0_is_idle,
1504 .wait_for_idle = sdma_v6_0_wait_for_idle,
1505 .soft_reset = sdma_v6_0_soft_reset,
1506 .check_soft_reset = sdma_v6_0_check_soft_reset,
1507 .set_clockgating_state = sdma_v6_0_set_clockgating_state,
1508 .set_powergating_state = sdma_v6_0_set_powergating_state,
1509 .get_clockgating_state = sdma_v6_0_get_clockgating_state,
1510};
1511
1512static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = {
1513 .type = AMDGPU_RING_TYPE_SDMA,
1514 .align_mask = 0xf,
1515 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1516 .support_64bit_ptrs = true,
1517 .secure_submission_supported = true,
1518 .get_rptr = sdma_v6_0_ring_get_rptr,
1519 .get_wptr = sdma_v6_0_ring_get_wptr,
1520 .set_wptr = sdma_v6_0_ring_set_wptr,
1521 .emit_frame_size =
1522 5 + /* sdma_v6_0_ring_init_cond_exec */
1523 6 + /* sdma_v6_0_ring_emit_hdp_flush */
1524 6 + /* sdma_v6_0_ring_emit_pipeline_sync */
1525 /* sdma_v6_0_ring_emit_vm_flush */
1526 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1527 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1528 10 + 10 + 10, /* sdma_v6_0_ring_emit_fence x3 for user fence, vm fence */
1529 .emit_ib_size = 5 + 7 + 6, /* sdma_v6_0_ring_emit_ib */
1530 .emit_ib = sdma_v6_0_ring_emit_ib,
1531 .emit_mem_sync = sdma_v6_0_ring_emit_mem_sync,
1532 .emit_fence = sdma_v6_0_ring_emit_fence,
1533 .emit_pipeline_sync = sdma_v6_0_ring_emit_pipeline_sync,
1534 .emit_vm_flush = sdma_v6_0_ring_emit_vm_flush,
1535 .emit_hdp_flush = sdma_v6_0_ring_emit_hdp_flush,
1536 .test_ring = sdma_v6_0_ring_test_ring,
1537 .test_ib = sdma_v6_0_ring_test_ib,
1538 .insert_nop = sdma_v6_0_ring_insert_nop,
1539 .pad_ib = sdma_v6_0_ring_pad_ib,
1540 .emit_wreg = sdma_v6_0_ring_emit_wreg,
1541 .emit_reg_wait = sdma_v6_0_ring_emit_reg_wait,
1542 .emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait,
1543 .init_cond_exec = sdma_v6_0_ring_init_cond_exec,
1544 .patch_cond_exec = sdma_v6_0_ring_patch_cond_exec,
1545 .preempt_ib = sdma_v6_0_ring_preempt_ib,
1546};
1547
1548static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1549{
1550 int i;
1551
1552 for (i = 0; i < adev->sdma.num_instances; i++) {
1553 adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs;
1554 adev->sdma.instance[i].ring.me = i;
1555 }
1556}
1557
1558static const struct amdgpu_irq_src_funcs sdma_v6_0_trap_irq_funcs = {
1559 .set = sdma_v6_0_set_trap_irq_state,
1560 .process = sdma_v6_0_process_trap_irq,
1561};
1562
1563static const struct amdgpu_irq_src_funcs sdma_v6_0_illegal_inst_irq_funcs = {
1564 .process = sdma_v6_0_process_illegal_inst_irq,
1565};
1566
1567static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1568{
1569 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1570 adev->sdma.num_instances;
1571 adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs;
1572 adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs;
1573}
1574
1575/**
1576 * sdma_v6_0_emit_copy_buffer - copy buffer using the sDMA engine
1577 *
1578 * @ib: indirect buffer to fill with commands
1579 * @src_offset: src GPU address
1580 * @dst_offset: dst GPU address
1581 * @byte_count: number of bytes to xfer
1582 * @tmz: if a secure copy should be used
1583 *
1584 * Copy GPU buffers using the DMA engine.
1585 * Used by the amdgpu ttm implementation to move pages if
1586 * registered as the asic copy callback.
1587 */
1588static void sdma_v6_0_emit_copy_buffer(struct amdgpu_ib *ib,
1589 uint64_t src_offset,
1590 uint64_t dst_offset,
1591 uint32_t byte_count,
1592 bool tmz)
1593{
1594 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1595 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1596 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1597 ib->ptr[ib->length_dw++] = byte_count - 1;
1598 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1599 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1600 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1601 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1602 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1603}
1604
1605/**
1606 * sdma_v6_0_emit_fill_buffer - fill buffer using the sDMA engine
1607 *
1608 * @ib: indirect buffer to fill
1609 * @src_data: value to write to buffer
1610 * @dst_offset: dst GPU address
1611 * @byte_count: number of bytes to xfer
1612 *
1613 * Fill GPU buffers using the DMA engine.
1614 */
1615static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib,
1616 uint32_t src_data,
1617 uint64_t dst_offset,
1618 uint32_t byte_count)
1619{
1620 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_CONST_FILL);
1621 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1622 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1623 ib->ptr[ib->length_dw++] = src_data;
1624 ib->ptr[ib->length_dw++] = byte_count - 1;
1625}
1626
1627static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = {
1628 .copy_max_bytes = 0x400000,
1629 .copy_num_dw = 7,
1630 .emit_copy_buffer = sdma_v6_0_emit_copy_buffer,
1631
1632 .fill_max_bytes = 0x400000,
1633 .fill_num_dw = 5,
1634 .emit_fill_buffer = sdma_v6_0_emit_fill_buffer,
1635};
1636
1637static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev)
1638{
1639 adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs;
1640 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1641}
1642
1643static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = {
1644 .copy_pte_num_dw = 7,
1645 .copy_pte = sdma_v6_0_vm_copy_pte,
1646 .write_pte = sdma_v6_0_vm_write_pte,
1647 .set_pte_pde = sdma_v6_0_vm_set_pte_pde,
1648};
1649
1650static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1651{
1652 unsigned i;
1653
1654 adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs;
1655 for (i = 0; i < adev->sdma.num_instances; i++) {
1656 adev->vm_manager.vm_pte_scheds[i] =
1657 &adev->sdma.instance[i].ring.sched;
1658 }
1659 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1660}
1661
1662const struct amdgpu_ip_block_version sdma_v6_0_ip_block = {
1663 .type = AMD_IP_BLOCK_TYPE_SDMA,
1664 .major = 6,
1665 .minor = 0,
1666 .rev = 0,
1667 .funcs = &sdma_v6_0_ip_funcs,
1668};
1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/delay.h>
25#include <linux/firmware.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28
29#include "amdgpu.h"
30#include "amdgpu_ucode.h"
31#include "amdgpu_trace.h"
32
33#include "gc/gc_11_0_0_offset.h"
34#include "gc/gc_11_0_0_sh_mask.h"
35#include "gc/gc_11_0_0_default.h"
36#include "hdp/hdp_6_0_0_offset.h"
37#include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
38
39#include "soc15_common.h"
40#include "soc15.h"
41#include "sdma_v6_0_0_pkt_open.h"
42#include "nbio_v4_3.h"
43#include "sdma_common.h"
44#include "sdma_v6_0.h"
45#include "v11_structs.h"
46
47MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin");
48MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin");
49MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin");
50MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin");
51
52#define SDMA1_REG_OFFSET 0x600
53#define SDMA0_HYP_DEC_REG_START 0x5880
54#define SDMA0_HYP_DEC_REG_END 0x589a
55#define SDMA1_HYP_DEC_REG_OFFSET 0x20
56
57static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev);
58static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev);
59static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev);
60static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev);
61static int sdma_v6_0_start(struct amdgpu_device *adev);
62
63static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
64{
65 u32 base;
66
67 if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
68 internal_offset <= SDMA0_HYP_DEC_REG_END) {
69 base = adev->reg_offset[GC_HWIP][0][1];
70 if (instance != 0)
71 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
72 } else {
73 base = adev->reg_offset[GC_HWIP][0][0];
74 if (instance == 1)
75 internal_offset += SDMA1_REG_OFFSET;
76 }
77
78 return base + internal_offset;
79}
80
81/**
82 * sdma_v6_0_init_microcode - load ucode images from disk
83 *
84 * @adev: amdgpu_device pointer
85 *
86 * Use the firmware interface to load the ucode images into
87 * the driver (not loaded into hw).
88 * Returns 0 on success, error on failure.
89 */
90static int sdma_v6_0_init_microcode(struct amdgpu_device *adev)
91{
92 char fw_name[30];
93 char ucode_prefix[30];
94
95 DRM_DEBUG("\n");
96
97 amdgpu_ucode_ip_version_decode(adev, SDMA0_HWIP, ucode_prefix, sizeof(ucode_prefix));
98
99 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix);
100
101 return amdgpu_sdma_init_microcode(adev, fw_name, 0, true);
102}
103
104static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring)
105{
106 unsigned ret;
107
108 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE));
109 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
110 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
111 amdgpu_ring_write(ring, 1);
112 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
113 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
114
115 return ret;
116}
117
118static void sdma_v6_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
119 unsigned offset)
120{
121 unsigned cur;
122
123 BUG_ON(offset > ring->buf_mask);
124 BUG_ON(ring->ring[offset] != 0x55aa55aa);
125
126 cur = (ring->wptr - 1) & ring->buf_mask;
127 if (cur > offset)
128 ring->ring[offset] = cur - offset;
129 else
130 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
131}
132
133/**
134 * sdma_v6_0_ring_get_rptr - get the current read pointer
135 *
136 * @ring: amdgpu ring pointer
137 *
138 * Get the current rptr from the hardware.
139 */
140static uint64_t sdma_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
141{
142 u64 *rptr;
143
144 /* XXX check if swapping is necessary on BE */
145 rptr = (u64 *)ring->rptr_cpu_addr;
146
147 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
148 return ((*rptr) >> 2);
149}
150
151/**
152 * sdma_v6_0_ring_get_wptr - get the current write pointer
153 *
154 * @ring: amdgpu ring pointer
155 *
156 * Get the current wptr from the hardware.
157 */
158static uint64_t sdma_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
159{
160 u64 wptr = 0;
161
162 if (ring->use_doorbell) {
163 /* XXX check if swapping is necessary on BE */
164 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
165 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
166 }
167
168 return wptr >> 2;
169}
170
171/**
172 * sdma_v6_0_ring_set_wptr - commit the write pointer
173 *
174 * @ring: amdgpu ring pointer
175 *
176 * Write the wptr back to the hardware.
177 */
178static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
179{
180 struct amdgpu_device *adev = ring->adev;
181 uint32_t *wptr_saved;
182 uint32_t *is_queue_unmap;
183 uint64_t aggregated_db_index;
184 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size;
185
186 DRM_DEBUG("Setting write pointer\n");
187
188 if (ring->is_mes_queue) {
189 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
190 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
191 sizeof(uint32_t));
192 aggregated_db_index =
193 amdgpu_mes_get_aggregated_doorbell_index(adev,
194 ring->hw_prio);
195
196 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
197 ring->wptr << 2);
198 *wptr_saved = ring->wptr << 2;
199 if (*is_queue_unmap) {
200 WDOORBELL64(aggregated_db_index, ring->wptr << 2);
201 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
202 ring->doorbell_index, ring->wptr << 2);
203 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
204 } else {
205 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
206 ring->doorbell_index, ring->wptr << 2);
207 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
208
209 if (*is_queue_unmap)
210 WDOORBELL64(aggregated_db_index,
211 ring->wptr << 2);
212 }
213 } else {
214 if (ring->use_doorbell) {
215 DRM_DEBUG("Using doorbell -- "
216 "wptr_offs == 0x%08x "
217 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
218 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
219 ring->wptr_offs,
220 lower_32_bits(ring->wptr << 2),
221 upper_32_bits(ring->wptr << 2));
222 /* XXX check if swapping is necessary on BE */
223 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
224 ring->wptr << 2);
225 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
226 ring->doorbell_index, ring->wptr << 2);
227 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
228 } else {
229 DRM_DEBUG("Not using doorbell -- "
230 "regSDMA%i_GFX_RB_WPTR == 0x%08x "
231 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
232 ring->me,
233 lower_32_bits(ring->wptr << 2),
234 ring->me,
235 upper_32_bits(ring->wptr << 2));
236 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,
237 ring->me, regSDMA0_QUEUE0_RB_WPTR),
238 lower_32_bits(ring->wptr << 2));
239 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,
240 ring->me, regSDMA0_QUEUE0_RB_WPTR_HI),
241 upper_32_bits(ring->wptr << 2));
242 }
243 }
244}
245
246static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
247{
248 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
249 int i;
250
251 for (i = 0; i < count; i++)
252 if (sdma && sdma->burst_nop && (i == 0))
253 amdgpu_ring_write(ring, ring->funcs->nop |
254 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
255 else
256 amdgpu_ring_write(ring, ring->funcs->nop);
257}
258
259/**
260 * sdma_v6_0_ring_emit_ib - Schedule an IB on the DMA engine
261 *
262 * @ring: amdgpu ring pointer
263 * @ib: IB object to schedule
264 *
265 * Schedule an IB in the DMA ring.
266 */
267static void sdma_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
268 struct amdgpu_job *job,
269 struct amdgpu_ib *ib,
270 uint32_t flags)
271{
272 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
273 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
274
275 /* An IB packet must end on a 8 DW boundary--the next dword
276 * must be on a 8-dword boundary. Our IB packet below is 6
277 * dwords long, thus add x number of NOPs, such that, in
278 * modular arithmetic,
279 * wptr + 6 + x = 8k, k >= 0, which in C is,
280 * (wptr + 6 + x) % 8 = 0.
281 * The expression below, is a solution of x.
282 */
283 sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
284
285 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) |
286 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
287 /* base must be 32 byte aligned */
288 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
289 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
290 amdgpu_ring_write(ring, ib->length_dw);
291 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
292 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
293}
294
295/**
296 * sdma_v6_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
297 *
298 * @ring: amdgpu ring pointer
299 * @job: job to retrieve vmid from
300 * @ib: IB object to schedule
301 *
302 * flush the IB by graphics cache rinse.
303 */
304static void sdma_v6_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
305{
306 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
307 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
308 SDMA_GCR_GLI_INV(1);
309
310 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
311 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ));
312 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
313 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
314 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
315 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
316 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
317 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
318 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
319}
320
321
322/**
323 * sdma_v6_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
324 *
325 * @ring: amdgpu ring pointer
326 *
327 * Emit an hdp flush packet on the requested DMA ring.
328 */
329static void sdma_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
330{
331 struct amdgpu_device *adev = ring->adev;
332 u32 ref_and_mask = 0;
333 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
334
335 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
336
337 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
338 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
339 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
340 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
341 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
342 amdgpu_ring_write(ring, ref_and_mask); /* reference */
343 amdgpu_ring_write(ring, ref_and_mask); /* mask */
344 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
345 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
346}
347
348/**
349 * sdma_v6_0_ring_emit_fence - emit a fence on the DMA ring
350 *
351 * @ring: amdgpu ring pointer
352 * @fence: amdgpu fence object
353 *
354 * Add a DMA fence packet to the ring to write
355 * the fence seq number and DMA trap packet to generate
356 * an interrupt if needed.
357 */
358static void sdma_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
359 unsigned flags)
360{
361 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
362 /* write the fence */
363 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
364 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
365 /* zero in first two bits */
366 BUG_ON(addr & 0x3);
367 amdgpu_ring_write(ring, lower_32_bits(addr));
368 amdgpu_ring_write(ring, upper_32_bits(addr));
369 amdgpu_ring_write(ring, lower_32_bits(seq));
370
371 /* optionally write high bits as well */
372 if (write64bit) {
373 addr += 4;
374 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
375 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
376 /* zero in first two bits */
377 BUG_ON(addr & 0x3);
378 amdgpu_ring_write(ring, lower_32_bits(addr));
379 amdgpu_ring_write(ring, upper_32_bits(addr));
380 amdgpu_ring_write(ring, upper_32_bits(seq));
381 }
382
383 if (flags & AMDGPU_FENCE_FLAG_INT) {
384 uint32_t ctx = ring->is_mes_queue ?
385 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
386 /* generate an interrupt */
387 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP));
388 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
389 }
390}
391
392/**
393 * sdma_v6_0_gfx_stop - stop the gfx async dma engines
394 *
395 * @adev: amdgpu_device pointer
396 *
397 * Stop the gfx async dma ring buffers.
398 */
399static void sdma_v6_0_gfx_stop(struct amdgpu_device *adev)
400{
401 u32 rb_cntl, ib_cntl;
402 int i;
403
404 amdgpu_sdma_unset_buffer_funcs_helper(adev);
405
406 for (i = 0; i < adev->sdma.num_instances; i++) {
407 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
408 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0);
409 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
410 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
411 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0);
412 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
413 }
414}
415
416/**
417 * sdma_v6_0_rlc_stop - stop the compute async dma engines
418 *
419 * @adev: amdgpu_device pointer
420 *
421 * Stop the compute async dma queues.
422 */
423static void sdma_v6_0_rlc_stop(struct amdgpu_device *adev)
424{
425 /* XXX todo */
426}
427
428/**
429 * sdma_v6_0_ctx_switch_enable - stop the async dma engines context switch
430 *
431 * @adev: amdgpu_device pointer
432 * @enable: enable/disable the DMA MEs context switch.
433 *
434 * Halt or unhalt the async dma engines context switch.
435 */
436static void sdma_v6_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
437{
438}
439
440/**
441 * sdma_v6_0_enable - stop the async dma engines
442 *
443 * @adev: amdgpu_device pointer
444 * @enable: enable/disable the DMA MEs.
445 *
446 * Halt or unhalt the async dma engines.
447 */
448static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable)
449{
450 u32 f32_cntl;
451 int i;
452
453 if (!enable) {
454 sdma_v6_0_gfx_stop(adev);
455 sdma_v6_0_rlc_stop(adev);
456 }
457
458 if (amdgpu_sriov_vf(adev))
459 return;
460
461 for (i = 0; i < adev->sdma.num_instances; i++) {
462 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
463 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
464 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl);
465 }
466}
467
468/**
469 * sdma_v6_0_gfx_resume - setup and start the async dma engines
470 *
471 * @adev: amdgpu_device pointer
472 *
473 * Set up the gfx DMA ring buffers and enable them.
474 * Returns 0 for success, error for failure.
475 */
476static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)
477{
478 struct amdgpu_ring *ring;
479 u32 rb_cntl, ib_cntl;
480 u32 rb_bufsz;
481 u32 doorbell;
482 u32 doorbell_offset;
483 u32 temp;
484 u64 wptr_gpu_addr;
485 int i, r;
486
487 for (i = 0; i < adev->sdma.num_instances; i++) {
488 ring = &adev->sdma.instance[i].ring;
489
490 if (!amdgpu_sriov_vf(adev))
491 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
492
493 /* Set ring buffer size in dwords */
494 rb_bufsz = order_base_2(ring->ring_size / 4);
495 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
496 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);
497#ifdef __BIG_ENDIAN
498 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1);
499 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL,
500 RPTR_WRITEBACK_SWAP_ENABLE, 1);
501#endif
502 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1);
503 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
504
505 /* Initialize the ring buffer's read and write pointers */
506 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);
507 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);
508 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);
509 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);
510
511 /* setup the wptr shadow polling */
512 wptr_gpu_addr = ring->wptr_gpu_addr;
513 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),
514 lower_32_bits(wptr_gpu_addr));
515 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),
516 upper_32_bits(wptr_gpu_addr));
517
518 /* set the wb address whether it's enabled or not */
519 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),
520 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
521 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),
522 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
523
524 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
525 if (amdgpu_sriov_vf(adev))
526 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 1);
527 else
528 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);
529 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1);
530
531 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
532 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);
533
534 ring->wptr = 0;
535
536 /* before programing wptr to a less value, need set minor_ptr_update first */
537 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);
538
539 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
540 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);
541 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
542 }
543
544 doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));
545 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET));
546
547 if (ring->use_doorbell) {
548 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
549 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET,
550 OFFSET, ring->doorbell_index);
551 } else {
552 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);
553 }
554 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);
555 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);
556
557 if (i == 0)
558 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
559 ring->doorbell_index,
560 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances);
561
562 if (amdgpu_sriov_vf(adev))
563 sdma_v6_0_ring_set_wptr(ring);
564
565 /* set minor_ptr_update to 0 after wptr programed */
566 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);
567
568 /* Set up RESP_MODE to non-copy addresses */
569 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));
570 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
571 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
572 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);
573
574 /* program default cache read and write policy */
575 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));
576 /* clean read policy and write policy bits */
577 temp &= 0xFF0FFF;
578 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
579 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
580 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
581 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);
582
583 if (!amdgpu_sriov_vf(adev)) {
584 /* unhalt engine */
585 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
586 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
587 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0);
588 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp);
589 }
590
591 /* enable DMA RB */
592 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1);
593 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
594
595 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
596 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1);
597#ifdef __BIG_ENDIAN
598 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1);
599#endif
600 /* enable DMA IBs */
601 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
602
603 ring->sched.ready = true;
604
605 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
606 sdma_v6_0_ctx_switch_enable(adev, true);
607 sdma_v6_0_enable(adev, true);
608 }
609
610 r = amdgpu_ring_test_helper(ring);
611 if (r) {
612 ring->sched.ready = false;
613 return r;
614 }
615
616 if (adev->mman.buffer_funcs_ring == ring)
617 amdgpu_ttm_set_buffer_funcs_status(adev, true);
618 }
619
620 return 0;
621}
622
623/**
624 * sdma_v6_0_rlc_resume - setup and start the async dma engines
625 *
626 * @adev: amdgpu_device pointer
627 *
628 * Set up the compute DMA queues and enable them.
629 * Returns 0 for success, error for failure.
630 */
631static int sdma_v6_0_rlc_resume(struct amdgpu_device *adev)
632{
633 return 0;
634}
635
636/**
637 * sdma_v6_0_load_microcode - load the sDMA ME ucode
638 *
639 * @adev: amdgpu_device pointer
640 *
641 * Loads the sDMA0/1 ucode.
642 * Returns 0 for success, -EINVAL if the ucode is not available.
643 */
644static int sdma_v6_0_load_microcode(struct amdgpu_device *adev)
645{
646 const struct sdma_firmware_header_v2_0 *hdr;
647 const __le32 *fw_data;
648 u32 fw_size;
649 int i, j;
650 bool use_broadcast;
651
652 /* halt the MEs */
653 sdma_v6_0_enable(adev, false);
654
655 if (!adev->sdma.instance[0].fw)
656 return -EINVAL;
657
658 /* use broadcast mode to load SDMA microcode by default */
659 use_broadcast = true;
660
661 if (use_broadcast) {
662 dev_info(adev->dev, "Use broadcast method to load SDMA firmware\n");
663 /* load Control Thread microcode */
664 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;
665 amdgpu_ucode_print_sdma_hdr(&hdr->header);
666 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4;
667
668 fw_data = (const __le32 *)
669 (adev->sdma.instance[0].fw->data +
670 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
671
672 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0);
673
674 for (j = 0; j < fw_size; j++) {
675 if (amdgpu_emu_mode == 1 && j % 500 == 0)
676 msleep(1);
677 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));
678 }
679
680 /* load Context Switch microcode */
681 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4;
682
683 fw_data = (const __le32 *)
684 (adev->sdma.instance[0].fw->data +
685 le32_to_cpu(hdr->ctl_ucode_offset));
686
687 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000);
688
689 for (j = 0; j < fw_size; j++) {
690 if (amdgpu_emu_mode == 1 && j % 500 == 0)
691 msleep(1);
692 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));
693 }
694 } else {
695 dev_info(adev->dev, "Use legacy method to load SDMA firmware\n");
696 for (i = 0; i < adev->sdma.num_instances; i++) {
697 /* load Control Thread microcode */
698 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;
699 amdgpu_ucode_print_sdma_hdr(&hdr->header);
700 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4;
701
702 fw_data = (const __le32 *)
703 (adev->sdma.instance[0].fw->data +
704 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
705
706 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0);
707
708 for (j = 0; j < fw_size; j++) {
709 if (amdgpu_emu_mode == 1 && j % 500 == 0)
710 msleep(1);
711 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
712 }
713
714 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
715
716 /* load Context Switch microcode */
717 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4;
718
719 fw_data = (const __le32 *)
720 (adev->sdma.instance[0].fw->data +
721 le32_to_cpu(hdr->ctl_ucode_offset));
722
723 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000);
724
725 for (j = 0; j < fw_size; j++) {
726 if (amdgpu_emu_mode == 1 && j % 500 == 0)
727 msleep(1);
728 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
729 }
730
731 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
732 }
733 }
734
735 return 0;
736}
737
738static int sdma_v6_0_soft_reset(void *handle)
739{
740 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
741 u32 tmp;
742 int i;
743
744 sdma_v6_0_gfx_stop(adev);
745
746 for (i = 0; i < adev->sdma.num_instances; i++) {
747 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE));
748 tmp |= SDMA0_FREEZE__FREEZE_MASK;
749 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp);
750 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
751 tmp |= SDMA0_F32_CNTL__HALT_MASK;
752 tmp |= SDMA0_F32_CNTL__TH1_RESET_MASK;
753 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp);
754
755 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0);
756
757 udelay(100);
758
759 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i;
760 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
761 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
762
763 udelay(100);
764
765 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0);
766 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
767
768 udelay(100);
769 }
770
771 return sdma_v6_0_start(adev);
772}
773
774static bool sdma_v6_0_check_soft_reset(void *handle)
775{
776 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
777 struct amdgpu_ring *ring;
778 int i, r;
779 long tmo = msecs_to_jiffies(1000);
780
781 for (i = 0; i < adev->sdma.num_instances; i++) {
782 ring = &adev->sdma.instance[i].ring;
783 r = amdgpu_ring_test_ib(ring, tmo);
784 if (r)
785 return true;
786 }
787
788 return false;
789}
790
791/**
792 * sdma_v6_0_start - setup and start the async dma engines
793 *
794 * @adev: amdgpu_device pointer
795 *
796 * Set up the DMA engines and enable them.
797 * Returns 0 for success, error for failure.
798 */
799static int sdma_v6_0_start(struct amdgpu_device *adev)
800{
801 int r = 0;
802
803 if (amdgpu_sriov_vf(adev)) {
804 sdma_v6_0_ctx_switch_enable(adev, false);
805 sdma_v6_0_enable(adev, false);
806
807 /* set RB registers */
808 r = sdma_v6_0_gfx_resume(adev);
809 return r;
810 }
811
812 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
813 r = sdma_v6_0_load_microcode(adev);
814 if (r)
815 return r;
816
817 /* The value of regSDMA_F32_CNTL is invalid the moment after loading fw */
818 if (amdgpu_emu_mode == 1)
819 msleep(1000);
820 }
821
822 /* unhalt the MEs */
823 sdma_v6_0_enable(adev, true);
824 /* enable sdma ring preemption */
825 sdma_v6_0_ctx_switch_enable(adev, true);
826
827 /* start the gfx rings and rlc compute queues */
828 r = sdma_v6_0_gfx_resume(adev);
829 if (r)
830 return r;
831 r = sdma_v6_0_rlc_resume(adev);
832
833 return r;
834}
835
836static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, void *mqd,
837 struct amdgpu_mqd_prop *prop)
838{
839 struct v11_sdma_mqd *m = mqd;
840 uint64_t wb_gpu_addr;
841
842 m->sdmax_rlcx_rb_cntl =
843 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT |
844 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
845 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
846 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT;
847
848 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
849 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
850
851 wb_gpu_addr = prop->wptr_gpu_addr;
852 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
853 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
854
855 wb_gpu_addr = prop->rptr_gpu_addr;
856 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
857 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
858
859 m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0,
860 regSDMA0_QUEUE0_IB_CNTL));
861
862 m->sdmax_rlcx_doorbell_offset =
863 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT;
864
865 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
866
867 m->sdmax_rlcx_skip_cntl = 0;
868 m->sdmax_rlcx_context_status = 0;
869 m->sdmax_rlcx_doorbell_log = 0;
870
871 m->sdmax_rlcx_rb_aql_cntl = regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT;
872 m->sdmax_rlcx_dummy_reg = regSDMA0_QUEUE0_DUMMY_REG_DEFAULT;
873
874 return 0;
875}
876
877static void sdma_v6_0_set_mqd_funcs(struct amdgpu_device *adev)
878{
879 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v11_sdma_mqd);
880 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v6_0_mqd_init;
881}
882
883/**
884 * sdma_v6_0_ring_test_ring - simple async dma engine test
885 *
886 * @ring: amdgpu_ring structure holding ring information
887 *
888 * Test the DMA engine by writing using it to write an
889 * value to memory.
890 * Returns 0 for success, error for failure.
891 */
892static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring)
893{
894 struct amdgpu_device *adev = ring->adev;
895 unsigned i;
896 unsigned index;
897 int r;
898 u32 tmp;
899 u64 gpu_addr;
900 volatile uint32_t *cpu_ptr = NULL;
901
902 tmp = 0xCAFEDEAD;
903
904 if (ring->is_mes_queue) {
905 uint32_t offset = 0;
906 offset = amdgpu_mes_ctx_get_offs(ring,
907 AMDGPU_MES_CTX_PADDING_OFFS);
908 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
909 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
910 *cpu_ptr = tmp;
911 } else {
912 r = amdgpu_device_wb_get(adev, &index);
913 if (r) {
914 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
915 return r;
916 }
917
918 gpu_addr = adev->wb.gpu_addr + (index * 4);
919 adev->wb.wb[index] = cpu_to_le32(tmp);
920 }
921
922 r = amdgpu_ring_alloc(ring, 5);
923 if (r) {
924 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
925 amdgpu_device_wb_free(adev, index);
926 return r;
927 }
928
929 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
930 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
931 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
932 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
933 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
934 amdgpu_ring_write(ring, 0xDEADBEEF);
935 amdgpu_ring_commit(ring);
936
937 for (i = 0; i < adev->usec_timeout; i++) {
938 if (ring->is_mes_queue)
939 tmp = le32_to_cpu(*cpu_ptr);
940 else
941 tmp = le32_to_cpu(adev->wb.wb[index]);
942 if (tmp == 0xDEADBEEF)
943 break;
944 if (amdgpu_emu_mode == 1)
945 msleep(1);
946 else
947 udelay(1);
948 }
949
950 if (i >= adev->usec_timeout)
951 r = -ETIMEDOUT;
952
953 if (!ring->is_mes_queue)
954 amdgpu_device_wb_free(adev, index);
955
956 return r;
957}
958
959/**
960 * sdma_v6_0_ring_test_ib - test an IB on the DMA engine
961 *
962 * @ring: amdgpu_ring structure holding ring information
963 *
964 * Test a simple IB in the DMA ring.
965 * Returns 0 on success, error on failure.
966 */
967static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
968{
969 struct amdgpu_device *adev = ring->adev;
970 struct amdgpu_ib ib;
971 struct dma_fence *f = NULL;
972 unsigned index;
973 long r;
974 u32 tmp = 0;
975 u64 gpu_addr;
976 volatile uint32_t *cpu_ptr = NULL;
977
978 tmp = 0xCAFEDEAD;
979 memset(&ib, 0, sizeof(ib));
980
981 if (ring->is_mes_queue) {
982 uint32_t offset = 0;
983 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
984 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
985 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
986
987 offset = amdgpu_mes_ctx_get_offs(ring,
988 AMDGPU_MES_CTX_PADDING_OFFS);
989 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
990 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
991 *cpu_ptr = tmp;
992 } else {
993 r = amdgpu_device_wb_get(adev, &index);
994 if (r) {
995 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
996 return r;
997 }
998
999 gpu_addr = adev->wb.gpu_addr + (index * 4);
1000 adev->wb.wb[index] = cpu_to_le32(tmp);
1001
1002 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
1003 if (r) {
1004 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1005 goto err0;
1006 }
1007 }
1008
1009 ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
1010 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1011 ib.ptr[1] = lower_32_bits(gpu_addr);
1012 ib.ptr[2] = upper_32_bits(gpu_addr);
1013 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1014 ib.ptr[4] = 0xDEADBEEF;
1015 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1016 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1017 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1018 ib.length_dw = 8;
1019
1020 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1021 if (r)
1022 goto err1;
1023
1024 r = dma_fence_wait_timeout(f, false, timeout);
1025 if (r == 0) {
1026 DRM_ERROR("amdgpu: IB test timed out\n");
1027 r = -ETIMEDOUT;
1028 goto err1;
1029 } else if (r < 0) {
1030 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1031 goto err1;
1032 }
1033
1034 if (ring->is_mes_queue)
1035 tmp = le32_to_cpu(*cpu_ptr);
1036 else
1037 tmp = le32_to_cpu(adev->wb.wb[index]);
1038
1039 if (tmp == 0xDEADBEEF)
1040 r = 0;
1041 else
1042 r = -EINVAL;
1043
1044err1:
1045 amdgpu_ib_free(adev, &ib, NULL);
1046 dma_fence_put(f);
1047err0:
1048 if (!ring->is_mes_queue)
1049 amdgpu_device_wb_free(adev, index);
1050 return r;
1051}
1052
1053
1054/**
1055 * sdma_v6_0_vm_copy_pte - update PTEs by copying them from the GART
1056 *
1057 * @ib: indirect buffer to fill with commands
1058 * @pe: addr of the page entry
1059 * @src: src addr to copy from
1060 * @count: number of page entries to update
1061 *
1062 * Update PTEs by copying them from the GART using sDMA.
1063 */
1064static void sdma_v6_0_vm_copy_pte(struct amdgpu_ib *ib,
1065 uint64_t pe, uint64_t src,
1066 unsigned count)
1067{
1068 unsigned bytes = count * 8;
1069
1070 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1071 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1072 ib->ptr[ib->length_dw++] = bytes - 1;
1073 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1074 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1075 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1076 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1077 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1078
1079}
1080
1081/**
1082 * sdma_v6_0_vm_write_pte - update PTEs by writing them manually
1083 *
1084 * @ib: indirect buffer to fill with commands
1085 * @pe: addr of the page entry
1086 * @addr: dst addr to write into pe
1087 * @count: number of page entries to update
1088 * @incr: increase next addr by incr bytes
1089 * @flags: access flags
1090 *
1091 * Update PTEs by writing them manually using sDMA.
1092 */
1093static void sdma_v6_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1094 uint64_t value, unsigned count,
1095 uint32_t incr)
1096{
1097 unsigned ndw = count * 2;
1098
1099 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
1100 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1101 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1102 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1103 ib->ptr[ib->length_dw++] = ndw - 1;
1104 for (; ndw > 0; ndw -= 2) {
1105 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1106 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1107 value += incr;
1108 }
1109}
1110
1111/**
1112 * sdma_v6_0_vm_set_pte_pde - update the page tables using sDMA
1113 *
1114 * @ib: indirect buffer to fill with commands
1115 * @pe: addr of the page entry
1116 * @addr: dst addr to write into pe
1117 * @count: number of page entries to update
1118 * @incr: increase next addr by incr bytes
1119 * @flags: access flags
1120 *
1121 * Update the page tables using sDMA.
1122 */
1123static void sdma_v6_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1124 uint64_t pe,
1125 uint64_t addr, unsigned count,
1126 uint32_t incr, uint64_t flags)
1127{
1128 /* for physically contiguous pages (vram) */
1129 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE);
1130 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1131 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1132 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1133 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1134 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1135 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1136 ib->ptr[ib->length_dw++] = incr; /* increment size */
1137 ib->ptr[ib->length_dw++] = 0;
1138 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1139}
1140
1141/**
1142 * sdma_v6_0_ring_pad_ib - pad the IB
1143 * @ib: indirect buffer to fill with padding
1144 *
1145 * Pad the IB with NOPs to a boundary multiple of 8.
1146 */
1147static void sdma_v6_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1148{
1149 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1150 u32 pad_count;
1151 int i;
1152
1153 pad_count = (-ib->length_dw) & 0x7;
1154 for (i = 0; i < pad_count; i++)
1155 if (sdma && sdma->burst_nop && (i == 0))
1156 ib->ptr[ib->length_dw++] =
1157 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) |
1158 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1159 else
1160 ib->ptr[ib->length_dw++] =
1161 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP);
1162}
1163
1164/**
1165 * sdma_v6_0_ring_emit_pipeline_sync - sync the pipeline
1166 *
1167 * @ring: amdgpu_ring pointer
1168 *
1169 * Make sure all previous operations are completed (CIK).
1170 */
1171static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1172{
1173 uint32_t seq = ring->fence_drv.sync_seq;
1174 uint64_t addr = ring->fence_drv.gpu_addr;
1175
1176 /* wait for idle */
1177 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1178 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1179 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1180 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1181 amdgpu_ring_write(ring, addr & 0xfffffffc);
1182 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1183 amdgpu_ring_write(ring, seq); /* reference */
1184 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1185 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1186 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1187}
1188
1189/**
1190 * sdma_v6_0_ring_emit_vm_flush - vm flush using sDMA
1191 *
1192 * @ring: amdgpu_ring pointer
1193 * @vm: amdgpu_vm pointer
1194 *
1195 * Update the page table base and flush the VM TLB
1196 * using sDMA.
1197 */
1198static void sdma_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1199 unsigned vmid, uint64_t pd_addr)
1200{
1201 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1202}
1203
1204static void sdma_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
1205 uint32_t reg, uint32_t val)
1206{
1207 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1208 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1209 amdgpu_ring_write(ring, reg);
1210 amdgpu_ring_write(ring, val);
1211}
1212
1213static void sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1214 uint32_t val, uint32_t mask)
1215{
1216 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1217 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1218 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1219 amdgpu_ring_write(ring, reg << 2);
1220 amdgpu_ring_write(ring, 0);
1221 amdgpu_ring_write(ring, val); /* reference */
1222 amdgpu_ring_write(ring, mask); /* mask */
1223 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1224 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1225}
1226
1227static void sdma_v6_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1228 uint32_t reg0, uint32_t reg1,
1229 uint32_t ref, uint32_t mask)
1230{
1231 amdgpu_ring_emit_wreg(ring, reg0, ref);
1232 /* wait for a cycle to reset vm_inv_eng*_ack */
1233 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1234 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1235}
1236
1237static int sdma_v6_0_early_init(void *handle)
1238{
1239 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1240
1241 sdma_v6_0_set_ring_funcs(adev);
1242 sdma_v6_0_set_buffer_funcs(adev);
1243 sdma_v6_0_set_vm_pte_funcs(adev);
1244 sdma_v6_0_set_irq_funcs(adev);
1245 sdma_v6_0_set_mqd_funcs(adev);
1246
1247 return 0;
1248}
1249
1250static int sdma_v6_0_sw_init(void *handle)
1251{
1252 struct amdgpu_ring *ring;
1253 int r, i;
1254 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1255
1256 /* SDMA trap event */
1257 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
1258 GFX_11_0_0__SRCID__SDMA_TRAP,
1259 &adev->sdma.trap_irq);
1260 if (r)
1261 return r;
1262
1263 r = sdma_v6_0_init_microcode(adev);
1264 if (r) {
1265 DRM_ERROR("Failed to load sdma firmware!\n");
1266 return r;
1267 }
1268
1269 for (i = 0; i < adev->sdma.num_instances; i++) {
1270 ring = &adev->sdma.instance[i].ring;
1271 ring->ring_obj = NULL;
1272 ring->use_doorbell = true;
1273 ring->me = i;
1274
1275 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1276 ring->use_doorbell?"true":"false");
1277
1278 ring->doorbell_index =
1279 (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset
1280
1281 sprintf(ring->name, "sdma%d", i);
1282 r = amdgpu_ring_init(adev, ring, 1024,
1283 &adev->sdma.trap_irq,
1284 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1285 AMDGPU_RING_PRIO_DEFAULT, NULL);
1286 if (r)
1287 return r;
1288 }
1289
1290 return r;
1291}
1292
1293static int sdma_v6_0_sw_fini(void *handle)
1294{
1295 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1296 int i;
1297
1298 for (i = 0; i < adev->sdma.num_instances; i++)
1299 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1300
1301 amdgpu_sdma_destroy_inst_ctx(adev, true);
1302
1303 return 0;
1304}
1305
1306static int sdma_v6_0_hw_init(void *handle)
1307{
1308 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1309
1310 return sdma_v6_0_start(adev);
1311}
1312
1313static int sdma_v6_0_hw_fini(void *handle)
1314{
1315 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1316
1317 if (amdgpu_sriov_vf(adev)) {
1318 /* disable the scheduler for SDMA */
1319 amdgpu_sdma_unset_buffer_funcs_helper(adev);
1320 return 0;
1321 }
1322
1323 sdma_v6_0_ctx_switch_enable(adev, false);
1324 sdma_v6_0_enable(adev, false);
1325
1326 return 0;
1327}
1328
1329static int sdma_v6_0_suspend(void *handle)
1330{
1331 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1332
1333 return sdma_v6_0_hw_fini(adev);
1334}
1335
1336static int sdma_v6_0_resume(void *handle)
1337{
1338 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1339
1340 return sdma_v6_0_hw_init(adev);
1341}
1342
1343static bool sdma_v6_0_is_idle(void *handle)
1344{
1345 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1346 u32 i;
1347
1348 for (i = 0; i < adev->sdma.num_instances; i++) {
1349 u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));
1350
1351 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1352 return false;
1353 }
1354
1355 return true;
1356}
1357
1358static int sdma_v6_0_wait_for_idle(void *handle)
1359{
1360 unsigned i;
1361 u32 sdma0, sdma1;
1362 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1363
1364 for (i = 0; i < adev->usec_timeout; i++) {
1365 sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG));
1366 sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG));
1367
1368 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1369 return 0;
1370 udelay(1);
1371 }
1372 return -ETIMEDOUT;
1373}
1374
1375static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring)
1376{
1377 int i, r = 0;
1378 struct amdgpu_device *adev = ring->adev;
1379 u32 index = 0;
1380 u64 sdma_gfx_preempt;
1381
1382 amdgpu_sdma_get_index_from_ring(ring, &index);
1383 sdma_gfx_preempt =
1384 sdma_v6_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT);
1385
1386 /* assert preemption condition */
1387 amdgpu_ring_set_preempt_cond_exec(ring, false);
1388
1389 /* emit the trailing fence */
1390 ring->trail_seq += 1;
1391 amdgpu_ring_alloc(ring, 10);
1392 sdma_v6_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1393 ring->trail_seq, 0);
1394 amdgpu_ring_commit(ring);
1395
1396 /* assert IB preemption */
1397 WREG32(sdma_gfx_preempt, 1);
1398
1399 /* poll the trailing fence */
1400 for (i = 0; i < adev->usec_timeout; i++) {
1401 if (ring->trail_seq ==
1402 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1403 break;
1404 udelay(1);
1405 }
1406
1407 if (i >= adev->usec_timeout) {
1408 r = -EINVAL;
1409 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1410 }
1411
1412 /* deassert IB preemption */
1413 WREG32(sdma_gfx_preempt, 0);
1414
1415 /* deassert the preemption condition */
1416 amdgpu_ring_set_preempt_cond_exec(ring, true);
1417 return r;
1418}
1419
1420static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev,
1421 struct amdgpu_irq_src *source,
1422 unsigned type,
1423 enum amdgpu_interrupt_state state)
1424{
1425 u32 sdma_cntl;
1426
1427 u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL);
1428
1429 sdma_cntl = RREG32(reg_offset);
1430 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1431 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1432 WREG32(reg_offset, sdma_cntl);
1433
1434 return 0;
1435}
1436
1437static int sdma_v6_0_process_trap_irq(struct amdgpu_device *adev,
1438 struct amdgpu_irq_src *source,
1439 struct amdgpu_iv_entry *entry)
1440{
1441 int instances, queue;
1442 uint32_t mes_queue_id = entry->src_data[0];
1443
1444 DRM_DEBUG("IH: SDMA trap\n");
1445
1446 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1447 struct amdgpu_mes_queue *queue;
1448
1449 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1450
1451 spin_lock(&adev->mes.queue_id_lock);
1452 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1453 if (queue) {
1454 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1455 amdgpu_fence_process(queue->ring);
1456 }
1457 spin_unlock(&adev->mes.queue_id_lock);
1458 return 0;
1459 }
1460
1461 queue = entry->ring_id & 0xf;
1462 instances = (entry->ring_id & 0xf0) >> 4;
1463 if (instances > 1) {
1464 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n");
1465 return -EINVAL;
1466 }
1467
1468 switch (entry->client_id) {
1469 case SOC21_IH_CLIENTID_GFX:
1470 switch (queue) {
1471 case 0:
1472 amdgpu_fence_process(&adev->sdma.instance[instances].ring);
1473 break;
1474 default:
1475 break;
1476 }
1477 break;
1478 }
1479 return 0;
1480}
1481
1482static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1483 struct amdgpu_irq_src *source,
1484 struct amdgpu_iv_entry *entry)
1485{
1486 return 0;
1487}
1488
1489static int sdma_v6_0_set_clockgating_state(void *handle,
1490 enum amd_clockgating_state state)
1491{
1492 return 0;
1493}
1494
1495static int sdma_v6_0_set_powergating_state(void *handle,
1496 enum amd_powergating_state state)
1497{
1498 return 0;
1499}
1500
1501static void sdma_v6_0_get_clockgating_state(void *handle, u64 *flags)
1502{
1503}
1504
1505const struct amd_ip_funcs sdma_v6_0_ip_funcs = {
1506 .name = "sdma_v6_0",
1507 .early_init = sdma_v6_0_early_init,
1508 .late_init = NULL,
1509 .sw_init = sdma_v6_0_sw_init,
1510 .sw_fini = sdma_v6_0_sw_fini,
1511 .hw_init = sdma_v6_0_hw_init,
1512 .hw_fini = sdma_v6_0_hw_fini,
1513 .suspend = sdma_v6_0_suspend,
1514 .resume = sdma_v6_0_resume,
1515 .is_idle = sdma_v6_0_is_idle,
1516 .wait_for_idle = sdma_v6_0_wait_for_idle,
1517 .soft_reset = sdma_v6_0_soft_reset,
1518 .check_soft_reset = sdma_v6_0_check_soft_reset,
1519 .set_clockgating_state = sdma_v6_0_set_clockgating_state,
1520 .set_powergating_state = sdma_v6_0_set_powergating_state,
1521 .get_clockgating_state = sdma_v6_0_get_clockgating_state,
1522};
1523
1524static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = {
1525 .type = AMDGPU_RING_TYPE_SDMA,
1526 .align_mask = 0xf,
1527 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1528 .support_64bit_ptrs = true,
1529 .secure_submission_supported = true,
1530 .vmhub = AMDGPU_GFXHUB_0,
1531 .get_rptr = sdma_v6_0_ring_get_rptr,
1532 .get_wptr = sdma_v6_0_ring_get_wptr,
1533 .set_wptr = sdma_v6_0_ring_set_wptr,
1534 .emit_frame_size =
1535 5 + /* sdma_v6_0_ring_init_cond_exec */
1536 6 + /* sdma_v6_0_ring_emit_hdp_flush */
1537 6 + /* sdma_v6_0_ring_emit_pipeline_sync */
1538 /* sdma_v6_0_ring_emit_vm_flush */
1539 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1540 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1541 10 + 10 + 10, /* sdma_v6_0_ring_emit_fence x3 for user fence, vm fence */
1542 .emit_ib_size = 5 + 7 + 6, /* sdma_v6_0_ring_emit_ib */
1543 .emit_ib = sdma_v6_0_ring_emit_ib,
1544 .emit_mem_sync = sdma_v6_0_ring_emit_mem_sync,
1545 .emit_fence = sdma_v6_0_ring_emit_fence,
1546 .emit_pipeline_sync = sdma_v6_0_ring_emit_pipeline_sync,
1547 .emit_vm_flush = sdma_v6_0_ring_emit_vm_flush,
1548 .emit_hdp_flush = sdma_v6_0_ring_emit_hdp_flush,
1549 .test_ring = sdma_v6_0_ring_test_ring,
1550 .test_ib = sdma_v6_0_ring_test_ib,
1551 .insert_nop = sdma_v6_0_ring_insert_nop,
1552 .pad_ib = sdma_v6_0_ring_pad_ib,
1553 .emit_wreg = sdma_v6_0_ring_emit_wreg,
1554 .emit_reg_wait = sdma_v6_0_ring_emit_reg_wait,
1555 .emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait,
1556 .init_cond_exec = sdma_v6_0_ring_init_cond_exec,
1557 .patch_cond_exec = sdma_v6_0_ring_patch_cond_exec,
1558 .preempt_ib = sdma_v6_0_ring_preempt_ib,
1559};
1560
1561static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1562{
1563 int i;
1564
1565 for (i = 0; i < adev->sdma.num_instances; i++) {
1566 adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs;
1567 adev->sdma.instance[i].ring.me = i;
1568 }
1569}
1570
1571static const struct amdgpu_irq_src_funcs sdma_v6_0_trap_irq_funcs = {
1572 .set = sdma_v6_0_set_trap_irq_state,
1573 .process = sdma_v6_0_process_trap_irq,
1574};
1575
1576static const struct amdgpu_irq_src_funcs sdma_v6_0_illegal_inst_irq_funcs = {
1577 .process = sdma_v6_0_process_illegal_inst_irq,
1578};
1579
1580static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1581{
1582 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1583 adev->sdma.num_instances;
1584 adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs;
1585 adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs;
1586}
1587
1588/**
1589 * sdma_v6_0_emit_copy_buffer - copy buffer using the sDMA engine
1590 *
1591 * @ring: amdgpu_ring structure holding ring information
1592 * @src_offset: src GPU address
1593 * @dst_offset: dst GPU address
1594 * @byte_count: number of bytes to xfer
1595 *
1596 * Copy GPU buffers using the DMA engine.
1597 * Used by the amdgpu ttm implementation to move pages if
1598 * registered as the asic copy callback.
1599 */
1600static void sdma_v6_0_emit_copy_buffer(struct amdgpu_ib *ib,
1601 uint64_t src_offset,
1602 uint64_t dst_offset,
1603 uint32_t byte_count,
1604 bool tmz)
1605{
1606 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1607 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1608 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1609 ib->ptr[ib->length_dw++] = byte_count - 1;
1610 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1611 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1612 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1613 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1614 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1615}
1616
1617/**
1618 * sdma_v6_0_emit_fill_buffer - fill buffer using the sDMA engine
1619 *
1620 * @ring: amdgpu_ring structure holding ring information
1621 * @src_data: value to write to buffer
1622 * @dst_offset: dst GPU address
1623 * @byte_count: number of bytes to xfer
1624 *
1625 * Fill GPU buffers using the DMA engine.
1626 */
1627static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib,
1628 uint32_t src_data,
1629 uint64_t dst_offset,
1630 uint32_t byte_count)
1631{
1632 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_CONST_FILL);
1633 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1634 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1635 ib->ptr[ib->length_dw++] = src_data;
1636 ib->ptr[ib->length_dw++] = byte_count - 1;
1637}
1638
1639static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = {
1640 .copy_max_bytes = 0x400000,
1641 .copy_num_dw = 7,
1642 .emit_copy_buffer = sdma_v6_0_emit_copy_buffer,
1643
1644 .fill_max_bytes = 0x400000,
1645 .fill_num_dw = 5,
1646 .emit_fill_buffer = sdma_v6_0_emit_fill_buffer,
1647};
1648
1649static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev)
1650{
1651 adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs;
1652 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1653}
1654
1655static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = {
1656 .copy_pte_num_dw = 7,
1657 .copy_pte = sdma_v6_0_vm_copy_pte,
1658 .write_pte = sdma_v6_0_vm_write_pte,
1659 .set_pte_pde = sdma_v6_0_vm_set_pte_pde,
1660};
1661
1662static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1663{
1664 unsigned i;
1665
1666 adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs;
1667 for (i = 0; i < adev->sdma.num_instances; i++) {
1668 adev->vm_manager.vm_pte_scheds[i] =
1669 &adev->sdma.instance[i].ring.sched;
1670 }
1671 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1672}
1673
1674const struct amdgpu_ip_block_version sdma_v6_0_ip_block = {
1675 .type = AMD_IP_BLOCK_TYPE_SDMA,
1676 .major = 6,
1677 .minor = 0,
1678 .rev = 0,
1679 .funcs = &sdma_v6_0_ip_funcs,
1680};