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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/dma-fence-array.h>
30#include <linux/interval_tree_generic.h>
31#include <linux/idr.h>
32#include <linux/dma-buf.h>
33
34#include <drm/amdgpu_drm.h>
35#include <drm/drm_drv.h>
36#include <drm/ttm/ttm_tt.h>
37#include <drm/drm_exec.h>
38#include "amdgpu.h"
39#include "amdgpu_trace.h"
40#include "amdgpu_amdkfd.h"
41#include "amdgpu_gmc.h"
42#include "amdgpu_xgmi.h"
43#include "amdgpu_dma_buf.h"
44#include "amdgpu_res_cursor.h"
45#include "kfd_svm.h"
46
47/**
48 * DOC: GPUVM
49 *
50 * GPUVM is the MMU functionality provided on the GPU.
51 * GPUVM is similar to the legacy GART on older asics, however
52 * rather than there being a single global GART table
53 * for the entire GPU, there can be multiple GPUVM page tables active
54 * at any given time. The GPUVM page tables can contain a mix
55 * VRAM pages and system pages (both memory and MMIO) and system pages
56 * can be mapped as snooped (cached system pages) or unsnooped
57 * (uncached system pages).
58 *
59 * Each active GPUVM has an ID associated with it and there is a page table
60 * linked with each VMID. When executing a command buffer,
61 * the kernel tells the engine what VMID to use for that command
62 * buffer. VMIDs are allocated dynamically as commands are submitted.
63 * The userspace drivers maintain their own address space and the kernel
64 * sets up their pages tables accordingly when they submit their
65 * command buffers and a VMID is assigned.
66 * The hardware supports up to 16 active GPUVMs at any given time.
67 *
68 * Each GPUVM is represented by a 1-2 or 1-5 level page table, depending
69 * on the ASIC family. GPUVM supports RWX attributes on each page as well
70 * as other features such as encryption and caching attributes.
71 *
72 * VMID 0 is special. It is the GPUVM used for the kernel driver. In
73 * addition to an aperture managed by a page table, VMID 0 also has
74 * several other apertures. There is an aperture for direct access to VRAM
75 * and there is a legacy AGP aperture which just forwards accesses directly
76 * to the matching system physical addresses (or IOVAs when an IOMMU is
77 * present). These apertures provide direct access to these memories without
78 * incurring the overhead of a page table. VMID 0 is used by the kernel
79 * driver for tasks like memory management.
80 *
81 * GPU clients (i.e., engines on the GPU) use GPUVM VMIDs to access memory.
82 * For user applications, each application can have their own unique GPUVM
83 * address space. The application manages the address space and the kernel
84 * driver manages the GPUVM page tables for each process. If an GPU client
85 * accesses an invalid page, it will generate a GPU page fault, similar to
86 * accessing an invalid page on a CPU.
87 */
88
89#define START(node) ((node)->start)
90#define LAST(node) ((node)->last)
91
92INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
93 START, LAST, static, amdgpu_vm_it)
94
95#undef START
96#undef LAST
97
98/**
99 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
100 */
101struct amdgpu_prt_cb {
102
103 /**
104 * @adev: amdgpu device
105 */
106 struct amdgpu_device *adev;
107
108 /**
109 * @cb: callback
110 */
111 struct dma_fence_cb cb;
112};
113
114/**
115 * struct amdgpu_vm_tlb_seq_struct - Helper to increment the TLB flush sequence
116 */
117struct amdgpu_vm_tlb_seq_struct {
118 /**
119 * @vm: pointer to the amdgpu_vm structure to set the fence sequence on
120 */
121 struct amdgpu_vm *vm;
122
123 /**
124 * @cb: callback
125 */
126 struct dma_fence_cb cb;
127};
128
129/**
130 * amdgpu_vm_set_pasid - manage pasid and vm ptr mapping
131 *
132 * @adev: amdgpu_device pointer
133 * @vm: amdgpu_vm pointer
134 * @pasid: the pasid the VM is using on this GPU
135 *
136 * Set the pasid this VM is using on this GPU, can also be used to remove the
137 * pasid by passing in zero.
138 *
139 */
140int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm,
141 u32 pasid)
142{
143 int r;
144
145 if (vm->pasid == pasid)
146 return 0;
147
148 if (vm->pasid) {
149 r = xa_err(xa_erase_irq(&adev->vm_manager.pasids, vm->pasid));
150 if (r < 0)
151 return r;
152
153 vm->pasid = 0;
154 }
155
156 if (pasid) {
157 r = xa_err(xa_store_irq(&adev->vm_manager.pasids, pasid, vm,
158 GFP_KERNEL));
159 if (r < 0)
160 return r;
161
162 vm->pasid = pasid;
163 }
164
165
166 return 0;
167}
168
169/**
170 * amdgpu_vm_bo_evicted - vm_bo is evicted
171 *
172 * @vm_bo: vm_bo which is evicted
173 *
174 * State for PDs/PTs and per VM BOs which are not at the location they should
175 * be.
176 */
177static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
178{
179 struct amdgpu_vm *vm = vm_bo->vm;
180 struct amdgpu_bo *bo = vm_bo->bo;
181
182 vm_bo->moved = true;
183 spin_lock(&vm_bo->vm->status_lock);
184 if (bo->tbo.type == ttm_bo_type_kernel)
185 list_move(&vm_bo->vm_status, &vm->evicted);
186 else
187 list_move_tail(&vm_bo->vm_status, &vm->evicted);
188 spin_unlock(&vm_bo->vm->status_lock);
189}
190/**
191 * amdgpu_vm_bo_moved - vm_bo is moved
192 *
193 * @vm_bo: vm_bo which is moved
194 *
195 * State for per VM BOs which are moved, but that change is not yet reflected
196 * in the page tables.
197 */
198static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
199{
200 spin_lock(&vm_bo->vm->status_lock);
201 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
202 spin_unlock(&vm_bo->vm->status_lock);
203}
204
205/**
206 * amdgpu_vm_bo_idle - vm_bo is idle
207 *
208 * @vm_bo: vm_bo which is now idle
209 *
210 * State for PDs/PTs and per VM BOs which have gone through the state machine
211 * and are now idle.
212 */
213static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
214{
215 spin_lock(&vm_bo->vm->status_lock);
216 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
217 spin_unlock(&vm_bo->vm->status_lock);
218 vm_bo->moved = false;
219}
220
221/**
222 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
223 *
224 * @vm_bo: vm_bo which is now invalidated
225 *
226 * State for normal BOs which are invalidated and that change not yet reflected
227 * in the PTs.
228 */
229static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
230{
231 spin_lock(&vm_bo->vm->status_lock);
232 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
233 spin_unlock(&vm_bo->vm->status_lock);
234}
235
236/**
237 * amdgpu_vm_bo_relocated - vm_bo is reloacted
238 *
239 * @vm_bo: vm_bo which is relocated
240 *
241 * State for PDs/PTs which needs to update their parent PD.
242 * For the root PD, just move to idle state.
243 */
244static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
245{
246 if (vm_bo->bo->parent) {
247 spin_lock(&vm_bo->vm->status_lock);
248 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
249 spin_unlock(&vm_bo->vm->status_lock);
250 } else {
251 amdgpu_vm_bo_idle(vm_bo);
252 }
253}
254
255/**
256 * amdgpu_vm_bo_done - vm_bo is done
257 *
258 * @vm_bo: vm_bo which is now done
259 *
260 * State for normal BOs which are invalidated and that change has been updated
261 * in the PTs.
262 */
263static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
264{
265 spin_lock(&vm_bo->vm->status_lock);
266 list_move(&vm_bo->vm_status, &vm_bo->vm->done);
267 spin_unlock(&vm_bo->vm->status_lock);
268}
269
270/**
271 * amdgpu_vm_bo_reset_state_machine - reset the vm_bo state machine
272 * @vm: the VM which state machine to reset
273 *
274 * Move all vm_bo object in the VM into a state where they will be updated
275 * again during validation.
276 */
277static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm)
278{
279 struct amdgpu_vm_bo_base *vm_bo, *tmp;
280
281 spin_lock(&vm->status_lock);
282 list_splice_init(&vm->done, &vm->invalidated);
283 list_for_each_entry(vm_bo, &vm->invalidated, vm_status)
284 vm_bo->moved = true;
285 list_for_each_entry_safe(vm_bo, tmp, &vm->idle, vm_status) {
286 struct amdgpu_bo *bo = vm_bo->bo;
287
288 vm_bo->moved = true;
289 if (!bo || bo->tbo.type != ttm_bo_type_kernel)
290 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
291 else if (bo->parent)
292 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
293 }
294 spin_unlock(&vm->status_lock);
295}
296
297/**
298 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
299 *
300 * @base: base structure for tracking BO usage in a VM
301 * @vm: vm to which bo is to be added
302 * @bo: amdgpu buffer object
303 *
304 * Initialize a bo_va_base structure and add it to the appropriate lists
305 *
306 */
307void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
308 struct amdgpu_vm *vm, struct amdgpu_bo *bo)
309{
310 base->vm = vm;
311 base->bo = bo;
312 base->next = NULL;
313 INIT_LIST_HEAD(&base->vm_status);
314
315 if (!bo)
316 return;
317 base->next = bo->vm_bo;
318 bo->vm_bo = base;
319
320 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
321 return;
322
323 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
324
325 ttm_bo_set_bulk_move(&bo->tbo, &vm->lru_bulk_move);
326 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
327 amdgpu_vm_bo_relocated(base);
328 else
329 amdgpu_vm_bo_idle(base);
330
331 if (bo->preferred_domains &
332 amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type))
333 return;
334
335 /*
336 * we checked all the prerequisites, but it looks like this per vm bo
337 * is currently evicted. add the bo to the evicted list to make sure it
338 * is validated on next vm use to avoid fault.
339 * */
340 amdgpu_vm_bo_evicted(base);
341}
342
343/**
344 * amdgpu_vm_lock_pd - lock PD in drm_exec
345 *
346 * @vm: vm providing the BOs
347 * @exec: drm execution context
348 * @num_fences: number of extra fences to reserve
349 *
350 * Lock the VM root PD in the DRM execution context.
351 */
352int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec,
353 unsigned int num_fences)
354{
355 /* We need at least two fences for the VM PD/PT updates */
356 return drm_exec_prepare_obj(exec, &vm->root.bo->tbo.base,
357 2 + num_fences);
358}
359
360/**
361 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
362 *
363 * @adev: amdgpu device pointer
364 * @vm: vm providing the BOs
365 *
366 * Move all BOs to the end of LRU and remember their positions to put them
367 * together.
368 */
369void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
370 struct amdgpu_vm *vm)
371{
372 spin_lock(&adev->mman.bdev.lru_lock);
373 ttm_lru_bulk_move_tail(&vm->lru_bulk_move);
374 spin_unlock(&adev->mman.bdev.lru_lock);
375}
376
377/* Create scheduler entities for page table updates */
378static int amdgpu_vm_init_entities(struct amdgpu_device *adev,
379 struct amdgpu_vm *vm)
380{
381 int r;
382
383 r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
384 adev->vm_manager.vm_pte_scheds,
385 adev->vm_manager.vm_pte_num_scheds, NULL);
386 if (r)
387 goto error;
388
389 return drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
390 adev->vm_manager.vm_pte_scheds,
391 adev->vm_manager.vm_pte_num_scheds, NULL);
392
393error:
394 drm_sched_entity_destroy(&vm->immediate);
395 return r;
396}
397
398/* Destroy the entities for page table updates again */
399static void amdgpu_vm_fini_entities(struct amdgpu_vm *vm)
400{
401 drm_sched_entity_destroy(&vm->immediate);
402 drm_sched_entity_destroy(&vm->delayed);
403}
404
405/**
406 * amdgpu_vm_generation - return the page table re-generation counter
407 * @adev: the amdgpu_device
408 * @vm: optional VM to check, might be NULL
409 *
410 * Returns a page table re-generation token to allow checking if submissions
411 * are still valid to use this VM. The VM parameter might be NULL in which case
412 * just the VRAM lost counter will be used.
413 */
414uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm)
415{
416 uint64_t result = (u64)atomic_read(&adev->vram_lost_counter) << 32;
417
418 if (!vm)
419 return result;
420
421 result += vm->generation;
422 /* Add one if the page tables will be re-generated on next CS */
423 if (drm_sched_entity_error(&vm->delayed))
424 ++result;
425
426 return result;
427}
428
429/**
430 * amdgpu_vm_validate_pt_bos - validate the page table BOs
431 *
432 * @adev: amdgpu device pointer
433 * @vm: vm providing the BOs
434 * @validate: callback to do the validation
435 * @param: parameter for the validation callback
436 *
437 * Validate the page table BOs on command submission if neccessary.
438 *
439 * Returns:
440 * Validation result.
441 */
442int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
443 int (*validate)(void *p, struct amdgpu_bo *bo),
444 void *param)
445{
446 struct amdgpu_vm_bo_base *bo_base;
447 struct amdgpu_bo *shadow;
448 struct amdgpu_bo *bo;
449 int r;
450
451 if (drm_sched_entity_error(&vm->delayed)) {
452 ++vm->generation;
453 amdgpu_vm_bo_reset_state_machine(vm);
454 amdgpu_vm_fini_entities(vm);
455 r = amdgpu_vm_init_entities(adev, vm);
456 if (r)
457 return r;
458 }
459
460 spin_lock(&vm->status_lock);
461 while (!list_empty(&vm->evicted)) {
462 bo_base = list_first_entry(&vm->evicted,
463 struct amdgpu_vm_bo_base,
464 vm_status);
465 spin_unlock(&vm->status_lock);
466
467 bo = bo_base->bo;
468 shadow = amdgpu_bo_shadowed(bo);
469
470 r = validate(param, bo);
471 if (r)
472 return r;
473 if (shadow) {
474 r = validate(param, shadow);
475 if (r)
476 return r;
477 }
478
479 if (bo->tbo.type != ttm_bo_type_kernel) {
480 amdgpu_vm_bo_moved(bo_base);
481 } else {
482 vm->update_funcs->map_table(to_amdgpu_bo_vm(bo));
483 amdgpu_vm_bo_relocated(bo_base);
484 }
485 spin_lock(&vm->status_lock);
486 }
487 spin_unlock(&vm->status_lock);
488
489 amdgpu_vm_eviction_lock(vm);
490 vm->evicting = false;
491 amdgpu_vm_eviction_unlock(vm);
492
493 return 0;
494}
495
496/**
497 * amdgpu_vm_ready - check VM is ready for updates
498 *
499 * @vm: VM to check
500 *
501 * Check if all VM PDs/PTs are ready for updates
502 *
503 * Returns:
504 * True if VM is not evicting.
505 */
506bool amdgpu_vm_ready(struct amdgpu_vm *vm)
507{
508 bool empty;
509 bool ret;
510
511 amdgpu_vm_eviction_lock(vm);
512 ret = !vm->evicting;
513 amdgpu_vm_eviction_unlock(vm);
514
515 spin_lock(&vm->status_lock);
516 empty = list_empty(&vm->evicted);
517 spin_unlock(&vm->status_lock);
518
519 return ret && empty;
520}
521
522/**
523 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
524 *
525 * @adev: amdgpu_device pointer
526 */
527void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
528{
529 const struct amdgpu_ip_block *ip_block;
530 bool has_compute_vm_bug;
531 struct amdgpu_ring *ring;
532 int i;
533
534 has_compute_vm_bug = false;
535
536 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
537 if (ip_block) {
538 /* Compute has a VM bug for GFX version < 7.
539 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
540 if (ip_block->version->major <= 7)
541 has_compute_vm_bug = true;
542 else if (ip_block->version->major == 8)
543 if (adev->gfx.mec_fw_version < 673)
544 has_compute_vm_bug = true;
545 }
546
547 for (i = 0; i < adev->num_rings; i++) {
548 ring = adev->rings[i];
549 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
550 /* only compute rings */
551 ring->has_compute_vm_bug = has_compute_vm_bug;
552 else
553 ring->has_compute_vm_bug = false;
554 }
555}
556
557/**
558 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
559 *
560 * @ring: ring on which the job will be submitted
561 * @job: job to submit
562 *
563 * Returns:
564 * True if sync is needed.
565 */
566bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
567 struct amdgpu_job *job)
568{
569 struct amdgpu_device *adev = ring->adev;
570 unsigned vmhub = ring->vm_hub;
571 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
572
573 if (job->vmid == 0)
574 return false;
575
576 if (job->vm_needs_flush || ring->has_compute_vm_bug)
577 return true;
578
579 if (ring->funcs->emit_gds_switch && job->gds_switch_needed)
580 return true;
581
582 if (amdgpu_vmid_had_gpu_reset(adev, &id_mgr->ids[job->vmid]))
583 return true;
584
585 return false;
586}
587
588/**
589 * amdgpu_vm_flush - hardware flush the vm
590 *
591 * @ring: ring to use for flush
592 * @job: related job
593 * @need_pipe_sync: is pipe sync needed
594 *
595 * Emit a VM flush when it is necessary.
596 *
597 * Returns:
598 * 0 on success, errno otherwise.
599 */
600int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
601 bool need_pipe_sync)
602{
603 struct amdgpu_device *adev = ring->adev;
604 unsigned vmhub = ring->vm_hub;
605 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
606 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
607 bool spm_update_needed = job->spm_update_needed;
608 bool gds_switch_needed = ring->funcs->emit_gds_switch &&
609 job->gds_switch_needed;
610 bool vm_flush_needed = job->vm_needs_flush;
611 struct dma_fence *fence = NULL;
612 bool pasid_mapping_needed = false;
613 unsigned patch_offset = 0;
614 int r;
615
616 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
617 gds_switch_needed = true;
618 vm_flush_needed = true;
619 pasid_mapping_needed = true;
620 spm_update_needed = true;
621 }
622
623 mutex_lock(&id_mgr->lock);
624 if (id->pasid != job->pasid || !id->pasid_mapping ||
625 !dma_fence_is_signaled(id->pasid_mapping))
626 pasid_mapping_needed = true;
627 mutex_unlock(&id_mgr->lock);
628
629 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
630 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
631 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
632 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
633 ring->funcs->emit_wreg;
634
635 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
636 return 0;
637
638 amdgpu_ring_ib_begin(ring);
639 if (ring->funcs->init_cond_exec)
640 patch_offset = amdgpu_ring_init_cond_exec(ring);
641
642 if (need_pipe_sync)
643 amdgpu_ring_emit_pipeline_sync(ring);
644
645 if (vm_flush_needed) {
646 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
647 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
648 }
649
650 if (pasid_mapping_needed)
651 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
652
653 if (spm_update_needed && adev->gfx.rlc.funcs->update_spm_vmid)
654 adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid);
655
656 if (!ring->is_mes_queue && ring->funcs->emit_gds_switch &&
657 gds_switch_needed) {
658 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
659 job->gds_size, job->gws_base,
660 job->gws_size, job->oa_base,
661 job->oa_size);
662 }
663
664 if (vm_flush_needed || pasid_mapping_needed) {
665 r = amdgpu_fence_emit(ring, &fence, NULL, 0);
666 if (r)
667 return r;
668 }
669
670 if (vm_flush_needed) {
671 mutex_lock(&id_mgr->lock);
672 dma_fence_put(id->last_flush);
673 id->last_flush = dma_fence_get(fence);
674 id->current_gpu_reset_count =
675 atomic_read(&adev->gpu_reset_counter);
676 mutex_unlock(&id_mgr->lock);
677 }
678
679 if (pasid_mapping_needed) {
680 mutex_lock(&id_mgr->lock);
681 id->pasid = job->pasid;
682 dma_fence_put(id->pasid_mapping);
683 id->pasid_mapping = dma_fence_get(fence);
684 mutex_unlock(&id_mgr->lock);
685 }
686 dma_fence_put(fence);
687
688 if (ring->funcs->patch_cond_exec)
689 amdgpu_ring_patch_cond_exec(ring, patch_offset);
690
691 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
692 if (ring->funcs->emit_switch_buffer) {
693 amdgpu_ring_emit_switch_buffer(ring);
694 amdgpu_ring_emit_switch_buffer(ring);
695 }
696 amdgpu_ring_ib_end(ring);
697 return 0;
698}
699
700/**
701 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
702 *
703 * @vm: requested vm
704 * @bo: requested buffer object
705 *
706 * Find @bo inside the requested vm.
707 * Search inside the @bos vm list for the requested vm
708 * Returns the found bo_va or NULL if none is found
709 *
710 * Object has to be reserved!
711 *
712 * Returns:
713 * Found bo_va or NULL.
714 */
715struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
716 struct amdgpu_bo *bo)
717{
718 struct amdgpu_vm_bo_base *base;
719
720 for (base = bo->vm_bo; base; base = base->next) {
721 if (base->vm != vm)
722 continue;
723
724 return container_of(base, struct amdgpu_bo_va, base);
725 }
726 return NULL;
727}
728
729/**
730 * amdgpu_vm_map_gart - Resolve gart mapping of addr
731 *
732 * @pages_addr: optional DMA address to use for lookup
733 * @addr: the unmapped addr
734 *
735 * Look up the physical address of the page that the pte resolves
736 * to.
737 *
738 * Returns:
739 * The pointer for the page table entry.
740 */
741uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
742{
743 uint64_t result;
744
745 /* page table offset */
746 result = pages_addr[addr >> PAGE_SHIFT];
747
748 /* in case cpu page size != gpu page size*/
749 result |= addr & (~PAGE_MASK);
750
751 result &= 0xFFFFFFFFFFFFF000ULL;
752
753 return result;
754}
755
756/**
757 * amdgpu_vm_update_pdes - make sure that all directories are valid
758 *
759 * @adev: amdgpu_device pointer
760 * @vm: requested vm
761 * @immediate: submit immediately to the paging queue
762 *
763 * Makes sure all directories are up to date.
764 *
765 * Returns:
766 * 0 for success, error for failure.
767 */
768int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
769 struct amdgpu_vm *vm, bool immediate)
770{
771 struct amdgpu_vm_update_params params;
772 struct amdgpu_vm_bo_base *entry;
773 bool flush_tlb_needed = false;
774 LIST_HEAD(relocated);
775 int r, idx;
776
777 spin_lock(&vm->status_lock);
778 list_splice_init(&vm->relocated, &relocated);
779 spin_unlock(&vm->status_lock);
780
781 if (list_empty(&relocated))
782 return 0;
783
784 if (!drm_dev_enter(adev_to_drm(adev), &idx))
785 return -ENODEV;
786
787 memset(¶ms, 0, sizeof(params));
788 params.adev = adev;
789 params.vm = vm;
790 params.immediate = immediate;
791
792 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
793 if (r)
794 goto error;
795
796 list_for_each_entry(entry, &relocated, vm_status) {
797 /* vm_flush_needed after updating moved PDEs */
798 flush_tlb_needed |= entry->moved;
799
800 r = amdgpu_vm_pde_update(¶ms, entry);
801 if (r)
802 goto error;
803 }
804
805 r = vm->update_funcs->commit(¶ms, &vm->last_update);
806 if (r)
807 goto error;
808
809 if (flush_tlb_needed)
810 atomic64_inc(&vm->tlb_seq);
811
812 while (!list_empty(&relocated)) {
813 entry = list_first_entry(&relocated, struct amdgpu_vm_bo_base,
814 vm_status);
815 amdgpu_vm_bo_idle(entry);
816 }
817
818error:
819 drm_dev_exit(idx);
820 return r;
821}
822
823/**
824 * amdgpu_vm_tlb_seq_cb - make sure to increment tlb sequence
825 * @fence: unused
826 * @cb: the callback structure
827 *
828 * Increments the tlb sequence to make sure that future CS execute a VM flush.
829 */
830static void amdgpu_vm_tlb_seq_cb(struct dma_fence *fence,
831 struct dma_fence_cb *cb)
832{
833 struct amdgpu_vm_tlb_seq_struct *tlb_cb;
834
835 tlb_cb = container_of(cb, typeof(*tlb_cb), cb);
836 atomic64_inc(&tlb_cb->vm->tlb_seq);
837 kfree(tlb_cb);
838}
839
840/**
841 * amdgpu_vm_update_range - update a range in the vm page table
842 *
843 * @adev: amdgpu_device pointer to use for commands
844 * @vm: the VM to update the range
845 * @immediate: immediate submission in a page fault
846 * @unlocked: unlocked invalidation during MM callback
847 * @flush_tlb: trigger tlb invalidation after update completed
848 * @allow_override: change MTYPE for local NUMA nodes
849 * @resv: fences we need to sync to
850 * @start: start of mapped range
851 * @last: last mapped entry
852 * @flags: flags for the entries
853 * @offset: offset into nodes and pages_addr
854 * @vram_base: base for vram mappings
855 * @res: ttm_resource to map
856 * @pages_addr: DMA addresses to use for mapping
857 * @fence: optional resulting fence
858 *
859 * Fill in the page table entries between @start and @last.
860 *
861 * Returns:
862 * 0 for success, negative erro code for failure.
863 */
864int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
865 bool immediate, bool unlocked, bool flush_tlb, bool allow_override,
866 struct dma_resv *resv, uint64_t start, uint64_t last,
867 uint64_t flags, uint64_t offset, uint64_t vram_base,
868 struct ttm_resource *res, dma_addr_t *pages_addr,
869 struct dma_fence **fence)
870{
871 struct amdgpu_vm_update_params params;
872 struct amdgpu_vm_tlb_seq_struct *tlb_cb;
873 struct amdgpu_res_cursor cursor;
874 enum amdgpu_sync_mode sync_mode;
875 int r, idx;
876
877 if (!drm_dev_enter(adev_to_drm(adev), &idx))
878 return -ENODEV;
879
880 tlb_cb = kmalloc(sizeof(*tlb_cb), GFP_KERNEL);
881 if (!tlb_cb) {
882 r = -ENOMEM;
883 goto error_unlock;
884 }
885
886 /* Vega20+XGMI where PTEs get inadvertently cached in L2 texture cache,
887 * heavy-weight flush TLB unconditionally.
888 */
889 flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
890 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0);
891
892 /*
893 * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB
894 */
895 flush_tlb |= amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 0, 0);
896
897 memset(¶ms, 0, sizeof(params));
898 params.adev = adev;
899 params.vm = vm;
900 params.immediate = immediate;
901 params.pages_addr = pages_addr;
902 params.unlocked = unlocked;
903 params.allow_override = allow_override;
904
905 /* Implicitly sync to command submissions in the same VM before
906 * unmapping. Sync to moving fences before mapping.
907 */
908 if (!(flags & AMDGPU_PTE_VALID))
909 sync_mode = AMDGPU_SYNC_EQ_OWNER;
910 else
911 sync_mode = AMDGPU_SYNC_EXPLICIT;
912
913 amdgpu_vm_eviction_lock(vm);
914 if (vm->evicting) {
915 r = -EBUSY;
916 goto error_free;
917 }
918
919 if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
920 struct dma_fence *tmp = dma_fence_get_stub();
921
922 amdgpu_bo_fence(vm->root.bo, vm->last_unlocked, true);
923 swap(vm->last_unlocked, tmp);
924 dma_fence_put(tmp);
925 }
926
927 r = vm->update_funcs->prepare(¶ms, resv, sync_mode);
928 if (r)
929 goto error_free;
930
931 amdgpu_res_first(pages_addr ? NULL : res, offset,
932 (last - start + 1) * AMDGPU_GPU_PAGE_SIZE, &cursor);
933 while (cursor.remaining) {
934 uint64_t tmp, num_entries, addr;
935
936 num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT;
937 if (pages_addr) {
938 bool contiguous = true;
939
940 if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) {
941 uint64_t pfn = cursor.start >> PAGE_SHIFT;
942 uint64_t count;
943
944 contiguous = pages_addr[pfn + 1] ==
945 pages_addr[pfn] + PAGE_SIZE;
946
947 tmp = num_entries /
948 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
949 for (count = 2; count < tmp; ++count) {
950 uint64_t idx = pfn + count;
951
952 if (contiguous != (pages_addr[idx] ==
953 pages_addr[idx - 1] + PAGE_SIZE))
954 break;
955 }
956 if (!contiguous)
957 count--;
958 num_entries = count *
959 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
960 }
961
962 if (!contiguous) {
963 addr = cursor.start;
964 params.pages_addr = pages_addr;
965 } else {
966 addr = pages_addr[cursor.start >> PAGE_SHIFT];
967 params.pages_addr = NULL;
968 }
969
970 } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
971 addr = vram_base + cursor.start;
972 } else {
973 addr = 0;
974 }
975
976 tmp = start + num_entries;
977 r = amdgpu_vm_ptes_update(¶ms, start, tmp, addr, flags);
978 if (r)
979 goto error_free;
980
981 amdgpu_res_next(&cursor, num_entries * AMDGPU_GPU_PAGE_SIZE);
982 start = tmp;
983 }
984
985 r = vm->update_funcs->commit(¶ms, fence);
986
987 if (flush_tlb || params.table_freed) {
988 tlb_cb->vm = vm;
989 if (fence && *fence &&
990 !dma_fence_add_callback(*fence, &tlb_cb->cb,
991 amdgpu_vm_tlb_seq_cb)) {
992 dma_fence_put(vm->last_tlb_flush);
993 vm->last_tlb_flush = dma_fence_get(*fence);
994 } else {
995 amdgpu_vm_tlb_seq_cb(NULL, &tlb_cb->cb);
996 }
997 tlb_cb = NULL;
998 }
999
1000error_free:
1001 kfree(tlb_cb);
1002
1003error_unlock:
1004 amdgpu_vm_eviction_unlock(vm);
1005 drm_dev_exit(idx);
1006 return r;
1007}
1008
1009static void amdgpu_vm_bo_get_memory(struct amdgpu_bo_va *bo_va,
1010 struct amdgpu_mem_stats *stats)
1011{
1012 struct amdgpu_vm *vm = bo_va->base.vm;
1013 struct amdgpu_bo *bo = bo_va->base.bo;
1014
1015 if (!bo)
1016 return;
1017
1018 /*
1019 * For now ignore BOs which are currently locked and potentially
1020 * changing their location.
1021 */
1022 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv &&
1023 !dma_resv_trylock(bo->tbo.base.resv))
1024 return;
1025
1026 amdgpu_bo_get_memory(bo, stats);
1027 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
1028 dma_resv_unlock(bo->tbo.base.resv);
1029}
1030
1031void amdgpu_vm_get_memory(struct amdgpu_vm *vm,
1032 struct amdgpu_mem_stats *stats)
1033{
1034 struct amdgpu_bo_va *bo_va, *tmp;
1035
1036 spin_lock(&vm->status_lock);
1037 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status)
1038 amdgpu_vm_bo_get_memory(bo_va, stats);
1039
1040 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status)
1041 amdgpu_vm_bo_get_memory(bo_va, stats);
1042
1043 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status)
1044 amdgpu_vm_bo_get_memory(bo_va, stats);
1045
1046 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status)
1047 amdgpu_vm_bo_get_memory(bo_va, stats);
1048
1049 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status)
1050 amdgpu_vm_bo_get_memory(bo_va, stats);
1051
1052 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status)
1053 amdgpu_vm_bo_get_memory(bo_va, stats);
1054 spin_unlock(&vm->status_lock);
1055}
1056
1057/**
1058 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1059 *
1060 * @adev: amdgpu_device pointer
1061 * @bo_va: requested BO and VM object
1062 * @clear: if true clear the entries
1063 *
1064 * Fill in the page table entries for @bo_va.
1065 *
1066 * Returns:
1067 * 0 for success, -EINVAL for failure.
1068 */
1069int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
1070 bool clear)
1071{
1072 struct amdgpu_bo *bo = bo_va->base.bo;
1073 struct amdgpu_vm *vm = bo_va->base.vm;
1074 struct amdgpu_bo_va_mapping *mapping;
1075 dma_addr_t *pages_addr = NULL;
1076 struct ttm_resource *mem;
1077 struct dma_fence **last_update;
1078 bool flush_tlb = clear;
1079 bool uncached;
1080 struct dma_resv *resv;
1081 uint64_t vram_base;
1082 uint64_t flags;
1083 int r;
1084
1085 if (clear || !bo) {
1086 mem = NULL;
1087 resv = vm->root.bo->tbo.base.resv;
1088 } else {
1089 struct drm_gem_object *obj = &bo->tbo.base;
1090
1091 resv = bo->tbo.base.resv;
1092 if (obj->import_attach && bo_va->is_xgmi) {
1093 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
1094 struct drm_gem_object *gobj = dma_buf->priv;
1095 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
1096
1097 if (abo->tbo.resource &&
1098 abo->tbo.resource->mem_type == TTM_PL_VRAM)
1099 bo = gem_to_amdgpu_bo(gobj);
1100 }
1101 mem = bo->tbo.resource;
1102 if (mem && (mem->mem_type == TTM_PL_TT ||
1103 mem->mem_type == AMDGPU_PL_PREEMPT))
1104 pages_addr = bo->tbo.ttm->dma_address;
1105 }
1106
1107 if (bo) {
1108 struct amdgpu_device *bo_adev;
1109
1110 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1111
1112 if (amdgpu_bo_encrypted(bo))
1113 flags |= AMDGPU_PTE_TMZ;
1114
1115 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1116 vram_base = bo_adev->vm_manager.vram_base_offset;
1117 uncached = (bo->flags & AMDGPU_GEM_CREATE_UNCACHED) != 0;
1118 } else {
1119 flags = 0x0;
1120 vram_base = 0;
1121 uncached = false;
1122 }
1123
1124 if (clear || (bo && bo->tbo.base.resv ==
1125 vm->root.bo->tbo.base.resv))
1126 last_update = &vm->last_update;
1127 else
1128 last_update = &bo_va->last_pt_update;
1129
1130 if (!clear && bo_va->base.moved) {
1131 flush_tlb = true;
1132 list_splice_init(&bo_va->valids, &bo_va->invalids);
1133
1134 } else if (bo_va->cleared != clear) {
1135 list_splice_init(&bo_va->valids, &bo_va->invalids);
1136 }
1137
1138 list_for_each_entry(mapping, &bo_va->invalids, list) {
1139 uint64_t update_flags = flags;
1140
1141 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1142 * but in case of something, we filter the flags in first place
1143 */
1144 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1145 update_flags &= ~AMDGPU_PTE_READABLE;
1146 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1147 update_flags &= ~AMDGPU_PTE_WRITEABLE;
1148
1149 /* Apply ASIC specific mapping flags */
1150 amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags);
1151
1152 trace_amdgpu_vm_bo_update(mapping);
1153
1154 r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb,
1155 !uncached, resv, mapping->start, mapping->last,
1156 update_flags, mapping->offset,
1157 vram_base, mem, pages_addr,
1158 last_update);
1159 if (r)
1160 return r;
1161 }
1162
1163 /* If the BO is not in its preferred location add it back to
1164 * the evicted list so that it gets validated again on the
1165 * next command submission.
1166 */
1167 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
1168 uint32_t mem_type = bo->tbo.resource->mem_type;
1169
1170 if (!(bo->preferred_domains &
1171 amdgpu_mem_type_to_domain(mem_type)))
1172 amdgpu_vm_bo_evicted(&bo_va->base);
1173 else
1174 amdgpu_vm_bo_idle(&bo_va->base);
1175 } else {
1176 amdgpu_vm_bo_done(&bo_va->base);
1177 }
1178
1179 list_splice_init(&bo_va->invalids, &bo_va->valids);
1180 bo_va->cleared = clear;
1181 bo_va->base.moved = false;
1182
1183 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1184 list_for_each_entry(mapping, &bo_va->valids, list)
1185 trace_amdgpu_vm_bo_mapping(mapping);
1186 }
1187
1188 return 0;
1189}
1190
1191/**
1192 * amdgpu_vm_update_prt_state - update the global PRT state
1193 *
1194 * @adev: amdgpu_device pointer
1195 */
1196static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1197{
1198 unsigned long flags;
1199 bool enable;
1200
1201 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1202 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1203 adev->gmc.gmc_funcs->set_prt(adev, enable);
1204 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1205}
1206
1207/**
1208 * amdgpu_vm_prt_get - add a PRT user
1209 *
1210 * @adev: amdgpu_device pointer
1211 */
1212static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1213{
1214 if (!adev->gmc.gmc_funcs->set_prt)
1215 return;
1216
1217 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1218 amdgpu_vm_update_prt_state(adev);
1219}
1220
1221/**
1222 * amdgpu_vm_prt_put - drop a PRT user
1223 *
1224 * @adev: amdgpu_device pointer
1225 */
1226static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1227{
1228 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1229 amdgpu_vm_update_prt_state(adev);
1230}
1231
1232/**
1233 * amdgpu_vm_prt_cb - callback for updating the PRT status
1234 *
1235 * @fence: fence for the callback
1236 * @_cb: the callback function
1237 */
1238static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1239{
1240 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1241
1242 amdgpu_vm_prt_put(cb->adev);
1243 kfree(cb);
1244}
1245
1246/**
1247 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1248 *
1249 * @adev: amdgpu_device pointer
1250 * @fence: fence for the callback
1251 */
1252static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1253 struct dma_fence *fence)
1254{
1255 struct amdgpu_prt_cb *cb;
1256
1257 if (!adev->gmc.gmc_funcs->set_prt)
1258 return;
1259
1260 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1261 if (!cb) {
1262 /* Last resort when we are OOM */
1263 if (fence)
1264 dma_fence_wait(fence, false);
1265
1266 amdgpu_vm_prt_put(adev);
1267 } else {
1268 cb->adev = adev;
1269 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1270 amdgpu_vm_prt_cb))
1271 amdgpu_vm_prt_cb(fence, &cb->cb);
1272 }
1273}
1274
1275/**
1276 * amdgpu_vm_free_mapping - free a mapping
1277 *
1278 * @adev: amdgpu_device pointer
1279 * @vm: requested vm
1280 * @mapping: mapping to be freed
1281 * @fence: fence of the unmap operation
1282 *
1283 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1284 */
1285static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1286 struct amdgpu_vm *vm,
1287 struct amdgpu_bo_va_mapping *mapping,
1288 struct dma_fence *fence)
1289{
1290 if (mapping->flags & AMDGPU_PTE_PRT)
1291 amdgpu_vm_add_prt_cb(adev, fence);
1292 kfree(mapping);
1293}
1294
1295/**
1296 * amdgpu_vm_prt_fini - finish all prt mappings
1297 *
1298 * @adev: amdgpu_device pointer
1299 * @vm: requested vm
1300 *
1301 * Register a cleanup callback to disable PRT support after VM dies.
1302 */
1303static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1304{
1305 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1306 struct dma_resv_iter cursor;
1307 struct dma_fence *fence;
1308
1309 dma_resv_for_each_fence(&cursor, resv, DMA_RESV_USAGE_BOOKKEEP, fence) {
1310 /* Add a callback for each fence in the reservation object */
1311 amdgpu_vm_prt_get(adev);
1312 amdgpu_vm_add_prt_cb(adev, fence);
1313 }
1314}
1315
1316/**
1317 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1318 *
1319 * @adev: amdgpu_device pointer
1320 * @vm: requested vm
1321 * @fence: optional resulting fence (unchanged if no work needed to be done
1322 * or if an error occurred)
1323 *
1324 * Make sure all freed BOs are cleared in the PT.
1325 * PTs have to be reserved and mutex must be locked!
1326 *
1327 * Returns:
1328 * 0 for success.
1329 *
1330 */
1331int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1332 struct amdgpu_vm *vm,
1333 struct dma_fence **fence)
1334{
1335 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1336 struct amdgpu_bo_va_mapping *mapping;
1337 uint64_t init_pte_value = 0;
1338 struct dma_fence *f = NULL;
1339 int r;
1340
1341 while (!list_empty(&vm->freed)) {
1342 mapping = list_first_entry(&vm->freed,
1343 struct amdgpu_bo_va_mapping, list);
1344 list_del(&mapping->list);
1345
1346 if (vm->pte_support_ats &&
1347 mapping->start < AMDGPU_GMC_HOLE_START)
1348 init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
1349
1350 r = amdgpu_vm_update_range(adev, vm, false, false, true, false,
1351 resv, mapping->start, mapping->last,
1352 init_pte_value, 0, 0, NULL, NULL,
1353 &f);
1354 amdgpu_vm_free_mapping(adev, vm, mapping, f);
1355 if (r) {
1356 dma_fence_put(f);
1357 return r;
1358 }
1359 }
1360
1361 if (fence && f) {
1362 dma_fence_put(*fence);
1363 *fence = f;
1364 } else {
1365 dma_fence_put(f);
1366 }
1367
1368 return 0;
1369
1370}
1371
1372/**
1373 * amdgpu_vm_handle_moved - handle moved BOs in the PT
1374 *
1375 * @adev: amdgpu_device pointer
1376 * @vm: requested vm
1377 * @ticket: optional reservation ticket used to reserve the VM
1378 *
1379 * Make sure all BOs which are moved are updated in the PTs.
1380 *
1381 * Returns:
1382 * 0 for success.
1383 *
1384 * PTs have to be reserved!
1385 */
1386int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
1387 struct amdgpu_vm *vm,
1388 struct ww_acquire_ctx *ticket)
1389{
1390 struct amdgpu_bo_va *bo_va;
1391 struct dma_resv *resv;
1392 bool clear, unlock;
1393 int r;
1394
1395 spin_lock(&vm->status_lock);
1396 while (!list_empty(&vm->moved)) {
1397 bo_va = list_first_entry(&vm->moved, struct amdgpu_bo_va,
1398 base.vm_status);
1399 spin_unlock(&vm->status_lock);
1400
1401 /* Per VM BOs never need to bo cleared in the page tables */
1402 r = amdgpu_vm_bo_update(adev, bo_va, false);
1403 if (r)
1404 return r;
1405 spin_lock(&vm->status_lock);
1406 }
1407
1408 while (!list_empty(&vm->invalidated)) {
1409 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
1410 base.vm_status);
1411 resv = bo_va->base.bo->tbo.base.resv;
1412 spin_unlock(&vm->status_lock);
1413
1414 /* Try to reserve the BO to avoid clearing its ptes */
1415 if (!adev->debug_vm && dma_resv_trylock(resv)) {
1416 clear = false;
1417 unlock = true;
1418 /* The caller is already holding the reservation lock */
1419 } else if (ticket && dma_resv_locking_ctx(resv) == ticket) {
1420 clear = false;
1421 unlock = false;
1422 /* Somebody else is using the BO right now */
1423 } else {
1424 clear = true;
1425 unlock = false;
1426 }
1427
1428 r = amdgpu_vm_bo_update(adev, bo_va, clear);
1429 if (r)
1430 return r;
1431
1432 if (unlock)
1433 dma_resv_unlock(resv);
1434 spin_lock(&vm->status_lock);
1435 }
1436 spin_unlock(&vm->status_lock);
1437
1438 return 0;
1439}
1440
1441/**
1442 * amdgpu_vm_flush_compute_tlb - Flush TLB on compute VM
1443 *
1444 * @adev: amdgpu_device pointer
1445 * @vm: requested vm
1446 * @flush_type: flush type
1447 * @xcc_mask: mask of XCCs that belong to the compute partition in need of a TLB flush.
1448 *
1449 * Flush TLB if needed for a compute VM.
1450 *
1451 * Returns:
1452 * 0 for success.
1453 */
1454int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev,
1455 struct amdgpu_vm *vm,
1456 uint32_t flush_type,
1457 uint32_t xcc_mask)
1458{
1459 uint64_t tlb_seq = amdgpu_vm_tlb_seq(vm);
1460 bool all_hub = false;
1461 int xcc = 0, r = 0;
1462
1463 WARN_ON_ONCE(!vm->is_compute_context);
1464
1465 /*
1466 * It can be that we race and lose here, but that is extremely unlikely
1467 * and the worst thing which could happen is that we flush the changes
1468 * into the TLB once more which is harmless.
1469 */
1470 if (atomic64_xchg(&vm->kfd_last_flushed_seq, tlb_seq) == tlb_seq)
1471 return 0;
1472
1473 if (adev->family == AMDGPU_FAMILY_AI ||
1474 adev->family == AMDGPU_FAMILY_RV)
1475 all_hub = true;
1476
1477 for_each_inst(xcc, xcc_mask) {
1478 r = amdgpu_gmc_flush_gpu_tlb_pasid(adev, vm->pasid, flush_type,
1479 all_hub, xcc);
1480 if (r)
1481 break;
1482 }
1483 return r;
1484}
1485
1486/**
1487 * amdgpu_vm_bo_add - add a bo to a specific vm
1488 *
1489 * @adev: amdgpu_device pointer
1490 * @vm: requested vm
1491 * @bo: amdgpu buffer object
1492 *
1493 * Add @bo into the requested vm.
1494 * Add @bo to the list of bos associated with the vm
1495 *
1496 * Returns:
1497 * Newly added bo_va or NULL for failure
1498 *
1499 * Object has to be reserved!
1500 */
1501struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1502 struct amdgpu_vm *vm,
1503 struct amdgpu_bo *bo)
1504{
1505 struct amdgpu_bo_va *bo_va;
1506
1507 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1508 if (bo_va == NULL) {
1509 return NULL;
1510 }
1511 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
1512
1513 bo_va->ref_count = 1;
1514 bo_va->last_pt_update = dma_fence_get_stub();
1515 INIT_LIST_HEAD(&bo_va->valids);
1516 INIT_LIST_HEAD(&bo_va->invalids);
1517
1518 if (!bo)
1519 return bo_va;
1520
1521 dma_resv_assert_held(bo->tbo.base.resv);
1522 if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) {
1523 bo_va->is_xgmi = true;
1524 /* Power up XGMI if it can be potentially used */
1525 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
1526 }
1527
1528 return bo_va;
1529}
1530
1531
1532/**
1533 * amdgpu_vm_bo_insert_map - insert a new mapping
1534 *
1535 * @adev: amdgpu_device pointer
1536 * @bo_va: bo_va to store the address
1537 * @mapping: the mapping to insert
1538 *
1539 * Insert a new mapping into all structures.
1540 */
1541static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
1542 struct amdgpu_bo_va *bo_va,
1543 struct amdgpu_bo_va_mapping *mapping)
1544{
1545 struct amdgpu_vm *vm = bo_va->base.vm;
1546 struct amdgpu_bo *bo = bo_va->base.bo;
1547
1548 mapping->bo_va = bo_va;
1549 list_add(&mapping->list, &bo_va->invalids);
1550 amdgpu_vm_it_insert(mapping, &vm->va);
1551
1552 if (mapping->flags & AMDGPU_PTE_PRT)
1553 amdgpu_vm_prt_get(adev);
1554
1555 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1556 !bo_va->base.moved) {
1557 amdgpu_vm_bo_moved(&bo_va->base);
1558 }
1559 trace_amdgpu_vm_bo_map(bo_va, mapping);
1560}
1561
1562/**
1563 * amdgpu_vm_bo_map - map bo inside a vm
1564 *
1565 * @adev: amdgpu_device pointer
1566 * @bo_va: bo_va to store the address
1567 * @saddr: where to map the BO
1568 * @offset: requested offset in the BO
1569 * @size: BO size in bytes
1570 * @flags: attributes of pages (read/write/valid/etc.)
1571 *
1572 * Add a mapping of the BO at the specefied addr into the VM.
1573 *
1574 * Returns:
1575 * 0 for success, error for failure.
1576 *
1577 * Object has to be reserved and unreserved outside!
1578 */
1579int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1580 struct amdgpu_bo_va *bo_va,
1581 uint64_t saddr, uint64_t offset,
1582 uint64_t size, uint64_t flags)
1583{
1584 struct amdgpu_bo_va_mapping *mapping, *tmp;
1585 struct amdgpu_bo *bo = bo_va->base.bo;
1586 struct amdgpu_vm *vm = bo_va->base.vm;
1587 uint64_t eaddr;
1588
1589 /* validate the parameters */
1590 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK || size & ~PAGE_MASK)
1591 return -EINVAL;
1592 if (saddr + size <= saddr || offset + size <= offset)
1593 return -EINVAL;
1594
1595 /* make sure object fit at this offset */
1596 eaddr = saddr + size - 1;
1597 if ((bo && offset + size > amdgpu_bo_size(bo)) ||
1598 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
1599 return -EINVAL;
1600
1601 saddr /= AMDGPU_GPU_PAGE_SIZE;
1602 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1603
1604 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1605 if (tmp) {
1606 /* bo and tmp overlap, invalid addr */
1607 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1608 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
1609 tmp->start, tmp->last + 1);
1610 return -EINVAL;
1611 }
1612
1613 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1614 if (!mapping)
1615 return -ENOMEM;
1616
1617 mapping->start = saddr;
1618 mapping->last = eaddr;
1619 mapping->offset = offset;
1620 mapping->flags = flags;
1621
1622 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1623
1624 return 0;
1625}
1626
1627/**
1628 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
1629 *
1630 * @adev: amdgpu_device pointer
1631 * @bo_va: bo_va to store the address
1632 * @saddr: where to map the BO
1633 * @offset: requested offset in the BO
1634 * @size: BO size in bytes
1635 * @flags: attributes of pages (read/write/valid/etc.)
1636 *
1637 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
1638 * mappings as we do so.
1639 *
1640 * Returns:
1641 * 0 for success, error for failure.
1642 *
1643 * Object has to be reserved and unreserved outside!
1644 */
1645int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
1646 struct amdgpu_bo_va *bo_va,
1647 uint64_t saddr, uint64_t offset,
1648 uint64_t size, uint64_t flags)
1649{
1650 struct amdgpu_bo_va_mapping *mapping;
1651 struct amdgpu_bo *bo = bo_va->base.bo;
1652 uint64_t eaddr;
1653 int r;
1654
1655 /* validate the parameters */
1656 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK || size & ~PAGE_MASK)
1657 return -EINVAL;
1658 if (saddr + size <= saddr || offset + size <= offset)
1659 return -EINVAL;
1660
1661 /* make sure object fit at this offset */
1662 eaddr = saddr + size - 1;
1663 if ((bo && offset + size > amdgpu_bo_size(bo)) ||
1664 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
1665 return -EINVAL;
1666
1667 /* Allocate all the needed memory */
1668 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1669 if (!mapping)
1670 return -ENOMEM;
1671
1672 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
1673 if (r) {
1674 kfree(mapping);
1675 return r;
1676 }
1677
1678 saddr /= AMDGPU_GPU_PAGE_SIZE;
1679 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1680
1681 mapping->start = saddr;
1682 mapping->last = eaddr;
1683 mapping->offset = offset;
1684 mapping->flags = flags;
1685
1686 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1687
1688 return 0;
1689}
1690
1691/**
1692 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1693 *
1694 * @adev: amdgpu_device pointer
1695 * @bo_va: bo_va to remove the address from
1696 * @saddr: where to the BO is mapped
1697 *
1698 * Remove a mapping of the BO at the specefied addr from the VM.
1699 *
1700 * Returns:
1701 * 0 for success, error for failure.
1702 *
1703 * Object has to be reserved and unreserved outside!
1704 */
1705int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1706 struct amdgpu_bo_va *bo_va,
1707 uint64_t saddr)
1708{
1709 struct amdgpu_bo_va_mapping *mapping;
1710 struct amdgpu_vm *vm = bo_va->base.vm;
1711 bool valid = true;
1712
1713 saddr /= AMDGPU_GPU_PAGE_SIZE;
1714
1715 list_for_each_entry(mapping, &bo_va->valids, list) {
1716 if (mapping->start == saddr)
1717 break;
1718 }
1719
1720 if (&mapping->list == &bo_va->valids) {
1721 valid = false;
1722
1723 list_for_each_entry(mapping, &bo_va->invalids, list) {
1724 if (mapping->start == saddr)
1725 break;
1726 }
1727
1728 if (&mapping->list == &bo_va->invalids)
1729 return -ENOENT;
1730 }
1731
1732 list_del(&mapping->list);
1733 amdgpu_vm_it_remove(mapping, &vm->va);
1734 mapping->bo_va = NULL;
1735 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1736
1737 if (valid)
1738 list_add(&mapping->list, &vm->freed);
1739 else
1740 amdgpu_vm_free_mapping(adev, vm, mapping,
1741 bo_va->last_pt_update);
1742
1743 return 0;
1744}
1745
1746/**
1747 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
1748 *
1749 * @adev: amdgpu_device pointer
1750 * @vm: VM structure to use
1751 * @saddr: start of the range
1752 * @size: size of the range
1753 *
1754 * Remove all mappings in a range, split them as appropriate.
1755 *
1756 * Returns:
1757 * 0 for success, error for failure.
1758 */
1759int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
1760 struct amdgpu_vm *vm,
1761 uint64_t saddr, uint64_t size)
1762{
1763 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
1764 LIST_HEAD(removed);
1765 uint64_t eaddr;
1766
1767 eaddr = saddr + size - 1;
1768 saddr /= AMDGPU_GPU_PAGE_SIZE;
1769 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1770
1771 /* Allocate all the needed memory */
1772 before = kzalloc(sizeof(*before), GFP_KERNEL);
1773 if (!before)
1774 return -ENOMEM;
1775 INIT_LIST_HEAD(&before->list);
1776
1777 after = kzalloc(sizeof(*after), GFP_KERNEL);
1778 if (!after) {
1779 kfree(before);
1780 return -ENOMEM;
1781 }
1782 INIT_LIST_HEAD(&after->list);
1783
1784 /* Now gather all removed mappings */
1785 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1786 while (tmp) {
1787 /* Remember mapping split at the start */
1788 if (tmp->start < saddr) {
1789 before->start = tmp->start;
1790 before->last = saddr - 1;
1791 before->offset = tmp->offset;
1792 before->flags = tmp->flags;
1793 before->bo_va = tmp->bo_va;
1794 list_add(&before->list, &tmp->bo_va->invalids);
1795 }
1796
1797 /* Remember mapping split at the end */
1798 if (tmp->last > eaddr) {
1799 after->start = eaddr + 1;
1800 after->last = tmp->last;
1801 after->offset = tmp->offset;
1802 after->offset += (after->start - tmp->start) << PAGE_SHIFT;
1803 after->flags = tmp->flags;
1804 after->bo_va = tmp->bo_va;
1805 list_add(&after->list, &tmp->bo_va->invalids);
1806 }
1807
1808 list_del(&tmp->list);
1809 list_add(&tmp->list, &removed);
1810
1811 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
1812 }
1813
1814 /* And free them up */
1815 list_for_each_entry_safe(tmp, next, &removed, list) {
1816 amdgpu_vm_it_remove(tmp, &vm->va);
1817 list_del(&tmp->list);
1818
1819 if (tmp->start < saddr)
1820 tmp->start = saddr;
1821 if (tmp->last > eaddr)
1822 tmp->last = eaddr;
1823
1824 tmp->bo_va = NULL;
1825 list_add(&tmp->list, &vm->freed);
1826 trace_amdgpu_vm_bo_unmap(NULL, tmp);
1827 }
1828
1829 /* Insert partial mapping before the range */
1830 if (!list_empty(&before->list)) {
1831 struct amdgpu_bo *bo = before->bo_va->base.bo;
1832
1833 amdgpu_vm_it_insert(before, &vm->va);
1834 if (before->flags & AMDGPU_PTE_PRT)
1835 amdgpu_vm_prt_get(adev);
1836
1837 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1838 !before->bo_va->base.moved)
1839 amdgpu_vm_bo_moved(&before->bo_va->base);
1840 } else {
1841 kfree(before);
1842 }
1843
1844 /* Insert partial mapping after the range */
1845 if (!list_empty(&after->list)) {
1846 struct amdgpu_bo *bo = after->bo_va->base.bo;
1847
1848 amdgpu_vm_it_insert(after, &vm->va);
1849 if (after->flags & AMDGPU_PTE_PRT)
1850 amdgpu_vm_prt_get(adev);
1851
1852 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1853 !after->bo_va->base.moved)
1854 amdgpu_vm_bo_moved(&after->bo_va->base);
1855 } else {
1856 kfree(after);
1857 }
1858
1859 return 0;
1860}
1861
1862/**
1863 * amdgpu_vm_bo_lookup_mapping - find mapping by address
1864 *
1865 * @vm: the requested VM
1866 * @addr: the address
1867 *
1868 * Find a mapping by it's address.
1869 *
1870 * Returns:
1871 * The amdgpu_bo_va_mapping matching for addr or NULL
1872 *
1873 */
1874struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
1875 uint64_t addr)
1876{
1877 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
1878}
1879
1880/**
1881 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
1882 *
1883 * @vm: the requested vm
1884 * @ticket: CS ticket
1885 *
1886 * Trace all mappings of BOs reserved during a command submission.
1887 */
1888void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
1889{
1890 struct amdgpu_bo_va_mapping *mapping;
1891
1892 if (!trace_amdgpu_vm_bo_cs_enabled())
1893 return;
1894
1895 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
1896 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
1897 if (mapping->bo_va && mapping->bo_va->base.bo) {
1898 struct amdgpu_bo *bo;
1899
1900 bo = mapping->bo_va->base.bo;
1901 if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
1902 ticket)
1903 continue;
1904 }
1905
1906 trace_amdgpu_vm_bo_cs(mapping);
1907 }
1908}
1909
1910/**
1911 * amdgpu_vm_bo_del - remove a bo from a specific vm
1912 *
1913 * @adev: amdgpu_device pointer
1914 * @bo_va: requested bo_va
1915 *
1916 * Remove @bo_va->bo from the requested vm.
1917 *
1918 * Object have to be reserved!
1919 */
1920void amdgpu_vm_bo_del(struct amdgpu_device *adev,
1921 struct amdgpu_bo_va *bo_va)
1922{
1923 struct amdgpu_bo_va_mapping *mapping, *next;
1924 struct amdgpu_bo *bo = bo_va->base.bo;
1925 struct amdgpu_vm *vm = bo_va->base.vm;
1926 struct amdgpu_vm_bo_base **base;
1927
1928 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
1929
1930 if (bo) {
1931 dma_resv_assert_held(bo->tbo.base.resv);
1932 if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
1933 ttm_bo_set_bulk_move(&bo->tbo, NULL);
1934
1935 for (base = &bo_va->base.bo->vm_bo; *base;
1936 base = &(*base)->next) {
1937 if (*base != &bo_va->base)
1938 continue;
1939
1940 *base = bo_va->base.next;
1941 break;
1942 }
1943 }
1944
1945 spin_lock(&vm->status_lock);
1946 list_del(&bo_va->base.vm_status);
1947 spin_unlock(&vm->status_lock);
1948
1949 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
1950 list_del(&mapping->list);
1951 amdgpu_vm_it_remove(mapping, &vm->va);
1952 mapping->bo_va = NULL;
1953 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1954 list_add(&mapping->list, &vm->freed);
1955 }
1956 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
1957 list_del(&mapping->list);
1958 amdgpu_vm_it_remove(mapping, &vm->va);
1959 amdgpu_vm_free_mapping(adev, vm, mapping,
1960 bo_va->last_pt_update);
1961 }
1962
1963 dma_fence_put(bo_va->last_pt_update);
1964
1965 if (bo && bo_va->is_xgmi)
1966 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
1967
1968 kfree(bo_va);
1969}
1970
1971/**
1972 * amdgpu_vm_evictable - check if we can evict a VM
1973 *
1974 * @bo: A page table of the VM.
1975 *
1976 * Check if it is possible to evict a VM.
1977 */
1978bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
1979{
1980 struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
1981
1982 /* Page tables of a destroyed VM can go away immediately */
1983 if (!bo_base || !bo_base->vm)
1984 return true;
1985
1986 /* Don't evict VM page tables while they are busy */
1987 if (!dma_resv_test_signaled(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP))
1988 return false;
1989
1990 /* Try to block ongoing updates */
1991 if (!amdgpu_vm_eviction_trylock(bo_base->vm))
1992 return false;
1993
1994 /* Don't evict VM page tables while they are updated */
1995 if (!dma_fence_is_signaled(bo_base->vm->last_unlocked)) {
1996 amdgpu_vm_eviction_unlock(bo_base->vm);
1997 return false;
1998 }
1999
2000 bo_base->vm->evicting = true;
2001 amdgpu_vm_eviction_unlock(bo_base->vm);
2002 return true;
2003}
2004
2005/**
2006 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2007 *
2008 * @adev: amdgpu_device pointer
2009 * @bo: amdgpu buffer object
2010 * @evicted: is the BO evicted
2011 *
2012 * Mark @bo as invalid.
2013 */
2014void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2015 struct amdgpu_bo *bo, bool evicted)
2016{
2017 struct amdgpu_vm_bo_base *bo_base;
2018
2019 /* shadow bo doesn't have bo base, its validation needs its parent */
2020 if (bo->parent && (amdgpu_bo_shadowed(bo->parent) == bo))
2021 bo = bo->parent;
2022
2023 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2024 struct amdgpu_vm *vm = bo_base->vm;
2025
2026 if (evicted && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
2027 amdgpu_vm_bo_evicted(bo_base);
2028 continue;
2029 }
2030
2031 if (bo_base->moved)
2032 continue;
2033 bo_base->moved = true;
2034
2035 if (bo->tbo.type == ttm_bo_type_kernel)
2036 amdgpu_vm_bo_relocated(bo_base);
2037 else if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
2038 amdgpu_vm_bo_moved(bo_base);
2039 else
2040 amdgpu_vm_bo_invalidated(bo_base);
2041 }
2042}
2043
2044/**
2045 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2046 *
2047 * @vm_size: VM size
2048 *
2049 * Returns:
2050 * VM page table as power of two
2051 */
2052static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2053{
2054 /* Total bits covered by PD + PTs */
2055 unsigned bits = ilog2(vm_size) + 18;
2056
2057 /* Make sure the PD is 4K in size up to 8GB address space.
2058 Above that split equal between PD and PTs */
2059 if (vm_size <= 8)
2060 return (bits - 9);
2061 else
2062 return ((bits + 3) / 2);
2063}
2064
2065/**
2066 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2067 *
2068 * @adev: amdgpu_device pointer
2069 * @min_vm_size: the minimum vm size in GB if it's set auto
2070 * @fragment_size_default: Default PTE fragment size
2071 * @max_level: max VMPT level
2072 * @max_bits: max address space size in bits
2073 *
2074 */
2075void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2076 uint32_t fragment_size_default, unsigned max_level,
2077 unsigned max_bits)
2078{
2079 unsigned int max_size = 1 << (max_bits - 30);
2080 unsigned int vm_size;
2081 uint64_t tmp;
2082
2083 /* adjust vm size first */
2084 if (amdgpu_vm_size != -1) {
2085 vm_size = amdgpu_vm_size;
2086 if (vm_size > max_size) {
2087 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2088 amdgpu_vm_size, max_size);
2089 vm_size = max_size;
2090 }
2091 } else {
2092 struct sysinfo si;
2093 unsigned int phys_ram_gb;
2094
2095 /* Optimal VM size depends on the amount of physical
2096 * RAM available. Underlying requirements and
2097 * assumptions:
2098 *
2099 * - Need to map system memory and VRAM from all GPUs
2100 * - VRAM from other GPUs not known here
2101 * - Assume VRAM <= system memory
2102 * - On GFX8 and older, VM space can be segmented for
2103 * different MTYPEs
2104 * - Need to allow room for fragmentation, guard pages etc.
2105 *
2106 * This adds up to a rough guess of system memory x3.
2107 * Round up to power of two to maximize the available
2108 * VM size with the given page table size.
2109 */
2110 si_meminfo(&si);
2111 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2112 (1 << 30) - 1) >> 30;
2113 vm_size = roundup_pow_of_two(
2114 min(max(phys_ram_gb * 3, min_vm_size), max_size));
2115 }
2116
2117 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2118
2119 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2120 if (amdgpu_vm_block_size != -1)
2121 tmp >>= amdgpu_vm_block_size - 9;
2122 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2123 adev->vm_manager.num_level = min_t(unsigned int, max_level, tmp);
2124 switch (adev->vm_manager.num_level) {
2125 case 3:
2126 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2127 break;
2128 case 2:
2129 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2130 break;
2131 case 1:
2132 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2133 break;
2134 default:
2135 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2136 }
2137 /* block size depends on vm size and hw setup*/
2138 if (amdgpu_vm_block_size != -1)
2139 adev->vm_manager.block_size =
2140 min((unsigned)amdgpu_vm_block_size, max_bits
2141 - AMDGPU_GPU_PAGE_SHIFT
2142 - 9 * adev->vm_manager.num_level);
2143 else if (adev->vm_manager.num_level > 1)
2144 adev->vm_manager.block_size = 9;
2145 else
2146 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2147
2148 if (amdgpu_vm_fragment_size == -1)
2149 adev->vm_manager.fragment_size = fragment_size_default;
2150 else
2151 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2152
2153 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2154 vm_size, adev->vm_manager.num_level + 1,
2155 adev->vm_manager.block_size,
2156 adev->vm_manager.fragment_size);
2157}
2158
2159/**
2160 * amdgpu_vm_wait_idle - wait for the VM to become idle
2161 *
2162 * @vm: VM object to wait for
2163 * @timeout: timeout to wait for VM to become idle
2164 */
2165long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2166{
2167 timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv,
2168 DMA_RESV_USAGE_BOOKKEEP,
2169 true, timeout);
2170 if (timeout <= 0)
2171 return timeout;
2172
2173 return dma_fence_wait_timeout(vm->last_unlocked, true, timeout);
2174}
2175
2176/**
2177 * amdgpu_vm_init - initialize a vm instance
2178 *
2179 * @adev: amdgpu_device pointer
2180 * @vm: requested vm
2181 * @xcp_id: GPU partition selection id
2182 *
2183 * Init @vm fields.
2184 *
2185 * Returns:
2186 * 0 for success, error for failure.
2187 */
2188int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2189 int32_t xcp_id)
2190{
2191 struct amdgpu_bo *root_bo;
2192 struct amdgpu_bo_vm *root;
2193 int r, i;
2194
2195 vm->va = RB_ROOT_CACHED;
2196 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2197 vm->reserved_vmid[i] = NULL;
2198 INIT_LIST_HEAD(&vm->evicted);
2199 INIT_LIST_HEAD(&vm->relocated);
2200 INIT_LIST_HEAD(&vm->moved);
2201 INIT_LIST_HEAD(&vm->idle);
2202 INIT_LIST_HEAD(&vm->invalidated);
2203 spin_lock_init(&vm->status_lock);
2204 INIT_LIST_HEAD(&vm->freed);
2205 INIT_LIST_HEAD(&vm->done);
2206 INIT_LIST_HEAD(&vm->pt_freed);
2207 INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work);
2208 INIT_KFIFO(vm->faults);
2209
2210 r = amdgpu_vm_init_entities(adev, vm);
2211 if (r)
2212 return r;
2213
2214 vm->pte_support_ats = false;
2215 vm->is_compute_context = false;
2216
2217 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2218 AMDGPU_VM_USE_CPU_FOR_GFX);
2219
2220 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2221 vm->use_cpu_for_update ? "CPU" : "SDMA");
2222 WARN_ONCE((vm->use_cpu_for_update &&
2223 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2224 "CPU update of VM recommended only for large BAR system\n");
2225
2226 if (vm->use_cpu_for_update)
2227 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2228 else
2229 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2230
2231 vm->last_update = dma_fence_get_stub();
2232 vm->last_unlocked = dma_fence_get_stub();
2233 vm->last_tlb_flush = dma_fence_get_stub();
2234 vm->generation = 0;
2235
2236 mutex_init(&vm->eviction_lock);
2237 vm->evicting = false;
2238
2239 r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
2240 false, &root, xcp_id);
2241 if (r)
2242 goto error_free_delayed;
2243
2244 root_bo = amdgpu_bo_ref(&root->bo);
2245 r = amdgpu_bo_reserve(root_bo, true);
2246 if (r) {
2247 amdgpu_bo_unref(&root->shadow);
2248 amdgpu_bo_unref(&root_bo);
2249 goto error_free_delayed;
2250 }
2251
2252 amdgpu_vm_bo_base_init(&vm->root, vm, root_bo);
2253 r = dma_resv_reserve_fences(root_bo->tbo.base.resv, 1);
2254 if (r)
2255 goto error_free_root;
2256
2257 r = amdgpu_vm_pt_clear(adev, vm, root, false);
2258 if (r)
2259 goto error_free_root;
2260
2261 amdgpu_bo_unreserve(vm->root.bo);
2262 amdgpu_bo_unref(&root_bo);
2263
2264 return 0;
2265
2266error_free_root:
2267 amdgpu_vm_pt_free_root(adev, vm);
2268 amdgpu_bo_unreserve(vm->root.bo);
2269 amdgpu_bo_unref(&root_bo);
2270
2271error_free_delayed:
2272 dma_fence_put(vm->last_tlb_flush);
2273 dma_fence_put(vm->last_unlocked);
2274 amdgpu_vm_fini_entities(vm);
2275
2276 return r;
2277}
2278
2279/**
2280 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2281 *
2282 * @adev: amdgpu_device pointer
2283 * @vm: requested vm
2284 *
2285 * This only works on GFX VMs that don't have any BOs added and no
2286 * page tables allocated yet.
2287 *
2288 * Changes the following VM parameters:
2289 * - use_cpu_for_update
2290 * - pte_supports_ats
2291 *
2292 * Reinitializes the page directory to reflect the changed ATS
2293 * setting.
2294 *
2295 * Returns:
2296 * 0 for success, -errno for errors.
2297 */
2298int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2299{
2300 bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
2301 int r;
2302
2303 r = amdgpu_bo_reserve(vm->root.bo, true);
2304 if (r)
2305 return r;
2306
2307 /* Check if PD needs to be reinitialized and do it before
2308 * changing any other state, in case it fails.
2309 */
2310 if (pte_support_ats != vm->pte_support_ats) {
2311 /* Sanity checks */
2312 if (!amdgpu_vm_pt_is_root_clean(adev, vm)) {
2313 r = -EINVAL;
2314 goto unreserve_bo;
2315 }
2316
2317 vm->pte_support_ats = pte_support_ats;
2318 r = amdgpu_vm_pt_clear(adev, vm, to_amdgpu_bo_vm(vm->root.bo),
2319 false);
2320 if (r)
2321 goto unreserve_bo;
2322 }
2323
2324 /* Update VM state */
2325 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2326 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2327 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2328 vm->use_cpu_for_update ? "CPU" : "SDMA");
2329 WARN_ONCE((vm->use_cpu_for_update &&
2330 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2331 "CPU update of VM recommended only for large BAR system\n");
2332
2333 if (vm->use_cpu_for_update) {
2334 /* Sync with last SDMA update/clear before switching to CPU */
2335 r = amdgpu_bo_sync_wait(vm->root.bo,
2336 AMDGPU_FENCE_OWNER_UNDEFINED, true);
2337 if (r)
2338 goto unreserve_bo;
2339
2340 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2341 r = amdgpu_vm_pt_map_tables(adev, vm);
2342 if (r)
2343 goto unreserve_bo;
2344
2345 } else {
2346 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2347 }
2348
2349 dma_fence_put(vm->last_update);
2350 vm->last_update = dma_fence_get_stub();
2351 vm->is_compute_context = true;
2352
2353 /* Free the shadow bo for compute VM */
2354 amdgpu_bo_unref(&to_amdgpu_bo_vm(vm->root.bo)->shadow);
2355
2356 goto unreserve_bo;
2357
2358unreserve_bo:
2359 amdgpu_bo_unreserve(vm->root.bo);
2360 return r;
2361}
2362
2363/**
2364 * amdgpu_vm_release_compute - release a compute vm
2365 * @adev: amdgpu_device pointer
2366 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
2367 *
2368 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
2369 * pasid from vm. Compute should stop use of vm after this call.
2370 */
2371void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2372{
2373 amdgpu_vm_set_pasid(adev, vm, 0);
2374 vm->is_compute_context = false;
2375}
2376
2377/**
2378 * amdgpu_vm_fini - tear down a vm instance
2379 *
2380 * @adev: amdgpu_device pointer
2381 * @vm: requested vm
2382 *
2383 * Tear down @vm.
2384 * Unbind the VM and remove all bos from the vm bo list
2385 */
2386void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2387{
2388 struct amdgpu_bo_va_mapping *mapping, *tmp;
2389 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
2390 struct amdgpu_bo *root;
2391 unsigned long flags;
2392 int i;
2393
2394 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
2395
2396 flush_work(&vm->pt_free_work);
2397
2398 root = amdgpu_bo_ref(vm->root.bo);
2399 amdgpu_bo_reserve(root, true);
2400 amdgpu_vm_set_pasid(adev, vm, 0);
2401 dma_fence_wait(vm->last_unlocked, false);
2402 dma_fence_put(vm->last_unlocked);
2403 dma_fence_wait(vm->last_tlb_flush, false);
2404 /* Make sure that all fence callbacks have completed */
2405 spin_lock_irqsave(vm->last_tlb_flush->lock, flags);
2406 spin_unlock_irqrestore(vm->last_tlb_flush->lock, flags);
2407 dma_fence_put(vm->last_tlb_flush);
2408
2409 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2410 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
2411 amdgpu_vm_prt_fini(adev, vm);
2412 prt_fini_needed = false;
2413 }
2414
2415 list_del(&mapping->list);
2416 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
2417 }
2418
2419 amdgpu_vm_pt_free_root(adev, vm);
2420 amdgpu_bo_unreserve(root);
2421 amdgpu_bo_unref(&root);
2422 WARN_ON(vm->root.bo);
2423
2424 amdgpu_vm_fini_entities(vm);
2425
2426 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
2427 dev_err(adev->dev, "still active bo inside vm\n");
2428 }
2429 rbtree_postorder_for_each_entry_safe(mapping, tmp,
2430 &vm->va.rb_root, rb) {
2431 /* Don't remove the mapping here, we don't want to trigger a
2432 * rebalance and the tree is about to be destroyed anyway.
2433 */
2434 list_del(&mapping->list);
2435 kfree(mapping);
2436 }
2437
2438 dma_fence_put(vm->last_update);
2439
2440 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) {
2441 if (vm->reserved_vmid[i]) {
2442 amdgpu_vmid_free_reserved(adev, i);
2443 vm->reserved_vmid[i] = false;
2444 }
2445 }
2446
2447}
2448
2449/**
2450 * amdgpu_vm_manager_init - init the VM manager
2451 *
2452 * @adev: amdgpu_device pointer
2453 *
2454 * Initialize the VM manager structures
2455 */
2456void amdgpu_vm_manager_init(struct amdgpu_device *adev)
2457{
2458 unsigned i;
2459
2460 /* Concurrent flushes are only possible starting with Vega10 and
2461 * are broken on Navi10 and Navi14.
2462 */
2463 adev->vm_manager.concurrent_flush = !(adev->asic_type < CHIP_VEGA10 ||
2464 adev->asic_type == CHIP_NAVI10 ||
2465 adev->asic_type == CHIP_NAVI14);
2466 amdgpu_vmid_mgr_init(adev);
2467
2468 adev->vm_manager.fence_context =
2469 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2470 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2471 adev->vm_manager.seqno[i] = 0;
2472
2473 spin_lock_init(&adev->vm_manager.prt_lock);
2474 atomic_set(&adev->vm_manager.num_prt_users, 0);
2475
2476 /* If not overridden by the user, by default, only in large BAR systems
2477 * Compute VM tables will be updated by CPU
2478 */
2479#ifdef CONFIG_X86_64
2480 if (amdgpu_vm_update_mode == -1) {
2481 /* For asic with VF MMIO access protection
2482 * avoid using CPU for VM table updates
2483 */
2484 if (amdgpu_gmc_vram_full_visible(&adev->gmc) &&
2485 !amdgpu_sriov_vf_mmio_access_protection(adev))
2486 adev->vm_manager.vm_update_mode =
2487 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
2488 else
2489 adev->vm_manager.vm_update_mode = 0;
2490 } else
2491 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
2492#else
2493 adev->vm_manager.vm_update_mode = 0;
2494#endif
2495
2496 xa_init_flags(&adev->vm_manager.pasids, XA_FLAGS_LOCK_IRQ);
2497}
2498
2499/**
2500 * amdgpu_vm_manager_fini - cleanup VM manager
2501 *
2502 * @adev: amdgpu_device pointer
2503 *
2504 * Cleanup the VM manager and free resources.
2505 */
2506void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
2507{
2508 WARN_ON(!xa_empty(&adev->vm_manager.pasids));
2509 xa_destroy(&adev->vm_manager.pasids);
2510
2511 amdgpu_vmid_mgr_fini(adev);
2512}
2513
2514/**
2515 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
2516 *
2517 * @dev: drm device pointer
2518 * @data: drm_amdgpu_vm
2519 * @filp: drm file pointer
2520 *
2521 * Returns:
2522 * 0 for success, -errno for errors.
2523 */
2524int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
2525{
2526 union drm_amdgpu_vm *args = data;
2527 struct amdgpu_device *adev = drm_to_adev(dev);
2528 struct amdgpu_fpriv *fpriv = filp->driver_priv;
2529
2530 /* No valid flags defined yet */
2531 if (args->in.flags)
2532 return -EINVAL;
2533
2534 switch (args->in.op) {
2535 case AMDGPU_VM_OP_RESERVE_VMID:
2536 /* We only have requirement to reserve vmid from gfxhub */
2537 if (!fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {
2538 amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0));
2539 fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = true;
2540 }
2541
2542 break;
2543 case AMDGPU_VM_OP_UNRESERVE_VMID:
2544 if (fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {
2545 amdgpu_vmid_free_reserved(adev, AMDGPU_GFXHUB(0));
2546 fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = false;
2547 }
2548 break;
2549 default:
2550 return -EINVAL;
2551 }
2552
2553 return 0;
2554}
2555
2556/**
2557 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
2558 *
2559 * @adev: drm device pointer
2560 * @pasid: PASID identifier for VM
2561 * @task_info: task_info to fill.
2562 */
2563void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid,
2564 struct amdgpu_task_info *task_info)
2565{
2566 struct amdgpu_vm *vm;
2567 unsigned long flags;
2568
2569 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
2570
2571 vm = xa_load(&adev->vm_manager.pasids, pasid);
2572 if (vm)
2573 *task_info = vm->task_info;
2574
2575 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
2576}
2577
2578/**
2579 * amdgpu_vm_set_task_info - Sets VMs task info.
2580 *
2581 * @vm: vm for which to set the info
2582 */
2583void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
2584{
2585 if (vm->task_info.pid)
2586 return;
2587
2588 vm->task_info.pid = current->pid;
2589 get_task_comm(vm->task_info.task_name, current);
2590
2591 if (current->group_leader->mm != current->mm)
2592 return;
2593
2594 vm->task_info.tgid = current->group_leader->pid;
2595 get_task_comm(vm->task_info.process_name, current->group_leader);
2596}
2597
2598/**
2599 * amdgpu_vm_handle_fault - graceful handling of VM faults.
2600 * @adev: amdgpu device pointer
2601 * @pasid: PASID of the VM
2602 * @vmid: VMID, only used for GFX 9.4.3.
2603 * @node_id: Node_id received in IH cookie. Only applicable for
2604 * GFX 9.4.3.
2605 * @addr: Address of the fault
2606 * @write_fault: true is write fault, false is read fault
2607 *
2608 * Try to gracefully handle a VM fault. Return true if the fault was handled and
2609 * shouldn't be reported any more.
2610 */
2611bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
2612 u32 vmid, u32 node_id, uint64_t addr,
2613 bool write_fault)
2614{
2615 bool is_compute_context = false;
2616 struct amdgpu_bo *root;
2617 unsigned long irqflags;
2618 uint64_t value, flags;
2619 struct amdgpu_vm *vm;
2620 int r;
2621
2622 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2623 vm = xa_load(&adev->vm_manager.pasids, pasid);
2624 if (vm) {
2625 root = amdgpu_bo_ref(vm->root.bo);
2626 is_compute_context = vm->is_compute_context;
2627 } else {
2628 root = NULL;
2629 }
2630 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2631
2632 if (!root)
2633 return false;
2634
2635 addr /= AMDGPU_GPU_PAGE_SIZE;
2636
2637 if (is_compute_context && !svm_range_restore_pages(adev, pasid, vmid,
2638 node_id, addr, write_fault)) {
2639 amdgpu_bo_unref(&root);
2640 return true;
2641 }
2642
2643 r = amdgpu_bo_reserve(root, true);
2644 if (r)
2645 goto error_unref;
2646
2647 /* Double check that the VM still exists */
2648 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2649 vm = xa_load(&adev->vm_manager.pasids, pasid);
2650 if (vm && vm->root.bo != root)
2651 vm = NULL;
2652 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2653 if (!vm)
2654 goto error_unlock;
2655
2656 flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
2657 AMDGPU_PTE_SYSTEM;
2658
2659 if (is_compute_context) {
2660 /* Intentionally setting invalid PTE flag
2661 * combination to force a no-retry-fault
2662 */
2663 flags = AMDGPU_VM_NORETRY_FLAGS;
2664 value = 0;
2665 } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
2666 /* Redirect the access to the dummy page */
2667 value = adev->dummy_page_addr;
2668 flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
2669 AMDGPU_PTE_WRITEABLE;
2670
2671 } else {
2672 /* Let the hw retry silently on the PTE */
2673 value = 0;
2674 }
2675
2676 r = dma_resv_reserve_fences(root->tbo.base.resv, 1);
2677 if (r) {
2678 pr_debug("failed %d to reserve fence slot\n", r);
2679 goto error_unlock;
2680 }
2681
2682 r = amdgpu_vm_update_range(adev, vm, true, false, false, false,
2683 NULL, addr, addr, flags, value, 0, NULL, NULL, NULL);
2684 if (r)
2685 goto error_unlock;
2686
2687 r = amdgpu_vm_update_pdes(adev, vm, true);
2688
2689error_unlock:
2690 amdgpu_bo_unreserve(root);
2691 if (r < 0)
2692 DRM_ERROR("Can't handle page fault (%d)\n", r);
2693
2694error_unref:
2695 amdgpu_bo_unref(&root);
2696
2697 return false;
2698}
2699
2700#if defined(CONFIG_DEBUG_FS)
2701/**
2702 * amdgpu_debugfs_vm_bo_info - print BO info for the VM
2703 *
2704 * @vm: Requested VM for printing BO info
2705 * @m: debugfs file
2706 *
2707 * Print BO information in debugfs file for the VM
2708 */
2709void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m)
2710{
2711 struct amdgpu_bo_va *bo_va, *tmp;
2712 u64 total_idle = 0;
2713 u64 total_evicted = 0;
2714 u64 total_relocated = 0;
2715 u64 total_moved = 0;
2716 u64 total_invalidated = 0;
2717 u64 total_done = 0;
2718 unsigned int total_idle_objs = 0;
2719 unsigned int total_evicted_objs = 0;
2720 unsigned int total_relocated_objs = 0;
2721 unsigned int total_moved_objs = 0;
2722 unsigned int total_invalidated_objs = 0;
2723 unsigned int total_done_objs = 0;
2724 unsigned int id = 0;
2725
2726 spin_lock(&vm->status_lock);
2727 seq_puts(m, "\tIdle BOs:\n");
2728 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
2729 if (!bo_va->base.bo)
2730 continue;
2731 total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2732 }
2733 total_idle_objs = id;
2734 id = 0;
2735
2736 seq_puts(m, "\tEvicted BOs:\n");
2737 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
2738 if (!bo_va->base.bo)
2739 continue;
2740 total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2741 }
2742 total_evicted_objs = id;
2743 id = 0;
2744
2745 seq_puts(m, "\tRelocated BOs:\n");
2746 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
2747 if (!bo_va->base.bo)
2748 continue;
2749 total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2750 }
2751 total_relocated_objs = id;
2752 id = 0;
2753
2754 seq_puts(m, "\tMoved BOs:\n");
2755 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2756 if (!bo_va->base.bo)
2757 continue;
2758 total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2759 }
2760 total_moved_objs = id;
2761 id = 0;
2762
2763 seq_puts(m, "\tInvalidated BOs:\n");
2764 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
2765 if (!bo_va->base.bo)
2766 continue;
2767 total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2768 }
2769 total_invalidated_objs = id;
2770 id = 0;
2771
2772 seq_puts(m, "\tDone BOs:\n");
2773 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
2774 if (!bo_va->base.bo)
2775 continue;
2776 total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2777 }
2778 spin_unlock(&vm->status_lock);
2779 total_done_objs = id;
2780
2781 seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle,
2782 total_idle_objs);
2783 seq_printf(m, "\tTotal evicted size: %12lld\tobjs:\t%d\n", total_evicted,
2784 total_evicted_objs);
2785 seq_printf(m, "\tTotal relocated size: %12lld\tobjs:\t%d\n", total_relocated,
2786 total_relocated_objs);
2787 seq_printf(m, "\tTotal moved size: %12lld\tobjs:\t%d\n", total_moved,
2788 total_moved_objs);
2789 seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated,
2790 total_invalidated_objs);
2791 seq_printf(m, "\tTotal done size: %12lld\tobjs:\t%d\n", total_done,
2792 total_done_objs);
2793}
2794#endif
2795
2796/**
2797 * amdgpu_vm_update_fault_cache - update cached fault into.
2798 * @adev: amdgpu device pointer
2799 * @pasid: PASID of the VM
2800 * @addr: Address of the fault
2801 * @status: GPUVM fault status register
2802 * @vmhub: which vmhub got the fault
2803 *
2804 * Cache the fault info for later use by userspace in debugging.
2805 */
2806void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev,
2807 unsigned int pasid,
2808 uint64_t addr,
2809 uint32_t status,
2810 unsigned int vmhub)
2811{
2812 struct amdgpu_vm *vm;
2813 unsigned long flags;
2814
2815 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
2816
2817 vm = xa_load(&adev->vm_manager.pasids, pasid);
2818 /* Don't update the fault cache if status is 0. In the multiple
2819 * fault case, subsequent faults will return a 0 status which is
2820 * useless for userspace and replaces the useful fault status, so
2821 * only update if status is non-0.
2822 */
2823 if (vm && status) {
2824 vm->fault_info.addr = addr;
2825 vm->fault_info.status = status;
2826 if (AMDGPU_IS_GFXHUB(vmhub)) {
2827 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_GFX;
2828 vm->fault_info.vmhub |=
2829 (vmhub - AMDGPU_GFXHUB_START) << AMDGPU_VMHUB_IDX_SHIFT;
2830 } else if (AMDGPU_IS_MMHUB0(vmhub)) {
2831 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_MM0;
2832 vm->fault_info.vmhub |=
2833 (vmhub - AMDGPU_MMHUB0_START) << AMDGPU_VMHUB_IDX_SHIFT;
2834 } else if (AMDGPU_IS_MMHUB1(vmhub)) {
2835 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_MM1;
2836 vm->fault_info.vmhub |=
2837 (vmhub - AMDGPU_MMHUB1_START) << AMDGPU_VMHUB_IDX_SHIFT;
2838 } else {
2839 WARN_ONCE(1, "Invalid vmhub %u\n", vmhub);
2840 }
2841 }
2842 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
2843}
2844
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/dma-fence-array.h>
30#include <linux/interval_tree_generic.h>
31#include <linux/idr.h>
32#include <linux/dma-buf.h>
33
34#include <drm/amdgpu_drm.h>
35#include <drm/drm_drv.h>
36#include "amdgpu.h"
37#include "amdgpu_trace.h"
38#include "amdgpu_amdkfd.h"
39#include "amdgpu_gmc.h"
40#include "amdgpu_xgmi.h"
41#include "amdgpu_dma_buf.h"
42#include "amdgpu_res_cursor.h"
43#include "kfd_svm.h"
44
45/**
46 * DOC: GPUVM
47 *
48 * GPUVM is the MMU functionality provided on the GPU.
49 * GPUVM is similar to the legacy GART on older asics, however
50 * rather than there being a single global GART table
51 * for the entire GPU, there can be multiple GPUVM page tables active
52 * at any given time. The GPUVM page tables can contain a mix
53 * VRAM pages and system pages (both memory and MMIO) and system pages
54 * can be mapped as snooped (cached system pages) or unsnooped
55 * (uncached system pages).
56 *
57 * Each active GPUVM has an ID associated with it and there is a page table
58 * linked with each VMID. When executing a command buffer,
59 * the kernel tells the engine what VMID to use for that command
60 * buffer. VMIDs are allocated dynamically as commands are submitted.
61 * The userspace drivers maintain their own address space and the kernel
62 * sets up their pages tables accordingly when they submit their
63 * command buffers and a VMID is assigned.
64 * The hardware supports up to 16 active GPUVMs at any given time.
65 *
66 * Each GPUVM is represented by a 1-2 or 1-5 level page table, depending
67 * on the ASIC family. GPUVM supports RWX attributes on each page as well
68 * as other features such as encryption and caching attributes.
69 *
70 * VMID 0 is special. It is the GPUVM used for the kernel driver. In
71 * addition to an aperture managed by a page table, VMID 0 also has
72 * several other apertures. There is an aperture for direct access to VRAM
73 * and there is a legacy AGP aperture which just forwards accesses directly
74 * to the matching system physical addresses (or IOVAs when an IOMMU is
75 * present). These apertures provide direct access to these memories without
76 * incurring the overhead of a page table. VMID 0 is used by the kernel
77 * driver for tasks like memory management.
78 *
79 * GPU clients (i.e., engines on the GPU) use GPUVM VMIDs to access memory.
80 * For user applications, each application can have their own unique GPUVM
81 * address space. The application manages the address space and the kernel
82 * driver manages the GPUVM page tables for each process. If an GPU client
83 * accesses an invalid page, it will generate a GPU page fault, similar to
84 * accessing an invalid page on a CPU.
85 */
86
87#define START(node) ((node)->start)
88#define LAST(node) ((node)->last)
89
90INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
91 START, LAST, static, amdgpu_vm_it)
92
93#undef START
94#undef LAST
95
96/**
97 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
98 */
99struct amdgpu_prt_cb {
100
101 /**
102 * @adev: amdgpu device
103 */
104 struct amdgpu_device *adev;
105
106 /**
107 * @cb: callback
108 */
109 struct dma_fence_cb cb;
110};
111
112/**
113 * struct amdgpu_vm_tlb_seq_cb - Helper to increment the TLB flush sequence
114 */
115struct amdgpu_vm_tlb_seq_cb {
116 /**
117 * @vm: pointer to the amdgpu_vm structure to set the fence sequence on
118 */
119 struct amdgpu_vm *vm;
120
121 /**
122 * @cb: callback
123 */
124 struct dma_fence_cb cb;
125};
126
127/**
128 * amdgpu_vm_set_pasid - manage pasid and vm ptr mapping
129 *
130 * @adev: amdgpu_device pointer
131 * @vm: amdgpu_vm pointer
132 * @pasid: the pasid the VM is using on this GPU
133 *
134 * Set the pasid this VM is using on this GPU, can also be used to remove the
135 * pasid by passing in zero.
136 *
137 */
138int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm,
139 u32 pasid)
140{
141 int r;
142
143 if (vm->pasid == pasid)
144 return 0;
145
146 if (vm->pasid) {
147 r = xa_err(xa_erase_irq(&adev->vm_manager.pasids, vm->pasid));
148 if (r < 0)
149 return r;
150
151 vm->pasid = 0;
152 }
153
154 if (pasid) {
155 r = xa_err(xa_store_irq(&adev->vm_manager.pasids, pasid, vm,
156 GFP_KERNEL));
157 if (r < 0)
158 return r;
159
160 vm->pasid = pasid;
161 }
162
163
164 return 0;
165}
166
167/**
168 * amdgpu_vm_bo_evicted - vm_bo is evicted
169 *
170 * @vm_bo: vm_bo which is evicted
171 *
172 * State for PDs/PTs and per VM BOs which are not at the location they should
173 * be.
174 */
175static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
176{
177 struct amdgpu_vm *vm = vm_bo->vm;
178 struct amdgpu_bo *bo = vm_bo->bo;
179
180 vm_bo->moved = true;
181 spin_lock(&vm_bo->vm->status_lock);
182 if (bo->tbo.type == ttm_bo_type_kernel)
183 list_move(&vm_bo->vm_status, &vm->evicted);
184 else
185 list_move_tail(&vm_bo->vm_status, &vm->evicted);
186 spin_unlock(&vm_bo->vm->status_lock);
187}
188/**
189 * amdgpu_vm_bo_moved - vm_bo is moved
190 *
191 * @vm_bo: vm_bo which is moved
192 *
193 * State for per VM BOs which are moved, but that change is not yet reflected
194 * in the page tables.
195 */
196static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
197{
198 spin_lock(&vm_bo->vm->status_lock);
199 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
200 spin_unlock(&vm_bo->vm->status_lock);
201}
202
203/**
204 * amdgpu_vm_bo_idle - vm_bo is idle
205 *
206 * @vm_bo: vm_bo which is now idle
207 *
208 * State for PDs/PTs and per VM BOs which have gone through the state machine
209 * and are now idle.
210 */
211static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
212{
213 spin_lock(&vm_bo->vm->status_lock);
214 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
215 spin_unlock(&vm_bo->vm->status_lock);
216 vm_bo->moved = false;
217}
218
219/**
220 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
221 *
222 * @vm_bo: vm_bo which is now invalidated
223 *
224 * State for normal BOs which are invalidated and that change not yet reflected
225 * in the PTs.
226 */
227static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
228{
229 spin_lock(&vm_bo->vm->status_lock);
230 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
231 spin_unlock(&vm_bo->vm->status_lock);
232}
233
234/**
235 * amdgpu_vm_bo_relocated - vm_bo is reloacted
236 *
237 * @vm_bo: vm_bo which is relocated
238 *
239 * State for PDs/PTs which needs to update their parent PD.
240 * For the root PD, just move to idle state.
241 */
242static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
243{
244 if (vm_bo->bo->parent) {
245 spin_lock(&vm_bo->vm->status_lock);
246 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
247 spin_unlock(&vm_bo->vm->status_lock);
248 } else {
249 amdgpu_vm_bo_idle(vm_bo);
250 }
251}
252
253/**
254 * amdgpu_vm_bo_done - vm_bo is done
255 *
256 * @vm_bo: vm_bo which is now done
257 *
258 * State for normal BOs which are invalidated and that change has been updated
259 * in the PTs.
260 */
261static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
262{
263 spin_lock(&vm_bo->vm->status_lock);
264 list_move(&vm_bo->vm_status, &vm_bo->vm->done);
265 spin_unlock(&vm_bo->vm->status_lock);
266}
267
268/**
269 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
270 *
271 * @base: base structure for tracking BO usage in a VM
272 * @vm: vm to which bo is to be added
273 * @bo: amdgpu buffer object
274 *
275 * Initialize a bo_va_base structure and add it to the appropriate lists
276 *
277 */
278void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
279 struct amdgpu_vm *vm, struct amdgpu_bo *bo)
280{
281 base->vm = vm;
282 base->bo = bo;
283 base->next = NULL;
284 INIT_LIST_HEAD(&base->vm_status);
285
286 if (!bo)
287 return;
288 base->next = bo->vm_bo;
289 bo->vm_bo = base;
290
291 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
292 return;
293
294 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
295
296 ttm_bo_set_bulk_move(&bo->tbo, &vm->lru_bulk_move);
297 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
298 amdgpu_vm_bo_relocated(base);
299 else
300 amdgpu_vm_bo_idle(base);
301
302 if (bo->preferred_domains &
303 amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type))
304 return;
305
306 /*
307 * we checked all the prerequisites, but it looks like this per vm bo
308 * is currently evicted. add the bo to the evicted list to make sure it
309 * is validated on next vm use to avoid fault.
310 * */
311 amdgpu_vm_bo_evicted(base);
312}
313
314/**
315 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
316 *
317 * @vm: vm providing the BOs
318 * @validated: head of validation list
319 * @entry: entry to add
320 *
321 * Add the page directory to the list of BOs to
322 * validate for command submission.
323 */
324void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
325 struct list_head *validated,
326 struct amdgpu_bo_list_entry *entry)
327{
328 entry->priority = 0;
329 entry->tv.bo = &vm->root.bo->tbo;
330 /* Two for VM updates, one for TTM and one for the CS job */
331 entry->tv.num_shared = 4;
332 entry->user_pages = NULL;
333 list_add(&entry->tv.head, validated);
334}
335
336/**
337 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
338 *
339 * @adev: amdgpu device pointer
340 * @vm: vm providing the BOs
341 *
342 * Move all BOs to the end of LRU and remember their positions to put them
343 * together.
344 */
345void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
346 struct amdgpu_vm *vm)
347{
348 spin_lock(&adev->mman.bdev.lru_lock);
349 ttm_lru_bulk_move_tail(&vm->lru_bulk_move);
350 spin_unlock(&adev->mman.bdev.lru_lock);
351}
352
353/**
354 * amdgpu_vm_validate_pt_bos - validate the page table BOs
355 *
356 * @adev: amdgpu device pointer
357 * @vm: vm providing the BOs
358 * @validate: callback to do the validation
359 * @param: parameter for the validation callback
360 *
361 * Validate the page table BOs on command submission if neccessary.
362 *
363 * Returns:
364 * Validation result.
365 */
366int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
367 int (*validate)(void *p, struct amdgpu_bo *bo),
368 void *param)
369{
370 struct amdgpu_vm_bo_base *bo_base;
371 struct amdgpu_bo *shadow;
372 struct amdgpu_bo *bo;
373 int r;
374
375 spin_lock(&vm->status_lock);
376 while (!list_empty(&vm->evicted)) {
377 bo_base = list_first_entry(&vm->evicted,
378 struct amdgpu_vm_bo_base,
379 vm_status);
380 spin_unlock(&vm->status_lock);
381
382 bo = bo_base->bo;
383 shadow = amdgpu_bo_shadowed(bo);
384
385 r = validate(param, bo);
386 if (r)
387 return r;
388 if (shadow) {
389 r = validate(param, shadow);
390 if (r)
391 return r;
392 }
393
394 if (bo->tbo.type != ttm_bo_type_kernel) {
395 amdgpu_vm_bo_moved(bo_base);
396 } else {
397 vm->update_funcs->map_table(to_amdgpu_bo_vm(bo));
398 amdgpu_vm_bo_relocated(bo_base);
399 }
400 spin_lock(&vm->status_lock);
401 }
402 spin_unlock(&vm->status_lock);
403
404 amdgpu_vm_eviction_lock(vm);
405 vm->evicting = false;
406 amdgpu_vm_eviction_unlock(vm);
407
408 return 0;
409}
410
411/**
412 * amdgpu_vm_ready - check VM is ready for updates
413 *
414 * @vm: VM to check
415 *
416 * Check if all VM PDs/PTs are ready for updates
417 *
418 * Returns:
419 * True if VM is not evicting.
420 */
421bool amdgpu_vm_ready(struct amdgpu_vm *vm)
422{
423 bool empty;
424 bool ret;
425
426 amdgpu_vm_eviction_lock(vm);
427 ret = !vm->evicting;
428 amdgpu_vm_eviction_unlock(vm);
429
430 spin_lock(&vm->status_lock);
431 empty = list_empty(&vm->evicted);
432 spin_unlock(&vm->status_lock);
433
434 return ret && empty;
435}
436
437/**
438 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
439 *
440 * @adev: amdgpu_device pointer
441 */
442void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
443{
444 const struct amdgpu_ip_block *ip_block;
445 bool has_compute_vm_bug;
446 struct amdgpu_ring *ring;
447 int i;
448
449 has_compute_vm_bug = false;
450
451 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
452 if (ip_block) {
453 /* Compute has a VM bug for GFX version < 7.
454 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
455 if (ip_block->version->major <= 7)
456 has_compute_vm_bug = true;
457 else if (ip_block->version->major == 8)
458 if (adev->gfx.mec_fw_version < 673)
459 has_compute_vm_bug = true;
460 }
461
462 for (i = 0; i < adev->num_rings; i++) {
463 ring = adev->rings[i];
464 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
465 /* only compute rings */
466 ring->has_compute_vm_bug = has_compute_vm_bug;
467 else
468 ring->has_compute_vm_bug = false;
469 }
470}
471
472/**
473 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
474 *
475 * @ring: ring on which the job will be submitted
476 * @job: job to submit
477 *
478 * Returns:
479 * True if sync is needed.
480 */
481bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
482 struct amdgpu_job *job)
483{
484 struct amdgpu_device *adev = ring->adev;
485 unsigned vmhub = ring->funcs->vmhub;
486 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
487
488 if (job->vmid == 0)
489 return false;
490
491 if (job->vm_needs_flush || ring->has_compute_vm_bug)
492 return true;
493
494 if (ring->funcs->emit_gds_switch && job->gds_switch_needed)
495 return true;
496
497 if (amdgpu_vmid_had_gpu_reset(adev, &id_mgr->ids[job->vmid]))
498 return true;
499
500 return false;
501}
502
503/**
504 * amdgpu_vm_flush - hardware flush the vm
505 *
506 * @ring: ring to use for flush
507 * @job: related job
508 * @need_pipe_sync: is pipe sync needed
509 *
510 * Emit a VM flush when it is necessary.
511 *
512 * Returns:
513 * 0 on success, errno otherwise.
514 */
515int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
516 bool need_pipe_sync)
517{
518 struct amdgpu_device *adev = ring->adev;
519 unsigned vmhub = ring->funcs->vmhub;
520 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
521 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
522 bool spm_update_needed = job->spm_update_needed;
523 bool gds_switch_needed = ring->funcs->emit_gds_switch &&
524 job->gds_switch_needed;
525 bool vm_flush_needed = job->vm_needs_flush;
526 struct dma_fence *fence = NULL;
527 bool pasid_mapping_needed = false;
528 unsigned patch_offset = 0;
529 int r;
530
531 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
532 gds_switch_needed = true;
533 vm_flush_needed = true;
534 pasid_mapping_needed = true;
535 spm_update_needed = true;
536 }
537
538 mutex_lock(&id_mgr->lock);
539 if (id->pasid != job->pasid || !id->pasid_mapping ||
540 !dma_fence_is_signaled(id->pasid_mapping))
541 pasid_mapping_needed = true;
542 mutex_unlock(&id_mgr->lock);
543
544 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
545 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
546 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
547 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
548 ring->funcs->emit_wreg;
549
550 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
551 return 0;
552
553 amdgpu_ring_ib_begin(ring);
554 if (ring->funcs->init_cond_exec)
555 patch_offset = amdgpu_ring_init_cond_exec(ring);
556
557 if (need_pipe_sync)
558 amdgpu_ring_emit_pipeline_sync(ring);
559
560 if (vm_flush_needed) {
561 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
562 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
563 }
564
565 if (pasid_mapping_needed)
566 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
567
568 if (spm_update_needed && adev->gfx.rlc.funcs->update_spm_vmid)
569 adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid);
570
571 if (!ring->is_mes_queue && ring->funcs->emit_gds_switch &&
572 gds_switch_needed) {
573 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
574 job->gds_size, job->gws_base,
575 job->gws_size, job->oa_base,
576 job->oa_size);
577 }
578
579 if (vm_flush_needed || pasid_mapping_needed) {
580 r = amdgpu_fence_emit(ring, &fence, NULL, 0);
581 if (r)
582 return r;
583 }
584
585 if (vm_flush_needed) {
586 mutex_lock(&id_mgr->lock);
587 dma_fence_put(id->last_flush);
588 id->last_flush = dma_fence_get(fence);
589 id->current_gpu_reset_count =
590 atomic_read(&adev->gpu_reset_counter);
591 mutex_unlock(&id_mgr->lock);
592 }
593
594 if (pasid_mapping_needed) {
595 mutex_lock(&id_mgr->lock);
596 id->pasid = job->pasid;
597 dma_fence_put(id->pasid_mapping);
598 id->pasid_mapping = dma_fence_get(fence);
599 mutex_unlock(&id_mgr->lock);
600 }
601 dma_fence_put(fence);
602
603 if (ring->funcs->patch_cond_exec)
604 amdgpu_ring_patch_cond_exec(ring, patch_offset);
605
606 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
607 if (ring->funcs->emit_switch_buffer) {
608 amdgpu_ring_emit_switch_buffer(ring);
609 amdgpu_ring_emit_switch_buffer(ring);
610 }
611 amdgpu_ring_ib_end(ring);
612 return 0;
613}
614
615/**
616 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
617 *
618 * @vm: requested vm
619 * @bo: requested buffer object
620 *
621 * Find @bo inside the requested vm.
622 * Search inside the @bos vm list for the requested vm
623 * Returns the found bo_va or NULL if none is found
624 *
625 * Object has to be reserved!
626 *
627 * Returns:
628 * Found bo_va or NULL.
629 */
630struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
631 struct amdgpu_bo *bo)
632{
633 struct amdgpu_vm_bo_base *base;
634
635 for (base = bo->vm_bo; base; base = base->next) {
636 if (base->vm != vm)
637 continue;
638
639 return container_of(base, struct amdgpu_bo_va, base);
640 }
641 return NULL;
642}
643
644/**
645 * amdgpu_vm_map_gart - Resolve gart mapping of addr
646 *
647 * @pages_addr: optional DMA address to use for lookup
648 * @addr: the unmapped addr
649 *
650 * Look up the physical address of the page that the pte resolves
651 * to.
652 *
653 * Returns:
654 * The pointer for the page table entry.
655 */
656uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
657{
658 uint64_t result;
659
660 /* page table offset */
661 result = pages_addr[addr >> PAGE_SHIFT];
662
663 /* in case cpu page size != gpu page size*/
664 result |= addr & (~PAGE_MASK);
665
666 result &= 0xFFFFFFFFFFFFF000ULL;
667
668 return result;
669}
670
671/**
672 * amdgpu_vm_update_pdes - make sure that all directories are valid
673 *
674 * @adev: amdgpu_device pointer
675 * @vm: requested vm
676 * @immediate: submit immediately to the paging queue
677 *
678 * Makes sure all directories are up to date.
679 *
680 * Returns:
681 * 0 for success, error for failure.
682 */
683int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
684 struct amdgpu_vm *vm, bool immediate)
685{
686 struct amdgpu_vm_update_params params;
687 struct amdgpu_vm_bo_base *entry;
688 bool flush_tlb_needed = false;
689 LIST_HEAD(relocated);
690 int r, idx;
691
692 spin_lock(&vm->status_lock);
693 list_splice_init(&vm->relocated, &relocated);
694 spin_unlock(&vm->status_lock);
695
696 if (list_empty(&relocated))
697 return 0;
698
699 if (!drm_dev_enter(adev_to_drm(adev), &idx))
700 return -ENODEV;
701
702 memset(¶ms, 0, sizeof(params));
703 params.adev = adev;
704 params.vm = vm;
705 params.immediate = immediate;
706
707 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
708 if (r)
709 goto error;
710
711 list_for_each_entry(entry, &relocated, vm_status) {
712 /* vm_flush_needed after updating moved PDEs */
713 flush_tlb_needed |= entry->moved;
714
715 r = amdgpu_vm_pde_update(¶ms, entry);
716 if (r)
717 goto error;
718 }
719
720 r = vm->update_funcs->commit(¶ms, &vm->last_update);
721 if (r)
722 goto error;
723
724 if (flush_tlb_needed)
725 atomic64_inc(&vm->tlb_seq);
726
727 while (!list_empty(&relocated)) {
728 entry = list_first_entry(&relocated, struct amdgpu_vm_bo_base,
729 vm_status);
730 amdgpu_vm_bo_idle(entry);
731 }
732
733error:
734 drm_dev_exit(idx);
735 return r;
736}
737
738/**
739 * amdgpu_vm_tlb_seq_cb - make sure to increment tlb sequence
740 * @fence: unused
741 * @cb: the callback structure
742 *
743 * Increments the tlb sequence to make sure that future CS execute a VM flush.
744 */
745static void amdgpu_vm_tlb_seq_cb(struct dma_fence *fence,
746 struct dma_fence_cb *cb)
747{
748 struct amdgpu_vm_tlb_seq_cb *tlb_cb;
749
750 tlb_cb = container_of(cb, typeof(*tlb_cb), cb);
751 atomic64_inc(&tlb_cb->vm->tlb_seq);
752 kfree(tlb_cb);
753}
754
755/**
756 * amdgpu_vm_update_range - update a range in the vm page table
757 *
758 * @adev: amdgpu_device pointer to use for commands
759 * @vm: the VM to update the range
760 * @immediate: immediate submission in a page fault
761 * @unlocked: unlocked invalidation during MM callback
762 * @flush_tlb: trigger tlb invalidation after update completed
763 * @resv: fences we need to sync to
764 * @start: start of mapped range
765 * @last: last mapped entry
766 * @flags: flags for the entries
767 * @offset: offset into nodes and pages_addr
768 * @vram_base: base for vram mappings
769 * @res: ttm_resource to map
770 * @pages_addr: DMA addresses to use for mapping
771 * @fence: optional resulting fence
772 *
773 * Fill in the page table entries between @start and @last.
774 *
775 * Returns:
776 * 0 for success, negative erro code for failure.
777 */
778int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
779 bool immediate, bool unlocked, bool flush_tlb,
780 struct dma_resv *resv, uint64_t start, uint64_t last,
781 uint64_t flags, uint64_t offset, uint64_t vram_base,
782 struct ttm_resource *res, dma_addr_t *pages_addr,
783 struct dma_fence **fence)
784{
785 struct amdgpu_vm_update_params params;
786 struct amdgpu_vm_tlb_seq_cb *tlb_cb;
787 struct amdgpu_res_cursor cursor;
788 enum amdgpu_sync_mode sync_mode;
789 int r, idx;
790
791 if (!drm_dev_enter(adev_to_drm(adev), &idx))
792 return -ENODEV;
793
794 tlb_cb = kmalloc(sizeof(*tlb_cb), GFP_KERNEL);
795 if (!tlb_cb) {
796 r = -ENOMEM;
797 goto error_unlock;
798 }
799
800 /* Vega20+XGMI where PTEs get inadvertently cached in L2 texture cache,
801 * heavy-weight flush TLB unconditionally.
802 */
803 flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
804 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0);
805
806 /*
807 * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB
808 */
809 flush_tlb |= adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 0, 0);
810
811 memset(¶ms, 0, sizeof(params));
812 params.adev = adev;
813 params.vm = vm;
814 params.immediate = immediate;
815 params.pages_addr = pages_addr;
816 params.unlocked = unlocked;
817
818 /* Implicitly sync to command submissions in the same VM before
819 * unmapping. Sync to moving fences before mapping.
820 */
821 if (!(flags & AMDGPU_PTE_VALID))
822 sync_mode = AMDGPU_SYNC_EQ_OWNER;
823 else
824 sync_mode = AMDGPU_SYNC_EXPLICIT;
825
826 amdgpu_vm_eviction_lock(vm);
827 if (vm->evicting) {
828 r = -EBUSY;
829 goto error_free;
830 }
831
832 if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
833 struct dma_fence *tmp = dma_fence_get_stub();
834
835 amdgpu_bo_fence(vm->root.bo, vm->last_unlocked, true);
836 swap(vm->last_unlocked, tmp);
837 dma_fence_put(tmp);
838 }
839
840 r = vm->update_funcs->prepare(¶ms, resv, sync_mode);
841 if (r)
842 goto error_free;
843
844 amdgpu_res_first(pages_addr ? NULL : res, offset,
845 (last - start + 1) * AMDGPU_GPU_PAGE_SIZE, &cursor);
846 while (cursor.remaining) {
847 uint64_t tmp, num_entries, addr;
848
849 num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT;
850 if (pages_addr) {
851 bool contiguous = true;
852
853 if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) {
854 uint64_t pfn = cursor.start >> PAGE_SHIFT;
855 uint64_t count;
856
857 contiguous = pages_addr[pfn + 1] ==
858 pages_addr[pfn] + PAGE_SIZE;
859
860 tmp = num_entries /
861 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
862 for (count = 2; count < tmp; ++count) {
863 uint64_t idx = pfn + count;
864
865 if (contiguous != (pages_addr[idx] ==
866 pages_addr[idx - 1] + PAGE_SIZE))
867 break;
868 }
869 num_entries = count *
870 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
871 }
872
873 if (!contiguous) {
874 addr = cursor.start;
875 params.pages_addr = pages_addr;
876 } else {
877 addr = pages_addr[cursor.start >> PAGE_SHIFT];
878 params.pages_addr = NULL;
879 }
880
881 } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
882 addr = vram_base + cursor.start;
883 } else {
884 addr = 0;
885 }
886
887 tmp = start + num_entries;
888 r = amdgpu_vm_ptes_update(¶ms, start, tmp, addr, flags);
889 if (r)
890 goto error_free;
891
892 amdgpu_res_next(&cursor, num_entries * AMDGPU_GPU_PAGE_SIZE);
893 start = tmp;
894 }
895
896 r = vm->update_funcs->commit(¶ms, fence);
897
898 if (flush_tlb || params.table_freed) {
899 tlb_cb->vm = vm;
900 if (fence && *fence &&
901 !dma_fence_add_callback(*fence, &tlb_cb->cb,
902 amdgpu_vm_tlb_seq_cb)) {
903 dma_fence_put(vm->last_tlb_flush);
904 vm->last_tlb_flush = dma_fence_get(*fence);
905 } else {
906 amdgpu_vm_tlb_seq_cb(NULL, &tlb_cb->cb);
907 }
908 tlb_cb = NULL;
909 }
910
911error_free:
912 kfree(tlb_cb);
913
914error_unlock:
915 amdgpu_vm_eviction_unlock(vm);
916 drm_dev_exit(idx);
917 return r;
918}
919
920void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem,
921 uint64_t *gtt_mem, uint64_t *cpu_mem)
922{
923 struct amdgpu_bo_va *bo_va, *tmp;
924
925 spin_lock(&vm->status_lock);
926 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
927 if (!bo_va->base.bo)
928 continue;
929 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
930 gtt_mem, cpu_mem);
931 }
932 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
933 if (!bo_va->base.bo)
934 continue;
935 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
936 gtt_mem, cpu_mem);
937 }
938 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
939 if (!bo_va->base.bo)
940 continue;
941 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
942 gtt_mem, cpu_mem);
943 }
944 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
945 if (!bo_va->base.bo)
946 continue;
947 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
948 gtt_mem, cpu_mem);
949 }
950 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
951 if (!bo_va->base.bo)
952 continue;
953 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
954 gtt_mem, cpu_mem);
955 }
956 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
957 if (!bo_va->base.bo)
958 continue;
959 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
960 gtt_mem, cpu_mem);
961 }
962 spin_unlock(&vm->status_lock);
963}
964/**
965 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
966 *
967 * @adev: amdgpu_device pointer
968 * @bo_va: requested BO and VM object
969 * @clear: if true clear the entries
970 *
971 * Fill in the page table entries for @bo_va.
972 *
973 * Returns:
974 * 0 for success, -EINVAL for failure.
975 */
976int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
977 bool clear)
978{
979 struct amdgpu_bo *bo = bo_va->base.bo;
980 struct amdgpu_vm *vm = bo_va->base.vm;
981 struct amdgpu_bo_va_mapping *mapping;
982 dma_addr_t *pages_addr = NULL;
983 struct ttm_resource *mem;
984 struct dma_fence **last_update;
985 bool flush_tlb = clear;
986 struct dma_resv *resv;
987 uint64_t vram_base;
988 uint64_t flags;
989 int r;
990
991 if (clear || !bo) {
992 mem = NULL;
993 resv = vm->root.bo->tbo.base.resv;
994 } else {
995 struct drm_gem_object *obj = &bo->tbo.base;
996
997 resv = bo->tbo.base.resv;
998 if (obj->import_attach && bo_va->is_xgmi) {
999 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
1000 struct drm_gem_object *gobj = dma_buf->priv;
1001 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
1002
1003 if (abo->tbo.resource->mem_type == TTM_PL_VRAM)
1004 bo = gem_to_amdgpu_bo(gobj);
1005 }
1006 mem = bo->tbo.resource;
1007 if (mem->mem_type == TTM_PL_TT ||
1008 mem->mem_type == AMDGPU_PL_PREEMPT)
1009 pages_addr = bo->tbo.ttm->dma_address;
1010 }
1011
1012 if (bo) {
1013 struct amdgpu_device *bo_adev;
1014
1015 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1016
1017 if (amdgpu_bo_encrypted(bo))
1018 flags |= AMDGPU_PTE_TMZ;
1019
1020 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1021 vram_base = bo_adev->vm_manager.vram_base_offset;
1022 } else {
1023 flags = 0x0;
1024 vram_base = 0;
1025 }
1026
1027 if (clear || (bo && bo->tbo.base.resv ==
1028 vm->root.bo->tbo.base.resv))
1029 last_update = &vm->last_update;
1030 else
1031 last_update = &bo_va->last_pt_update;
1032
1033 if (!clear && bo_va->base.moved) {
1034 flush_tlb = true;
1035 list_splice_init(&bo_va->valids, &bo_va->invalids);
1036
1037 } else if (bo_va->cleared != clear) {
1038 list_splice_init(&bo_va->valids, &bo_va->invalids);
1039 }
1040
1041 list_for_each_entry(mapping, &bo_va->invalids, list) {
1042 uint64_t update_flags = flags;
1043
1044 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1045 * but in case of something, we filter the flags in first place
1046 */
1047 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1048 update_flags &= ~AMDGPU_PTE_READABLE;
1049 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1050 update_flags &= ~AMDGPU_PTE_WRITEABLE;
1051
1052 /* Apply ASIC specific mapping flags */
1053 amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags);
1054
1055 trace_amdgpu_vm_bo_update(mapping);
1056
1057 r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb,
1058 resv, mapping->start, mapping->last,
1059 update_flags, mapping->offset,
1060 vram_base, mem, pages_addr,
1061 last_update);
1062 if (r)
1063 return r;
1064 }
1065
1066 /* If the BO is not in its preferred location add it back to
1067 * the evicted list so that it gets validated again on the
1068 * next command submission.
1069 */
1070 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
1071 uint32_t mem_type = bo->tbo.resource->mem_type;
1072
1073 if (!(bo->preferred_domains &
1074 amdgpu_mem_type_to_domain(mem_type)))
1075 amdgpu_vm_bo_evicted(&bo_va->base);
1076 else
1077 amdgpu_vm_bo_idle(&bo_va->base);
1078 } else {
1079 amdgpu_vm_bo_done(&bo_va->base);
1080 }
1081
1082 list_splice_init(&bo_va->invalids, &bo_va->valids);
1083 bo_va->cleared = clear;
1084 bo_va->base.moved = false;
1085
1086 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1087 list_for_each_entry(mapping, &bo_va->valids, list)
1088 trace_amdgpu_vm_bo_mapping(mapping);
1089 }
1090
1091 return 0;
1092}
1093
1094/**
1095 * amdgpu_vm_update_prt_state - update the global PRT state
1096 *
1097 * @adev: amdgpu_device pointer
1098 */
1099static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1100{
1101 unsigned long flags;
1102 bool enable;
1103
1104 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1105 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1106 adev->gmc.gmc_funcs->set_prt(adev, enable);
1107 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1108}
1109
1110/**
1111 * amdgpu_vm_prt_get - add a PRT user
1112 *
1113 * @adev: amdgpu_device pointer
1114 */
1115static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1116{
1117 if (!adev->gmc.gmc_funcs->set_prt)
1118 return;
1119
1120 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1121 amdgpu_vm_update_prt_state(adev);
1122}
1123
1124/**
1125 * amdgpu_vm_prt_put - drop a PRT user
1126 *
1127 * @adev: amdgpu_device pointer
1128 */
1129static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1130{
1131 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1132 amdgpu_vm_update_prt_state(adev);
1133}
1134
1135/**
1136 * amdgpu_vm_prt_cb - callback for updating the PRT status
1137 *
1138 * @fence: fence for the callback
1139 * @_cb: the callback function
1140 */
1141static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1142{
1143 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1144
1145 amdgpu_vm_prt_put(cb->adev);
1146 kfree(cb);
1147}
1148
1149/**
1150 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1151 *
1152 * @adev: amdgpu_device pointer
1153 * @fence: fence for the callback
1154 */
1155static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1156 struct dma_fence *fence)
1157{
1158 struct amdgpu_prt_cb *cb;
1159
1160 if (!adev->gmc.gmc_funcs->set_prt)
1161 return;
1162
1163 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1164 if (!cb) {
1165 /* Last resort when we are OOM */
1166 if (fence)
1167 dma_fence_wait(fence, false);
1168
1169 amdgpu_vm_prt_put(adev);
1170 } else {
1171 cb->adev = adev;
1172 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1173 amdgpu_vm_prt_cb))
1174 amdgpu_vm_prt_cb(fence, &cb->cb);
1175 }
1176}
1177
1178/**
1179 * amdgpu_vm_free_mapping - free a mapping
1180 *
1181 * @adev: amdgpu_device pointer
1182 * @vm: requested vm
1183 * @mapping: mapping to be freed
1184 * @fence: fence of the unmap operation
1185 *
1186 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1187 */
1188static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1189 struct amdgpu_vm *vm,
1190 struct amdgpu_bo_va_mapping *mapping,
1191 struct dma_fence *fence)
1192{
1193 if (mapping->flags & AMDGPU_PTE_PRT)
1194 amdgpu_vm_add_prt_cb(adev, fence);
1195 kfree(mapping);
1196}
1197
1198/**
1199 * amdgpu_vm_prt_fini - finish all prt mappings
1200 *
1201 * @adev: amdgpu_device pointer
1202 * @vm: requested vm
1203 *
1204 * Register a cleanup callback to disable PRT support after VM dies.
1205 */
1206static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1207{
1208 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1209 struct dma_resv_iter cursor;
1210 struct dma_fence *fence;
1211
1212 dma_resv_for_each_fence(&cursor, resv, DMA_RESV_USAGE_BOOKKEEP, fence) {
1213 /* Add a callback for each fence in the reservation object */
1214 amdgpu_vm_prt_get(adev);
1215 amdgpu_vm_add_prt_cb(adev, fence);
1216 }
1217}
1218
1219/**
1220 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1221 *
1222 * @adev: amdgpu_device pointer
1223 * @vm: requested vm
1224 * @fence: optional resulting fence (unchanged if no work needed to be done
1225 * or if an error occurred)
1226 *
1227 * Make sure all freed BOs are cleared in the PT.
1228 * PTs have to be reserved and mutex must be locked!
1229 *
1230 * Returns:
1231 * 0 for success.
1232 *
1233 */
1234int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1235 struct amdgpu_vm *vm,
1236 struct dma_fence **fence)
1237{
1238 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1239 struct amdgpu_bo_va_mapping *mapping;
1240 uint64_t init_pte_value = 0;
1241 struct dma_fence *f = NULL;
1242 int r;
1243
1244 while (!list_empty(&vm->freed)) {
1245 mapping = list_first_entry(&vm->freed,
1246 struct amdgpu_bo_va_mapping, list);
1247 list_del(&mapping->list);
1248
1249 if (vm->pte_support_ats &&
1250 mapping->start < AMDGPU_GMC_HOLE_START)
1251 init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
1252
1253 r = amdgpu_vm_update_range(adev, vm, false, false, true, resv,
1254 mapping->start, mapping->last,
1255 init_pte_value, 0, 0, NULL, NULL,
1256 &f);
1257 amdgpu_vm_free_mapping(adev, vm, mapping, f);
1258 if (r) {
1259 dma_fence_put(f);
1260 return r;
1261 }
1262 }
1263
1264 if (fence && f) {
1265 dma_fence_put(*fence);
1266 *fence = f;
1267 } else {
1268 dma_fence_put(f);
1269 }
1270
1271 return 0;
1272
1273}
1274
1275/**
1276 * amdgpu_vm_handle_moved - handle moved BOs in the PT
1277 *
1278 * @adev: amdgpu_device pointer
1279 * @vm: requested vm
1280 *
1281 * Make sure all BOs which are moved are updated in the PTs.
1282 *
1283 * Returns:
1284 * 0 for success.
1285 *
1286 * PTs have to be reserved!
1287 */
1288int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
1289 struct amdgpu_vm *vm)
1290{
1291 struct amdgpu_bo_va *bo_va;
1292 struct dma_resv *resv;
1293 bool clear;
1294 int r;
1295
1296 spin_lock(&vm->status_lock);
1297 while (!list_empty(&vm->moved)) {
1298 bo_va = list_first_entry(&vm->moved, struct amdgpu_bo_va,
1299 base.vm_status);
1300 spin_unlock(&vm->status_lock);
1301
1302 /* Per VM BOs never need to bo cleared in the page tables */
1303 r = amdgpu_vm_bo_update(adev, bo_va, false);
1304 if (r)
1305 return r;
1306 spin_lock(&vm->status_lock);
1307 }
1308
1309 while (!list_empty(&vm->invalidated)) {
1310 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
1311 base.vm_status);
1312 resv = bo_va->base.bo->tbo.base.resv;
1313 spin_unlock(&vm->status_lock);
1314
1315 /* Try to reserve the BO to avoid clearing its ptes */
1316 if (!amdgpu_vm_debug && dma_resv_trylock(resv))
1317 clear = false;
1318 /* Somebody else is using the BO right now */
1319 else
1320 clear = true;
1321
1322 r = amdgpu_vm_bo_update(adev, bo_va, clear);
1323 if (r)
1324 return r;
1325
1326 if (!clear)
1327 dma_resv_unlock(resv);
1328 spin_lock(&vm->status_lock);
1329 }
1330 spin_unlock(&vm->status_lock);
1331
1332 return 0;
1333}
1334
1335/**
1336 * amdgpu_vm_bo_add - add a bo to a specific vm
1337 *
1338 * @adev: amdgpu_device pointer
1339 * @vm: requested vm
1340 * @bo: amdgpu buffer object
1341 *
1342 * Add @bo into the requested vm.
1343 * Add @bo to the list of bos associated with the vm
1344 *
1345 * Returns:
1346 * Newly added bo_va or NULL for failure
1347 *
1348 * Object has to be reserved!
1349 */
1350struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1351 struct amdgpu_vm *vm,
1352 struct amdgpu_bo *bo)
1353{
1354 struct amdgpu_bo_va *bo_va;
1355
1356 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1357 if (bo_va == NULL) {
1358 return NULL;
1359 }
1360 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
1361
1362 bo_va->ref_count = 1;
1363 INIT_LIST_HEAD(&bo_va->valids);
1364 INIT_LIST_HEAD(&bo_va->invalids);
1365
1366 if (!bo)
1367 return bo_va;
1368
1369 dma_resv_assert_held(bo->tbo.base.resv);
1370 if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) {
1371 bo_va->is_xgmi = true;
1372 /* Power up XGMI if it can be potentially used */
1373 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
1374 }
1375
1376 return bo_va;
1377}
1378
1379
1380/**
1381 * amdgpu_vm_bo_insert_map - insert a new mapping
1382 *
1383 * @adev: amdgpu_device pointer
1384 * @bo_va: bo_va to store the address
1385 * @mapping: the mapping to insert
1386 *
1387 * Insert a new mapping into all structures.
1388 */
1389static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
1390 struct amdgpu_bo_va *bo_va,
1391 struct amdgpu_bo_va_mapping *mapping)
1392{
1393 struct amdgpu_vm *vm = bo_va->base.vm;
1394 struct amdgpu_bo *bo = bo_va->base.bo;
1395
1396 mapping->bo_va = bo_va;
1397 list_add(&mapping->list, &bo_va->invalids);
1398 amdgpu_vm_it_insert(mapping, &vm->va);
1399
1400 if (mapping->flags & AMDGPU_PTE_PRT)
1401 amdgpu_vm_prt_get(adev);
1402
1403 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1404 !bo_va->base.moved) {
1405 amdgpu_vm_bo_moved(&bo_va->base);
1406 }
1407 trace_amdgpu_vm_bo_map(bo_va, mapping);
1408}
1409
1410/**
1411 * amdgpu_vm_bo_map - map bo inside a vm
1412 *
1413 * @adev: amdgpu_device pointer
1414 * @bo_va: bo_va to store the address
1415 * @saddr: where to map the BO
1416 * @offset: requested offset in the BO
1417 * @size: BO size in bytes
1418 * @flags: attributes of pages (read/write/valid/etc.)
1419 *
1420 * Add a mapping of the BO at the specefied addr into the VM.
1421 *
1422 * Returns:
1423 * 0 for success, error for failure.
1424 *
1425 * Object has to be reserved and unreserved outside!
1426 */
1427int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1428 struct amdgpu_bo_va *bo_va,
1429 uint64_t saddr, uint64_t offset,
1430 uint64_t size, uint64_t flags)
1431{
1432 struct amdgpu_bo_va_mapping *mapping, *tmp;
1433 struct amdgpu_bo *bo = bo_va->base.bo;
1434 struct amdgpu_vm *vm = bo_va->base.vm;
1435 uint64_t eaddr;
1436
1437 /* validate the parameters */
1438 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK ||
1439 size == 0 || size & ~PAGE_MASK)
1440 return -EINVAL;
1441
1442 /* make sure object fit at this offset */
1443 eaddr = saddr + size - 1;
1444 if (saddr >= eaddr ||
1445 (bo && offset + size > amdgpu_bo_size(bo)) ||
1446 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
1447 return -EINVAL;
1448
1449 saddr /= AMDGPU_GPU_PAGE_SIZE;
1450 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1451
1452 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1453 if (tmp) {
1454 /* bo and tmp overlap, invalid addr */
1455 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1456 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
1457 tmp->start, tmp->last + 1);
1458 return -EINVAL;
1459 }
1460
1461 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1462 if (!mapping)
1463 return -ENOMEM;
1464
1465 mapping->start = saddr;
1466 mapping->last = eaddr;
1467 mapping->offset = offset;
1468 mapping->flags = flags;
1469
1470 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1471
1472 return 0;
1473}
1474
1475/**
1476 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
1477 *
1478 * @adev: amdgpu_device pointer
1479 * @bo_va: bo_va to store the address
1480 * @saddr: where to map the BO
1481 * @offset: requested offset in the BO
1482 * @size: BO size in bytes
1483 * @flags: attributes of pages (read/write/valid/etc.)
1484 *
1485 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
1486 * mappings as we do so.
1487 *
1488 * Returns:
1489 * 0 for success, error for failure.
1490 *
1491 * Object has to be reserved and unreserved outside!
1492 */
1493int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
1494 struct amdgpu_bo_va *bo_va,
1495 uint64_t saddr, uint64_t offset,
1496 uint64_t size, uint64_t flags)
1497{
1498 struct amdgpu_bo_va_mapping *mapping;
1499 struct amdgpu_bo *bo = bo_va->base.bo;
1500 uint64_t eaddr;
1501 int r;
1502
1503 /* validate the parameters */
1504 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK ||
1505 size == 0 || size & ~PAGE_MASK)
1506 return -EINVAL;
1507
1508 /* make sure object fit at this offset */
1509 eaddr = saddr + size - 1;
1510 if (saddr >= eaddr ||
1511 (bo && offset + size > amdgpu_bo_size(bo)) ||
1512 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
1513 return -EINVAL;
1514
1515 /* Allocate all the needed memory */
1516 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1517 if (!mapping)
1518 return -ENOMEM;
1519
1520 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
1521 if (r) {
1522 kfree(mapping);
1523 return r;
1524 }
1525
1526 saddr /= AMDGPU_GPU_PAGE_SIZE;
1527 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1528
1529 mapping->start = saddr;
1530 mapping->last = eaddr;
1531 mapping->offset = offset;
1532 mapping->flags = flags;
1533
1534 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1535
1536 return 0;
1537}
1538
1539/**
1540 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1541 *
1542 * @adev: amdgpu_device pointer
1543 * @bo_va: bo_va to remove the address from
1544 * @saddr: where to the BO is mapped
1545 *
1546 * Remove a mapping of the BO at the specefied addr from the VM.
1547 *
1548 * Returns:
1549 * 0 for success, error for failure.
1550 *
1551 * Object has to be reserved and unreserved outside!
1552 */
1553int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1554 struct amdgpu_bo_va *bo_va,
1555 uint64_t saddr)
1556{
1557 struct amdgpu_bo_va_mapping *mapping;
1558 struct amdgpu_vm *vm = bo_va->base.vm;
1559 bool valid = true;
1560
1561 saddr /= AMDGPU_GPU_PAGE_SIZE;
1562
1563 list_for_each_entry(mapping, &bo_va->valids, list) {
1564 if (mapping->start == saddr)
1565 break;
1566 }
1567
1568 if (&mapping->list == &bo_va->valids) {
1569 valid = false;
1570
1571 list_for_each_entry(mapping, &bo_va->invalids, list) {
1572 if (mapping->start == saddr)
1573 break;
1574 }
1575
1576 if (&mapping->list == &bo_va->invalids)
1577 return -ENOENT;
1578 }
1579
1580 list_del(&mapping->list);
1581 amdgpu_vm_it_remove(mapping, &vm->va);
1582 mapping->bo_va = NULL;
1583 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1584
1585 if (valid)
1586 list_add(&mapping->list, &vm->freed);
1587 else
1588 amdgpu_vm_free_mapping(adev, vm, mapping,
1589 bo_va->last_pt_update);
1590
1591 return 0;
1592}
1593
1594/**
1595 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
1596 *
1597 * @adev: amdgpu_device pointer
1598 * @vm: VM structure to use
1599 * @saddr: start of the range
1600 * @size: size of the range
1601 *
1602 * Remove all mappings in a range, split them as appropriate.
1603 *
1604 * Returns:
1605 * 0 for success, error for failure.
1606 */
1607int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
1608 struct amdgpu_vm *vm,
1609 uint64_t saddr, uint64_t size)
1610{
1611 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
1612 LIST_HEAD(removed);
1613 uint64_t eaddr;
1614
1615 eaddr = saddr + size - 1;
1616 saddr /= AMDGPU_GPU_PAGE_SIZE;
1617 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1618
1619 /* Allocate all the needed memory */
1620 before = kzalloc(sizeof(*before), GFP_KERNEL);
1621 if (!before)
1622 return -ENOMEM;
1623 INIT_LIST_HEAD(&before->list);
1624
1625 after = kzalloc(sizeof(*after), GFP_KERNEL);
1626 if (!after) {
1627 kfree(before);
1628 return -ENOMEM;
1629 }
1630 INIT_LIST_HEAD(&after->list);
1631
1632 /* Now gather all removed mappings */
1633 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1634 while (tmp) {
1635 /* Remember mapping split at the start */
1636 if (tmp->start < saddr) {
1637 before->start = tmp->start;
1638 before->last = saddr - 1;
1639 before->offset = tmp->offset;
1640 before->flags = tmp->flags;
1641 before->bo_va = tmp->bo_va;
1642 list_add(&before->list, &tmp->bo_va->invalids);
1643 }
1644
1645 /* Remember mapping split at the end */
1646 if (tmp->last > eaddr) {
1647 after->start = eaddr + 1;
1648 after->last = tmp->last;
1649 after->offset = tmp->offset;
1650 after->offset += (after->start - tmp->start) << PAGE_SHIFT;
1651 after->flags = tmp->flags;
1652 after->bo_va = tmp->bo_va;
1653 list_add(&after->list, &tmp->bo_va->invalids);
1654 }
1655
1656 list_del(&tmp->list);
1657 list_add(&tmp->list, &removed);
1658
1659 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
1660 }
1661
1662 /* And free them up */
1663 list_for_each_entry_safe(tmp, next, &removed, list) {
1664 amdgpu_vm_it_remove(tmp, &vm->va);
1665 list_del(&tmp->list);
1666
1667 if (tmp->start < saddr)
1668 tmp->start = saddr;
1669 if (tmp->last > eaddr)
1670 tmp->last = eaddr;
1671
1672 tmp->bo_va = NULL;
1673 list_add(&tmp->list, &vm->freed);
1674 trace_amdgpu_vm_bo_unmap(NULL, tmp);
1675 }
1676
1677 /* Insert partial mapping before the range */
1678 if (!list_empty(&before->list)) {
1679 amdgpu_vm_it_insert(before, &vm->va);
1680 if (before->flags & AMDGPU_PTE_PRT)
1681 amdgpu_vm_prt_get(adev);
1682 } else {
1683 kfree(before);
1684 }
1685
1686 /* Insert partial mapping after the range */
1687 if (!list_empty(&after->list)) {
1688 amdgpu_vm_it_insert(after, &vm->va);
1689 if (after->flags & AMDGPU_PTE_PRT)
1690 amdgpu_vm_prt_get(adev);
1691 } else {
1692 kfree(after);
1693 }
1694
1695 return 0;
1696}
1697
1698/**
1699 * amdgpu_vm_bo_lookup_mapping - find mapping by address
1700 *
1701 * @vm: the requested VM
1702 * @addr: the address
1703 *
1704 * Find a mapping by it's address.
1705 *
1706 * Returns:
1707 * The amdgpu_bo_va_mapping matching for addr or NULL
1708 *
1709 */
1710struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
1711 uint64_t addr)
1712{
1713 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
1714}
1715
1716/**
1717 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
1718 *
1719 * @vm: the requested vm
1720 * @ticket: CS ticket
1721 *
1722 * Trace all mappings of BOs reserved during a command submission.
1723 */
1724void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
1725{
1726 struct amdgpu_bo_va_mapping *mapping;
1727
1728 if (!trace_amdgpu_vm_bo_cs_enabled())
1729 return;
1730
1731 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
1732 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
1733 if (mapping->bo_va && mapping->bo_va->base.bo) {
1734 struct amdgpu_bo *bo;
1735
1736 bo = mapping->bo_va->base.bo;
1737 if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
1738 ticket)
1739 continue;
1740 }
1741
1742 trace_amdgpu_vm_bo_cs(mapping);
1743 }
1744}
1745
1746/**
1747 * amdgpu_vm_bo_del - remove a bo from a specific vm
1748 *
1749 * @adev: amdgpu_device pointer
1750 * @bo_va: requested bo_va
1751 *
1752 * Remove @bo_va->bo from the requested vm.
1753 *
1754 * Object have to be reserved!
1755 */
1756void amdgpu_vm_bo_del(struct amdgpu_device *adev,
1757 struct amdgpu_bo_va *bo_va)
1758{
1759 struct amdgpu_bo_va_mapping *mapping, *next;
1760 struct amdgpu_bo *bo = bo_va->base.bo;
1761 struct amdgpu_vm *vm = bo_va->base.vm;
1762 struct amdgpu_vm_bo_base **base;
1763
1764 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
1765
1766 if (bo) {
1767 dma_resv_assert_held(bo->tbo.base.resv);
1768 if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
1769 ttm_bo_set_bulk_move(&bo->tbo, NULL);
1770
1771 for (base = &bo_va->base.bo->vm_bo; *base;
1772 base = &(*base)->next) {
1773 if (*base != &bo_va->base)
1774 continue;
1775
1776 *base = bo_va->base.next;
1777 break;
1778 }
1779 }
1780
1781 spin_lock(&vm->status_lock);
1782 list_del(&bo_va->base.vm_status);
1783 spin_unlock(&vm->status_lock);
1784
1785 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
1786 list_del(&mapping->list);
1787 amdgpu_vm_it_remove(mapping, &vm->va);
1788 mapping->bo_va = NULL;
1789 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1790 list_add(&mapping->list, &vm->freed);
1791 }
1792 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
1793 list_del(&mapping->list);
1794 amdgpu_vm_it_remove(mapping, &vm->va);
1795 amdgpu_vm_free_mapping(adev, vm, mapping,
1796 bo_va->last_pt_update);
1797 }
1798
1799 dma_fence_put(bo_va->last_pt_update);
1800
1801 if (bo && bo_va->is_xgmi)
1802 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
1803
1804 kfree(bo_va);
1805}
1806
1807/**
1808 * amdgpu_vm_evictable - check if we can evict a VM
1809 *
1810 * @bo: A page table of the VM.
1811 *
1812 * Check if it is possible to evict a VM.
1813 */
1814bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
1815{
1816 struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
1817
1818 /* Page tables of a destroyed VM can go away immediately */
1819 if (!bo_base || !bo_base->vm)
1820 return true;
1821
1822 /* Don't evict VM page tables while they are busy */
1823 if (!dma_resv_test_signaled(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP))
1824 return false;
1825
1826 /* Try to block ongoing updates */
1827 if (!amdgpu_vm_eviction_trylock(bo_base->vm))
1828 return false;
1829
1830 /* Don't evict VM page tables while they are updated */
1831 if (!dma_fence_is_signaled(bo_base->vm->last_unlocked)) {
1832 amdgpu_vm_eviction_unlock(bo_base->vm);
1833 return false;
1834 }
1835
1836 bo_base->vm->evicting = true;
1837 amdgpu_vm_eviction_unlock(bo_base->vm);
1838 return true;
1839}
1840
1841/**
1842 * amdgpu_vm_bo_invalidate - mark the bo as invalid
1843 *
1844 * @adev: amdgpu_device pointer
1845 * @bo: amdgpu buffer object
1846 * @evicted: is the BO evicted
1847 *
1848 * Mark @bo as invalid.
1849 */
1850void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
1851 struct amdgpu_bo *bo, bool evicted)
1852{
1853 struct amdgpu_vm_bo_base *bo_base;
1854
1855 /* shadow bo doesn't have bo base, its validation needs its parent */
1856 if (bo->parent && (amdgpu_bo_shadowed(bo->parent) == bo))
1857 bo = bo->parent;
1858
1859 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
1860 struct amdgpu_vm *vm = bo_base->vm;
1861
1862 if (evicted && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
1863 amdgpu_vm_bo_evicted(bo_base);
1864 continue;
1865 }
1866
1867 if (bo_base->moved)
1868 continue;
1869 bo_base->moved = true;
1870
1871 if (bo->tbo.type == ttm_bo_type_kernel)
1872 amdgpu_vm_bo_relocated(bo_base);
1873 else if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
1874 amdgpu_vm_bo_moved(bo_base);
1875 else
1876 amdgpu_vm_bo_invalidated(bo_base);
1877 }
1878}
1879
1880/**
1881 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
1882 *
1883 * @vm_size: VM size
1884 *
1885 * Returns:
1886 * VM page table as power of two
1887 */
1888static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
1889{
1890 /* Total bits covered by PD + PTs */
1891 unsigned bits = ilog2(vm_size) + 18;
1892
1893 /* Make sure the PD is 4K in size up to 8GB address space.
1894 Above that split equal between PD and PTs */
1895 if (vm_size <= 8)
1896 return (bits - 9);
1897 else
1898 return ((bits + 3) / 2);
1899}
1900
1901/**
1902 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
1903 *
1904 * @adev: amdgpu_device pointer
1905 * @min_vm_size: the minimum vm size in GB if it's set auto
1906 * @fragment_size_default: Default PTE fragment size
1907 * @max_level: max VMPT level
1908 * @max_bits: max address space size in bits
1909 *
1910 */
1911void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
1912 uint32_t fragment_size_default, unsigned max_level,
1913 unsigned max_bits)
1914{
1915 unsigned int max_size = 1 << (max_bits - 30);
1916 unsigned int vm_size;
1917 uint64_t tmp;
1918
1919 /* adjust vm size first */
1920 if (amdgpu_vm_size != -1) {
1921 vm_size = amdgpu_vm_size;
1922 if (vm_size > max_size) {
1923 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
1924 amdgpu_vm_size, max_size);
1925 vm_size = max_size;
1926 }
1927 } else {
1928 struct sysinfo si;
1929 unsigned int phys_ram_gb;
1930
1931 /* Optimal VM size depends on the amount of physical
1932 * RAM available. Underlying requirements and
1933 * assumptions:
1934 *
1935 * - Need to map system memory and VRAM from all GPUs
1936 * - VRAM from other GPUs not known here
1937 * - Assume VRAM <= system memory
1938 * - On GFX8 and older, VM space can be segmented for
1939 * different MTYPEs
1940 * - Need to allow room for fragmentation, guard pages etc.
1941 *
1942 * This adds up to a rough guess of system memory x3.
1943 * Round up to power of two to maximize the available
1944 * VM size with the given page table size.
1945 */
1946 si_meminfo(&si);
1947 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
1948 (1 << 30) - 1) >> 30;
1949 vm_size = roundup_pow_of_two(
1950 min(max(phys_ram_gb * 3, min_vm_size), max_size));
1951 }
1952
1953 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
1954
1955 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
1956 if (amdgpu_vm_block_size != -1)
1957 tmp >>= amdgpu_vm_block_size - 9;
1958 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
1959 adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
1960 switch (adev->vm_manager.num_level) {
1961 case 3:
1962 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
1963 break;
1964 case 2:
1965 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
1966 break;
1967 case 1:
1968 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
1969 break;
1970 default:
1971 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
1972 }
1973 /* block size depends on vm size and hw setup*/
1974 if (amdgpu_vm_block_size != -1)
1975 adev->vm_manager.block_size =
1976 min((unsigned)amdgpu_vm_block_size, max_bits
1977 - AMDGPU_GPU_PAGE_SHIFT
1978 - 9 * adev->vm_manager.num_level);
1979 else if (adev->vm_manager.num_level > 1)
1980 adev->vm_manager.block_size = 9;
1981 else
1982 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
1983
1984 if (amdgpu_vm_fragment_size == -1)
1985 adev->vm_manager.fragment_size = fragment_size_default;
1986 else
1987 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
1988
1989 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
1990 vm_size, adev->vm_manager.num_level + 1,
1991 adev->vm_manager.block_size,
1992 adev->vm_manager.fragment_size);
1993}
1994
1995/**
1996 * amdgpu_vm_wait_idle - wait for the VM to become idle
1997 *
1998 * @vm: VM object to wait for
1999 * @timeout: timeout to wait for VM to become idle
2000 */
2001long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2002{
2003 timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv,
2004 DMA_RESV_USAGE_BOOKKEEP,
2005 true, timeout);
2006 if (timeout <= 0)
2007 return timeout;
2008
2009 return dma_fence_wait_timeout(vm->last_unlocked, true, timeout);
2010}
2011
2012/**
2013 * amdgpu_vm_init - initialize a vm instance
2014 *
2015 * @adev: amdgpu_device pointer
2016 * @vm: requested vm
2017 *
2018 * Init @vm fields.
2019 *
2020 * Returns:
2021 * 0 for success, error for failure.
2022 */
2023int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2024{
2025 struct amdgpu_bo *root_bo;
2026 struct amdgpu_bo_vm *root;
2027 int r, i;
2028
2029 vm->va = RB_ROOT_CACHED;
2030 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2031 vm->reserved_vmid[i] = NULL;
2032 INIT_LIST_HEAD(&vm->evicted);
2033 INIT_LIST_HEAD(&vm->relocated);
2034 INIT_LIST_HEAD(&vm->moved);
2035 INIT_LIST_HEAD(&vm->idle);
2036 INIT_LIST_HEAD(&vm->invalidated);
2037 spin_lock_init(&vm->status_lock);
2038 INIT_LIST_HEAD(&vm->freed);
2039 INIT_LIST_HEAD(&vm->done);
2040 INIT_LIST_HEAD(&vm->pt_freed);
2041 INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work);
2042
2043 /* create scheduler entities for page table updates */
2044 r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
2045 adev->vm_manager.vm_pte_scheds,
2046 adev->vm_manager.vm_pte_num_scheds, NULL);
2047 if (r)
2048 return r;
2049
2050 r = drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
2051 adev->vm_manager.vm_pte_scheds,
2052 adev->vm_manager.vm_pte_num_scheds, NULL);
2053 if (r)
2054 goto error_free_immediate;
2055
2056 vm->pte_support_ats = false;
2057 vm->is_compute_context = false;
2058
2059 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2060 AMDGPU_VM_USE_CPU_FOR_GFX);
2061
2062 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2063 vm->use_cpu_for_update ? "CPU" : "SDMA");
2064 WARN_ONCE((vm->use_cpu_for_update &&
2065 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2066 "CPU update of VM recommended only for large BAR system\n");
2067
2068 if (vm->use_cpu_for_update)
2069 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2070 else
2071 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2072 vm->last_update = NULL;
2073 vm->last_unlocked = dma_fence_get_stub();
2074 vm->last_tlb_flush = dma_fence_get_stub();
2075
2076 mutex_init(&vm->eviction_lock);
2077 vm->evicting = false;
2078
2079 r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
2080 false, &root);
2081 if (r)
2082 goto error_free_delayed;
2083 root_bo = &root->bo;
2084 r = amdgpu_bo_reserve(root_bo, true);
2085 if (r)
2086 goto error_free_root;
2087
2088 r = dma_resv_reserve_fences(root_bo->tbo.base.resv, 1);
2089 if (r)
2090 goto error_unreserve;
2091
2092 amdgpu_vm_bo_base_init(&vm->root, vm, root_bo);
2093
2094 r = amdgpu_vm_pt_clear(adev, vm, root, false);
2095 if (r)
2096 goto error_unreserve;
2097
2098 amdgpu_bo_unreserve(vm->root.bo);
2099
2100 INIT_KFIFO(vm->faults);
2101
2102 return 0;
2103
2104error_unreserve:
2105 amdgpu_bo_unreserve(vm->root.bo);
2106
2107error_free_root:
2108 amdgpu_bo_unref(&root->shadow);
2109 amdgpu_bo_unref(&root_bo);
2110 vm->root.bo = NULL;
2111
2112error_free_delayed:
2113 dma_fence_put(vm->last_tlb_flush);
2114 dma_fence_put(vm->last_unlocked);
2115 drm_sched_entity_destroy(&vm->delayed);
2116
2117error_free_immediate:
2118 drm_sched_entity_destroy(&vm->immediate);
2119
2120 return r;
2121}
2122
2123/**
2124 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2125 *
2126 * @adev: amdgpu_device pointer
2127 * @vm: requested vm
2128 *
2129 * This only works on GFX VMs that don't have any BOs added and no
2130 * page tables allocated yet.
2131 *
2132 * Changes the following VM parameters:
2133 * - use_cpu_for_update
2134 * - pte_supports_ats
2135 *
2136 * Reinitializes the page directory to reflect the changed ATS
2137 * setting.
2138 *
2139 * Returns:
2140 * 0 for success, -errno for errors.
2141 */
2142int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2143{
2144 bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
2145 int r;
2146
2147 r = amdgpu_bo_reserve(vm->root.bo, true);
2148 if (r)
2149 return r;
2150
2151 /* Sanity checks */
2152 if (!amdgpu_vm_pt_is_root_clean(adev, vm)) {
2153 r = -EINVAL;
2154 goto unreserve_bo;
2155 }
2156
2157 /* Check if PD needs to be reinitialized and do it before
2158 * changing any other state, in case it fails.
2159 */
2160 if (pte_support_ats != vm->pte_support_ats) {
2161 vm->pte_support_ats = pte_support_ats;
2162 r = amdgpu_vm_pt_clear(adev, vm, to_amdgpu_bo_vm(vm->root.bo),
2163 false);
2164 if (r)
2165 goto unreserve_bo;
2166 }
2167
2168 /* Update VM state */
2169 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2170 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2171 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2172 vm->use_cpu_for_update ? "CPU" : "SDMA");
2173 WARN_ONCE((vm->use_cpu_for_update &&
2174 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2175 "CPU update of VM recommended only for large BAR system\n");
2176
2177 if (vm->use_cpu_for_update) {
2178 /* Sync with last SDMA update/clear before switching to CPU */
2179 r = amdgpu_bo_sync_wait(vm->root.bo,
2180 AMDGPU_FENCE_OWNER_UNDEFINED, true);
2181 if (r)
2182 goto unreserve_bo;
2183
2184 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2185 } else {
2186 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2187 }
2188 /*
2189 * Make sure root PD gets mapped. As vm_update_mode could be changed
2190 * when turning a GFX VM into a compute VM.
2191 */
2192 r = vm->update_funcs->map_table(to_amdgpu_bo_vm(vm->root.bo));
2193 if (r)
2194 goto unreserve_bo;
2195
2196 dma_fence_put(vm->last_update);
2197 vm->last_update = NULL;
2198 vm->is_compute_context = true;
2199
2200 /* Free the shadow bo for compute VM */
2201 amdgpu_bo_unref(&to_amdgpu_bo_vm(vm->root.bo)->shadow);
2202
2203 goto unreserve_bo;
2204
2205unreserve_bo:
2206 amdgpu_bo_unreserve(vm->root.bo);
2207 return r;
2208}
2209
2210/**
2211 * amdgpu_vm_release_compute - release a compute vm
2212 * @adev: amdgpu_device pointer
2213 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
2214 *
2215 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
2216 * pasid from vm. Compute should stop use of vm after this call.
2217 */
2218void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2219{
2220 amdgpu_vm_set_pasid(adev, vm, 0);
2221 vm->is_compute_context = false;
2222}
2223
2224/**
2225 * amdgpu_vm_fini - tear down a vm instance
2226 *
2227 * @adev: amdgpu_device pointer
2228 * @vm: requested vm
2229 *
2230 * Tear down @vm.
2231 * Unbind the VM and remove all bos from the vm bo list
2232 */
2233void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2234{
2235 struct amdgpu_bo_va_mapping *mapping, *tmp;
2236 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
2237 struct amdgpu_bo *root;
2238 unsigned long flags;
2239 int i;
2240
2241 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
2242
2243 flush_work(&vm->pt_free_work);
2244
2245 root = amdgpu_bo_ref(vm->root.bo);
2246 amdgpu_bo_reserve(root, true);
2247 amdgpu_vm_set_pasid(adev, vm, 0);
2248 dma_fence_wait(vm->last_unlocked, false);
2249 dma_fence_put(vm->last_unlocked);
2250 dma_fence_wait(vm->last_tlb_flush, false);
2251 /* Make sure that all fence callbacks have completed */
2252 spin_lock_irqsave(vm->last_tlb_flush->lock, flags);
2253 spin_unlock_irqrestore(vm->last_tlb_flush->lock, flags);
2254 dma_fence_put(vm->last_tlb_flush);
2255
2256 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2257 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
2258 amdgpu_vm_prt_fini(adev, vm);
2259 prt_fini_needed = false;
2260 }
2261
2262 list_del(&mapping->list);
2263 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
2264 }
2265
2266 amdgpu_vm_pt_free_root(adev, vm);
2267 amdgpu_bo_unreserve(root);
2268 amdgpu_bo_unref(&root);
2269 WARN_ON(vm->root.bo);
2270
2271 drm_sched_entity_destroy(&vm->immediate);
2272 drm_sched_entity_destroy(&vm->delayed);
2273
2274 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
2275 dev_err(adev->dev, "still active bo inside vm\n");
2276 }
2277 rbtree_postorder_for_each_entry_safe(mapping, tmp,
2278 &vm->va.rb_root, rb) {
2279 /* Don't remove the mapping here, we don't want to trigger a
2280 * rebalance and the tree is about to be destroyed anyway.
2281 */
2282 list_del(&mapping->list);
2283 kfree(mapping);
2284 }
2285
2286 dma_fence_put(vm->last_update);
2287 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2288 amdgpu_vmid_free_reserved(adev, vm, i);
2289}
2290
2291/**
2292 * amdgpu_vm_manager_init - init the VM manager
2293 *
2294 * @adev: amdgpu_device pointer
2295 *
2296 * Initialize the VM manager structures
2297 */
2298void amdgpu_vm_manager_init(struct amdgpu_device *adev)
2299{
2300 unsigned i;
2301
2302 /* Concurrent flushes are only possible starting with Vega10 and
2303 * are broken on Navi10 and Navi14.
2304 */
2305 adev->vm_manager.concurrent_flush = !(adev->asic_type < CHIP_VEGA10 ||
2306 adev->asic_type == CHIP_NAVI10 ||
2307 adev->asic_type == CHIP_NAVI14);
2308 amdgpu_vmid_mgr_init(adev);
2309
2310 adev->vm_manager.fence_context =
2311 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2312 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2313 adev->vm_manager.seqno[i] = 0;
2314
2315 spin_lock_init(&adev->vm_manager.prt_lock);
2316 atomic_set(&adev->vm_manager.num_prt_users, 0);
2317
2318 /* If not overridden by the user, by default, only in large BAR systems
2319 * Compute VM tables will be updated by CPU
2320 */
2321#ifdef CONFIG_X86_64
2322 if (amdgpu_vm_update_mode == -1) {
2323 /* For asic with VF MMIO access protection
2324 * avoid using CPU for VM table updates
2325 */
2326 if (amdgpu_gmc_vram_full_visible(&adev->gmc) &&
2327 !amdgpu_sriov_vf_mmio_access_protection(adev))
2328 adev->vm_manager.vm_update_mode =
2329 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
2330 else
2331 adev->vm_manager.vm_update_mode = 0;
2332 } else
2333 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
2334#else
2335 adev->vm_manager.vm_update_mode = 0;
2336#endif
2337
2338 xa_init_flags(&adev->vm_manager.pasids, XA_FLAGS_LOCK_IRQ);
2339}
2340
2341/**
2342 * amdgpu_vm_manager_fini - cleanup VM manager
2343 *
2344 * @adev: amdgpu_device pointer
2345 *
2346 * Cleanup the VM manager and free resources.
2347 */
2348void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
2349{
2350 WARN_ON(!xa_empty(&adev->vm_manager.pasids));
2351 xa_destroy(&adev->vm_manager.pasids);
2352
2353 amdgpu_vmid_mgr_fini(adev);
2354}
2355
2356/**
2357 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
2358 *
2359 * @dev: drm device pointer
2360 * @data: drm_amdgpu_vm
2361 * @filp: drm file pointer
2362 *
2363 * Returns:
2364 * 0 for success, -errno for errors.
2365 */
2366int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
2367{
2368 union drm_amdgpu_vm *args = data;
2369 struct amdgpu_device *adev = drm_to_adev(dev);
2370 struct amdgpu_fpriv *fpriv = filp->driver_priv;
2371 int r;
2372
2373 switch (args->in.op) {
2374 case AMDGPU_VM_OP_RESERVE_VMID:
2375 /* We only have requirement to reserve vmid from gfxhub */
2376 r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm,
2377 AMDGPU_GFXHUB_0);
2378 if (r)
2379 return r;
2380 break;
2381 case AMDGPU_VM_OP_UNRESERVE_VMID:
2382 amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
2383 break;
2384 default:
2385 return -EINVAL;
2386 }
2387
2388 return 0;
2389}
2390
2391/**
2392 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
2393 *
2394 * @adev: drm device pointer
2395 * @pasid: PASID identifier for VM
2396 * @task_info: task_info to fill.
2397 */
2398void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid,
2399 struct amdgpu_task_info *task_info)
2400{
2401 struct amdgpu_vm *vm;
2402 unsigned long flags;
2403
2404 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
2405
2406 vm = xa_load(&adev->vm_manager.pasids, pasid);
2407 if (vm)
2408 *task_info = vm->task_info;
2409
2410 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
2411}
2412
2413/**
2414 * amdgpu_vm_set_task_info - Sets VMs task info.
2415 *
2416 * @vm: vm for which to set the info
2417 */
2418void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
2419{
2420 if (vm->task_info.pid)
2421 return;
2422
2423 vm->task_info.pid = current->pid;
2424 get_task_comm(vm->task_info.task_name, current);
2425
2426 if (current->group_leader->mm != current->mm)
2427 return;
2428
2429 vm->task_info.tgid = current->group_leader->pid;
2430 get_task_comm(vm->task_info.process_name, current->group_leader);
2431}
2432
2433/**
2434 * amdgpu_vm_handle_fault - graceful handling of VM faults.
2435 * @adev: amdgpu device pointer
2436 * @pasid: PASID of the VM
2437 * @addr: Address of the fault
2438 * @write_fault: true is write fault, false is read fault
2439 *
2440 * Try to gracefully handle a VM fault. Return true if the fault was handled and
2441 * shouldn't be reported any more.
2442 */
2443bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
2444 uint64_t addr, bool write_fault)
2445{
2446 bool is_compute_context = false;
2447 struct amdgpu_bo *root;
2448 unsigned long irqflags;
2449 uint64_t value, flags;
2450 struct amdgpu_vm *vm;
2451 int r;
2452
2453 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2454 vm = xa_load(&adev->vm_manager.pasids, pasid);
2455 if (vm) {
2456 root = amdgpu_bo_ref(vm->root.bo);
2457 is_compute_context = vm->is_compute_context;
2458 } else {
2459 root = NULL;
2460 }
2461 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2462
2463 if (!root)
2464 return false;
2465
2466 addr /= AMDGPU_GPU_PAGE_SIZE;
2467
2468 if (is_compute_context &&
2469 !svm_range_restore_pages(adev, pasid, addr, write_fault)) {
2470 amdgpu_bo_unref(&root);
2471 return true;
2472 }
2473
2474 r = amdgpu_bo_reserve(root, true);
2475 if (r)
2476 goto error_unref;
2477
2478 /* Double check that the VM still exists */
2479 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2480 vm = xa_load(&adev->vm_manager.pasids, pasid);
2481 if (vm && vm->root.bo != root)
2482 vm = NULL;
2483 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2484 if (!vm)
2485 goto error_unlock;
2486
2487 flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
2488 AMDGPU_PTE_SYSTEM;
2489
2490 if (is_compute_context) {
2491 /* Intentionally setting invalid PTE flag
2492 * combination to force a no-retry-fault
2493 */
2494 flags = AMDGPU_PTE_SNOOPED | AMDGPU_PTE_PRT;
2495 value = 0;
2496 } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
2497 /* Redirect the access to the dummy page */
2498 value = adev->dummy_page_addr;
2499 flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
2500 AMDGPU_PTE_WRITEABLE;
2501
2502 } else {
2503 /* Let the hw retry silently on the PTE */
2504 value = 0;
2505 }
2506
2507 r = dma_resv_reserve_fences(root->tbo.base.resv, 1);
2508 if (r) {
2509 pr_debug("failed %d to reserve fence slot\n", r);
2510 goto error_unlock;
2511 }
2512
2513 r = amdgpu_vm_update_range(adev, vm, true, false, false, NULL, addr,
2514 addr, flags, value, 0, NULL, NULL, NULL);
2515 if (r)
2516 goto error_unlock;
2517
2518 r = amdgpu_vm_update_pdes(adev, vm, true);
2519
2520error_unlock:
2521 amdgpu_bo_unreserve(root);
2522 if (r < 0)
2523 DRM_ERROR("Can't handle page fault (%d)\n", r);
2524
2525error_unref:
2526 amdgpu_bo_unref(&root);
2527
2528 return false;
2529}
2530
2531#if defined(CONFIG_DEBUG_FS)
2532/**
2533 * amdgpu_debugfs_vm_bo_info - print BO info for the VM
2534 *
2535 * @vm: Requested VM for printing BO info
2536 * @m: debugfs file
2537 *
2538 * Print BO information in debugfs file for the VM
2539 */
2540void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m)
2541{
2542 struct amdgpu_bo_va *bo_va, *tmp;
2543 u64 total_idle = 0;
2544 u64 total_evicted = 0;
2545 u64 total_relocated = 0;
2546 u64 total_moved = 0;
2547 u64 total_invalidated = 0;
2548 u64 total_done = 0;
2549 unsigned int total_idle_objs = 0;
2550 unsigned int total_evicted_objs = 0;
2551 unsigned int total_relocated_objs = 0;
2552 unsigned int total_moved_objs = 0;
2553 unsigned int total_invalidated_objs = 0;
2554 unsigned int total_done_objs = 0;
2555 unsigned int id = 0;
2556
2557 spin_lock(&vm->status_lock);
2558 seq_puts(m, "\tIdle BOs:\n");
2559 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
2560 if (!bo_va->base.bo)
2561 continue;
2562 total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2563 }
2564 total_idle_objs = id;
2565 id = 0;
2566
2567 seq_puts(m, "\tEvicted BOs:\n");
2568 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
2569 if (!bo_va->base.bo)
2570 continue;
2571 total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2572 }
2573 total_evicted_objs = id;
2574 id = 0;
2575
2576 seq_puts(m, "\tRelocated BOs:\n");
2577 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
2578 if (!bo_va->base.bo)
2579 continue;
2580 total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2581 }
2582 total_relocated_objs = id;
2583 id = 0;
2584
2585 seq_puts(m, "\tMoved BOs:\n");
2586 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2587 if (!bo_va->base.bo)
2588 continue;
2589 total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2590 }
2591 total_moved_objs = id;
2592 id = 0;
2593
2594 seq_puts(m, "\tInvalidated BOs:\n");
2595 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
2596 if (!bo_va->base.bo)
2597 continue;
2598 total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2599 }
2600 total_invalidated_objs = id;
2601 id = 0;
2602
2603 seq_puts(m, "\tDone BOs:\n");
2604 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
2605 if (!bo_va->base.bo)
2606 continue;
2607 total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2608 }
2609 spin_unlock(&vm->status_lock);
2610 total_done_objs = id;
2611
2612 seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle,
2613 total_idle_objs);
2614 seq_printf(m, "\tTotal evicted size: %12lld\tobjs:\t%d\n", total_evicted,
2615 total_evicted_objs);
2616 seq_printf(m, "\tTotal relocated size: %12lld\tobjs:\t%d\n", total_relocated,
2617 total_relocated_objs);
2618 seq_printf(m, "\tTotal moved size: %12lld\tobjs:\t%d\n", total_moved,
2619 total_moved_objs);
2620 seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated,
2621 total_invalidated_objs);
2622 seq_printf(m, "\tTotal done size: %12lld\tobjs:\t%d\n", total_done,
2623 total_done_objs);
2624}
2625#endif