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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/plat-pxa/gpio.c
4 *
5 * Generic PXA GPIO handling
6 *
7 * Author: Nicolas Pitre
8 * Created: Jun 15, 2001
9 * Copyright: MontaVista Software Inc.
10 */
11#include <linux/module.h>
12#include <linux/clk.h>
13#include <linux/err.h>
14#include <linux/gpio/driver.h>
15#include <linux/gpio-pxa.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/irqdomain.h>
20#include <linux/irqchip/chained_irq.h>
21#include <linux/io.h>
22#include <linux/of.h>
23#include <linux/pinctrl/consumer.h>
24#include <linux/platform_device.h>
25#include <linux/syscore_ops.h>
26#include <linux/slab.h>
27
28/*
29 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
30 * one set of registers. The register offsets are organized below:
31 *
32 * GPLR GPDR GPSR GPCR GRER GFER GEDR
33 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
34 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
35 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
36 *
37 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
38 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
39 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
40 *
41 * BANK 6 - 0x0200 0x020C 0x0218 0x0224 0x0230 0x023C 0x0248
42 *
43 * NOTE:
44 * BANK 3 is only available on PXA27x and later processors.
45 * BANK 4 and 5 are only available on PXA935, PXA1928
46 * BANK 6 is only available on PXA1928
47 */
48
49#define GPLR_OFFSET 0x00
50#define GPDR_OFFSET 0x0C
51#define GPSR_OFFSET 0x18
52#define GPCR_OFFSET 0x24
53#define GRER_OFFSET 0x30
54#define GFER_OFFSET 0x3C
55#define GEDR_OFFSET 0x48
56#define GAFR_OFFSET 0x54
57#define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
58
59#define BANK_OFF(n) (((n) / 3) << 8) + (((n) % 3) << 2)
60
61int pxa_last_gpio;
62static int irq_base;
63
64struct pxa_gpio_bank {
65 void __iomem *regbase;
66 unsigned long irq_mask;
67 unsigned long irq_edge_rise;
68 unsigned long irq_edge_fall;
69
70#ifdef CONFIG_PM
71 unsigned long saved_gplr;
72 unsigned long saved_gpdr;
73 unsigned long saved_grer;
74 unsigned long saved_gfer;
75#endif
76};
77
78struct pxa_gpio_chip {
79 struct device *dev;
80 struct gpio_chip chip;
81 struct pxa_gpio_bank *banks;
82 struct irq_domain *irqdomain;
83
84 int irq0;
85 int irq1;
86 int (*set_wake)(unsigned int gpio, unsigned int on);
87};
88
89enum pxa_gpio_type {
90 PXA25X_GPIO = 0,
91 PXA26X_GPIO,
92 PXA27X_GPIO,
93 PXA3XX_GPIO,
94 PXA93X_GPIO,
95 MMP_GPIO = 0x10,
96 MMP2_GPIO,
97 PXA1928_GPIO,
98};
99
100struct pxa_gpio_id {
101 enum pxa_gpio_type type;
102 int gpio_nums;
103};
104
105static DEFINE_SPINLOCK(gpio_lock);
106static struct pxa_gpio_chip *pxa_gpio_chip;
107static enum pxa_gpio_type gpio_type;
108
109static struct pxa_gpio_id pxa25x_id = {
110 .type = PXA25X_GPIO,
111 .gpio_nums = 85,
112};
113
114static struct pxa_gpio_id pxa26x_id = {
115 .type = PXA26X_GPIO,
116 .gpio_nums = 90,
117};
118
119static struct pxa_gpio_id pxa27x_id = {
120 .type = PXA27X_GPIO,
121 .gpio_nums = 121,
122};
123
124static struct pxa_gpio_id pxa3xx_id = {
125 .type = PXA3XX_GPIO,
126 .gpio_nums = 128,
127};
128
129static struct pxa_gpio_id pxa93x_id = {
130 .type = PXA93X_GPIO,
131 .gpio_nums = 192,
132};
133
134static struct pxa_gpio_id mmp_id = {
135 .type = MMP_GPIO,
136 .gpio_nums = 128,
137};
138
139static struct pxa_gpio_id mmp2_id = {
140 .type = MMP2_GPIO,
141 .gpio_nums = 192,
142};
143
144static struct pxa_gpio_id pxa1928_id = {
145 .type = PXA1928_GPIO,
146 .gpio_nums = 224,
147};
148
149#define for_each_gpio_bank(i, b, pc) \
150 for (i = 0, b = pc->banks; i <= pxa_last_gpio; i += 32, b++)
151
152static inline struct pxa_gpio_chip *chip_to_pxachip(struct gpio_chip *c)
153{
154 struct pxa_gpio_chip *pxa_chip = gpiochip_get_data(c);
155
156 return pxa_chip;
157}
158
159static inline void __iomem *gpio_bank_base(struct gpio_chip *c, int gpio)
160{
161 struct pxa_gpio_chip *p = gpiochip_get_data(c);
162 struct pxa_gpio_bank *bank = p->banks + (gpio / 32);
163
164 return bank->regbase;
165}
166
167static inline struct pxa_gpio_bank *gpio_to_pxabank(struct gpio_chip *c,
168 unsigned gpio)
169{
170 return chip_to_pxachip(c)->banks + gpio / 32;
171}
172
173static inline int gpio_is_mmp_type(int type)
174{
175 return (type & MMP_GPIO) != 0;
176}
177
178/* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
179 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
180 */
181static inline int __gpio_is_inverted(int gpio)
182{
183 if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
184 return 1;
185 return 0;
186}
187
188/*
189 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
190 * function of a GPIO, and GPDRx cannot be altered once configured. It
191 * is attributed as "occupied" here (I know this terminology isn't
192 * accurate, you are welcome to propose a better one :-)
193 */
194static inline int __gpio_is_occupied(struct pxa_gpio_chip *pchip, unsigned gpio)
195{
196 void __iomem *base;
197 unsigned long gafr = 0, gpdr = 0;
198 int ret, af = 0, dir = 0;
199
200 base = gpio_bank_base(&pchip->chip, gpio);
201 gpdr = readl_relaxed(base + GPDR_OFFSET);
202
203 switch (gpio_type) {
204 case PXA25X_GPIO:
205 case PXA26X_GPIO:
206 case PXA27X_GPIO:
207 gafr = readl_relaxed(base + GAFR_OFFSET);
208 af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
209 dir = gpdr & GPIO_bit(gpio);
210
211 if (__gpio_is_inverted(gpio))
212 ret = (af != 1) || (dir == 0);
213 else
214 ret = (af != 0) || (dir != 0);
215 break;
216 default:
217 ret = gpdr & GPIO_bit(gpio);
218 break;
219 }
220 return ret;
221}
222
223int pxa_irq_to_gpio(int irq)
224{
225 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
226 int irq_gpio0;
227
228 irq_gpio0 = irq_find_mapping(pchip->irqdomain, 0);
229 if (irq_gpio0 > 0)
230 return irq - irq_gpio0;
231
232 return irq_gpio0;
233}
234
235static bool pxa_gpio_has_pinctrl(void)
236{
237 switch (gpio_type) {
238 case PXA3XX_GPIO:
239 case MMP2_GPIO:
240 case MMP_GPIO:
241 return false;
242
243 default:
244 return true;
245 }
246}
247
248static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
249{
250 struct pxa_gpio_chip *pchip = chip_to_pxachip(chip);
251
252 return irq_find_mapping(pchip->irqdomain, offset);
253}
254
255static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
256{
257 void __iomem *base = gpio_bank_base(chip, offset);
258 uint32_t value, mask = GPIO_bit(offset);
259 unsigned long flags;
260 int ret;
261
262 if (pxa_gpio_has_pinctrl()) {
263 ret = pinctrl_gpio_direction_input(chip, offset);
264 if (ret)
265 return ret;
266 }
267
268 spin_lock_irqsave(&gpio_lock, flags);
269
270 value = readl_relaxed(base + GPDR_OFFSET);
271 if (__gpio_is_inverted(chip->base + offset))
272 value |= mask;
273 else
274 value &= ~mask;
275 writel_relaxed(value, base + GPDR_OFFSET);
276
277 spin_unlock_irqrestore(&gpio_lock, flags);
278 return 0;
279}
280
281static int pxa_gpio_direction_output(struct gpio_chip *chip,
282 unsigned offset, int value)
283{
284 void __iomem *base = gpio_bank_base(chip, offset);
285 uint32_t tmp, mask = GPIO_bit(offset);
286 unsigned long flags;
287 int ret;
288
289 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
290
291 if (pxa_gpio_has_pinctrl()) {
292 ret = pinctrl_gpio_direction_output(chip, offset);
293 if (ret)
294 return ret;
295 }
296
297 spin_lock_irqsave(&gpio_lock, flags);
298
299 tmp = readl_relaxed(base + GPDR_OFFSET);
300 if (__gpio_is_inverted(chip->base + offset))
301 tmp &= ~mask;
302 else
303 tmp |= mask;
304 writel_relaxed(tmp, base + GPDR_OFFSET);
305
306 spin_unlock_irqrestore(&gpio_lock, flags);
307 return 0;
308}
309
310static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
311{
312 void __iomem *base = gpio_bank_base(chip, offset);
313 u32 gplr = readl_relaxed(base + GPLR_OFFSET);
314
315 return !!(gplr & GPIO_bit(offset));
316}
317
318static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
319{
320 void __iomem *base = gpio_bank_base(chip, offset);
321
322 writel_relaxed(GPIO_bit(offset),
323 base + (value ? GPSR_OFFSET : GPCR_OFFSET));
324}
325
326#ifdef CONFIG_OF_GPIO
327static int pxa_gpio_of_xlate(struct gpio_chip *gc,
328 const struct of_phandle_args *gpiospec,
329 u32 *flags)
330{
331 if (gpiospec->args[0] > pxa_last_gpio)
332 return -EINVAL;
333
334 if (flags)
335 *flags = gpiospec->args[1];
336
337 return gpiospec->args[0];
338}
339#endif
340
341static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio, void __iomem *regbase)
342{
343 int i, gpio, nbanks = DIV_ROUND_UP(ngpio, 32);
344 struct pxa_gpio_bank *bank;
345
346 pchip->banks = devm_kcalloc(pchip->dev, nbanks, sizeof(*pchip->banks),
347 GFP_KERNEL);
348 if (!pchip->banks)
349 return -ENOMEM;
350
351 pchip->chip.parent = pchip->dev;
352 pchip->chip.label = "gpio-pxa";
353 pchip->chip.direction_input = pxa_gpio_direction_input;
354 pchip->chip.direction_output = pxa_gpio_direction_output;
355 pchip->chip.get = pxa_gpio_get;
356 pchip->chip.set = pxa_gpio_set;
357 pchip->chip.to_irq = pxa_gpio_to_irq;
358 pchip->chip.ngpio = ngpio;
359 pchip->chip.request = gpiochip_generic_request;
360 pchip->chip.free = gpiochip_generic_free;
361
362#ifdef CONFIG_OF_GPIO
363 pchip->chip.of_xlate = pxa_gpio_of_xlate;
364 pchip->chip.of_gpio_n_cells = 2;
365#endif
366
367 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
368 bank = pchip->banks + i;
369 bank->regbase = regbase + BANK_OFF(i);
370 }
371
372 return gpiochip_add_data(&pchip->chip, pchip);
373}
374
375/* Update only those GRERx and GFERx edge detection register bits if those
376 * bits are set in c->irq_mask
377 */
378static inline void update_edge_detect(struct pxa_gpio_bank *c)
379{
380 uint32_t grer, gfer;
381
382 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
383 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
384 grer |= c->irq_edge_rise & c->irq_mask;
385 gfer |= c->irq_edge_fall & c->irq_mask;
386 writel_relaxed(grer, c->regbase + GRER_OFFSET);
387 writel_relaxed(gfer, c->regbase + GFER_OFFSET);
388}
389
390static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
391{
392 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
393 unsigned int gpio = irqd_to_hwirq(d);
394 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
395 unsigned long gpdr, mask = GPIO_bit(gpio);
396
397 if (type == IRQ_TYPE_PROBE) {
398 /* Don't mess with enabled GPIOs using preconfigured edges or
399 * GPIOs set to alternate function or to output during probe
400 */
401 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
402 return 0;
403
404 if (__gpio_is_occupied(pchip, gpio))
405 return 0;
406
407 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
408 }
409
410 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
411
412 if (__gpio_is_inverted(gpio))
413 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET);
414 else
415 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
416
417 if (type & IRQ_TYPE_EDGE_RISING)
418 c->irq_edge_rise |= mask;
419 else
420 c->irq_edge_rise &= ~mask;
421
422 if (type & IRQ_TYPE_EDGE_FALLING)
423 c->irq_edge_fall |= mask;
424 else
425 c->irq_edge_fall &= ~mask;
426
427 update_edge_detect(c);
428
429 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
430 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
431 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
432 return 0;
433}
434
435static irqreturn_t pxa_gpio_demux_handler(int in_irq, void *d)
436{
437 int loop, gpio, n, handled = 0;
438 unsigned long gedr;
439 struct pxa_gpio_chip *pchip = d;
440 struct pxa_gpio_bank *c;
441
442 do {
443 loop = 0;
444 for_each_gpio_bank(gpio, c, pchip) {
445 gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
446 gedr = gedr & c->irq_mask;
447 writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
448
449 for_each_set_bit(n, &gedr, BITS_PER_LONG) {
450 loop = 1;
451
452 generic_handle_domain_irq(pchip->irqdomain,
453 gpio + n);
454 }
455 }
456 handled += loop;
457 } while (loop);
458
459 return handled ? IRQ_HANDLED : IRQ_NONE;
460}
461
462static irqreturn_t pxa_gpio_direct_handler(int in_irq, void *d)
463{
464 struct pxa_gpio_chip *pchip = d;
465
466 if (in_irq == pchip->irq0) {
467 generic_handle_domain_irq(pchip->irqdomain, 0);
468 } else if (in_irq == pchip->irq1) {
469 generic_handle_domain_irq(pchip->irqdomain, 1);
470 } else {
471 pr_err("%s() unknown irq %d\n", __func__, in_irq);
472 return IRQ_NONE;
473 }
474 return IRQ_HANDLED;
475}
476
477static void pxa_ack_muxed_gpio(struct irq_data *d)
478{
479 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
480 unsigned int gpio = irqd_to_hwirq(d);
481 void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
482
483 writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET);
484}
485
486static void pxa_mask_muxed_gpio(struct irq_data *d)
487{
488 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
489 unsigned int gpio = irqd_to_hwirq(d);
490 struct pxa_gpio_bank *b = gpio_to_pxabank(&pchip->chip, gpio);
491 void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
492 uint32_t grer, gfer;
493
494 b->irq_mask &= ~GPIO_bit(gpio);
495
496 grer = readl_relaxed(base + GRER_OFFSET) & ~GPIO_bit(gpio);
497 gfer = readl_relaxed(base + GFER_OFFSET) & ~GPIO_bit(gpio);
498 writel_relaxed(grer, base + GRER_OFFSET);
499 writel_relaxed(gfer, base + GFER_OFFSET);
500}
501
502static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
503{
504 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
505 unsigned int gpio = irqd_to_hwirq(d);
506
507 if (pchip->set_wake)
508 return pchip->set_wake(gpio, on);
509 else
510 return 0;
511}
512
513static void pxa_unmask_muxed_gpio(struct irq_data *d)
514{
515 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
516 unsigned int gpio = irqd_to_hwirq(d);
517 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
518
519 c->irq_mask |= GPIO_bit(gpio);
520 update_edge_detect(c);
521}
522
523static struct irq_chip pxa_muxed_gpio_chip = {
524 .name = "GPIO",
525 .irq_ack = pxa_ack_muxed_gpio,
526 .irq_mask = pxa_mask_muxed_gpio,
527 .irq_unmask = pxa_unmask_muxed_gpio,
528 .irq_set_type = pxa_gpio_irq_type,
529 .irq_set_wake = pxa_gpio_set_wake,
530};
531
532static int pxa_gpio_nums(struct platform_device *pdev)
533{
534 const struct platform_device_id *id = platform_get_device_id(pdev);
535 struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data;
536 int count = 0;
537
538 switch (pxa_id->type) {
539 case PXA25X_GPIO:
540 case PXA26X_GPIO:
541 case PXA27X_GPIO:
542 case PXA3XX_GPIO:
543 case PXA93X_GPIO:
544 case MMP_GPIO:
545 case MMP2_GPIO:
546 case PXA1928_GPIO:
547 gpio_type = pxa_id->type;
548 count = pxa_id->gpio_nums - 1;
549 break;
550 default:
551 count = -EINVAL;
552 break;
553 }
554 return count;
555}
556
557static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
558 irq_hw_number_t hw)
559{
560 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
561 handle_edge_irq);
562 irq_set_chip_data(irq, d->host_data);
563 irq_set_noprobe(irq);
564 return 0;
565}
566
567static const struct irq_domain_ops pxa_irq_domain_ops = {
568 .map = pxa_irq_domain_map,
569 .xlate = irq_domain_xlate_twocell,
570};
571
572#ifdef CONFIG_OF
573static const struct of_device_id pxa_gpio_dt_ids[] = {
574 { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, },
575 { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, },
576 { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, },
577 { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, },
578 { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, },
579 { .compatible = "marvell,mmp-gpio", .data = &mmp_id, },
580 { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, },
581 { .compatible = "marvell,pxa1928-gpio", .data = &pxa1928_id, },
582 {}
583};
584
585static int pxa_gpio_probe_dt(struct platform_device *pdev,
586 struct pxa_gpio_chip *pchip)
587{
588 int nr_gpios;
589 const struct pxa_gpio_id *gpio_id;
590
591 gpio_id = of_device_get_match_data(&pdev->dev);
592 gpio_type = gpio_id->type;
593
594 nr_gpios = gpio_id->gpio_nums;
595 pxa_last_gpio = nr_gpios - 1;
596
597 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, nr_gpios, 0);
598 if (irq_base < 0) {
599 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
600 return irq_base;
601 }
602 return irq_base;
603}
604#else
605#define pxa_gpio_probe_dt(pdev, pchip) (-1)
606#endif
607
608static int pxa_gpio_probe(struct platform_device *pdev)
609{
610 struct pxa_gpio_chip *pchip;
611 struct pxa_gpio_bank *c;
612 struct clk *clk;
613 struct pxa_gpio_platform_data *info;
614 void __iomem *gpio_reg_base;
615 int gpio, ret;
616 int irq0 = 0, irq1 = 0, irq_mux;
617
618 pchip = devm_kzalloc(&pdev->dev, sizeof(*pchip), GFP_KERNEL);
619 if (!pchip)
620 return -ENOMEM;
621 pchip->dev = &pdev->dev;
622
623 info = dev_get_platdata(&pdev->dev);
624 if (info) {
625 irq_base = info->irq_base;
626 if (irq_base <= 0)
627 return -EINVAL;
628 pxa_last_gpio = pxa_gpio_nums(pdev);
629 pchip->set_wake = info->gpio_set_wake;
630 } else {
631 irq_base = pxa_gpio_probe_dt(pdev, pchip);
632 if (irq_base < 0)
633 return -EINVAL;
634 }
635
636 if (!pxa_last_gpio)
637 return -EINVAL;
638
639 pchip->irqdomain = irq_domain_add_legacy(pdev->dev.of_node,
640 pxa_last_gpio + 1, irq_base,
641 0, &pxa_irq_domain_ops, pchip);
642 if (!pchip->irqdomain)
643 return -ENOMEM;
644
645 irq0 = platform_get_irq_byname_optional(pdev, "gpio0");
646 irq1 = platform_get_irq_byname_optional(pdev, "gpio1");
647 irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
648 if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
649 || (irq_mux <= 0))
650 return -EINVAL;
651
652 pchip->irq0 = irq0;
653 pchip->irq1 = irq1;
654
655 gpio_reg_base = devm_platform_ioremap_resource(pdev, 0);
656 if (IS_ERR(gpio_reg_base))
657 return PTR_ERR(gpio_reg_base);
658
659 clk = devm_clk_get_enabled(&pdev->dev, NULL);
660 if (IS_ERR(clk)) {
661 dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
662 PTR_ERR(clk));
663 return PTR_ERR(clk);
664 }
665
666 /* Initialize GPIO chips */
667 ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, gpio_reg_base);
668 if (ret)
669 return ret;
670
671 /* clear all GPIO edge detects */
672 for_each_gpio_bank(gpio, c, pchip) {
673 writel_relaxed(0, c->regbase + GFER_OFFSET);
674 writel_relaxed(0, c->regbase + GRER_OFFSET);
675 writel_relaxed(~0, c->regbase + GEDR_OFFSET);
676 /* unmask GPIO edge detect for AP side */
677 if (gpio_is_mmp_type(gpio_type))
678 writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
679 }
680
681 if (irq0 > 0) {
682 ret = devm_request_irq(&pdev->dev,
683 irq0, pxa_gpio_direct_handler, 0,
684 "gpio-0", pchip);
685 if (ret)
686 dev_err(&pdev->dev, "request of gpio0 irq failed: %d\n",
687 ret);
688 }
689 if (irq1 > 0) {
690 ret = devm_request_irq(&pdev->dev,
691 irq1, pxa_gpio_direct_handler, 0,
692 "gpio-1", pchip);
693 if (ret)
694 dev_err(&pdev->dev, "request of gpio1 irq failed: %d\n",
695 ret);
696 }
697 ret = devm_request_irq(&pdev->dev,
698 irq_mux, pxa_gpio_demux_handler, 0,
699 "gpio-mux", pchip);
700 if (ret)
701 dev_err(&pdev->dev, "request of gpio-mux irq failed: %d\n",
702 ret);
703
704 pxa_gpio_chip = pchip;
705
706 return 0;
707}
708
709static const struct platform_device_id gpio_id_table[] = {
710 { "pxa25x-gpio", (unsigned long)&pxa25x_id },
711 { "pxa26x-gpio", (unsigned long)&pxa26x_id },
712 { "pxa27x-gpio", (unsigned long)&pxa27x_id },
713 { "pxa3xx-gpio", (unsigned long)&pxa3xx_id },
714 { "pxa93x-gpio", (unsigned long)&pxa93x_id },
715 { "mmp-gpio", (unsigned long)&mmp_id },
716 { "mmp2-gpio", (unsigned long)&mmp2_id },
717 { "pxa1928-gpio", (unsigned long)&pxa1928_id },
718 { },
719};
720
721static struct platform_driver pxa_gpio_driver = {
722 .probe = pxa_gpio_probe,
723 .driver = {
724 .name = "pxa-gpio",
725 .of_match_table = of_match_ptr(pxa_gpio_dt_ids),
726 },
727 .id_table = gpio_id_table,
728};
729
730static int __init pxa_gpio_legacy_init(void)
731{
732 if (of_have_populated_dt())
733 return 0;
734
735 return platform_driver_register(&pxa_gpio_driver);
736}
737postcore_initcall(pxa_gpio_legacy_init);
738
739static int __init pxa_gpio_dt_init(void)
740{
741 if (of_have_populated_dt())
742 return platform_driver_register(&pxa_gpio_driver);
743
744 return 0;
745}
746device_initcall(pxa_gpio_dt_init);
747
748#ifdef CONFIG_PM
749static int pxa_gpio_suspend(void)
750{
751 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
752 struct pxa_gpio_bank *c;
753 int gpio;
754
755 if (!pchip)
756 return 0;
757
758 for_each_gpio_bank(gpio, c, pchip) {
759 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
760 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
761 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
762 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
763
764 /* Clear GPIO transition detect bits */
765 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
766 }
767 return 0;
768}
769
770static void pxa_gpio_resume(void)
771{
772 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
773 struct pxa_gpio_bank *c;
774 int gpio;
775
776 if (!pchip)
777 return;
778
779 for_each_gpio_bank(gpio, c, pchip) {
780 /* restore level with set/clear */
781 writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET);
782 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
783
784 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
785 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
786 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
787 }
788}
789#else
790#define pxa_gpio_suspend NULL
791#define pxa_gpio_resume NULL
792#endif
793
794static struct syscore_ops pxa_gpio_syscore_ops = {
795 .suspend = pxa_gpio_suspend,
796 .resume = pxa_gpio_resume,
797};
798
799static int __init pxa_gpio_sysinit(void)
800{
801 register_syscore_ops(&pxa_gpio_syscore_ops);
802 return 0;
803}
804postcore_initcall(pxa_gpio_sysinit);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/plat-pxa/gpio.c
4 *
5 * Generic PXA GPIO handling
6 *
7 * Author: Nicolas Pitre
8 * Created: Jun 15, 2001
9 * Copyright: MontaVista Software Inc.
10 */
11#include <linux/module.h>
12#include <linux/clk.h>
13#include <linux/err.h>
14#include <linux/gpio/driver.h>
15#include <linux/gpio-pxa.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/irqdomain.h>
20#include <linux/irqchip/chained_irq.h>
21#include <linux/io.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/pinctrl/consumer.h>
25#include <linux/platform_device.h>
26#include <linux/syscore_ops.h>
27#include <linux/slab.h>
28
29/*
30 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
31 * one set of registers. The register offsets are organized below:
32 *
33 * GPLR GPDR GPSR GPCR GRER GFER GEDR
34 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
35 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
36 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
37 *
38 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
39 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
40 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
41 *
42 * BANK 6 - 0x0200 0x020C 0x0218 0x0224 0x0230 0x023C 0x0248
43 *
44 * NOTE:
45 * BANK 3 is only available on PXA27x and later processors.
46 * BANK 4 and 5 are only available on PXA935, PXA1928
47 * BANK 6 is only available on PXA1928
48 */
49
50#define GPLR_OFFSET 0x00
51#define GPDR_OFFSET 0x0C
52#define GPSR_OFFSET 0x18
53#define GPCR_OFFSET 0x24
54#define GRER_OFFSET 0x30
55#define GFER_OFFSET 0x3C
56#define GEDR_OFFSET 0x48
57#define GAFR_OFFSET 0x54
58#define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
59
60#define BANK_OFF(n) (((n) / 3) << 8) + (((n) % 3) << 2)
61
62int pxa_last_gpio;
63static int irq_base;
64
65struct pxa_gpio_bank {
66 void __iomem *regbase;
67 unsigned long irq_mask;
68 unsigned long irq_edge_rise;
69 unsigned long irq_edge_fall;
70
71#ifdef CONFIG_PM
72 unsigned long saved_gplr;
73 unsigned long saved_gpdr;
74 unsigned long saved_grer;
75 unsigned long saved_gfer;
76#endif
77};
78
79struct pxa_gpio_chip {
80 struct device *dev;
81 struct gpio_chip chip;
82 struct pxa_gpio_bank *banks;
83 struct irq_domain *irqdomain;
84
85 int irq0;
86 int irq1;
87 int (*set_wake)(unsigned int gpio, unsigned int on);
88};
89
90enum pxa_gpio_type {
91 PXA25X_GPIO = 0,
92 PXA26X_GPIO,
93 PXA27X_GPIO,
94 PXA3XX_GPIO,
95 PXA93X_GPIO,
96 MMP_GPIO = 0x10,
97 MMP2_GPIO,
98 PXA1928_GPIO,
99};
100
101struct pxa_gpio_id {
102 enum pxa_gpio_type type;
103 int gpio_nums;
104};
105
106static DEFINE_SPINLOCK(gpio_lock);
107static struct pxa_gpio_chip *pxa_gpio_chip;
108static enum pxa_gpio_type gpio_type;
109
110static struct pxa_gpio_id pxa25x_id = {
111 .type = PXA25X_GPIO,
112 .gpio_nums = 85,
113};
114
115static struct pxa_gpio_id pxa26x_id = {
116 .type = PXA26X_GPIO,
117 .gpio_nums = 90,
118};
119
120static struct pxa_gpio_id pxa27x_id = {
121 .type = PXA27X_GPIO,
122 .gpio_nums = 121,
123};
124
125static struct pxa_gpio_id pxa3xx_id = {
126 .type = PXA3XX_GPIO,
127 .gpio_nums = 128,
128};
129
130static struct pxa_gpio_id pxa93x_id = {
131 .type = PXA93X_GPIO,
132 .gpio_nums = 192,
133};
134
135static struct pxa_gpio_id mmp_id = {
136 .type = MMP_GPIO,
137 .gpio_nums = 128,
138};
139
140static struct pxa_gpio_id mmp2_id = {
141 .type = MMP2_GPIO,
142 .gpio_nums = 192,
143};
144
145static struct pxa_gpio_id pxa1928_id = {
146 .type = PXA1928_GPIO,
147 .gpio_nums = 224,
148};
149
150#define for_each_gpio_bank(i, b, pc) \
151 for (i = 0, b = pc->banks; i <= pxa_last_gpio; i += 32, b++)
152
153static inline struct pxa_gpio_chip *chip_to_pxachip(struct gpio_chip *c)
154{
155 struct pxa_gpio_chip *pxa_chip = gpiochip_get_data(c);
156
157 return pxa_chip;
158}
159
160static inline void __iomem *gpio_bank_base(struct gpio_chip *c, int gpio)
161{
162 struct pxa_gpio_chip *p = gpiochip_get_data(c);
163 struct pxa_gpio_bank *bank = p->banks + (gpio / 32);
164
165 return bank->regbase;
166}
167
168static inline struct pxa_gpio_bank *gpio_to_pxabank(struct gpio_chip *c,
169 unsigned gpio)
170{
171 return chip_to_pxachip(c)->banks + gpio / 32;
172}
173
174static inline int gpio_is_pxa_type(int type)
175{
176 return (type & MMP_GPIO) == 0;
177}
178
179static inline int gpio_is_mmp_type(int type)
180{
181 return (type & MMP_GPIO) != 0;
182}
183
184/* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
185 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
186 */
187static inline int __gpio_is_inverted(int gpio)
188{
189 if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
190 return 1;
191 return 0;
192}
193
194/*
195 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
196 * function of a GPIO, and GPDRx cannot be altered once configured. It
197 * is attributed as "occupied" here (I know this terminology isn't
198 * accurate, you are welcome to propose a better one :-)
199 */
200static inline int __gpio_is_occupied(struct pxa_gpio_chip *pchip, unsigned gpio)
201{
202 void __iomem *base;
203 unsigned long gafr = 0, gpdr = 0;
204 int ret, af = 0, dir = 0;
205
206 base = gpio_bank_base(&pchip->chip, gpio);
207 gpdr = readl_relaxed(base + GPDR_OFFSET);
208
209 switch (gpio_type) {
210 case PXA25X_GPIO:
211 case PXA26X_GPIO:
212 case PXA27X_GPIO:
213 gafr = readl_relaxed(base + GAFR_OFFSET);
214 af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
215 dir = gpdr & GPIO_bit(gpio);
216
217 if (__gpio_is_inverted(gpio))
218 ret = (af != 1) || (dir == 0);
219 else
220 ret = (af != 0) || (dir != 0);
221 break;
222 default:
223 ret = gpdr & GPIO_bit(gpio);
224 break;
225 }
226 return ret;
227}
228
229int pxa_irq_to_gpio(int irq)
230{
231 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
232 int irq_gpio0;
233
234 irq_gpio0 = irq_find_mapping(pchip->irqdomain, 0);
235 if (irq_gpio0 > 0)
236 return irq - irq_gpio0;
237
238 return irq_gpio0;
239}
240
241static bool pxa_gpio_has_pinctrl(void)
242{
243 switch (gpio_type) {
244 case PXA3XX_GPIO:
245 case MMP2_GPIO:
246 return false;
247
248 default:
249 return true;
250 }
251}
252
253static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
254{
255 struct pxa_gpio_chip *pchip = chip_to_pxachip(chip);
256
257 return irq_find_mapping(pchip->irqdomain, offset);
258}
259
260static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
261{
262 void __iomem *base = gpio_bank_base(chip, offset);
263 uint32_t value, mask = GPIO_bit(offset);
264 unsigned long flags;
265 int ret;
266
267 if (pxa_gpio_has_pinctrl()) {
268 ret = pinctrl_gpio_direction_input(chip->base + offset);
269 if (ret)
270 return ret;
271 }
272
273 spin_lock_irqsave(&gpio_lock, flags);
274
275 value = readl_relaxed(base + GPDR_OFFSET);
276 if (__gpio_is_inverted(chip->base + offset))
277 value |= mask;
278 else
279 value &= ~mask;
280 writel_relaxed(value, base + GPDR_OFFSET);
281
282 spin_unlock_irqrestore(&gpio_lock, flags);
283 return 0;
284}
285
286static int pxa_gpio_direction_output(struct gpio_chip *chip,
287 unsigned offset, int value)
288{
289 void __iomem *base = gpio_bank_base(chip, offset);
290 uint32_t tmp, mask = GPIO_bit(offset);
291 unsigned long flags;
292 int ret;
293
294 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
295
296 if (pxa_gpio_has_pinctrl()) {
297 ret = pinctrl_gpio_direction_output(chip->base + offset);
298 if (ret)
299 return ret;
300 }
301
302 spin_lock_irqsave(&gpio_lock, flags);
303
304 tmp = readl_relaxed(base + GPDR_OFFSET);
305 if (__gpio_is_inverted(chip->base + offset))
306 tmp &= ~mask;
307 else
308 tmp |= mask;
309 writel_relaxed(tmp, base + GPDR_OFFSET);
310
311 spin_unlock_irqrestore(&gpio_lock, flags);
312 return 0;
313}
314
315static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
316{
317 void __iomem *base = gpio_bank_base(chip, offset);
318 u32 gplr = readl_relaxed(base + GPLR_OFFSET);
319
320 return !!(gplr & GPIO_bit(offset));
321}
322
323static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
324{
325 void __iomem *base = gpio_bank_base(chip, offset);
326
327 writel_relaxed(GPIO_bit(offset),
328 base + (value ? GPSR_OFFSET : GPCR_OFFSET));
329}
330
331#ifdef CONFIG_OF_GPIO
332static int pxa_gpio_of_xlate(struct gpio_chip *gc,
333 const struct of_phandle_args *gpiospec,
334 u32 *flags)
335{
336 if (gpiospec->args[0] > pxa_last_gpio)
337 return -EINVAL;
338
339 if (flags)
340 *flags = gpiospec->args[1];
341
342 return gpiospec->args[0];
343}
344#endif
345
346static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio, void __iomem *regbase)
347{
348 int i, gpio, nbanks = DIV_ROUND_UP(ngpio, 32);
349 struct pxa_gpio_bank *bank;
350
351 pchip->banks = devm_kcalloc(pchip->dev, nbanks, sizeof(*pchip->banks),
352 GFP_KERNEL);
353 if (!pchip->banks)
354 return -ENOMEM;
355
356 pchip->chip.parent = pchip->dev;
357 pchip->chip.label = "gpio-pxa";
358 pchip->chip.direction_input = pxa_gpio_direction_input;
359 pchip->chip.direction_output = pxa_gpio_direction_output;
360 pchip->chip.get = pxa_gpio_get;
361 pchip->chip.set = pxa_gpio_set;
362 pchip->chip.to_irq = pxa_gpio_to_irq;
363 pchip->chip.ngpio = ngpio;
364 pchip->chip.request = gpiochip_generic_request;
365 pchip->chip.free = gpiochip_generic_free;
366
367#ifdef CONFIG_OF_GPIO
368 pchip->chip.of_xlate = pxa_gpio_of_xlate;
369 pchip->chip.of_gpio_n_cells = 2;
370#endif
371
372 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
373 bank = pchip->banks + i;
374 bank->regbase = regbase + BANK_OFF(i);
375 }
376
377 return gpiochip_add_data(&pchip->chip, pchip);
378}
379
380/* Update only those GRERx and GFERx edge detection register bits if those
381 * bits are set in c->irq_mask
382 */
383static inline void update_edge_detect(struct pxa_gpio_bank *c)
384{
385 uint32_t grer, gfer;
386
387 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
388 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
389 grer |= c->irq_edge_rise & c->irq_mask;
390 gfer |= c->irq_edge_fall & c->irq_mask;
391 writel_relaxed(grer, c->regbase + GRER_OFFSET);
392 writel_relaxed(gfer, c->regbase + GFER_OFFSET);
393}
394
395static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
396{
397 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
398 unsigned int gpio = irqd_to_hwirq(d);
399 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
400 unsigned long gpdr, mask = GPIO_bit(gpio);
401
402 if (type == IRQ_TYPE_PROBE) {
403 /* Don't mess with enabled GPIOs using preconfigured edges or
404 * GPIOs set to alternate function or to output during probe
405 */
406 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
407 return 0;
408
409 if (__gpio_is_occupied(pchip, gpio))
410 return 0;
411
412 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
413 }
414
415 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
416
417 if (__gpio_is_inverted(gpio))
418 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET);
419 else
420 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
421
422 if (type & IRQ_TYPE_EDGE_RISING)
423 c->irq_edge_rise |= mask;
424 else
425 c->irq_edge_rise &= ~mask;
426
427 if (type & IRQ_TYPE_EDGE_FALLING)
428 c->irq_edge_fall |= mask;
429 else
430 c->irq_edge_fall &= ~mask;
431
432 update_edge_detect(c);
433
434 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
435 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
436 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
437 return 0;
438}
439
440static irqreturn_t pxa_gpio_demux_handler(int in_irq, void *d)
441{
442 int loop, gpio, n, handled = 0;
443 unsigned long gedr;
444 struct pxa_gpio_chip *pchip = d;
445 struct pxa_gpio_bank *c;
446
447 do {
448 loop = 0;
449 for_each_gpio_bank(gpio, c, pchip) {
450 gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
451 gedr = gedr & c->irq_mask;
452 writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
453
454 for_each_set_bit(n, &gedr, BITS_PER_LONG) {
455 loop = 1;
456
457 generic_handle_domain_irq(pchip->irqdomain,
458 gpio + n);
459 }
460 }
461 handled += loop;
462 } while (loop);
463
464 return handled ? IRQ_HANDLED : IRQ_NONE;
465}
466
467static irqreturn_t pxa_gpio_direct_handler(int in_irq, void *d)
468{
469 struct pxa_gpio_chip *pchip = d;
470
471 if (in_irq == pchip->irq0) {
472 generic_handle_domain_irq(pchip->irqdomain, 0);
473 } else if (in_irq == pchip->irq1) {
474 generic_handle_domain_irq(pchip->irqdomain, 1);
475 } else {
476 pr_err("%s() unknown irq %d\n", __func__, in_irq);
477 return IRQ_NONE;
478 }
479 return IRQ_HANDLED;
480}
481
482static void pxa_ack_muxed_gpio(struct irq_data *d)
483{
484 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
485 unsigned int gpio = irqd_to_hwirq(d);
486 void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
487
488 writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET);
489}
490
491static void pxa_mask_muxed_gpio(struct irq_data *d)
492{
493 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
494 unsigned int gpio = irqd_to_hwirq(d);
495 struct pxa_gpio_bank *b = gpio_to_pxabank(&pchip->chip, gpio);
496 void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
497 uint32_t grer, gfer;
498
499 b->irq_mask &= ~GPIO_bit(gpio);
500
501 grer = readl_relaxed(base + GRER_OFFSET) & ~GPIO_bit(gpio);
502 gfer = readl_relaxed(base + GFER_OFFSET) & ~GPIO_bit(gpio);
503 writel_relaxed(grer, base + GRER_OFFSET);
504 writel_relaxed(gfer, base + GFER_OFFSET);
505}
506
507static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
508{
509 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
510 unsigned int gpio = irqd_to_hwirq(d);
511
512 if (pchip->set_wake)
513 return pchip->set_wake(gpio, on);
514 else
515 return 0;
516}
517
518static void pxa_unmask_muxed_gpio(struct irq_data *d)
519{
520 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
521 unsigned int gpio = irqd_to_hwirq(d);
522 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
523
524 c->irq_mask |= GPIO_bit(gpio);
525 update_edge_detect(c);
526}
527
528static struct irq_chip pxa_muxed_gpio_chip = {
529 .name = "GPIO",
530 .irq_ack = pxa_ack_muxed_gpio,
531 .irq_mask = pxa_mask_muxed_gpio,
532 .irq_unmask = pxa_unmask_muxed_gpio,
533 .irq_set_type = pxa_gpio_irq_type,
534 .irq_set_wake = pxa_gpio_set_wake,
535};
536
537static int pxa_gpio_nums(struct platform_device *pdev)
538{
539 const struct platform_device_id *id = platform_get_device_id(pdev);
540 struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data;
541 int count = 0;
542
543 switch (pxa_id->type) {
544 case PXA25X_GPIO:
545 case PXA26X_GPIO:
546 case PXA27X_GPIO:
547 case PXA3XX_GPIO:
548 case PXA93X_GPIO:
549 case MMP_GPIO:
550 case MMP2_GPIO:
551 case PXA1928_GPIO:
552 gpio_type = pxa_id->type;
553 count = pxa_id->gpio_nums - 1;
554 break;
555 default:
556 count = -EINVAL;
557 break;
558 }
559 return count;
560}
561
562static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
563 irq_hw_number_t hw)
564{
565 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
566 handle_edge_irq);
567 irq_set_chip_data(irq, d->host_data);
568 irq_set_noprobe(irq);
569 return 0;
570}
571
572static const struct irq_domain_ops pxa_irq_domain_ops = {
573 .map = pxa_irq_domain_map,
574 .xlate = irq_domain_xlate_twocell,
575};
576
577#ifdef CONFIG_OF
578static const struct of_device_id pxa_gpio_dt_ids[] = {
579 { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, },
580 { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, },
581 { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, },
582 { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, },
583 { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, },
584 { .compatible = "marvell,mmp-gpio", .data = &mmp_id, },
585 { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, },
586 { .compatible = "marvell,pxa1928-gpio", .data = &pxa1928_id, },
587 {}
588};
589
590static int pxa_gpio_probe_dt(struct platform_device *pdev,
591 struct pxa_gpio_chip *pchip)
592{
593 int nr_gpios;
594 const struct pxa_gpio_id *gpio_id;
595
596 gpio_id = of_device_get_match_data(&pdev->dev);
597 gpio_type = gpio_id->type;
598
599 nr_gpios = gpio_id->gpio_nums;
600 pxa_last_gpio = nr_gpios - 1;
601
602 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, nr_gpios, 0);
603 if (irq_base < 0) {
604 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
605 return irq_base;
606 }
607 return irq_base;
608}
609#else
610#define pxa_gpio_probe_dt(pdev, pchip) (-1)
611#endif
612
613static int pxa_gpio_probe(struct platform_device *pdev)
614{
615 struct pxa_gpio_chip *pchip;
616 struct pxa_gpio_bank *c;
617 struct clk *clk;
618 struct pxa_gpio_platform_data *info;
619 void __iomem *gpio_reg_base;
620 int gpio, ret;
621 int irq0 = 0, irq1 = 0, irq_mux;
622
623 pchip = devm_kzalloc(&pdev->dev, sizeof(*pchip), GFP_KERNEL);
624 if (!pchip)
625 return -ENOMEM;
626 pchip->dev = &pdev->dev;
627
628 info = dev_get_platdata(&pdev->dev);
629 if (info) {
630 irq_base = info->irq_base;
631 if (irq_base <= 0)
632 return -EINVAL;
633 pxa_last_gpio = pxa_gpio_nums(pdev);
634 pchip->set_wake = info->gpio_set_wake;
635 } else {
636 irq_base = pxa_gpio_probe_dt(pdev, pchip);
637 if (irq_base < 0)
638 return -EINVAL;
639 }
640
641 if (!pxa_last_gpio)
642 return -EINVAL;
643
644 pchip->irqdomain = irq_domain_add_legacy(pdev->dev.of_node,
645 pxa_last_gpio + 1, irq_base,
646 0, &pxa_irq_domain_ops, pchip);
647 if (!pchip->irqdomain)
648 return -ENOMEM;
649
650 irq0 = platform_get_irq_byname_optional(pdev, "gpio0");
651 irq1 = platform_get_irq_byname_optional(pdev, "gpio1");
652 irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
653 if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
654 || (irq_mux <= 0))
655 return -EINVAL;
656
657 pchip->irq0 = irq0;
658 pchip->irq1 = irq1;
659
660 gpio_reg_base = devm_platform_ioremap_resource(pdev, 0);
661 if (IS_ERR(gpio_reg_base))
662 return PTR_ERR(gpio_reg_base);
663
664 clk = devm_clk_get_enabled(&pdev->dev, NULL);
665 if (IS_ERR(clk)) {
666 dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
667 PTR_ERR(clk));
668 return PTR_ERR(clk);
669 }
670
671 /* Initialize GPIO chips */
672 ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, gpio_reg_base);
673 if (ret)
674 return ret;
675
676 /* clear all GPIO edge detects */
677 for_each_gpio_bank(gpio, c, pchip) {
678 writel_relaxed(0, c->regbase + GFER_OFFSET);
679 writel_relaxed(0, c->regbase + GRER_OFFSET);
680 writel_relaxed(~0, c->regbase + GEDR_OFFSET);
681 /* unmask GPIO edge detect for AP side */
682 if (gpio_is_mmp_type(gpio_type))
683 writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
684 }
685
686 if (irq0 > 0) {
687 ret = devm_request_irq(&pdev->dev,
688 irq0, pxa_gpio_direct_handler, 0,
689 "gpio-0", pchip);
690 if (ret)
691 dev_err(&pdev->dev, "request of gpio0 irq failed: %d\n",
692 ret);
693 }
694 if (irq1 > 0) {
695 ret = devm_request_irq(&pdev->dev,
696 irq1, pxa_gpio_direct_handler, 0,
697 "gpio-1", pchip);
698 if (ret)
699 dev_err(&pdev->dev, "request of gpio1 irq failed: %d\n",
700 ret);
701 }
702 ret = devm_request_irq(&pdev->dev,
703 irq_mux, pxa_gpio_demux_handler, 0,
704 "gpio-mux", pchip);
705 if (ret)
706 dev_err(&pdev->dev, "request of gpio-mux irq failed: %d\n",
707 ret);
708
709 pxa_gpio_chip = pchip;
710
711 return 0;
712}
713
714static const struct platform_device_id gpio_id_table[] = {
715 { "pxa25x-gpio", (unsigned long)&pxa25x_id },
716 { "pxa26x-gpio", (unsigned long)&pxa26x_id },
717 { "pxa27x-gpio", (unsigned long)&pxa27x_id },
718 { "pxa3xx-gpio", (unsigned long)&pxa3xx_id },
719 { "pxa93x-gpio", (unsigned long)&pxa93x_id },
720 { "mmp-gpio", (unsigned long)&mmp_id },
721 { "mmp2-gpio", (unsigned long)&mmp2_id },
722 { "pxa1928-gpio", (unsigned long)&pxa1928_id },
723 { },
724};
725
726static struct platform_driver pxa_gpio_driver = {
727 .probe = pxa_gpio_probe,
728 .driver = {
729 .name = "pxa-gpio",
730 .of_match_table = of_match_ptr(pxa_gpio_dt_ids),
731 },
732 .id_table = gpio_id_table,
733};
734
735static int __init pxa_gpio_legacy_init(void)
736{
737 if (of_have_populated_dt())
738 return 0;
739
740 return platform_driver_register(&pxa_gpio_driver);
741}
742postcore_initcall(pxa_gpio_legacy_init);
743
744static int __init pxa_gpio_dt_init(void)
745{
746 if (of_have_populated_dt())
747 return platform_driver_register(&pxa_gpio_driver);
748
749 return 0;
750}
751device_initcall(pxa_gpio_dt_init);
752
753#ifdef CONFIG_PM
754static int pxa_gpio_suspend(void)
755{
756 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
757 struct pxa_gpio_bank *c;
758 int gpio;
759
760 if (!pchip)
761 return 0;
762
763 for_each_gpio_bank(gpio, c, pchip) {
764 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
765 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
766 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
767 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
768
769 /* Clear GPIO transition detect bits */
770 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
771 }
772 return 0;
773}
774
775static void pxa_gpio_resume(void)
776{
777 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
778 struct pxa_gpio_bank *c;
779 int gpio;
780
781 if (!pchip)
782 return;
783
784 for_each_gpio_bank(gpio, c, pchip) {
785 /* restore level with set/clear */
786 writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET);
787 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
788
789 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
790 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
791 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
792 }
793}
794#else
795#define pxa_gpio_suspend NULL
796#define pxa_gpio_resume NULL
797#endif
798
799static struct syscore_ops pxa_gpio_syscore_ops = {
800 .suspend = pxa_gpio_suspend,
801 .resume = pxa_gpio_resume,
802};
803
804static int __init pxa_gpio_sysinit(void)
805{
806 register_syscore_ops(&pxa_gpio_syscore_ops);
807 return 0;
808}
809postcore_initcall(pxa_gpio_sysinit);