Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Support for OMAP DES and Triple DES HW acceleration.
4 *
5 * Copyright (c) 2013 Texas Instruments Incorporated
6 * Author: Joel Fernandes <joelf@ti.com>
7 */
8
9#define pr_fmt(fmt) "%s: " fmt, __func__
10
11#ifdef DEBUG
12#define prn(num) printk(#num "=%d\n", num)
13#define prx(num) printk(#num "=%x\n", num)
14#else
15#define prn(num) do { } while (0)
16#define prx(num) do { } while (0)
17#endif
18
19#include <crypto/engine.h>
20#include <crypto/internal/des.h>
21#include <crypto/internal/skcipher.h>
22#include <crypto/scatterwalk.h>
23#include <linux/dma-mapping.h>
24#include <linux/dmaengine.h>
25#include <linux/err.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/of.h>
32#include <linux/platform_device.h>
33#include <linux/pm_runtime.h>
34#include <linux/scatterlist.h>
35#include <linux/string.h>
36
37#include "omap-crypto.h"
38
39#define DST_MAXBURST 2
40
41#define DES_BLOCK_WORDS (DES_BLOCK_SIZE >> 2)
42
43#define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
44
45#define DES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \
46 ((x ^ 0x01) * 0x04))
47
48#define DES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04))
49
50#define DES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs)
51#define DES_REG_CTRL_CBC BIT(4)
52#define DES_REG_CTRL_TDES BIT(3)
53#define DES_REG_CTRL_DIRECTION BIT(2)
54#define DES_REG_CTRL_INPUT_READY BIT(1)
55#define DES_REG_CTRL_OUTPUT_READY BIT(0)
56
57#define DES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04))
58
59#define DES_REG_REV(dd) ((dd)->pdata->rev_ofs)
60
61#define DES_REG_MASK(dd) ((dd)->pdata->mask_ofs)
62
63#define DES_REG_LENGTH_N(x) (0x24 + ((x) * 0x04))
64
65#define DES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs)
66#define DES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs)
67#define DES_REG_IRQ_DATA_IN BIT(1)
68#define DES_REG_IRQ_DATA_OUT BIT(2)
69
70#define FLAGS_MODE_MASK 0x000f
71#define FLAGS_ENCRYPT BIT(0)
72#define FLAGS_CBC BIT(1)
73#define FLAGS_INIT BIT(4)
74#define FLAGS_BUSY BIT(6)
75
76#define DEFAULT_AUTOSUSPEND_DELAY 1000
77
78#define FLAGS_IN_DATA_ST_SHIFT 8
79#define FLAGS_OUT_DATA_ST_SHIFT 10
80
81struct omap_des_ctx {
82 struct omap_des_dev *dd;
83
84 int keylen;
85 __le32 key[(3 * DES_KEY_SIZE) / sizeof(u32)];
86 unsigned long flags;
87};
88
89struct omap_des_reqctx {
90 unsigned long mode;
91};
92
93#define OMAP_DES_QUEUE_LENGTH 1
94#define OMAP_DES_CACHE_SIZE 0
95
96struct omap_des_algs_info {
97 struct skcipher_engine_alg *algs_list;
98 unsigned int size;
99 unsigned int registered;
100};
101
102struct omap_des_pdata {
103 struct omap_des_algs_info *algs_info;
104 unsigned int algs_info_size;
105
106 void (*trigger)(struct omap_des_dev *dd, int length);
107
108 u32 key_ofs;
109 u32 iv_ofs;
110 u32 ctrl_ofs;
111 u32 data_ofs;
112 u32 rev_ofs;
113 u32 mask_ofs;
114 u32 irq_enable_ofs;
115 u32 irq_status_ofs;
116
117 u32 dma_enable_in;
118 u32 dma_enable_out;
119 u32 dma_start;
120
121 u32 major_mask;
122 u32 major_shift;
123 u32 minor_mask;
124 u32 minor_shift;
125};
126
127struct omap_des_dev {
128 struct list_head list;
129 unsigned long phys_base;
130 void __iomem *io_base;
131 struct omap_des_ctx *ctx;
132 struct device *dev;
133 unsigned long flags;
134 int err;
135
136 struct tasklet_struct done_task;
137
138 struct skcipher_request *req;
139 struct crypto_engine *engine;
140 /*
141 * total is used by PIO mode for book keeping so introduce
142 * variable total_save as need it to calc page_order
143 */
144 size_t total;
145 size_t total_save;
146
147 struct scatterlist *in_sg;
148 struct scatterlist *out_sg;
149
150 /* Buffers for copying for unaligned cases */
151 struct scatterlist in_sgl;
152 struct scatterlist out_sgl;
153 struct scatterlist *orig_out;
154
155 struct scatter_walk in_walk;
156 struct scatter_walk out_walk;
157 struct dma_chan *dma_lch_in;
158 struct dma_chan *dma_lch_out;
159 int in_sg_len;
160 int out_sg_len;
161 int pio_only;
162 const struct omap_des_pdata *pdata;
163};
164
165/* keep registered devices data here */
166static LIST_HEAD(dev_list);
167static DEFINE_SPINLOCK(list_lock);
168
169#ifdef DEBUG
170#define omap_des_read(dd, offset) \
171 ({ \
172 int _read_ret; \
173 _read_ret = __raw_readl(dd->io_base + offset); \
174 pr_err("omap_des_read(" #offset "=%#x)= %#x\n", \
175 offset, _read_ret); \
176 _read_ret; \
177 })
178#else
179static inline u32 omap_des_read(struct omap_des_dev *dd, u32 offset)
180{
181 return __raw_readl(dd->io_base + offset);
182}
183#endif
184
185#ifdef DEBUG
186#define omap_des_write(dd, offset, value) \
187 do { \
188 pr_err("omap_des_write(" #offset "=%#x) value=%#x\n", \
189 offset, value); \
190 __raw_writel(value, dd->io_base + offset); \
191 } while (0)
192#else
193static inline void omap_des_write(struct omap_des_dev *dd, u32 offset,
194 u32 value)
195{
196 __raw_writel(value, dd->io_base + offset);
197}
198#endif
199
200static inline void omap_des_write_mask(struct omap_des_dev *dd, u32 offset,
201 u32 value, u32 mask)
202{
203 u32 val;
204
205 val = omap_des_read(dd, offset);
206 val &= ~mask;
207 val |= value;
208 omap_des_write(dd, offset, val);
209}
210
211static void omap_des_write_n(struct omap_des_dev *dd, u32 offset,
212 u32 *value, int count)
213{
214 for (; count--; value++, offset += 4)
215 omap_des_write(dd, offset, *value);
216}
217
218static int omap_des_hw_init(struct omap_des_dev *dd)
219{
220 int err;
221
222 /*
223 * clocks are enabled when request starts and disabled when finished.
224 * It may be long delays between requests.
225 * Device might go to off mode to save power.
226 */
227 err = pm_runtime_resume_and_get(dd->dev);
228 if (err < 0) {
229 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
230 return err;
231 }
232
233 if (!(dd->flags & FLAGS_INIT)) {
234 dd->flags |= FLAGS_INIT;
235 dd->err = 0;
236 }
237
238 return 0;
239}
240
241static int omap_des_write_ctrl(struct omap_des_dev *dd)
242{
243 unsigned int key32;
244 int i, err;
245 u32 val = 0, mask = 0;
246
247 err = omap_des_hw_init(dd);
248 if (err)
249 return err;
250
251 key32 = dd->ctx->keylen / sizeof(u32);
252
253 /* it seems a key should always be set even if it has not changed */
254 for (i = 0; i < key32; i++) {
255 omap_des_write(dd, DES_REG_KEY(dd, i),
256 __le32_to_cpu(dd->ctx->key[i]));
257 }
258
259 if ((dd->flags & FLAGS_CBC) && dd->req->iv)
260 omap_des_write_n(dd, DES_REG_IV(dd, 0), (void *)dd->req->iv, 2);
261
262 if (dd->flags & FLAGS_CBC)
263 val |= DES_REG_CTRL_CBC;
264 if (dd->flags & FLAGS_ENCRYPT)
265 val |= DES_REG_CTRL_DIRECTION;
266 if (key32 == 6)
267 val |= DES_REG_CTRL_TDES;
268
269 mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION | DES_REG_CTRL_TDES;
270
271 omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask);
272
273 return 0;
274}
275
276static void omap_des_dma_trigger_omap4(struct omap_des_dev *dd, int length)
277{
278 u32 mask, val;
279
280 omap_des_write(dd, DES_REG_LENGTH_N(0), length);
281
282 val = dd->pdata->dma_start;
283
284 if (dd->dma_lch_out != NULL)
285 val |= dd->pdata->dma_enable_out;
286 if (dd->dma_lch_in != NULL)
287 val |= dd->pdata->dma_enable_in;
288
289 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
290 dd->pdata->dma_start;
291
292 omap_des_write_mask(dd, DES_REG_MASK(dd), val, mask);
293}
294
295static void omap_des_dma_stop(struct omap_des_dev *dd)
296{
297 u32 mask;
298
299 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
300 dd->pdata->dma_start;
301
302 omap_des_write_mask(dd, DES_REG_MASK(dd), 0, mask);
303}
304
305static struct omap_des_dev *omap_des_find_dev(struct omap_des_ctx *ctx)
306{
307 struct omap_des_dev *dd = NULL, *tmp;
308
309 spin_lock_bh(&list_lock);
310 if (!ctx->dd) {
311 list_for_each_entry(tmp, &dev_list, list) {
312 /* FIXME: take fist available des core */
313 dd = tmp;
314 break;
315 }
316 ctx->dd = dd;
317 } else {
318 /* already found before */
319 dd = ctx->dd;
320 }
321 spin_unlock_bh(&list_lock);
322
323 return dd;
324}
325
326static void omap_des_dma_out_callback(void *data)
327{
328 struct omap_des_dev *dd = data;
329
330 /* dma_lch_out - completed */
331 tasklet_schedule(&dd->done_task);
332}
333
334static int omap_des_dma_init(struct omap_des_dev *dd)
335{
336 int err;
337
338 dd->dma_lch_out = NULL;
339 dd->dma_lch_in = NULL;
340
341 dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
342 if (IS_ERR(dd->dma_lch_in)) {
343 dev_err(dd->dev, "Unable to request in DMA channel\n");
344 return PTR_ERR(dd->dma_lch_in);
345 }
346
347 dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
348 if (IS_ERR(dd->dma_lch_out)) {
349 dev_err(dd->dev, "Unable to request out DMA channel\n");
350 err = PTR_ERR(dd->dma_lch_out);
351 goto err_dma_out;
352 }
353
354 return 0;
355
356err_dma_out:
357 dma_release_channel(dd->dma_lch_in);
358
359 return err;
360}
361
362static void omap_des_dma_cleanup(struct omap_des_dev *dd)
363{
364 if (dd->pio_only)
365 return;
366
367 dma_release_channel(dd->dma_lch_out);
368 dma_release_channel(dd->dma_lch_in);
369}
370
371static int omap_des_crypt_dma(struct crypto_tfm *tfm,
372 struct scatterlist *in_sg, struct scatterlist *out_sg,
373 int in_sg_len, int out_sg_len)
374{
375 struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm);
376 struct omap_des_dev *dd = ctx->dd;
377 struct dma_async_tx_descriptor *tx_in, *tx_out;
378 struct dma_slave_config cfg;
379 int ret;
380
381 if (dd->pio_only) {
382 scatterwalk_start(&dd->in_walk, dd->in_sg);
383 scatterwalk_start(&dd->out_walk, dd->out_sg);
384
385 /* Enable DATAIN interrupt and let it take
386 care of the rest */
387 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
388 return 0;
389 }
390
391 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
392
393 memset(&cfg, 0, sizeof(cfg));
394
395 cfg.src_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
396 cfg.dst_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
397 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
398 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
399 cfg.src_maxburst = DST_MAXBURST;
400 cfg.dst_maxburst = DST_MAXBURST;
401
402 /* IN */
403 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
404 if (ret) {
405 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
406 ret);
407 return ret;
408 }
409
410 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
411 DMA_MEM_TO_DEV,
412 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
413 if (!tx_in) {
414 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
415 return -EINVAL;
416 }
417
418 /* No callback necessary */
419 tx_in->callback_param = dd;
420
421 /* OUT */
422 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
423 if (ret) {
424 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
425 ret);
426 return ret;
427 }
428
429 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
430 DMA_DEV_TO_MEM,
431 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
432 if (!tx_out) {
433 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
434 return -EINVAL;
435 }
436
437 tx_out->callback = omap_des_dma_out_callback;
438 tx_out->callback_param = dd;
439
440 dmaengine_submit(tx_in);
441 dmaengine_submit(tx_out);
442
443 dma_async_issue_pending(dd->dma_lch_in);
444 dma_async_issue_pending(dd->dma_lch_out);
445
446 /* start DMA */
447 dd->pdata->trigger(dd, dd->total);
448
449 return 0;
450}
451
452static int omap_des_crypt_dma_start(struct omap_des_dev *dd)
453{
454 struct crypto_tfm *tfm = crypto_skcipher_tfm(
455 crypto_skcipher_reqtfm(dd->req));
456 int err;
457
458 pr_debug("total: %zd\n", dd->total);
459
460 if (!dd->pio_only) {
461 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
462 DMA_TO_DEVICE);
463 if (!err) {
464 dev_err(dd->dev, "dma_map_sg() error\n");
465 return -EINVAL;
466 }
467
468 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
469 DMA_FROM_DEVICE);
470 if (!err) {
471 dev_err(dd->dev, "dma_map_sg() error\n");
472 return -EINVAL;
473 }
474 }
475
476 err = omap_des_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
477 dd->out_sg_len);
478 if (err && !dd->pio_only) {
479 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
480 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
481 DMA_FROM_DEVICE);
482 }
483
484 return err;
485}
486
487static void omap_des_finish_req(struct omap_des_dev *dd, int err)
488{
489 struct skcipher_request *req = dd->req;
490
491 pr_debug("err: %d\n", err);
492
493 crypto_finalize_skcipher_request(dd->engine, req, err);
494
495 pm_runtime_mark_last_busy(dd->dev);
496 pm_runtime_put_autosuspend(dd->dev);
497}
498
499static int omap_des_crypt_dma_stop(struct omap_des_dev *dd)
500{
501 pr_debug("total: %zd\n", dd->total);
502
503 omap_des_dma_stop(dd);
504
505 dmaengine_terminate_all(dd->dma_lch_in);
506 dmaengine_terminate_all(dd->dma_lch_out);
507
508 return 0;
509}
510
511static int omap_des_handle_queue(struct omap_des_dev *dd,
512 struct skcipher_request *req)
513{
514 if (req)
515 return crypto_transfer_skcipher_request_to_engine(dd->engine, req);
516
517 return 0;
518}
519
520static int omap_des_prepare_req(struct skcipher_request *req,
521 struct omap_des_dev *dd)
522{
523 struct omap_des_ctx *ctx = crypto_skcipher_ctx(
524 crypto_skcipher_reqtfm(req));
525 struct omap_des_reqctx *rctx;
526 int ret;
527 u16 flags;
528
529 /* assign new request to device */
530 dd->req = req;
531 dd->total = req->cryptlen;
532 dd->total_save = req->cryptlen;
533 dd->in_sg = req->src;
534 dd->out_sg = req->dst;
535 dd->orig_out = req->dst;
536
537 flags = OMAP_CRYPTO_COPY_DATA;
538 if (req->src == req->dst)
539 flags |= OMAP_CRYPTO_FORCE_COPY;
540
541 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, DES_BLOCK_SIZE,
542 &dd->in_sgl, flags,
543 FLAGS_IN_DATA_ST_SHIFT, &dd->flags);
544 if (ret)
545 return ret;
546
547 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, DES_BLOCK_SIZE,
548 &dd->out_sgl, 0,
549 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags);
550 if (ret)
551 return ret;
552
553 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
554 if (dd->in_sg_len < 0)
555 return dd->in_sg_len;
556
557 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
558 if (dd->out_sg_len < 0)
559 return dd->out_sg_len;
560
561 rctx = skcipher_request_ctx(req);
562 ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req));
563 rctx->mode &= FLAGS_MODE_MASK;
564 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
565
566 dd->ctx = ctx;
567 ctx->dd = dd;
568
569 return omap_des_write_ctrl(dd);
570}
571
572static int omap_des_crypt_req(struct crypto_engine *engine,
573 void *areq)
574{
575 struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
576 struct omap_des_ctx *ctx = crypto_skcipher_ctx(
577 crypto_skcipher_reqtfm(req));
578 struct omap_des_dev *dd = omap_des_find_dev(ctx);
579
580 if (!dd)
581 return -ENODEV;
582
583 return omap_des_prepare_req(req, dd) ?:
584 omap_des_crypt_dma_start(dd);
585}
586
587static void omap_des_done_task(unsigned long data)
588{
589 struct omap_des_dev *dd = (struct omap_des_dev *)data;
590 int i;
591
592 pr_debug("enter done_task\n");
593
594 if (!dd->pio_only) {
595 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
596 DMA_FROM_DEVICE);
597 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
598 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
599 DMA_FROM_DEVICE);
600 omap_des_crypt_dma_stop(dd);
601 }
602
603 omap_crypto_cleanup(&dd->in_sgl, NULL, 0, dd->total_save,
604 FLAGS_IN_DATA_ST_SHIFT, dd->flags);
605
606 omap_crypto_cleanup(&dd->out_sgl, dd->orig_out, 0, dd->total_save,
607 FLAGS_OUT_DATA_ST_SHIFT, dd->flags);
608
609 if ((dd->flags & FLAGS_CBC) && dd->req->iv)
610 for (i = 0; i < 2; i++)
611 ((u32 *)dd->req->iv)[i] =
612 omap_des_read(dd, DES_REG_IV(dd, i));
613
614 omap_des_finish_req(dd, 0);
615
616 pr_debug("exit\n");
617}
618
619static int omap_des_crypt(struct skcipher_request *req, unsigned long mode)
620{
621 struct omap_des_ctx *ctx = crypto_skcipher_ctx(
622 crypto_skcipher_reqtfm(req));
623 struct omap_des_reqctx *rctx = skcipher_request_ctx(req);
624 struct omap_des_dev *dd;
625
626 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->cryptlen,
627 !!(mode & FLAGS_ENCRYPT),
628 !!(mode & FLAGS_CBC));
629
630 if (!req->cryptlen)
631 return 0;
632
633 if (!IS_ALIGNED(req->cryptlen, DES_BLOCK_SIZE))
634 return -EINVAL;
635
636 dd = omap_des_find_dev(ctx);
637 if (!dd)
638 return -ENODEV;
639
640 rctx->mode = mode;
641
642 return omap_des_handle_queue(dd, req);
643}
644
645/* ********************** ALG API ************************************ */
646
647static int omap_des_setkey(struct crypto_skcipher *cipher, const u8 *key,
648 unsigned int keylen)
649{
650 struct omap_des_ctx *ctx = crypto_skcipher_ctx(cipher);
651 int err;
652
653 pr_debug("enter, keylen: %d\n", keylen);
654
655 err = verify_skcipher_des_key(cipher, key);
656 if (err)
657 return err;
658
659 memcpy(ctx->key, key, keylen);
660 ctx->keylen = keylen;
661
662 return 0;
663}
664
665static int omap_des3_setkey(struct crypto_skcipher *cipher, const u8 *key,
666 unsigned int keylen)
667{
668 struct omap_des_ctx *ctx = crypto_skcipher_ctx(cipher);
669 int err;
670
671 pr_debug("enter, keylen: %d\n", keylen);
672
673 err = verify_skcipher_des3_key(cipher, key);
674 if (err)
675 return err;
676
677 memcpy(ctx->key, key, keylen);
678 ctx->keylen = keylen;
679
680 return 0;
681}
682
683static int omap_des_ecb_encrypt(struct skcipher_request *req)
684{
685 return omap_des_crypt(req, FLAGS_ENCRYPT);
686}
687
688static int omap_des_ecb_decrypt(struct skcipher_request *req)
689{
690 return omap_des_crypt(req, 0);
691}
692
693static int omap_des_cbc_encrypt(struct skcipher_request *req)
694{
695 return omap_des_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
696}
697
698static int omap_des_cbc_decrypt(struct skcipher_request *req)
699{
700 return omap_des_crypt(req, FLAGS_CBC);
701}
702
703static int omap_des_init_tfm(struct crypto_skcipher *tfm)
704{
705 pr_debug("enter\n");
706
707 crypto_skcipher_set_reqsize(tfm, sizeof(struct omap_des_reqctx));
708
709 return 0;
710}
711
712/* ********************** ALGS ************************************ */
713
714static struct skcipher_engine_alg algs_ecb_cbc[] = {
715{
716 .base = {
717 .base.cra_name = "ecb(des)",
718 .base.cra_driver_name = "ecb-des-omap",
719 .base.cra_priority = 300,
720 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
721 CRYPTO_ALG_ASYNC,
722 .base.cra_blocksize = DES_BLOCK_SIZE,
723 .base.cra_ctxsize = sizeof(struct omap_des_ctx),
724 .base.cra_module = THIS_MODULE,
725
726 .min_keysize = DES_KEY_SIZE,
727 .max_keysize = DES_KEY_SIZE,
728 .setkey = omap_des_setkey,
729 .encrypt = omap_des_ecb_encrypt,
730 .decrypt = omap_des_ecb_decrypt,
731 .init = omap_des_init_tfm,
732 },
733 .op.do_one_request = omap_des_crypt_req,
734},
735{
736 .base = {
737 .base.cra_name = "cbc(des)",
738 .base.cra_driver_name = "cbc-des-omap",
739 .base.cra_priority = 300,
740 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
741 CRYPTO_ALG_ASYNC,
742 .base.cra_blocksize = DES_BLOCK_SIZE,
743 .base.cra_ctxsize = sizeof(struct omap_des_ctx),
744 .base.cra_module = THIS_MODULE,
745
746 .min_keysize = DES_KEY_SIZE,
747 .max_keysize = DES_KEY_SIZE,
748 .ivsize = DES_BLOCK_SIZE,
749 .setkey = omap_des_setkey,
750 .encrypt = omap_des_cbc_encrypt,
751 .decrypt = omap_des_cbc_decrypt,
752 .init = omap_des_init_tfm,
753 },
754 .op.do_one_request = omap_des_crypt_req,
755},
756{
757 .base = {
758 .base.cra_name = "ecb(des3_ede)",
759 .base.cra_driver_name = "ecb-des3-omap",
760 .base.cra_priority = 300,
761 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
762 CRYPTO_ALG_ASYNC,
763 .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
764 .base.cra_ctxsize = sizeof(struct omap_des_ctx),
765 .base.cra_module = THIS_MODULE,
766
767 .min_keysize = DES3_EDE_KEY_SIZE,
768 .max_keysize = DES3_EDE_KEY_SIZE,
769 .setkey = omap_des3_setkey,
770 .encrypt = omap_des_ecb_encrypt,
771 .decrypt = omap_des_ecb_decrypt,
772 .init = omap_des_init_tfm,
773 },
774 .op.do_one_request = omap_des_crypt_req,
775},
776{
777 .base = {
778 .base.cra_name = "cbc(des3_ede)",
779 .base.cra_driver_name = "cbc-des3-omap",
780 .base.cra_priority = 300,
781 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
782 CRYPTO_ALG_ASYNC,
783 .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
784 .base.cra_ctxsize = sizeof(struct omap_des_ctx),
785 .base.cra_module = THIS_MODULE,
786
787 .min_keysize = DES3_EDE_KEY_SIZE,
788 .max_keysize = DES3_EDE_KEY_SIZE,
789 .ivsize = DES3_EDE_BLOCK_SIZE,
790 .setkey = omap_des3_setkey,
791 .encrypt = omap_des_cbc_encrypt,
792 .decrypt = omap_des_cbc_decrypt,
793 .init = omap_des_init_tfm,
794 },
795 .op.do_one_request = omap_des_crypt_req,
796}
797};
798
799static struct omap_des_algs_info omap_des_algs_info_ecb_cbc[] = {
800 {
801 .algs_list = algs_ecb_cbc,
802 .size = ARRAY_SIZE(algs_ecb_cbc),
803 },
804};
805
806#ifdef CONFIG_OF
807static const struct omap_des_pdata omap_des_pdata_omap4 = {
808 .algs_info = omap_des_algs_info_ecb_cbc,
809 .algs_info_size = ARRAY_SIZE(omap_des_algs_info_ecb_cbc),
810 .trigger = omap_des_dma_trigger_omap4,
811 .key_ofs = 0x14,
812 .iv_ofs = 0x18,
813 .ctrl_ofs = 0x20,
814 .data_ofs = 0x28,
815 .rev_ofs = 0x30,
816 .mask_ofs = 0x34,
817 .irq_status_ofs = 0x3c,
818 .irq_enable_ofs = 0x40,
819 .dma_enable_in = BIT(5),
820 .dma_enable_out = BIT(6),
821 .major_mask = 0x0700,
822 .major_shift = 8,
823 .minor_mask = 0x003f,
824 .minor_shift = 0,
825};
826
827static irqreturn_t omap_des_irq(int irq, void *dev_id)
828{
829 struct omap_des_dev *dd = dev_id;
830 u32 status, i;
831 u32 *src, *dst;
832
833 status = omap_des_read(dd, DES_REG_IRQ_STATUS(dd));
834 if (status & DES_REG_IRQ_DATA_IN) {
835 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
836
837 BUG_ON(!dd->in_sg);
838
839 BUG_ON(_calc_walked(in) > dd->in_sg->length);
840
841 src = sg_virt(dd->in_sg) + _calc_walked(in);
842
843 for (i = 0; i < DES_BLOCK_WORDS; i++) {
844 omap_des_write(dd, DES_REG_DATA_N(dd, i), *src);
845
846 scatterwalk_advance(&dd->in_walk, 4);
847 if (dd->in_sg->length == _calc_walked(in)) {
848 dd->in_sg = sg_next(dd->in_sg);
849 if (dd->in_sg) {
850 scatterwalk_start(&dd->in_walk,
851 dd->in_sg);
852 src = sg_virt(dd->in_sg) +
853 _calc_walked(in);
854 }
855 } else {
856 src++;
857 }
858 }
859
860 /* Clear IRQ status */
861 status &= ~DES_REG_IRQ_DATA_IN;
862 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
863
864 /* Enable DATA_OUT interrupt */
865 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x4);
866
867 } else if (status & DES_REG_IRQ_DATA_OUT) {
868 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
869
870 BUG_ON(!dd->out_sg);
871
872 BUG_ON(_calc_walked(out) > dd->out_sg->length);
873
874 dst = sg_virt(dd->out_sg) + _calc_walked(out);
875
876 for (i = 0; i < DES_BLOCK_WORDS; i++) {
877 *dst = omap_des_read(dd, DES_REG_DATA_N(dd, i));
878 scatterwalk_advance(&dd->out_walk, 4);
879 if (dd->out_sg->length == _calc_walked(out)) {
880 dd->out_sg = sg_next(dd->out_sg);
881 if (dd->out_sg) {
882 scatterwalk_start(&dd->out_walk,
883 dd->out_sg);
884 dst = sg_virt(dd->out_sg) +
885 _calc_walked(out);
886 }
887 } else {
888 dst++;
889 }
890 }
891
892 BUG_ON(dd->total < DES_BLOCK_SIZE);
893
894 dd->total -= DES_BLOCK_SIZE;
895
896 /* Clear IRQ status */
897 status &= ~DES_REG_IRQ_DATA_OUT;
898 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
899
900 if (!dd->total)
901 /* All bytes read! */
902 tasklet_schedule(&dd->done_task);
903 else
904 /* Enable DATA_IN interrupt for next block */
905 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
906 }
907
908 return IRQ_HANDLED;
909}
910
911static const struct of_device_id omap_des_of_match[] = {
912 {
913 .compatible = "ti,omap4-des",
914 .data = &omap_des_pdata_omap4,
915 },
916 {},
917};
918MODULE_DEVICE_TABLE(of, omap_des_of_match);
919
920static int omap_des_get_of(struct omap_des_dev *dd,
921 struct platform_device *pdev)
922{
923
924 dd->pdata = of_device_get_match_data(&pdev->dev);
925 if (!dd->pdata) {
926 dev_err(&pdev->dev, "no compatible OF match\n");
927 return -EINVAL;
928 }
929
930 return 0;
931}
932#else
933static int omap_des_get_of(struct omap_des_dev *dd,
934 struct device *dev)
935{
936 return -EINVAL;
937}
938#endif
939
940static int omap_des_get_pdev(struct omap_des_dev *dd,
941 struct platform_device *pdev)
942{
943 /* non-DT devices get pdata from pdev */
944 dd->pdata = pdev->dev.platform_data;
945
946 return 0;
947}
948
949static int omap_des_probe(struct platform_device *pdev)
950{
951 struct device *dev = &pdev->dev;
952 struct omap_des_dev *dd;
953 struct skcipher_engine_alg *algp;
954 struct resource *res;
955 int err = -ENOMEM, i, j, irq = -1;
956 u32 reg;
957
958 dd = devm_kzalloc(dev, sizeof(struct omap_des_dev), GFP_KERNEL);
959 if (dd == NULL) {
960 dev_err(dev, "unable to alloc data struct.\n");
961 goto err_data;
962 }
963 dd->dev = dev;
964 platform_set_drvdata(pdev, dd);
965
966 err = (dev->of_node) ? omap_des_get_of(dd, pdev) :
967 omap_des_get_pdev(dd, pdev);
968 if (err)
969 goto err_res;
970
971 dd->io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
972 if (IS_ERR(dd->io_base)) {
973 err = PTR_ERR(dd->io_base);
974 goto err_res;
975 }
976 dd->phys_base = res->start;
977
978 pm_runtime_use_autosuspend(dev);
979 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
980
981 pm_runtime_enable(dev);
982 err = pm_runtime_resume_and_get(dev);
983 if (err < 0) {
984 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
985 goto err_get;
986 }
987
988 omap_des_dma_stop(dd);
989
990 reg = omap_des_read(dd, DES_REG_REV(dd));
991
992 pm_runtime_put_sync(dev);
993
994 dev_info(dev, "OMAP DES hw accel rev: %u.%u\n",
995 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
996 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
997
998 tasklet_init(&dd->done_task, omap_des_done_task, (unsigned long)dd);
999
1000 err = omap_des_dma_init(dd);
1001 if (err == -EPROBE_DEFER) {
1002 goto err_irq;
1003 } else if (err && DES_REG_IRQ_STATUS(dd) && DES_REG_IRQ_ENABLE(dd)) {
1004 dd->pio_only = 1;
1005
1006 irq = platform_get_irq(pdev, 0);
1007 if (irq < 0) {
1008 err = irq;
1009 goto err_irq;
1010 }
1011
1012 err = devm_request_irq(dev, irq, omap_des_irq, 0,
1013 dev_name(dev), dd);
1014 if (err) {
1015 dev_err(dev, "Unable to grab omap-des IRQ\n");
1016 goto err_irq;
1017 }
1018 }
1019
1020
1021 INIT_LIST_HEAD(&dd->list);
1022 spin_lock_bh(&list_lock);
1023 list_add_tail(&dd->list, &dev_list);
1024 spin_unlock_bh(&list_lock);
1025
1026 /* Initialize des crypto engine */
1027 dd->engine = crypto_engine_alloc_init(dev, 1);
1028 if (!dd->engine) {
1029 err = -ENOMEM;
1030 goto err_engine;
1031 }
1032
1033 err = crypto_engine_start(dd->engine);
1034 if (err)
1035 goto err_engine;
1036
1037 for (i = 0; i < dd->pdata->algs_info_size; i++) {
1038 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1039 algp = &dd->pdata->algs_info[i].algs_list[j];
1040
1041 pr_debug("reg alg: %s\n", algp->base.base.cra_name);
1042
1043 err = crypto_engine_register_skcipher(algp);
1044 if (err)
1045 goto err_algs;
1046
1047 dd->pdata->algs_info[i].registered++;
1048 }
1049 }
1050
1051 return 0;
1052
1053err_algs:
1054 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1055 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1056 crypto_engine_unregister_skcipher(
1057 &dd->pdata->algs_info[i].algs_list[j]);
1058
1059err_engine:
1060 if (dd->engine)
1061 crypto_engine_exit(dd->engine);
1062
1063 omap_des_dma_cleanup(dd);
1064err_irq:
1065 tasklet_kill(&dd->done_task);
1066err_get:
1067 pm_runtime_disable(dev);
1068err_res:
1069 dd = NULL;
1070err_data:
1071 dev_err(dev, "initialization failed.\n");
1072 return err;
1073}
1074
1075static void omap_des_remove(struct platform_device *pdev)
1076{
1077 struct omap_des_dev *dd = platform_get_drvdata(pdev);
1078 int i, j;
1079
1080 spin_lock_bh(&list_lock);
1081 list_del(&dd->list);
1082 spin_unlock_bh(&list_lock);
1083
1084 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1085 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1086 crypto_engine_unregister_skcipher(
1087 &dd->pdata->algs_info[i].algs_list[j]);
1088
1089 tasklet_kill(&dd->done_task);
1090 omap_des_dma_cleanup(dd);
1091 pm_runtime_disable(dd->dev);
1092}
1093
1094#ifdef CONFIG_PM_SLEEP
1095static int omap_des_suspend(struct device *dev)
1096{
1097 pm_runtime_put_sync(dev);
1098 return 0;
1099}
1100
1101static int omap_des_resume(struct device *dev)
1102{
1103 int err;
1104
1105 err = pm_runtime_resume_and_get(dev);
1106 if (err < 0) {
1107 dev_err(dev, "%s: failed to get_sync(%d)\n", __func__, err);
1108 return err;
1109 }
1110 return 0;
1111}
1112#endif
1113
1114static SIMPLE_DEV_PM_OPS(omap_des_pm_ops, omap_des_suspend, omap_des_resume);
1115
1116static struct platform_driver omap_des_driver = {
1117 .probe = omap_des_probe,
1118 .remove_new = omap_des_remove,
1119 .driver = {
1120 .name = "omap-des",
1121 .pm = &omap_des_pm_ops,
1122 .of_match_table = of_match_ptr(omap_des_of_match),
1123 },
1124};
1125
1126module_platform_driver(omap_des_driver);
1127
1128MODULE_DESCRIPTION("OMAP DES hw acceleration support.");
1129MODULE_LICENSE("GPL v2");
1130MODULE_AUTHOR("Joel Fernandes <joelf@ti.com>");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Support for OMAP DES and Triple DES HW acceleration.
4 *
5 * Copyright (c) 2013 Texas Instruments Incorporated
6 * Author: Joel Fernandes <joelf@ti.com>
7 */
8
9#define pr_fmt(fmt) "%s: " fmt, __func__
10
11#ifdef DEBUG
12#define prn(num) printk(#num "=%d\n", num)
13#define prx(num) printk(#num "=%x\n", num)
14#else
15#define prn(num) do { } while (0)
16#define prx(num) do { } while (0)
17#endif
18
19#include <linux/err.h>
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/kernel.h>
24#include <linux/platform_device.h>
25#include <linux/scatterlist.h>
26#include <linux/dma-mapping.h>
27#include <linux/dmaengine.h>
28#include <linux/pm_runtime.h>
29#include <linux/of.h>
30#include <linux/of_device.h>
31#include <linux/of_address.h>
32#include <linux/io.h>
33#include <linux/crypto.h>
34#include <linux/interrupt.h>
35#include <crypto/scatterwalk.h>
36#include <crypto/internal/des.h>
37#include <crypto/internal/skcipher.h>
38#include <crypto/algapi.h>
39#include <crypto/engine.h>
40
41#include "omap-crypto.h"
42
43#define DST_MAXBURST 2
44
45#define DES_BLOCK_WORDS (DES_BLOCK_SIZE >> 2)
46
47#define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
48
49#define DES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \
50 ((x ^ 0x01) * 0x04))
51
52#define DES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04))
53
54#define DES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs)
55#define DES_REG_CTRL_CBC BIT(4)
56#define DES_REG_CTRL_TDES BIT(3)
57#define DES_REG_CTRL_DIRECTION BIT(2)
58#define DES_REG_CTRL_INPUT_READY BIT(1)
59#define DES_REG_CTRL_OUTPUT_READY BIT(0)
60
61#define DES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04))
62
63#define DES_REG_REV(dd) ((dd)->pdata->rev_ofs)
64
65#define DES_REG_MASK(dd) ((dd)->pdata->mask_ofs)
66
67#define DES_REG_LENGTH_N(x) (0x24 + ((x) * 0x04))
68
69#define DES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs)
70#define DES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs)
71#define DES_REG_IRQ_DATA_IN BIT(1)
72#define DES_REG_IRQ_DATA_OUT BIT(2)
73
74#define FLAGS_MODE_MASK 0x000f
75#define FLAGS_ENCRYPT BIT(0)
76#define FLAGS_CBC BIT(1)
77#define FLAGS_INIT BIT(4)
78#define FLAGS_BUSY BIT(6)
79
80#define DEFAULT_AUTOSUSPEND_DELAY 1000
81
82#define FLAGS_IN_DATA_ST_SHIFT 8
83#define FLAGS_OUT_DATA_ST_SHIFT 10
84
85struct omap_des_ctx {
86 struct crypto_engine_ctx enginectx;
87 struct omap_des_dev *dd;
88
89 int keylen;
90 __le32 key[(3 * DES_KEY_SIZE) / sizeof(u32)];
91 unsigned long flags;
92};
93
94struct omap_des_reqctx {
95 unsigned long mode;
96};
97
98#define OMAP_DES_QUEUE_LENGTH 1
99#define OMAP_DES_CACHE_SIZE 0
100
101struct omap_des_algs_info {
102 struct skcipher_alg *algs_list;
103 unsigned int size;
104 unsigned int registered;
105};
106
107struct omap_des_pdata {
108 struct omap_des_algs_info *algs_info;
109 unsigned int algs_info_size;
110
111 void (*trigger)(struct omap_des_dev *dd, int length);
112
113 u32 key_ofs;
114 u32 iv_ofs;
115 u32 ctrl_ofs;
116 u32 data_ofs;
117 u32 rev_ofs;
118 u32 mask_ofs;
119 u32 irq_enable_ofs;
120 u32 irq_status_ofs;
121
122 u32 dma_enable_in;
123 u32 dma_enable_out;
124 u32 dma_start;
125
126 u32 major_mask;
127 u32 major_shift;
128 u32 minor_mask;
129 u32 minor_shift;
130};
131
132struct omap_des_dev {
133 struct list_head list;
134 unsigned long phys_base;
135 void __iomem *io_base;
136 struct omap_des_ctx *ctx;
137 struct device *dev;
138 unsigned long flags;
139 int err;
140
141 struct tasklet_struct done_task;
142
143 struct skcipher_request *req;
144 struct crypto_engine *engine;
145 /*
146 * total is used by PIO mode for book keeping so introduce
147 * variable total_save as need it to calc page_order
148 */
149 size_t total;
150 size_t total_save;
151
152 struct scatterlist *in_sg;
153 struct scatterlist *out_sg;
154
155 /* Buffers for copying for unaligned cases */
156 struct scatterlist in_sgl;
157 struct scatterlist out_sgl;
158 struct scatterlist *orig_out;
159
160 struct scatter_walk in_walk;
161 struct scatter_walk out_walk;
162 struct dma_chan *dma_lch_in;
163 struct dma_chan *dma_lch_out;
164 int in_sg_len;
165 int out_sg_len;
166 int pio_only;
167 const struct omap_des_pdata *pdata;
168};
169
170/* keep registered devices data here */
171static LIST_HEAD(dev_list);
172static DEFINE_SPINLOCK(list_lock);
173
174#ifdef DEBUG
175#define omap_des_read(dd, offset) \
176 ({ \
177 int _read_ret; \
178 _read_ret = __raw_readl(dd->io_base + offset); \
179 pr_err("omap_des_read(" #offset "=%#x)= %#x\n", \
180 offset, _read_ret); \
181 _read_ret; \
182 })
183#else
184static inline u32 omap_des_read(struct omap_des_dev *dd, u32 offset)
185{
186 return __raw_readl(dd->io_base + offset);
187}
188#endif
189
190#ifdef DEBUG
191#define omap_des_write(dd, offset, value) \
192 do { \
193 pr_err("omap_des_write(" #offset "=%#x) value=%#x\n", \
194 offset, value); \
195 __raw_writel(value, dd->io_base + offset); \
196 } while (0)
197#else
198static inline void omap_des_write(struct omap_des_dev *dd, u32 offset,
199 u32 value)
200{
201 __raw_writel(value, dd->io_base + offset);
202}
203#endif
204
205static inline void omap_des_write_mask(struct omap_des_dev *dd, u32 offset,
206 u32 value, u32 mask)
207{
208 u32 val;
209
210 val = omap_des_read(dd, offset);
211 val &= ~mask;
212 val |= value;
213 omap_des_write(dd, offset, val);
214}
215
216static void omap_des_write_n(struct omap_des_dev *dd, u32 offset,
217 u32 *value, int count)
218{
219 for (; count--; value++, offset += 4)
220 omap_des_write(dd, offset, *value);
221}
222
223static int omap_des_hw_init(struct omap_des_dev *dd)
224{
225 int err;
226
227 /*
228 * clocks are enabled when request starts and disabled when finished.
229 * It may be long delays between requests.
230 * Device might go to off mode to save power.
231 */
232 err = pm_runtime_resume_and_get(dd->dev);
233 if (err < 0) {
234 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
235 return err;
236 }
237
238 if (!(dd->flags & FLAGS_INIT)) {
239 dd->flags |= FLAGS_INIT;
240 dd->err = 0;
241 }
242
243 return 0;
244}
245
246static int omap_des_write_ctrl(struct omap_des_dev *dd)
247{
248 unsigned int key32;
249 int i, err;
250 u32 val = 0, mask = 0;
251
252 err = omap_des_hw_init(dd);
253 if (err)
254 return err;
255
256 key32 = dd->ctx->keylen / sizeof(u32);
257
258 /* it seems a key should always be set even if it has not changed */
259 for (i = 0; i < key32; i++) {
260 omap_des_write(dd, DES_REG_KEY(dd, i),
261 __le32_to_cpu(dd->ctx->key[i]));
262 }
263
264 if ((dd->flags & FLAGS_CBC) && dd->req->iv)
265 omap_des_write_n(dd, DES_REG_IV(dd, 0), (void *)dd->req->iv, 2);
266
267 if (dd->flags & FLAGS_CBC)
268 val |= DES_REG_CTRL_CBC;
269 if (dd->flags & FLAGS_ENCRYPT)
270 val |= DES_REG_CTRL_DIRECTION;
271 if (key32 == 6)
272 val |= DES_REG_CTRL_TDES;
273
274 mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION | DES_REG_CTRL_TDES;
275
276 omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask);
277
278 return 0;
279}
280
281static void omap_des_dma_trigger_omap4(struct omap_des_dev *dd, int length)
282{
283 u32 mask, val;
284
285 omap_des_write(dd, DES_REG_LENGTH_N(0), length);
286
287 val = dd->pdata->dma_start;
288
289 if (dd->dma_lch_out != NULL)
290 val |= dd->pdata->dma_enable_out;
291 if (dd->dma_lch_in != NULL)
292 val |= dd->pdata->dma_enable_in;
293
294 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
295 dd->pdata->dma_start;
296
297 omap_des_write_mask(dd, DES_REG_MASK(dd), val, mask);
298}
299
300static void omap_des_dma_stop(struct omap_des_dev *dd)
301{
302 u32 mask;
303
304 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
305 dd->pdata->dma_start;
306
307 omap_des_write_mask(dd, DES_REG_MASK(dd), 0, mask);
308}
309
310static struct omap_des_dev *omap_des_find_dev(struct omap_des_ctx *ctx)
311{
312 struct omap_des_dev *dd = NULL, *tmp;
313
314 spin_lock_bh(&list_lock);
315 if (!ctx->dd) {
316 list_for_each_entry(tmp, &dev_list, list) {
317 /* FIXME: take fist available des core */
318 dd = tmp;
319 break;
320 }
321 ctx->dd = dd;
322 } else {
323 /* already found before */
324 dd = ctx->dd;
325 }
326 spin_unlock_bh(&list_lock);
327
328 return dd;
329}
330
331static void omap_des_dma_out_callback(void *data)
332{
333 struct omap_des_dev *dd = data;
334
335 /* dma_lch_out - completed */
336 tasklet_schedule(&dd->done_task);
337}
338
339static int omap_des_dma_init(struct omap_des_dev *dd)
340{
341 int err;
342
343 dd->dma_lch_out = NULL;
344 dd->dma_lch_in = NULL;
345
346 dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
347 if (IS_ERR(dd->dma_lch_in)) {
348 dev_err(dd->dev, "Unable to request in DMA channel\n");
349 return PTR_ERR(dd->dma_lch_in);
350 }
351
352 dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
353 if (IS_ERR(dd->dma_lch_out)) {
354 dev_err(dd->dev, "Unable to request out DMA channel\n");
355 err = PTR_ERR(dd->dma_lch_out);
356 goto err_dma_out;
357 }
358
359 return 0;
360
361err_dma_out:
362 dma_release_channel(dd->dma_lch_in);
363
364 return err;
365}
366
367static void omap_des_dma_cleanup(struct omap_des_dev *dd)
368{
369 if (dd->pio_only)
370 return;
371
372 dma_release_channel(dd->dma_lch_out);
373 dma_release_channel(dd->dma_lch_in);
374}
375
376static int omap_des_crypt_dma(struct crypto_tfm *tfm,
377 struct scatterlist *in_sg, struct scatterlist *out_sg,
378 int in_sg_len, int out_sg_len)
379{
380 struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm);
381 struct omap_des_dev *dd = ctx->dd;
382 struct dma_async_tx_descriptor *tx_in, *tx_out;
383 struct dma_slave_config cfg;
384 int ret;
385
386 if (dd->pio_only) {
387 scatterwalk_start(&dd->in_walk, dd->in_sg);
388 scatterwalk_start(&dd->out_walk, dd->out_sg);
389
390 /* Enable DATAIN interrupt and let it take
391 care of the rest */
392 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
393 return 0;
394 }
395
396 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
397
398 memset(&cfg, 0, sizeof(cfg));
399
400 cfg.src_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
401 cfg.dst_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
402 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
403 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
404 cfg.src_maxburst = DST_MAXBURST;
405 cfg.dst_maxburst = DST_MAXBURST;
406
407 /* IN */
408 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
409 if (ret) {
410 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
411 ret);
412 return ret;
413 }
414
415 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
416 DMA_MEM_TO_DEV,
417 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
418 if (!tx_in) {
419 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
420 return -EINVAL;
421 }
422
423 /* No callback necessary */
424 tx_in->callback_param = dd;
425
426 /* OUT */
427 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
428 if (ret) {
429 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
430 ret);
431 return ret;
432 }
433
434 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
435 DMA_DEV_TO_MEM,
436 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
437 if (!tx_out) {
438 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
439 return -EINVAL;
440 }
441
442 tx_out->callback = omap_des_dma_out_callback;
443 tx_out->callback_param = dd;
444
445 dmaengine_submit(tx_in);
446 dmaengine_submit(tx_out);
447
448 dma_async_issue_pending(dd->dma_lch_in);
449 dma_async_issue_pending(dd->dma_lch_out);
450
451 /* start DMA */
452 dd->pdata->trigger(dd, dd->total);
453
454 return 0;
455}
456
457static int omap_des_crypt_dma_start(struct omap_des_dev *dd)
458{
459 struct crypto_tfm *tfm = crypto_skcipher_tfm(
460 crypto_skcipher_reqtfm(dd->req));
461 int err;
462
463 pr_debug("total: %zd\n", dd->total);
464
465 if (!dd->pio_only) {
466 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
467 DMA_TO_DEVICE);
468 if (!err) {
469 dev_err(dd->dev, "dma_map_sg() error\n");
470 return -EINVAL;
471 }
472
473 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
474 DMA_FROM_DEVICE);
475 if (!err) {
476 dev_err(dd->dev, "dma_map_sg() error\n");
477 return -EINVAL;
478 }
479 }
480
481 err = omap_des_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
482 dd->out_sg_len);
483 if (err && !dd->pio_only) {
484 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
485 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
486 DMA_FROM_DEVICE);
487 }
488
489 return err;
490}
491
492static void omap_des_finish_req(struct omap_des_dev *dd, int err)
493{
494 struct skcipher_request *req = dd->req;
495
496 pr_debug("err: %d\n", err);
497
498 crypto_finalize_skcipher_request(dd->engine, req, err);
499
500 pm_runtime_mark_last_busy(dd->dev);
501 pm_runtime_put_autosuspend(dd->dev);
502}
503
504static int omap_des_crypt_dma_stop(struct omap_des_dev *dd)
505{
506 pr_debug("total: %zd\n", dd->total);
507
508 omap_des_dma_stop(dd);
509
510 dmaengine_terminate_all(dd->dma_lch_in);
511 dmaengine_terminate_all(dd->dma_lch_out);
512
513 return 0;
514}
515
516static int omap_des_handle_queue(struct omap_des_dev *dd,
517 struct skcipher_request *req)
518{
519 if (req)
520 return crypto_transfer_skcipher_request_to_engine(dd->engine, req);
521
522 return 0;
523}
524
525static int omap_des_prepare_req(struct crypto_engine *engine,
526 void *areq)
527{
528 struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
529 struct omap_des_ctx *ctx = crypto_skcipher_ctx(
530 crypto_skcipher_reqtfm(req));
531 struct omap_des_dev *dd = omap_des_find_dev(ctx);
532 struct omap_des_reqctx *rctx;
533 int ret;
534 u16 flags;
535
536 if (!dd)
537 return -ENODEV;
538
539 /* assign new request to device */
540 dd->req = req;
541 dd->total = req->cryptlen;
542 dd->total_save = req->cryptlen;
543 dd->in_sg = req->src;
544 dd->out_sg = req->dst;
545 dd->orig_out = req->dst;
546
547 flags = OMAP_CRYPTO_COPY_DATA;
548 if (req->src == req->dst)
549 flags |= OMAP_CRYPTO_FORCE_COPY;
550
551 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, DES_BLOCK_SIZE,
552 &dd->in_sgl, flags,
553 FLAGS_IN_DATA_ST_SHIFT, &dd->flags);
554 if (ret)
555 return ret;
556
557 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, DES_BLOCK_SIZE,
558 &dd->out_sgl, 0,
559 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags);
560 if (ret)
561 return ret;
562
563 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
564 if (dd->in_sg_len < 0)
565 return dd->in_sg_len;
566
567 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
568 if (dd->out_sg_len < 0)
569 return dd->out_sg_len;
570
571 rctx = skcipher_request_ctx(req);
572 ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req));
573 rctx->mode &= FLAGS_MODE_MASK;
574 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
575
576 dd->ctx = ctx;
577 ctx->dd = dd;
578
579 return omap_des_write_ctrl(dd);
580}
581
582static int omap_des_crypt_req(struct crypto_engine *engine,
583 void *areq)
584{
585 struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
586 struct omap_des_ctx *ctx = crypto_skcipher_ctx(
587 crypto_skcipher_reqtfm(req));
588 struct omap_des_dev *dd = omap_des_find_dev(ctx);
589
590 if (!dd)
591 return -ENODEV;
592
593 return omap_des_crypt_dma_start(dd);
594}
595
596static void omap_des_done_task(unsigned long data)
597{
598 struct omap_des_dev *dd = (struct omap_des_dev *)data;
599 int i;
600
601 pr_debug("enter done_task\n");
602
603 if (!dd->pio_only) {
604 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
605 DMA_FROM_DEVICE);
606 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
607 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
608 DMA_FROM_DEVICE);
609 omap_des_crypt_dma_stop(dd);
610 }
611
612 omap_crypto_cleanup(&dd->in_sgl, NULL, 0, dd->total_save,
613 FLAGS_IN_DATA_ST_SHIFT, dd->flags);
614
615 omap_crypto_cleanup(&dd->out_sgl, dd->orig_out, 0, dd->total_save,
616 FLAGS_OUT_DATA_ST_SHIFT, dd->flags);
617
618 if ((dd->flags & FLAGS_CBC) && dd->req->iv)
619 for (i = 0; i < 2; i++)
620 ((u32 *)dd->req->iv)[i] =
621 omap_des_read(dd, DES_REG_IV(dd, i));
622
623 omap_des_finish_req(dd, 0);
624
625 pr_debug("exit\n");
626}
627
628static int omap_des_crypt(struct skcipher_request *req, unsigned long mode)
629{
630 struct omap_des_ctx *ctx = crypto_skcipher_ctx(
631 crypto_skcipher_reqtfm(req));
632 struct omap_des_reqctx *rctx = skcipher_request_ctx(req);
633 struct omap_des_dev *dd;
634
635 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->cryptlen,
636 !!(mode & FLAGS_ENCRYPT),
637 !!(mode & FLAGS_CBC));
638
639 if (!req->cryptlen)
640 return 0;
641
642 if (!IS_ALIGNED(req->cryptlen, DES_BLOCK_SIZE))
643 return -EINVAL;
644
645 dd = omap_des_find_dev(ctx);
646 if (!dd)
647 return -ENODEV;
648
649 rctx->mode = mode;
650
651 return omap_des_handle_queue(dd, req);
652}
653
654/* ********************** ALG API ************************************ */
655
656static int omap_des_setkey(struct crypto_skcipher *cipher, const u8 *key,
657 unsigned int keylen)
658{
659 struct omap_des_ctx *ctx = crypto_skcipher_ctx(cipher);
660 int err;
661
662 pr_debug("enter, keylen: %d\n", keylen);
663
664 err = verify_skcipher_des_key(cipher, key);
665 if (err)
666 return err;
667
668 memcpy(ctx->key, key, keylen);
669 ctx->keylen = keylen;
670
671 return 0;
672}
673
674static int omap_des3_setkey(struct crypto_skcipher *cipher, const u8 *key,
675 unsigned int keylen)
676{
677 struct omap_des_ctx *ctx = crypto_skcipher_ctx(cipher);
678 int err;
679
680 pr_debug("enter, keylen: %d\n", keylen);
681
682 err = verify_skcipher_des3_key(cipher, key);
683 if (err)
684 return err;
685
686 memcpy(ctx->key, key, keylen);
687 ctx->keylen = keylen;
688
689 return 0;
690}
691
692static int omap_des_ecb_encrypt(struct skcipher_request *req)
693{
694 return omap_des_crypt(req, FLAGS_ENCRYPT);
695}
696
697static int omap_des_ecb_decrypt(struct skcipher_request *req)
698{
699 return omap_des_crypt(req, 0);
700}
701
702static int omap_des_cbc_encrypt(struct skcipher_request *req)
703{
704 return omap_des_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
705}
706
707static int omap_des_cbc_decrypt(struct skcipher_request *req)
708{
709 return omap_des_crypt(req, FLAGS_CBC);
710}
711
712static int omap_des_prepare_req(struct crypto_engine *engine,
713 void *areq);
714static int omap_des_crypt_req(struct crypto_engine *engine,
715 void *areq);
716
717static int omap_des_init_tfm(struct crypto_skcipher *tfm)
718{
719 struct omap_des_ctx *ctx = crypto_skcipher_ctx(tfm);
720
721 pr_debug("enter\n");
722
723 crypto_skcipher_set_reqsize(tfm, sizeof(struct omap_des_reqctx));
724
725 ctx->enginectx.op.prepare_request = omap_des_prepare_req;
726 ctx->enginectx.op.unprepare_request = NULL;
727 ctx->enginectx.op.do_one_request = omap_des_crypt_req;
728
729 return 0;
730}
731
732/* ********************** ALGS ************************************ */
733
734static struct skcipher_alg algs_ecb_cbc[] = {
735{
736 .base.cra_name = "ecb(des)",
737 .base.cra_driver_name = "ecb-des-omap",
738 .base.cra_priority = 300,
739 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
740 CRYPTO_ALG_ASYNC,
741 .base.cra_blocksize = DES_BLOCK_SIZE,
742 .base.cra_ctxsize = sizeof(struct omap_des_ctx),
743 .base.cra_module = THIS_MODULE,
744
745 .min_keysize = DES_KEY_SIZE,
746 .max_keysize = DES_KEY_SIZE,
747 .setkey = omap_des_setkey,
748 .encrypt = omap_des_ecb_encrypt,
749 .decrypt = omap_des_ecb_decrypt,
750 .init = omap_des_init_tfm,
751},
752{
753 .base.cra_name = "cbc(des)",
754 .base.cra_driver_name = "cbc-des-omap",
755 .base.cra_priority = 300,
756 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
757 CRYPTO_ALG_ASYNC,
758 .base.cra_blocksize = DES_BLOCK_SIZE,
759 .base.cra_ctxsize = sizeof(struct omap_des_ctx),
760 .base.cra_module = THIS_MODULE,
761
762 .min_keysize = DES_KEY_SIZE,
763 .max_keysize = DES_KEY_SIZE,
764 .ivsize = DES_BLOCK_SIZE,
765 .setkey = omap_des_setkey,
766 .encrypt = omap_des_cbc_encrypt,
767 .decrypt = omap_des_cbc_decrypt,
768 .init = omap_des_init_tfm,
769},
770{
771 .base.cra_name = "ecb(des3_ede)",
772 .base.cra_driver_name = "ecb-des3-omap",
773 .base.cra_priority = 300,
774 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
775 CRYPTO_ALG_ASYNC,
776 .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
777 .base.cra_ctxsize = sizeof(struct omap_des_ctx),
778 .base.cra_module = THIS_MODULE,
779
780 .min_keysize = DES3_EDE_KEY_SIZE,
781 .max_keysize = DES3_EDE_KEY_SIZE,
782 .setkey = omap_des3_setkey,
783 .encrypt = omap_des_ecb_encrypt,
784 .decrypt = omap_des_ecb_decrypt,
785 .init = omap_des_init_tfm,
786},
787{
788 .base.cra_name = "cbc(des3_ede)",
789 .base.cra_driver_name = "cbc-des3-omap",
790 .base.cra_priority = 300,
791 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
792 CRYPTO_ALG_ASYNC,
793 .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
794 .base.cra_ctxsize = sizeof(struct omap_des_ctx),
795 .base.cra_module = THIS_MODULE,
796
797 .min_keysize = DES3_EDE_KEY_SIZE,
798 .max_keysize = DES3_EDE_KEY_SIZE,
799 .ivsize = DES3_EDE_BLOCK_SIZE,
800 .setkey = omap_des3_setkey,
801 .encrypt = omap_des_cbc_encrypt,
802 .decrypt = omap_des_cbc_decrypt,
803 .init = omap_des_init_tfm,
804}
805};
806
807static struct omap_des_algs_info omap_des_algs_info_ecb_cbc[] = {
808 {
809 .algs_list = algs_ecb_cbc,
810 .size = ARRAY_SIZE(algs_ecb_cbc),
811 },
812};
813
814#ifdef CONFIG_OF
815static const struct omap_des_pdata omap_des_pdata_omap4 = {
816 .algs_info = omap_des_algs_info_ecb_cbc,
817 .algs_info_size = ARRAY_SIZE(omap_des_algs_info_ecb_cbc),
818 .trigger = omap_des_dma_trigger_omap4,
819 .key_ofs = 0x14,
820 .iv_ofs = 0x18,
821 .ctrl_ofs = 0x20,
822 .data_ofs = 0x28,
823 .rev_ofs = 0x30,
824 .mask_ofs = 0x34,
825 .irq_status_ofs = 0x3c,
826 .irq_enable_ofs = 0x40,
827 .dma_enable_in = BIT(5),
828 .dma_enable_out = BIT(6),
829 .major_mask = 0x0700,
830 .major_shift = 8,
831 .minor_mask = 0x003f,
832 .minor_shift = 0,
833};
834
835static irqreturn_t omap_des_irq(int irq, void *dev_id)
836{
837 struct omap_des_dev *dd = dev_id;
838 u32 status, i;
839 u32 *src, *dst;
840
841 status = omap_des_read(dd, DES_REG_IRQ_STATUS(dd));
842 if (status & DES_REG_IRQ_DATA_IN) {
843 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
844
845 BUG_ON(!dd->in_sg);
846
847 BUG_ON(_calc_walked(in) > dd->in_sg->length);
848
849 src = sg_virt(dd->in_sg) + _calc_walked(in);
850
851 for (i = 0; i < DES_BLOCK_WORDS; i++) {
852 omap_des_write(dd, DES_REG_DATA_N(dd, i), *src);
853
854 scatterwalk_advance(&dd->in_walk, 4);
855 if (dd->in_sg->length == _calc_walked(in)) {
856 dd->in_sg = sg_next(dd->in_sg);
857 if (dd->in_sg) {
858 scatterwalk_start(&dd->in_walk,
859 dd->in_sg);
860 src = sg_virt(dd->in_sg) +
861 _calc_walked(in);
862 }
863 } else {
864 src++;
865 }
866 }
867
868 /* Clear IRQ status */
869 status &= ~DES_REG_IRQ_DATA_IN;
870 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
871
872 /* Enable DATA_OUT interrupt */
873 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x4);
874
875 } else if (status & DES_REG_IRQ_DATA_OUT) {
876 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
877
878 BUG_ON(!dd->out_sg);
879
880 BUG_ON(_calc_walked(out) > dd->out_sg->length);
881
882 dst = sg_virt(dd->out_sg) + _calc_walked(out);
883
884 for (i = 0; i < DES_BLOCK_WORDS; i++) {
885 *dst = omap_des_read(dd, DES_REG_DATA_N(dd, i));
886 scatterwalk_advance(&dd->out_walk, 4);
887 if (dd->out_sg->length == _calc_walked(out)) {
888 dd->out_sg = sg_next(dd->out_sg);
889 if (dd->out_sg) {
890 scatterwalk_start(&dd->out_walk,
891 dd->out_sg);
892 dst = sg_virt(dd->out_sg) +
893 _calc_walked(out);
894 }
895 } else {
896 dst++;
897 }
898 }
899
900 BUG_ON(dd->total < DES_BLOCK_SIZE);
901
902 dd->total -= DES_BLOCK_SIZE;
903
904 /* Clear IRQ status */
905 status &= ~DES_REG_IRQ_DATA_OUT;
906 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
907
908 if (!dd->total)
909 /* All bytes read! */
910 tasklet_schedule(&dd->done_task);
911 else
912 /* Enable DATA_IN interrupt for next block */
913 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
914 }
915
916 return IRQ_HANDLED;
917}
918
919static const struct of_device_id omap_des_of_match[] = {
920 {
921 .compatible = "ti,omap4-des",
922 .data = &omap_des_pdata_omap4,
923 },
924 {},
925};
926MODULE_DEVICE_TABLE(of, omap_des_of_match);
927
928static int omap_des_get_of(struct omap_des_dev *dd,
929 struct platform_device *pdev)
930{
931
932 dd->pdata = of_device_get_match_data(&pdev->dev);
933 if (!dd->pdata) {
934 dev_err(&pdev->dev, "no compatible OF match\n");
935 return -EINVAL;
936 }
937
938 return 0;
939}
940#else
941static int omap_des_get_of(struct omap_des_dev *dd,
942 struct device *dev)
943{
944 return -EINVAL;
945}
946#endif
947
948static int omap_des_get_pdev(struct omap_des_dev *dd,
949 struct platform_device *pdev)
950{
951 /* non-DT devices get pdata from pdev */
952 dd->pdata = pdev->dev.platform_data;
953
954 return 0;
955}
956
957static int omap_des_probe(struct platform_device *pdev)
958{
959 struct device *dev = &pdev->dev;
960 struct omap_des_dev *dd;
961 struct skcipher_alg *algp;
962 struct resource *res;
963 int err = -ENOMEM, i, j, irq = -1;
964 u32 reg;
965
966 dd = devm_kzalloc(dev, sizeof(struct omap_des_dev), GFP_KERNEL);
967 if (dd == NULL) {
968 dev_err(dev, "unable to alloc data struct.\n");
969 goto err_data;
970 }
971 dd->dev = dev;
972 platform_set_drvdata(pdev, dd);
973
974 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
975 if (!res) {
976 dev_err(dev, "no MEM resource info\n");
977 goto err_res;
978 }
979
980 err = (dev->of_node) ? omap_des_get_of(dd, pdev) :
981 omap_des_get_pdev(dd, pdev);
982 if (err)
983 goto err_res;
984
985 dd->io_base = devm_ioremap_resource(dev, res);
986 if (IS_ERR(dd->io_base)) {
987 err = PTR_ERR(dd->io_base);
988 goto err_res;
989 }
990 dd->phys_base = res->start;
991
992 pm_runtime_use_autosuspend(dev);
993 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
994
995 pm_runtime_enable(dev);
996 err = pm_runtime_resume_and_get(dev);
997 if (err < 0) {
998 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
999 goto err_get;
1000 }
1001
1002 omap_des_dma_stop(dd);
1003
1004 reg = omap_des_read(dd, DES_REG_REV(dd));
1005
1006 pm_runtime_put_sync(dev);
1007
1008 dev_info(dev, "OMAP DES hw accel rev: %u.%u\n",
1009 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1010 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1011
1012 tasklet_init(&dd->done_task, omap_des_done_task, (unsigned long)dd);
1013
1014 err = omap_des_dma_init(dd);
1015 if (err == -EPROBE_DEFER) {
1016 goto err_irq;
1017 } else if (err && DES_REG_IRQ_STATUS(dd) && DES_REG_IRQ_ENABLE(dd)) {
1018 dd->pio_only = 1;
1019
1020 irq = platform_get_irq(pdev, 0);
1021 if (irq < 0) {
1022 err = irq;
1023 goto err_irq;
1024 }
1025
1026 err = devm_request_irq(dev, irq, omap_des_irq, 0,
1027 dev_name(dev), dd);
1028 if (err) {
1029 dev_err(dev, "Unable to grab omap-des IRQ\n");
1030 goto err_irq;
1031 }
1032 }
1033
1034
1035 INIT_LIST_HEAD(&dd->list);
1036 spin_lock_bh(&list_lock);
1037 list_add_tail(&dd->list, &dev_list);
1038 spin_unlock_bh(&list_lock);
1039
1040 /* Initialize des crypto engine */
1041 dd->engine = crypto_engine_alloc_init(dev, 1);
1042 if (!dd->engine) {
1043 err = -ENOMEM;
1044 goto err_engine;
1045 }
1046
1047 err = crypto_engine_start(dd->engine);
1048 if (err)
1049 goto err_engine;
1050
1051 for (i = 0; i < dd->pdata->algs_info_size; i++) {
1052 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1053 algp = &dd->pdata->algs_info[i].algs_list[j];
1054
1055 pr_debug("reg alg: %s\n", algp->base.cra_name);
1056
1057 err = crypto_register_skcipher(algp);
1058 if (err)
1059 goto err_algs;
1060
1061 dd->pdata->algs_info[i].registered++;
1062 }
1063 }
1064
1065 return 0;
1066
1067err_algs:
1068 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1069 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1070 crypto_unregister_skcipher(
1071 &dd->pdata->algs_info[i].algs_list[j]);
1072
1073err_engine:
1074 if (dd->engine)
1075 crypto_engine_exit(dd->engine);
1076
1077 omap_des_dma_cleanup(dd);
1078err_irq:
1079 tasklet_kill(&dd->done_task);
1080err_get:
1081 pm_runtime_disable(dev);
1082err_res:
1083 dd = NULL;
1084err_data:
1085 dev_err(dev, "initialization failed.\n");
1086 return err;
1087}
1088
1089static int omap_des_remove(struct platform_device *pdev)
1090{
1091 struct omap_des_dev *dd = platform_get_drvdata(pdev);
1092 int i, j;
1093
1094 spin_lock_bh(&list_lock);
1095 list_del(&dd->list);
1096 spin_unlock_bh(&list_lock);
1097
1098 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1099 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1100 crypto_unregister_skcipher(
1101 &dd->pdata->algs_info[i].algs_list[j]);
1102
1103 tasklet_kill(&dd->done_task);
1104 omap_des_dma_cleanup(dd);
1105 pm_runtime_disable(dd->dev);
1106
1107 return 0;
1108}
1109
1110#ifdef CONFIG_PM_SLEEP
1111static int omap_des_suspend(struct device *dev)
1112{
1113 pm_runtime_put_sync(dev);
1114 return 0;
1115}
1116
1117static int omap_des_resume(struct device *dev)
1118{
1119 int err;
1120
1121 err = pm_runtime_resume_and_get(dev);
1122 if (err < 0) {
1123 dev_err(dev, "%s: failed to get_sync(%d)\n", __func__, err);
1124 return err;
1125 }
1126 return 0;
1127}
1128#endif
1129
1130static SIMPLE_DEV_PM_OPS(omap_des_pm_ops, omap_des_suspend, omap_des_resume);
1131
1132static struct platform_driver omap_des_driver = {
1133 .probe = omap_des_probe,
1134 .remove = omap_des_remove,
1135 .driver = {
1136 .name = "omap-des",
1137 .pm = &omap_des_pm_ops,
1138 .of_match_table = of_match_ptr(omap_des_of_match),
1139 },
1140};
1141
1142module_platform_driver(omap_des_driver);
1143
1144MODULE_DESCRIPTION("OMAP DES hw acceleration support.");
1145MODULE_LICENSE("GPL v2");
1146MODULE_AUTHOR("Joel Fernandes <joelf@ti.com>");