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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3* Copyright (C) 2015 Broadcom Corporation
4*
5*/
6/*
7 * DESCRIPTION: The Broadcom iProc RNG200 Driver
8 */
9
10#include <linux/hw_random.h>
11#include <linux/init.h>
12#include <linux/io.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/mod_devicetable.h>
16#include <linux/platform_device.h>
17#include <linux/delay.h>
18
19/* Registers */
20#define RNG_CTRL_OFFSET 0x00
21#define RNG_CTRL_RNG_RBGEN_MASK 0x00001FFF
22#define RNG_CTRL_RNG_RBGEN_ENABLE 0x00000001
23
24#define RNG_SOFT_RESET_OFFSET 0x04
25#define RNG_SOFT_RESET 0x00000001
26
27#define RBG_SOFT_RESET_OFFSET 0x08
28#define RBG_SOFT_RESET 0x00000001
29
30#define RNG_INT_STATUS_OFFSET 0x18
31#define RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK 0x80000000
32#define RNG_INT_STATUS_STARTUP_TRANSITIONS_MET_IRQ_MASK 0x00020000
33#define RNG_INT_STATUS_NIST_FAIL_IRQ_MASK 0x00000020
34#define RNG_INT_STATUS_TOTAL_BITS_COUNT_IRQ_MASK 0x00000001
35
36#define RNG_FIFO_DATA_OFFSET 0x20
37
38#define RNG_FIFO_COUNT_OFFSET 0x24
39#define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK 0x000000FF
40
41struct iproc_rng200_dev {
42 struct hwrng rng;
43 void __iomem *base;
44};
45
46#define to_rng_priv(rng) container_of(rng, struct iproc_rng200_dev, rng)
47
48static void iproc_rng200_enable_set(void __iomem *rng_base, bool enable)
49{
50 u32 val;
51
52 val = ioread32(rng_base + RNG_CTRL_OFFSET);
53 val &= ~RNG_CTRL_RNG_RBGEN_MASK;
54
55 if (enable)
56 val |= RNG_CTRL_RNG_RBGEN_ENABLE;
57
58 iowrite32(val, rng_base + RNG_CTRL_OFFSET);
59}
60
61static void iproc_rng200_restart(void __iomem *rng_base)
62{
63 uint32_t val;
64
65 iproc_rng200_enable_set(rng_base, false);
66
67 /* Clear all interrupt status */
68 iowrite32(0xFFFFFFFFUL, rng_base + RNG_INT_STATUS_OFFSET);
69
70 /* Reset RNG and RBG */
71 val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
72 val |= RBG_SOFT_RESET;
73 iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
74
75 val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
76 val |= RNG_SOFT_RESET;
77 iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
78
79 val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
80 val &= ~RNG_SOFT_RESET;
81 iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
82
83 val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
84 val &= ~RBG_SOFT_RESET;
85 iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
86
87 iproc_rng200_enable_set(rng_base, true);
88}
89
90static int iproc_rng200_read(struct hwrng *rng, void *buf, size_t max,
91 bool wait)
92{
93 struct iproc_rng200_dev *priv = to_rng_priv(rng);
94 uint32_t num_remaining = max;
95 uint32_t status;
96
97 #define MAX_RESETS_PER_READ 1
98 uint32_t num_resets = 0;
99
100 #define MAX_IDLE_TIME (1 * HZ)
101 unsigned long idle_endtime = jiffies + MAX_IDLE_TIME;
102
103 while ((num_remaining > 0) && time_before(jiffies, idle_endtime)) {
104
105 /* Is RNG sane? If not, reset it. */
106 status = ioread32(priv->base + RNG_INT_STATUS_OFFSET);
107 if ((status & (RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK |
108 RNG_INT_STATUS_NIST_FAIL_IRQ_MASK)) != 0) {
109
110 if (num_resets >= MAX_RESETS_PER_READ)
111 return max - num_remaining;
112
113 iproc_rng200_restart(priv->base);
114 num_resets++;
115 }
116
117 /* Are there any random numbers available? */
118 if ((ioread32(priv->base + RNG_FIFO_COUNT_OFFSET) &
119 RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK) > 0) {
120
121 if (num_remaining >= sizeof(uint32_t)) {
122 /* Buffer has room to store entire word */
123 *(uint32_t *)buf = ioread32(priv->base +
124 RNG_FIFO_DATA_OFFSET);
125 buf += sizeof(uint32_t);
126 num_remaining -= sizeof(uint32_t);
127 } else {
128 /* Buffer can only store partial word */
129 uint32_t rnd_number = ioread32(priv->base +
130 RNG_FIFO_DATA_OFFSET);
131 memcpy(buf, &rnd_number, num_remaining);
132 buf += num_remaining;
133 num_remaining = 0;
134 }
135
136 /* Reset the IDLE timeout */
137 idle_endtime = jiffies + MAX_IDLE_TIME;
138 } else {
139 if (!wait)
140 /* Cannot wait, return immediately */
141 return max - num_remaining;
142
143 /* Can wait, give others chance to run */
144 usleep_range(min(num_remaining * 10, 500U), 500);
145 }
146 }
147
148 return max - num_remaining;
149}
150
151static int iproc_rng200_init(struct hwrng *rng)
152{
153 struct iproc_rng200_dev *priv = to_rng_priv(rng);
154
155 iproc_rng200_enable_set(priv->base, true);
156
157 return 0;
158}
159
160static void iproc_rng200_cleanup(struct hwrng *rng)
161{
162 struct iproc_rng200_dev *priv = to_rng_priv(rng);
163
164 iproc_rng200_enable_set(priv->base, false);
165}
166
167static int iproc_rng200_probe(struct platform_device *pdev)
168{
169 struct iproc_rng200_dev *priv;
170 struct device *dev = &pdev->dev;
171 int ret;
172
173 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
174 if (!priv)
175 return -ENOMEM;
176
177 /* Map peripheral */
178 priv->base = devm_platform_ioremap_resource(pdev, 0);
179 if (IS_ERR(priv->base)) {
180 dev_err(dev, "failed to remap rng regs\n");
181 return PTR_ERR(priv->base);
182 }
183
184 dev_set_drvdata(dev, priv);
185
186 priv->rng.name = "iproc-rng200";
187 priv->rng.read = iproc_rng200_read;
188 priv->rng.init = iproc_rng200_init;
189 priv->rng.cleanup = iproc_rng200_cleanup;
190
191 /* Register driver */
192 ret = devm_hwrng_register(dev, &priv->rng);
193 if (ret) {
194 dev_err(dev, "hwrng registration failed\n");
195 return ret;
196 }
197
198 dev_info(dev, "hwrng registered\n");
199
200 return 0;
201}
202
203static int __maybe_unused iproc_rng200_suspend(struct device *dev)
204{
205 struct iproc_rng200_dev *priv = dev_get_drvdata(dev);
206
207 iproc_rng200_cleanup(&priv->rng);
208
209 return 0;
210}
211
212static int __maybe_unused iproc_rng200_resume(struct device *dev)
213{
214 struct iproc_rng200_dev *priv = dev_get_drvdata(dev);
215
216 iproc_rng200_init(&priv->rng);
217
218 return 0;
219}
220
221static const struct dev_pm_ops iproc_rng200_pm_ops = {
222 SET_SYSTEM_SLEEP_PM_OPS(iproc_rng200_suspend, iproc_rng200_resume)
223};
224
225static const struct of_device_id iproc_rng200_of_match[] = {
226 { .compatible = "brcm,bcm2711-rng200", },
227 { .compatible = "brcm,bcm7211-rng200", },
228 { .compatible = "brcm,bcm7278-rng200", },
229 { .compatible = "brcm,iproc-rng200", },
230 {},
231};
232MODULE_DEVICE_TABLE(of, iproc_rng200_of_match);
233
234static struct platform_driver iproc_rng200_driver = {
235 .driver = {
236 .name = "iproc-rng200",
237 .of_match_table = iproc_rng200_of_match,
238 .pm = &iproc_rng200_pm_ops,
239 },
240 .probe = iproc_rng200_probe,
241};
242module_platform_driver(iproc_rng200_driver);
243
244MODULE_AUTHOR("Broadcom");
245MODULE_DESCRIPTION("iProc RNG200 Random Number Generator driver");
246MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3* Copyright (C) 2015 Broadcom Corporation
4*
5*/
6/*
7 * DESCRIPTION: The Broadcom iProc RNG200 Driver
8 */
9
10#include <linux/hw_random.h>
11#include <linux/init.h>
12#include <linux/io.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/of_address.h>
16#include <linux/of_platform.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19
20/* Registers */
21#define RNG_CTRL_OFFSET 0x00
22#define RNG_CTRL_RNG_RBGEN_MASK 0x00001FFF
23#define RNG_CTRL_RNG_RBGEN_ENABLE 0x00000001
24
25#define RNG_SOFT_RESET_OFFSET 0x04
26#define RNG_SOFT_RESET 0x00000001
27
28#define RBG_SOFT_RESET_OFFSET 0x08
29#define RBG_SOFT_RESET 0x00000001
30
31#define RNG_INT_STATUS_OFFSET 0x18
32#define RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK 0x80000000
33#define RNG_INT_STATUS_STARTUP_TRANSITIONS_MET_IRQ_MASK 0x00020000
34#define RNG_INT_STATUS_NIST_FAIL_IRQ_MASK 0x00000020
35#define RNG_INT_STATUS_TOTAL_BITS_COUNT_IRQ_MASK 0x00000001
36
37#define RNG_FIFO_DATA_OFFSET 0x20
38
39#define RNG_FIFO_COUNT_OFFSET 0x24
40#define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK 0x000000FF
41
42struct iproc_rng200_dev {
43 struct hwrng rng;
44 void __iomem *base;
45};
46
47#define to_rng_priv(rng) container_of(rng, struct iproc_rng200_dev, rng)
48
49static void iproc_rng200_enable_set(void __iomem *rng_base, bool enable)
50{
51 u32 val;
52
53 val = ioread32(rng_base + RNG_CTRL_OFFSET);
54 val &= ~RNG_CTRL_RNG_RBGEN_MASK;
55
56 if (enable)
57 val |= RNG_CTRL_RNG_RBGEN_ENABLE;
58
59 iowrite32(val, rng_base + RNG_CTRL_OFFSET);
60}
61
62static void iproc_rng200_restart(void __iomem *rng_base)
63{
64 uint32_t val;
65
66 iproc_rng200_enable_set(rng_base, false);
67
68 /* Clear all interrupt status */
69 iowrite32(0xFFFFFFFFUL, rng_base + RNG_INT_STATUS_OFFSET);
70
71 /* Reset RNG and RBG */
72 val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
73 val |= RBG_SOFT_RESET;
74 iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
75
76 val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
77 val |= RNG_SOFT_RESET;
78 iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
79
80 val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
81 val &= ~RNG_SOFT_RESET;
82 iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
83
84 val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
85 val &= ~RBG_SOFT_RESET;
86 iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
87
88 iproc_rng200_enable_set(rng_base, true);
89}
90
91static int iproc_rng200_read(struct hwrng *rng, void *buf, size_t max,
92 bool wait)
93{
94 struct iproc_rng200_dev *priv = to_rng_priv(rng);
95 uint32_t num_remaining = max;
96 uint32_t status;
97
98 #define MAX_RESETS_PER_READ 1
99 uint32_t num_resets = 0;
100
101 #define MAX_IDLE_TIME (1 * HZ)
102 unsigned long idle_endtime = jiffies + MAX_IDLE_TIME;
103
104 while ((num_remaining > 0) && time_before(jiffies, idle_endtime)) {
105
106 /* Is RNG sane? If not, reset it. */
107 status = ioread32(priv->base + RNG_INT_STATUS_OFFSET);
108 if ((status & (RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK |
109 RNG_INT_STATUS_NIST_FAIL_IRQ_MASK)) != 0) {
110
111 if (num_resets >= MAX_RESETS_PER_READ)
112 return max - num_remaining;
113
114 iproc_rng200_restart(priv->base);
115 num_resets++;
116 }
117
118 /* Are there any random numbers available? */
119 if ((ioread32(priv->base + RNG_FIFO_COUNT_OFFSET) &
120 RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK) > 0) {
121
122 if (num_remaining >= sizeof(uint32_t)) {
123 /* Buffer has room to store entire word */
124 *(uint32_t *)buf = ioread32(priv->base +
125 RNG_FIFO_DATA_OFFSET);
126 buf += sizeof(uint32_t);
127 num_remaining -= sizeof(uint32_t);
128 } else {
129 /* Buffer can only store partial word */
130 uint32_t rnd_number = ioread32(priv->base +
131 RNG_FIFO_DATA_OFFSET);
132 memcpy(buf, &rnd_number, num_remaining);
133 buf += num_remaining;
134 num_remaining = 0;
135 }
136
137 /* Reset the IDLE timeout */
138 idle_endtime = jiffies + MAX_IDLE_TIME;
139 } else {
140 if (!wait)
141 /* Cannot wait, return immediately */
142 return max - num_remaining;
143
144 /* Can wait, give others chance to run */
145 usleep_range(min(num_remaining * 10, 500U), 500);
146 }
147 }
148
149 return max - num_remaining;
150}
151
152static int iproc_rng200_init(struct hwrng *rng)
153{
154 struct iproc_rng200_dev *priv = to_rng_priv(rng);
155
156 iproc_rng200_enable_set(priv->base, true);
157
158 return 0;
159}
160
161static void iproc_rng200_cleanup(struct hwrng *rng)
162{
163 struct iproc_rng200_dev *priv = to_rng_priv(rng);
164
165 iproc_rng200_enable_set(priv->base, false);
166}
167
168static int iproc_rng200_probe(struct platform_device *pdev)
169{
170 struct iproc_rng200_dev *priv;
171 struct device *dev = &pdev->dev;
172 int ret;
173
174 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
175 if (!priv)
176 return -ENOMEM;
177
178 /* Map peripheral */
179 priv->base = devm_platform_ioremap_resource(pdev, 0);
180 if (IS_ERR(priv->base)) {
181 dev_err(dev, "failed to remap rng regs\n");
182 return PTR_ERR(priv->base);
183 }
184
185 priv->rng.name = "iproc-rng200";
186 priv->rng.read = iproc_rng200_read;
187 priv->rng.init = iproc_rng200_init;
188 priv->rng.cleanup = iproc_rng200_cleanup;
189
190 /* Register driver */
191 ret = devm_hwrng_register(dev, &priv->rng);
192 if (ret) {
193 dev_err(dev, "hwrng registration failed\n");
194 return ret;
195 }
196
197 dev_info(dev, "hwrng registered\n");
198
199 return 0;
200}
201
202static const struct of_device_id iproc_rng200_of_match[] = {
203 { .compatible = "brcm,bcm2711-rng200", },
204 { .compatible = "brcm,bcm7211-rng200", },
205 { .compatible = "brcm,bcm7278-rng200", },
206 { .compatible = "brcm,iproc-rng200", },
207 {},
208};
209MODULE_DEVICE_TABLE(of, iproc_rng200_of_match);
210
211static struct platform_driver iproc_rng200_driver = {
212 .driver = {
213 .name = "iproc-rng200",
214 .of_match_table = iproc_rng200_of_match,
215 },
216 .probe = iproc_rng200_probe,
217};
218module_platform_driver(iproc_rng200_driver);
219
220MODULE_AUTHOR("Broadcom");
221MODULE_DESCRIPTION("iProc RNG200 Random Number Generator driver");
222MODULE_LICENSE("GPL v2");