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1/*
2 * RNG driver for AMD RNGs
3 *
4 * Copyright 2005 (c) MontaVista Software, Inc.
5 *
6 * with the majority of the code coming from:
7 *
8 * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
9 * (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
10 *
11 * derived from
12 *
13 * Hardware driver for the AMD 768 Random Number Generator (RNG)
14 * (c) Copyright 2001 Red Hat Inc
15 *
16 * derived from
17 *
18 * Hardware driver for Intel i810 Random Number Generator (RNG)
19 * Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
20 * Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
21 *
22 * This file is licensed under the terms of the GNU General Public
23 * License version 2. This program is licensed "as is" without any
24 * warranty of any kind, whether express or implied.
25 */
26
27#include <linux/delay.h>
28#include <linux/hw_random.h>
29#include <linux/io.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33
34#define DRV_NAME "AMD768-HWRNG"
35
36#define RNGDATA 0x00
37#define RNGDONE 0x04
38#define PMBASE_OFFSET 0xF0
39#define PMBASE_SIZE 8
40
41/*
42 * Data for PCI driver interface
43 *
44 * This data only exists for exporting the supported
45 * PCI ids via MODULE_DEVICE_TABLE. We do not actually
46 * register a pci_driver, because someone else might one day
47 * want to register another driver on the same PCI id.
48 */
49static const struct pci_device_id pci_tbl[] = {
50 { PCI_VDEVICE(AMD, 0x7443), 0, },
51 { PCI_VDEVICE(AMD, 0x746b), 0, },
52 { 0, }, /* terminate list */
53};
54MODULE_DEVICE_TABLE(pci, pci_tbl);
55
56struct amd768_priv {
57 void __iomem *iobase;
58 struct pci_dev *pcidev;
59 u32 pmbase;
60};
61
62static int amd_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
63{
64 u32 *data = buf;
65 struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
66 size_t read = 0;
67 /* We will wait at maximum one time per read */
68 int timeout = max / 4 + 1;
69
70 /*
71 * RNG data is available when RNGDONE is set to 1
72 * New random numbers are generated approximately 128 microseconds
73 * after RNGDATA is read
74 */
75 while (read < max) {
76 if (ioread32(priv->iobase + RNGDONE) == 0) {
77 if (wait) {
78 /* Delay given by datasheet */
79 usleep_range(128, 196);
80 if (timeout-- == 0)
81 return read;
82 } else {
83 return 0;
84 }
85 } else {
86 *data = ioread32(priv->iobase + RNGDATA);
87 data++;
88 read += 4;
89 }
90 }
91
92 return read;
93}
94
95static int amd_rng_init(struct hwrng *rng)
96{
97 struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
98 u8 rnen;
99
100 pci_read_config_byte(priv->pcidev, 0x40, &rnen);
101 rnen |= BIT(7); /* RNG on */
102 pci_write_config_byte(priv->pcidev, 0x40, rnen);
103
104 pci_read_config_byte(priv->pcidev, 0x41, &rnen);
105 rnen |= BIT(7); /* PMIO enable */
106 pci_write_config_byte(priv->pcidev, 0x41, rnen);
107
108 return 0;
109}
110
111static void amd_rng_cleanup(struct hwrng *rng)
112{
113 struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
114 u8 rnen;
115
116 pci_read_config_byte(priv->pcidev, 0x40, &rnen);
117 rnen &= ~BIT(7); /* RNG off */
118 pci_write_config_byte(priv->pcidev, 0x40, rnen);
119}
120
121static struct hwrng amd_rng = {
122 .name = "amd",
123 .init = amd_rng_init,
124 .cleanup = amd_rng_cleanup,
125 .read = amd_rng_read,
126};
127
128static int __init amd_rng_mod_init(void)
129{
130 int err;
131 struct pci_dev *pdev = NULL;
132 const struct pci_device_id *ent;
133 u32 pmbase;
134 struct amd768_priv *priv;
135
136 for_each_pci_dev(pdev) {
137 ent = pci_match_id(pci_tbl, pdev);
138 if (ent)
139 goto found;
140 }
141 /* Device not found. */
142 return -ENODEV;
143
144found:
145 err = pci_read_config_dword(pdev, 0x58, &pmbase);
146 if (err)
147 goto put_dev;
148
149 pmbase &= 0x0000FF00;
150 if (pmbase == 0) {
151 err = -EIO;
152 goto put_dev;
153 }
154
155 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
156 if (!priv) {
157 err = -ENOMEM;
158 goto put_dev;
159 }
160
161 if (!request_region(pmbase + PMBASE_OFFSET, PMBASE_SIZE, DRV_NAME)) {
162 dev_err(&pdev->dev, DRV_NAME " region 0x%x already in use!\n",
163 pmbase + 0xF0);
164 err = -EBUSY;
165 goto out;
166 }
167
168 priv->iobase = ioport_map(pmbase + PMBASE_OFFSET, PMBASE_SIZE);
169 if (!priv->iobase) {
170 pr_err(DRV_NAME "Cannot map ioport\n");
171 err = -EINVAL;
172 goto err_iomap;
173 }
174
175 amd_rng.priv = (unsigned long)priv;
176 priv->pmbase = pmbase;
177 priv->pcidev = pdev;
178
179 pr_info(DRV_NAME " detected\n");
180 err = hwrng_register(&amd_rng);
181 if (err) {
182 pr_err(DRV_NAME " registering failed (%d)\n", err);
183 goto err_hwrng;
184 }
185 return 0;
186
187err_hwrng:
188 ioport_unmap(priv->iobase);
189err_iomap:
190 release_region(pmbase + PMBASE_OFFSET, PMBASE_SIZE);
191out:
192 kfree(priv);
193put_dev:
194 pci_dev_put(pdev);
195 return err;
196}
197
198static void __exit amd_rng_mod_exit(void)
199{
200 struct amd768_priv *priv;
201
202 priv = (struct amd768_priv *)amd_rng.priv;
203
204 hwrng_unregister(&amd_rng);
205
206 ioport_unmap(priv->iobase);
207
208 release_region(priv->pmbase + PMBASE_OFFSET, PMBASE_SIZE);
209
210 pci_dev_put(priv->pcidev);
211
212 kfree(priv);
213}
214
215module_init(amd_rng_mod_init);
216module_exit(amd_rng_mod_exit);
217
218MODULE_AUTHOR("The Linux Kernel team");
219MODULE_DESCRIPTION("H/W RNG driver for AMD chipsets");
220MODULE_LICENSE("GPL");
1/*
2 * RNG driver for AMD RNGs
3 *
4 * Copyright 2005 (c) MontaVista Software, Inc.
5 *
6 * with the majority of the code coming from:
7 *
8 * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
9 * (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
10 *
11 * derived from
12 *
13 * Hardware driver for the AMD 768 Random Number Generator (RNG)
14 * (c) Copyright 2001 Red Hat Inc
15 *
16 * derived from
17 *
18 * Hardware driver for Intel i810 Random Number Generator (RNG)
19 * Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
20 * Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
21 *
22 * This file is licensed under the terms of the GNU General Public
23 * License version 2. This program is licensed "as is" without any
24 * warranty of any kind, whether express or implied.
25 */
26
27#include <linux/delay.h>
28#include <linux/hw_random.h>
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32
33#define DRV_NAME "AMD768-HWRNG"
34
35#define RNGDATA 0x00
36#define RNGDONE 0x04
37#define PMBASE_OFFSET 0xF0
38#define PMBASE_SIZE 8
39
40/*
41 * Data for PCI driver interface
42 *
43 * This data only exists for exporting the supported
44 * PCI ids via MODULE_DEVICE_TABLE. We do not actually
45 * register a pci_driver, because someone else might one day
46 * want to register another driver on the same PCI id.
47 */
48static const struct pci_device_id pci_tbl[] = {
49 { PCI_VDEVICE(AMD, 0x7443), 0, },
50 { PCI_VDEVICE(AMD, 0x746b), 0, },
51 { 0, }, /* terminate list */
52};
53MODULE_DEVICE_TABLE(pci, pci_tbl);
54
55struct amd768_priv {
56 void __iomem *iobase;
57 struct pci_dev *pcidev;
58 u32 pmbase;
59};
60
61static int amd_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
62{
63 u32 *data = buf;
64 struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
65 size_t read = 0;
66 /* We will wait at maximum one time per read */
67 int timeout = max / 4 + 1;
68
69 /*
70 * RNG data is available when RNGDONE is set to 1
71 * New random numbers are generated approximately 128 microseconds
72 * after RNGDATA is read
73 */
74 while (read < max) {
75 if (ioread32(priv->iobase + RNGDONE) == 0) {
76 if (wait) {
77 /* Delay given by datasheet */
78 usleep_range(128, 196);
79 if (timeout-- == 0)
80 return read;
81 } else {
82 return 0;
83 }
84 } else {
85 *data = ioread32(priv->iobase + RNGDATA);
86 data++;
87 read += 4;
88 }
89 }
90
91 return read;
92}
93
94static int amd_rng_init(struct hwrng *rng)
95{
96 struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
97 u8 rnen;
98
99 pci_read_config_byte(priv->pcidev, 0x40, &rnen);
100 rnen |= BIT(7); /* RNG on */
101 pci_write_config_byte(priv->pcidev, 0x40, rnen);
102
103 pci_read_config_byte(priv->pcidev, 0x41, &rnen);
104 rnen |= BIT(7); /* PMIO enable */
105 pci_write_config_byte(priv->pcidev, 0x41, rnen);
106
107 return 0;
108}
109
110static void amd_rng_cleanup(struct hwrng *rng)
111{
112 struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
113 u8 rnen;
114
115 pci_read_config_byte(priv->pcidev, 0x40, &rnen);
116 rnen &= ~BIT(7); /* RNG off */
117 pci_write_config_byte(priv->pcidev, 0x40, rnen);
118}
119
120static struct hwrng amd_rng = {
121 .name = "amd",
122 .init = amd_rng_init,
123 .cleanup = amd_rng_cleanup,
124 .read = amd_rng_read,
125};
126
127static int __init amd_rng_mod_init(void)
128{
129 int err;
130 struct pci_dev *pdev = NULL;
131 const struct pci_device_id *ent;
132 u32 pmbase;
133 struct amd768_priv *priv;
134
135 for_each_pci_dev(pdev) {
136 ent = pci_match_id(pci_tbl, pdev);
137 if (ent)
138 goto found;
139 }
140 /* Device not found. */
141 return -ENODEV;
142
143found:
144 err = pci_read_config_dword(pdev, 0x58, &pmbase);
145 if (err)
146 goto put_dev;
147
148 pmbase &= 0x0000FF00;
149 if (pmbase == 0) {
150 err = -EIO;
151 goto put_dev;
152 }
153
154 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
155 if (!priv) {
156 err = -ENOMEM;
157 goto put_dev;
158 }
159
160 if (!request_region(pmbase + PMBASE_OFFSET, PMBASE_SIZE, DRV_NAME)) {
161 dev_err(&pdev->dev, DRV_NAME " region 0x%x already in use!\n",
162 pmbase + 0xF0);
163 err = -EBUSY;
164 goto out;
165 }
166
167 priv->iobase = ioport_map(pmbase + PMBASE_OFFSET, PMBASE_SIZE);
168 if (!priv->iobase) {
169 pr_err(DRV_NAME "Cannot map ioport\n");
170 err = -EINVAL;
171 goto err_iomap;
172 }
173
174 amd_rng.priv = (unsigned long)priv;
175 priv->pmbase = pmbase;
176 priv->pcidev = pdev;
177
178 pr_info(DRV_NAME " detected\n");
179 err = hwrng_register(&amd_rng);
180 if (err) {
181 pr_err(DRV_NAME " registering failed (%d)\n", err);
182 goto err_hwrng;
183 }
184 return 0;
185
186err_hwrng:
187 ioport_unmap(priv->iobase);
188err_iomap:
189 release_region(pmbase + PMBASE_OFFSET, PMBASE_SIZE);
190out:
191 kfree(priv);
192put_dev:
193 pci_dev_put(pdev);
194 return err;
195}
196
197static void __exit amd_rng_mod_exit(void)
198{
199 struct amd768_priv *priv;
200
201 priv = (struct amd768_priv *)amd_rng.priv;
202
203 hwrng_unregister(&amd_rng);
204
205 ioport_unmap(priv->iobase);
206
207 release_region(priv->pmbase + PMBASE_OFFSET, PMBASE_SIZE);
208
209 pci_dev_put(priv->pcidev);
210
211 kfree(priv);
212}
213
214module_init(amd_rng_mod_init);
215module_exit(amd_rng_mod_exit);
216
217MODULE_AUTHOR("The Linux Kernel team");
218MODULE_DESCRIPTION("H/W RNG driver for AMD chipsets");
219MODULE_LICENSE("GPL");