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1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2020-2021 Microchip Technology Inc */
3
4/dts-v1/;
5
6#include "mpfs.dtsi"
7#include "mpfs-icicle-kit-fabric.dtsi"
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/leds/common.h>
10
11/ {
12 model = "Microchip PolarFire-SoC Icicle Kit";
13 compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
14 "microchip,mpfs";
15
16 aliases {
17 ethernet0 = &mac1;
18 serial0 = &mmuart0;
19 serial1 = &mmuart1;
20 serial2 = &mmuart2;
21 serial3 = &mmuart3;
22 serial4 = &mmuart4;
23 };
24
25 chosen {
26 stdout-path = "serial1:115200n8";
27 };
28
29 leds {
30 compatible = "gpio-leds";
31
32 led-1 {
33 gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
34 color = <LED_COLOR_ID_RED>;
35 label = "led1";
36 };
37
38 led-2 {
39 gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
40 color = <LED_COLOR_ID_RED>;
41 label = "led2";
42 };
43
44 led-3 {
45 gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
46 color = <LED_COLOR_ID_AMBER>;
47 label = "led3";
48 };
49
50 led-4 {
51 gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
52 color = <LED_COLOR_ID_AMBER>;
53 label = "led4";
54 };
55 };
56
57 ddrc_cache_lo: memory@80000000 {
58 device_type = "memory";
59 reg = <0x0 0x80000000 0x0 0x40000000>;
60 status = "okay";
61 };
62
63 ddrc_cache_hi: memory@1040000000 {
64 device_type = "memory";
65 reg = <0x10 0x40000000 0x0 0x40000000>;
66 status = "okay";
67 };
68
69 reserved-memory {
70 #address-cells = <2>;
71 #size-cells = <2>;
72 ranges;
73
74 hss_payload: region@BFC00000 {
75 reg = <0x0 0xBFC00000 0x0 0x400000>;
76 no-map;
77 };
78 };
79};
80
81&core_pwm0 {
82 status = "okay";
83};
84
85&gpio2 {
86 interrupts = <53>, <53>, <53>, <53>,
87 <53>, <53>, <53>, <53>,
88 <53>, <53>, <53>, <53>,
89 <53>, <53>, <53>, <53>,
90 <53>, <53>, <53>, <53>,
91 <53>, <53>, <53>, <53>,
92 <53>, <53>, <53>, <53>,
93 <53>, <53>, <53>, <53>;
94 status = "okay";
95};
96
97&i2c0 {
98 status = "okay";
99};
100
101&i2c1 {
102 status = "okay";
103};
104
105&i2c2 {
106 status = "okay";
107};
108
109&mac0 {
110 phy-mode = "sgmii";
111 phy-handle = <&phy0>;
112 status = "okay";
113};
114
115&mac1 {
116 phy-mode = "sgmii";
117 phy-handle = <&phy1>;
118 status = "okay";
119
120 phy1: ethernet-phy@9 {
121 reg = <9>;
122 };
123
124 phy0: ethernet-phy@8 {
125 reg = <8>;
126 };
127};
128
129&mbox {
130 status = "okay";
131};
132
133&mmc {
134 bus-width = <4>;
135 disable-wp;
136 cap-sd-highspeed;
137 cap-mmc-highspeed;
138 mmc-ddr-1_8v;
139 mmc-hs200-1_8v;
140 sd-uhs-sdr12;
141 sd-uhs-sdr25;
142 sd-uhs-sdr50;
143 sd-uhs-sdr104;
144 status = "okay";
145};
146
147&mmuart1 {
148 status = "okay";
149};
150
151&mmuart2 {
152 status = "okay";
153};
154
155&mmuart3 {
156 status = "okay";
157};
158
159&mmuart4 {
160 status = "okay";
161};
162
163&pcie {
164 status = "okay";
165};
166
167&qspi {
168 status = "okay";
169};
170
171&refclk {
172 clock-frequency = <125000000>;
173};
174
175&refclk_ccc {
176 clock-frequency = <50000000>;
177};
178
179&rtc {
180 status = "okay";
181};
182
183&spi0 {
184 status = "okay";
185};
186
187&spi1 {
188 status = "okay";
189};
190
191&syscontroller {
192 status = "okay";
193};
194
195&syscontroller_qspi {
196 /*
197 * The flash *is* there, but Icicle kits that have engineering sample
198 * silicon (write?) access to this flash to non-functional. The system
199 * controller itself can actually access it, but the MSS cannot write
200 * an image there. Instantiating a coreQSPI in the fabric & connecting
201 * it to the flash instead should work though. Pre-production or later
202 * silicon does not have this issue.
203 */
204 status = "disabled";
205
206 sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT
207 compatible = "jedec,spi-nor";
208 #address-cells = <1>;
209 #size-cells = <1>;
210 spi-max-frequency = <20000000>;
211 spi-rx-bus-width = <1>;
212 reg = <0>;
213 };
214};
215
216&usb {
217 status = "okay";
218 dr_mode = "host";
219};
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2020-2021 Microchip Technology Inc */
3
4/dts-v1/;
5
6#include "mpfs.dtsi"
7#include "mpfs-icicle-kit-fabric.dtsi"
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/leds/common.h>
10
11/* Clock frequency (in Hz) of the rtcclk */
12#define RTCCLK_FREQ 1000000
13
14/ {
15 model = "Microchip PolarFire-SoC Icicle Kit";
16 compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
17 "microchip,mpfs";
18
19 aliases {
20 ethernet0 = &mac1;
21 serial0 = &mmuart0;
22 serial1 = &mmuart1;
23 serial2 = &mmuart2;
24 serial3 = &mmuart3;
25 serial4 = &mmuart4;
26 };
27
28 chosen {
29 stdout-path = "serial1:115200n8";
30 };
31
32 cpus {
33 timebase-frequency = <RTCCLK_FREQ>;
34 };
35
36 leds {
37 compatible = "gpio-leds";
38
39 led-1 {
40 gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
41 color = <LED_COLOR_ID_RED>;
42 label = "led1";
43 };
44
45 led-2 {
46 gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
47 color = <LED_COLOR_ID_RED>;
48 label = "led2";
49 };
50
51 led-3 {
52 gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
53 color = <LED_COLOR_ID_AMBER>;
54 label = "led3";
55 };
56
57 led-4 {
58 gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
59 color = <LED_COLOR_ID_AMBER>;
60 label = "led4";
61 };
62 };
63
64 ddrc_cache_lo: memory@80000000 {
65 device_type = "memory";
66 reg = <0x0 0x80000000 0x0 0x40000000>;
67 status = "okay";
68 };
69
70 ddrc_cache_hi: memory@1040000000 {
71 device_type = "memory";
72 reg = <0x10 0x40000000 0x0 0x40000000>;
73 status = "okay";
74 };
75
76 reserved-memory {
77 #address-cells = <2>;
78 #size-cells = <2>;
79 ranges;
80
81 hss_payload: region@BFC00000 {
82 reg = <0x0 0xBFC00000 0x0 0x400000>;
83 no-map;
84 };
85 };
86};
87
88&core_pwm0 {
89 status = "okay";
90};
91
92&gpio2 {
93 interrupts = <53>, <53>, <53>, <53>,
94 <53>, <53>, <53>, <53>,
95 <53>, <53>, <53>, <53>,
96 <53>, <53>, <53>, <53>,
97 <53>, <53>, <53>, <53>,
98 <53>, <53>, <53>, <53>,
99 <53>, <53>, <53>, <53>,
100 <53>, <53>, <53>, <53>;
101 status = "okay";
102};
103
104&i2c0 {
105 status = "okay";
106};
107
108&i2c1 {
109 status = "okay";
110};
111
112&i2c2 {
113 status = "okay";
114};
115
116&mac0 {
117 phy-mode = "sgmii";
118 phy-handle = <&phy0>;
119 status = "okay";
120};
121
122&mac1 {
123 phy-mode = "sgmii";
124 phy-handle = <&phy1>;
125 status = "okay";
126
127 phy1: ethernet-phy@9 {
128 reg = <9>;
129 };
130
131 phy0: ethernet-phy@8 {
132 reg = <8>;
133 };
134};
135
136&mbox {
137 status = "okay";
138};
139
140&mmc {
141 bus-width = <4>;
142 disable-wp;
143 cap-sd-highspeed;
144 cap-mmc-highspeed;
145 mmc-ddr-1_8v;
146 mmc-hs200-1_8v;
147 sd-uhs-sdr12;
148 sd-uhs-sdr25;
149 sd-uhs-sdr50;
150 sd-uhs-sdr104;
151 status = "okay";
152};
153
154&mmuart1 {
155 status = "okay";
156};
157
158&mmuart2 {
159 status = "okay";
160};
161
162&mmuart3 {
163 status = "okay";
164};
165
166&mmuart4 {
167 status = "okay";
168};
169
170&pcie {
171 status = "okay";
172};
173
174&qspi {
175 status = "okay";
176};
177
178&refclk {
179 clock-frequency = <125000000>;
180};
181
182&refclk_ccc {
183 clock-frequency = <50000000>;
184};
185
186&rtc {
187 status = "okay";
188};
189
190&spi0 {
191 status = "okay";
192};
193
194&spi1 {
195 status = "okay";
196};
197
198&syscontroller {
199 status = "okay";
200};
201
202&usb {
203 status = "okay";
204 dr_mode = "host";
205};