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1/* ppc.h -- Header file for PowerPC opcode table
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
4
5This file is part of GDB, GAS, and the GNU binutils.
6
7GDB, GAS, and the GNU binutils are free software; you can redistribute
8them and/or modify them under the terms of the GNU General Public
9License as published by the Free Software Foundation; either version
101, or (at your option) any later version.
11
12GDB, GAS, and the GNU binutils are distributed in the hope that they
13will be useful, but WITHOUT ANY WARRANTY; without even the implied
14warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15the GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with this file; see the file COPYING. If not, write to the Free
19Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
20
21#ifndef PPC_H
22#define PPC_H
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28typedef uint64_t ppc_cpu_t;
29
30/* The opcode table is an array of struct powerpc_opcode. */
31
32struct powerpc_opcode
33{
34 /* The opcode name. */
35 const char *name;
36
37 /* The opcode itself. Those bits which will be filled in with
38 operands are zeroes. */
39 unsigned long opcode;
40
41 /* The opcode mask. This is used by the disassembler. This is a
42 mask containing ones indicating those bits which must match the
43 opcode field, and zeroes indicating those bits which need not
44 match (and are presumably filled in by operands). */
45 unsigned long mask;
46
47 /* One bit flags for the opcode. These are used to indicate which
48 specific processors support the instructions. The defined values
49 are listed below. */
50 ppc_cpu_t flags;
51
52 /* One bit flags for the opcode. These are used to indicate which
53 specific processors no longer support the instructions. The defined
54 values are listed below. */
55 ppc_cpu_t deprecated;
56
57 /* An array of operand codes. Each code is an index into the
58 operand table. They appear in the order which the operands must
59 appear in assembly code, and are terminated by a zero. */
60 unsigned char operands[8];
61};
62
63/* The table itself is sorted by major opcode number, and is otherwise
64 in the order in which the disassembler should consider
65 instructions. */
66extern const struct powerpc_opcode powerpc_opcodes[];
67extern const int powerpc_num_opcodes;
68extern const struct powerpc_opcode vle_opcodes[];
69extern const int vle_num_opcodes;
70
71/* Values defined for the flags field of a struct powerpc_opcode. */
72
73/* Opcode is defined for the PowerPC architecture. */
74#define PPC_OPCODE_PPC 1
75
76/* Opcode is defined for the POWER (RS/6000) architecture. */
77#define PPC_OPCODE_POWER 2
78
79/* Opcode is defined for the POWER2 (Rios 2) architecture. */
80#define PPC_OPCODE_POWER2 4
81
82/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
83 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
84 but it also supports many additional POWER instructions. */
85#define PPC_OPCODE_601 8
86
87/* Opcode is supported in both the Power and PowerPC architectures
88 (ie, compiler's -mcpu=common or assembler's -mcom). More than just
89 the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
90 and PPC_OPCODE_POWER2 because many instructions changed mnemonics
91 between POWER and POWERPC. */
92#define PPC_OPCODE_COMMON 0x10
93
94/* Opcode is supported for any Power or PowerPC platform (this is
95 for the assembler's -many option, and it eliminates duplicates). */
96#define PPC_OPCODE_ANY 0x20
97
98/* Opcode is only defined on 64 bit architectures. */
99#define PPC_OPCODE_64 0x40
100
101/* Opcode is supported as part of the 64-bit bridge. */
102#define PPC_OPCODE_64_BRIDGE 0x80
103
104/* Opcode is supported by Altivec Vector Unit */
105#define PPC_OPCODE_ALTIVEC 0x100
106
107/* Opcode is supported by PowerPC 403 processor. */
108#define PPC_OPCODE_403 0x200
109
110/* Opcode is supported by PowerPC BookE processor. */
111#define PPC_OPCODE_BOOKE 0x400
112
113/* Opcode is supported by PowerPC 440 processor. */
114#define PPC_OPCODE_440 0x800
115
116/* Opcode is only supported by Power4 architecture. */
117#define PPC_OPCODE_POWER4 0x1000
118
119/* Opcode is only supported by Power7 architecture. */
120#define PPC_OPCODE_POWER7 0x2000
121
122/* Opcode is only supported by e500x2 Core. */
123#define PPC_OPCODE_SPE 0x4000
124
125/* Opcode is supported by e500x2 Integer select APU. */
126#define PPC_OPCODE_ISEL 0x8000
127
128/* Opcode is an e500 SPE floating point instruction. */
129#define PPC_OPCODE_EFS 0x10000
130
131/* Opcode is supported by branch locking APU. */
132#define PPC_OPCODE_BRLOCK 0x20000
133
134/* Opcode is supported by performance monitor APU. */
135#define PPC_OPCODE_PMR 0x40000
136
137/* Opcode is supported by cache locking APU. */
138#define PPC_OPCODE_CACHELCK 0x80000
139
140/* Opcode is supported by machine check APU. */
141#define PPC_OPCODE_RFMCI 0x100000
142
143/* Opcode is only supported by Power5 architecture. */
144#define PPC_OPCODE_POWER5 0x200000
145
146/* Opcode is supported by PowerPC e300 family. */
147#define PPC_OPCODE_E300 0x400000
148
149/* Opcode is only supported by Power6 architecture. */
150#define PPC_OPCODE_POWER6 0x800000
151
152/* Opcode is only supported by PowerPC Cell family. */
153#define PPC_OPCODE_CELL 0x1000000
154
155/* Opcode is supported by CPUs with paired singles support. */
156#define PPC_OPCODE_PPCPS 0x2000000
157
158/* Opcode is supported by Power E500MC */
159#define PPC_OPCODE_E500MC 0x4000000
160
161/* Opcode is supported by PowerPC 405 processor. */
162#define PPC_OPCODE_405 0x8000000
163
164/* Opcode is supported by Vector-Scalar (VSX) Unit */
165#define PPC_OPCODE_VSX 0x10000000
166
167/* Opcode is supported by A2. */
168#define PPC_OPCODE_A2 0x20000000
169
170/* Opcode is supported by PowerPC 476 processor. */
171#define PPC_OPCODE_476 0x40000000
172
173/* Opcode is supported by AppliedMicro Titan core */
174#define PPC_OPCODE_TITAN 0x80000000
175
176/* Opcode which is supported by the e500 family */
177#define PPC_OPCODE_E500 0x100000000ull
178
179/* Opcode is supported by Extended Altivec Vector Unit */
180#define PPC_OPCODE_ALTIVEC2 0x200000000ull
181
182/* Opcode is supported by Power E6500 */
183#define PPC_OPCODE_E6500 0x400000000ull
184
185/* Opcode is supported by Thread management APU */
186#define PPC_OPCODE_TMR 0x800000000ull
187
188/* Opcode which is supported by the VLE extension. */
189#define PPC_OPCODE_VLE 0x1000000000ull
190
191/* Opcode is only supported by Power8 architecture. */
192#define PPC_OPCODE_POWER8 0x2000000000ull
193
194/* Opcode which is supported by the Hardware Transactional Memory extension. */
195/* Currently, this is the same as the POWER8 mask. If another cpu comes out
196 that isn't a superset of POWER8, we can define this to its own mask. */
197#define PPC_OPCODE_HTM PPC_OPCODE_POWER8
198
199/* Opcode is supported by ppc750cl. */
200#define PPC_OPCODE_750 0x4000000000ull
201
202/* Opcode is supported by ppc7450. */
203#define PPC_OPCODE_7450 0x8000000000ull
204
205/* Opcode is supported by ppc821/850/860. */
206#define PPC_OPCODE_860 0x10000000000ull
207
208/* Opcode is only supported by Power9 architecture. */
209#define PPC_OPCODE_POWER9 0x20000000000ull
210
211/* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08. */
212#define PPC_OPCODE_VSX3 0x40000000000ull
213
214 /* Opcode is supported by e200z4. */
215#define PPC_OPCODE_E200Z4 0x80000000000ull
216
217/* A macro to extract the major opcode from an instruction. */
218#define PPC_OP(i) (((i) >> 26) & 0x3f)
219
220/* A macro to determine if the instruction is a 2-byte VLE insn. */
221#define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
222
223/* A macro to extract the major opcode from a VLE instruction. */
224#define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
225
226/* A macro to convert a VLE opcode to a VLE opcode segment. */
227#define VLE_OP_TO_SEG(i) ((i) >> 1)
228
229/* The operands table is an array of struct powerpc_operand. */
230
231struct powerpc_operand
232{
233 /* A bitmask of bits in the operand. */
234 unsigned int bitm;
235
236 /* The shift operation to be applied to the operand. No shift
237 is made if this is zero. For positive values, the operand
238 is shifted left by SHIFT. For negative values, the operand
239 is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate
240 that BITM and SHIFT cannot be used to determine where the
241 operand goes in the insn. */
242 int shift;
243
244 /* Insertion function. This is used by the assembler. To insert an
245 operand value into an instruction, check this field.
246
247 If it is NULL, execute
248 if (o->shift >= 0)
249 i |= (op & o->bitm) << o->shift;
250 else
251 i |= (op & o->bitm) >> -o->shift;
252 (i is the instruction which we are filling in, o is a pointer to
253 this structure, and op is the operand value).
254
255 If this field is not NULL, then simply call it with the
256 instruction and the operand value. It will return the new value
257 of the instruction. If the ERRMSG argument is not NULL, then if
258 the operand value is illegal, *ERRMSG will be set to a warning
259 string (the operand will be inserted in any case). If the
260 operand value is legal, *ERRMSG will be unchanged (most operands
261 can accept any value). */
262 unsigned long (*insert)
263 (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
264
265 /* Extraction function. This is used by the disassembler. To
266 extract this operand type from an instruction, check this field.
267
268 If it is NULL, compute
269 if (o->shift >= 0)
270 op = (i >> o->shift) & o->bitm;
271 else
272 op = (i << -o->shift) & o->bitm;
273 if ((o->flags & PPC_OPERAND_SIGNED) != 0)
274 sign_extend (op);
275 (i is the instruction, o is a pointer to this structure, and op
276 is the result).
277
278 If this field is not NULL, then simply call it with the
279 instruction value. It will return the value of the operand. If
280 the INVALID argument is not NULL, *INVALID will be set to
281 non-zero if this operand type can not actually be extracted from
282 this operand (i.e., the instruction does not match). If the
283 operand is valid, *INVALID will not be changed. */
284 long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
285
286 /* One bit syntax flags. */
287 unsigned long flags;
288};
289
290/* Elements in the table are retrieved by indexing with values from
291 the operands field of the powerpc_opcodes table. */
292
293extern const struct powerpc_operand powerpc_operands[];
294extern const unsigned int num_powerpc_operands;
295
296/* Use with the shift field of a struct powerpc_operand to indicate
297 that BITM and SHIFT cannot be used to determine where the operand
298 goes in the insn. */
299#define PPC_OPSHIFT_INV (-1U << 31)
300
301/* Values defined for the flags field of a struct powerpc_operand. */
302
303/* This operand takes signed values. */
304#define PPC_OPERAND_SIGNED (0x1)
305
306/* This operand takes signed values, but also accepts a full positive
307 range of values when running in 32 bit mode. That is, if bits is
308 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
309 this flag is ignored. */
310#define PPC_OPERAND_SIGNOPT (0x2)
311
312/* This operand does not actually exist in the assembler input. This
313 is used to support extended mnemonics such as mr, for which two
314 operands fields are identical. The assembler should call the
315 insert function with any op value. The disassembler should call
316 the extract function, ignore the return value, and check the value
317 placed in the valid argument. */
318#define PPC_OPERAND_FAKE (0x4)
319
320/* The next operand should be wrapped in parentheses rather than
321 separated from this one by a comma. This is used for the load and
322 store instructions which want their operands to look like
323 reg,displacement(reg)
324 */
325#define PPC_OPERAND_PARENS (0x8)
326
327/* This operand may use the symbolic names for the CR fields, which
328 are
329 lt 0 gt 1 eq 2 so 3 un 3
330 cr0 0 cr1 1 cr2 2 cr3 3
331 cr4 4 cr5 5 cr6 6 cr7 7
332 These may be combined arithmetically, as in cr2*4+gt. These are
333 only supported on the PowerPC, not the POWER. */
334#define PPC_OPERAND_CR_BIT (0x10)
335
336/* This operand names a register. The disassembler uses this to print
337 register names with a leading 'r'. */
338#define PPC_OPERAND_GPR (0x20)
339
340/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
341#define PPC_OPERAND_GPR_0 (0x40)
342
343/* This operand names a floating point register. The disassembler
344 prints these with a leading 'f'. */
345#define PPC_OPERAND_FPR (0x80)
346
347/* This operand is a relative branch displacement. The disassembler
348 prints these symbolically if possible. */
349#define PPC_OPERAND_RELATIVE (0x100)
350
351/* This operand is an absolute branch address. The disassembler
352 prints these symbolically if possible. */
353#define PPC_OPERAND_ABSOLUTE (0x200)
354
355/* This operand is optional, and is zero if omitted. This is used for
356 example, in the optional BF field in the comparison instructions. The
357 assembler must count the number of operands remaining on the line,
358 and the number of operands remaining for the opcode, and decide
359 whether this operand is present or not. The disassembler should
360 print this operand out only if it is not zero. */
361#define PPC_OPERAND_OPTIONAL (0x400)
362
363/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
364 is omitted, then for the next operand use this operand value plus
365 1, ignoring the next operand field for the opcode. This wretched
366 hack is needed because the Power rotate instructions can take
367 either 4 or 5 operands. The disassembler should print this operand
368 out regardless of the PPC_OPERAND_OPTIONAL field. */
369#define PPC_OPERAND_NEXT (0x800)
370
371/* This operand should be regarded as a negative number for the
372 purposes of overflow checking (i.e., the normal most negative
373 number is disallowed and one more than the normal most positive
374 number is allowed). This flag will only be set for a signed
375 operand. */
376#define PPC_OPERAND_NEGATIVE (0x1000)
377
378/* This operand names a vector unit register. The disassembler
379 prints these with a leading 'v'. */
380#define PPC_OPERAND_VR (0x2000)
381
382/* This operand is for the DS field in a DS form instruction. */
383#define PPC_OPERAND_DS (0x4000)
384
385/* This operand is for the DQ field in a DQ form instruction. */
386#define PPC_OPERAND_DQ (0x8000)
387
388/* Valid range of operand is 0..n rather than 0..n-1. */
389#define PPC_OPERAND_PLUS1 (0x10000)
390
391/* Xilinx APU and FSL related operands */
392#define PPC_OPERAND_FSL (0x20000)
393#define PPC_OPERAND_FCR (0x40000)
394#define PPC_OPERAND_UDI (0x80000)
395
396/* This operand names a vector-scalar unit register. The disassembler
397 prints these with a leading 'vs'. */
398#define PPC_OPERAND_VSR (0x100000)
399
400/* This is a CR FIELD that does not use symbolic names. */
401#define PPC_OPERAND_CR_REG (0x200000)
402
403/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
404 is omitted, then the value it should use for the operand is stored
405 in the SHIFT field of the immediatly following operand field. */
406#define PPC_OPERAND_OPTIONAL_VALUE (0x400000)
407
408/* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is
409 only optional when generating 32-bit code. */
410#define PPC_OPERAND_OPTIONAL32 (0x800000)
411
412/* The POWER and PowerPC assemblers use a few macros. We keep them
413 with the operands table for simplicity. The macro table is an
414 array of struct powerpc_macro. */
415
416struct powerpc_macro
417{
418 /* The macro name. */
419 const char *name;
420
421 /* The number of operands the macro takes. */
422 unsigned int operands;
423
424 /* One bit flags for the opcode. These are used to indicate which
425 specific processors support the instructions. The values are the
426 same as those for the struct powerpc_opcode flags field. */
427 ppc_cpu_t flags;
428
429 /* A format string to turn the macro into a normal instruction.
430 Each %N in the string is replaced with operand number N (zero
431 based). */
432 const char *format;
433};
434
435extern const struct powerpc_macro powerpc_macros[];
436extern const int powerpc_num_macros;
437
438static inline long
439ppc_optional_operand_value (const struct powerpc_operand *operand)
440{
441 if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)
442 return (operand+1)->shift;
443 return 0;
444}
445
446#ifdef __cplusplus
447}
448#endif
449
450#endif /* PPC_H */
1/* ppc.h -- Header file for PowerPC opcode table
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
4
5This file is part of GDB, GAS, and the GNU binutils.
6
7GDB, GAS, and the GNU binutils are free software; you can redistribute
8them and/or modify them under the terms of the GNU General Public
9License as published by the Free Software Foundation; either version
101, or (at your option) any later version.
11
12GDB, GAS, and the GNU binutils are distributed in the hope that they
13will be useful, but WITHOUT ANY WARRANTY; without even the implied
14warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15the GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with this file; see the file COPYING. If not, write to the Free
19Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
20
21#ifndef PPC_H
22#define PPC_H
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28typedef uint64_t ppc_cpu_t;
29
30/* The opcode table is an array of struct powerpc_opcode. */
31
32struct powerpc_opcode
33{
34 /* The opcode name. */
35 const char *name;
36
37 /* The opcode itself. Those bits which will be filled in with
38 operands are zeroes. */
39 unsigned long opcode;
40
41 /* The opcode mask. This is used by the disassembler. This is a
42 mask containing ones indicating those bits which must match the
43 opcode field, and zeroes indicating those bits which need not
44 match (and are presumably filled in by operands). */
45 unsigned long mask;
46
47 /* One bit flags for the opcode. These are used to indicate which
48 specific processors support the instructions. The defined values
49 are listed below. */
50 ppc_cpu_t flags;
51
52 /* One bit flags for the opcode. These are used to indicate which
53 specific processors no longer support the instructions. The defined
54 values are listed below. */
55 ppc_cpu_t deprecated;
56
57 /* An array of operand codes. Each code is an index into the
58 operand table. They appear in the order which the operands must
59 appear in assembly code, and are terminated by a zero. */
60 unsigned char operands[8];
61};
62
63/* The table itself is sorted by major opcode number, and is otherwise
64 in the order in which the disassembler should consider
65 instructions. */
66extern const struct powerpc_opcode powerpc_opcodes[];
67extern const int powerpc_num_opcodes;
68extern const struct powerpc_opcode vle_opcodes[];
69extern const int vle_num_opcodes;
70
71/* Values defined for the flags field of a struct powerpc_opcode. */
72
73/* Opcode is defined for the PowerPC architecture. */
74#define PPC_OPCODE_PPC 1
75
76/* Opcode is defined for the POWER (RS/6000) architecture. */
77#define PPC_OPCODE_POWER 2
78
79/* Opcode is defined for the POWER2 (Rios 2) architecture. */
80#define PPC_OPCODE_POWER2 4
81
82/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
83 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
84 but it also supports many additional POWER instructions. */
85#define PPC_OPCODE_601 8
86
87/* Opcode is supported in both the Power and PowerPC architectures
88 (ie, compiler's -mcpu=common or assembler's -mcom). More than just
89 the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
90 and PPC_OPCODE_POWER2 because many instructions changed mnemonics
91 between POWER and POWERPC. */
92#define PPC_OPCODE_COMMON 0x10
93
94/* Opcode is supported for any Power or PowerPC platform (this is
95 for the assembler's -many option, and it eliminates duplicates). */
96#define PPC_OPCODE_ANY 0x20
97
98/* Opcode is only defined on 64 bit architectures. */
99#define PPC_OPCODE_64 0x40
100
101/* Opcode is supported as part of the 64-bit bridge. */
102#define PPC_OPCODE_64_BRIDGE 0x80
103
104/* Opcode is supported by Altivec Vector Unit */
105#define PPC_OPCODE_ALTIVEC 0x100
106
107/* Opcode is supported by PowerPC 403 processor. */
108#define PPC_OPCODE_403 0x200
109
110/* Opcode is supported by PowerPC BookE processor. */
111#define PPC_OPCODE_BOOKE 0x400
112
113/* Opcode is supported by PowerPC 440 processor. */
114#define PPC_OPCODE_440 0x800
115
116/* Opcode is only supported by Power4 architecture. */
117#define PPC_OPCODE_POWER4 0x1000
118
119/* Opcode is only supported by Power7 architecture. */
120#define PPC_OPCODE_POWER7 0x2000
121
122/* Opcode is only supported by e500x2 Core. */
123#define PPC_OPCODE_SPE 0x4000
124
125/* Opcode is supported by e500x2 Integer select APU. */
126#define PPC_OPCODE_ISEL 0x8000
127
128/* Opcode is an e500 SPE floating point instruction. */
129#define PPC_OPCODE_EFS 0x10000
130
131/* Opcode is supported by branch locking APU. */
132#define PPC_OPCODE_BRLOCK 0x20000
133
134/* Opcode is supported by performance monitor APU. */
135#define PPC_OPCODE_PMR 0x40000
136
137/* Opcode is supported by cache locking APU. */
138#define PPC_OPCODE_CACHELCK 0x80000
139
140/* Opcode is supported by machine check APU. */
141#define PPC_OPCODE_RFMCI 0x100000
142
143/* Opcode is only supported by Power5 architecture. */
144#define PPC_OPCODE_POWER5 0x200000
145
146/* Opcode is supported by PowerPC e300 family. */
147#define PPC_OPCODE_E300 0x400000
148
149/* Opcode is only supported by Power6 architecture. */
150#define PPC_OPCODE_POWER6 0x800000
151
152/* Opcode is only supported by PowerPC Cell family. */
153#define PPC_OPCODE_CELL 0x1000000
154
155/* Opcode is supported by CPUs with paired singles support. */
156#define PPC_OPCODE_PPCPS 0x2000000
157
158/* Opcode is supported by Power E500MC */
159#define PPC_OPCODE_E500MC 0x4000000
160
161/* Opcode is supported by PowerPC 405 processor. */
162#define PPC_OPCODE_405 0x8000000
163
164/* Opcode is supported by Vector-Scalar (VSX) Unit */
165#define PPC_OPCODE_VSX 0x10000000
166
167/* Opcode is supported by A2. */
168#define PPC_OPCODE_A2 0x20000000
169
170/* Opcode is supported by PowerPC 476 processor. */
171#define PPC_OPCODE_476 0x40000000
172
173/* Opcode is supported by AppliedMicro Titan core */
174#define PPC_OPCODE_TITAN 0x80000000
175
176/* Opcode which is supported by the e500 family */
177#define PPC_OPCODE_E500 0x100000000ull
178
179/* Opcode is supported by Extended Altivec Vector Unit */
180#define PPC_OPCODE_ALTIVEC2 0x200000000ull
181
182/* Opcode is supported by Power E6500 */
183#define PPC_OPCODE_E6500 0x400000000ull
184
185/* Opcode is supported by Thread management APU */
186#define PPC_OPCODE_TMR 0x800000000ull
187
188/* Opcode which is supported by the VLE extension. */
189#define PPC_OPCODE_VLE 0x1000000000ull
190
191/* Opcode is only supported by Power8 architecture. */
192#define PPC_OPCODE_POWER8 0x2000000000ull
193
194/* Opcode which is supported by the Hardware Transactional Memory extension. */
195/* Currently, this is the same as the POWER8 mask. If another cpu comes out
196 that isn't a superset of POWER8, we can define this to its own mask. */
197#define PPC_OPCODE_HTM PPC_OPCODE_POWER8
198
199/* Opcode is supported by ppc750cl. */
200#define PPC_OPCODE_750 0x4000000000ull
201
202/* Opcode is supported by ppc7450. */
203#define PPC_OPCODE_7450 0x8000000000ull
204
205/* Opcode is supported by ppc821/850/860. */
206#define PPC_OPCODE_860 0x10000000000ull
207
208/* Opcode is only supported by Power9 architecture. */
209#define PPC_OPCODE_POWER9 0x20000000000ull
210
211/* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08. */
212#define PPC_OPCODE_VSX3 0x40000000000ull
213
214 /* Opcode is supported by e200z4. */
215#define PPC_OPCODE_E200Z4 0x80000000000ull
216
217/* A macro to extract the major opcode from an instruction. */
218#define PPC_OP(i) (((i) >> 26) & 0x3f)
219
220/* A macro to determine if the instruction is a 2-byte VLE insn. */
221#define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
222
223/* A macro to extract the major opcode from a VLE instruction. */
224#define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
225
226/* A macro to convert a VLE opcode to a VLE opcode segment. */
227#define VLE_OP_TO_SEG(i) ((i) >> 1)
228
229/* The operands table is an array of struct powerpc_operand. */
230
231struct powerpc_operand
232{
233 /* A bitmask of bits in the operand. */
234 unsigned int bitm;
235
236 /* The shift operation to be applied to the operand. No shift
237 is made if this is zero. For positive values, the operand
238 is shifted left by SHIFT. For negative values, the operand
239 is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate
240 that BITM and SHIFT cannot be used to determine where the
241 operand goes in the insn. */
242 int shift;
243
244 /* Insertion function. This is used by the assembler. To insert an
245 operand value into an instruction, check this field.
246
247 If it is NULL, execute
248 if (o->shift >= 0)
249 i |= (op & o->bitm) << o->shift;
250 else
251 i |= (op & o->bitm) >> -o->shift;
252 (i is the instruction which we are filling in, o is a pointer to
253 this structure, and op is the operand value).
254
255 If this field is not NULL, then simply call it with the
256 instruction and the operand value. It will return the new value
257 of the instruction. If the ERRMSG argument is not NULL, then if
258 the operand value is illegal, *ERRMSG will be set to a warning
259 string (the operand will be inserted in any case). If the
260 operand value is legal, *ERRMSG will be unchanged (most operands
261 can accept any value). */
262 unsigned long (*insert)
263 (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
264
265 /* Extraction function. This is used by the disassembler. To
266 extract this operand type from an instruction, check this field.
267
268 If it is NULL, compute
269 if (o->shift >= 0)
270 op = (i >> o->shift) & o->bitm;
271 else
272 op = (i << -o->shift) & o->bitm;
273 if ((o->flags & PPC_OPERAND_SIGNED) != 0)
274 sign_extend (op);
275 (i is the instruction, o is a pointer to this structure, and op
276 is the result).
277
278 If this field is not NULL, then simply call it with the
279 instruction value. It will return the value of the operand. If
280 the INVALID argument is not NULL, *INVALID will be set to
281 non-zero if this operand type can not actually be extracted from
282 this operand (i.e., the instruction does not match). If the
283 operand is valid, *INVALID will not be changed. */
284 long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
285
286 /* One bit syntax flags. */
287 unsigned long flags;
288};
289
290/* Elements in the table are retrieved by indexing with values from
291 the operands field of the powerpc_opcodes table. */
292
293extern const struct powerpc_operand powerpc_operands[];
294extern const unsigned int num_powerpc_operands;
295
296/* Use with the shift field of a struct powerpc_operand to indicate
297 that BITM and SHIFT cannot be used to determine where the operand
298 goes in the insn. */
299#define PPC_OPSHIFT_INV (-1U << 31)
300
301/* Values defined for the flags field of a struct powerpc_operand. */
302
303/* This operand takes signed values. */
304#define PPC_OPERAND_SIGNED (0x1)
305
306/* This operand takes signed values, but also accepts a full positive
307 range of values when running in 32 bit mode. That is, if bits is
308 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
309 this flag is ignored. */
310#define PPC_OPERAND_SIGNOPT (0x2)
311
312/* This operand does not actually exist in the assembler input. This
313 is used to support extended mnemonics such as mr, for which two
314 operands fields are identical. The assembler should call the
315 insert function with any op value. The disassembler should call
316 the extract function, ignore the return value, and check the value
317 placed in the valid argument. */
318#define PPC_OPERAND_FAKE (0x4)
319
320/* The next operand should be wrapped in parentheses rather than
321 separated from this one by a comma. This is used for the load and
322 store instructions which want their operands to look like
323 reg,displacement(reg)
324 */
325#define PPC_OPERAND_PARENS (0x8)
326
327/* This operand may use the symbolic names for the CR fields, which
328 are
329 lt 0 gt 1 eq 2 so 3 un 3
330 cr0 0 cr1 1 cr2 2 cr3 3
331 cr4 4 cr5 5 cr6 6 cr7 7
332 These may be combined arithmetically, as in cr2*4+gt. These are
333 only supported on the PowerPC, not the POWER. */
334#define PPC_OPERAND_CR_BIT (0x10)
335
336/* This operand names a register. The disassembler uses this to print
337 register names with a leading 'r'. */
338#define PPC_OPERAND_GPR (0x20)
339
340/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
341#define PPC_OPERAND_GPR_0 (0x40)
342
343/* This operand names a floating point register. The disassembler
344 prints these with a leading 'f'. */
345#define PPC_OPERAND_FPR (0x80)
346
347/* This operand is a relative branch displacement. The disassembler
348 prints these symbolically if possible. */
349#define PPC_OPERAND_RELATIVE (0x100)
350
351/* This operand is an absolute branch address. The disassembler
352 prints these symbolically if possible. */
353#define PPC_OPERAND_ABSOLUTE (0x200)
354
355/* This operand is optional, and is zero if omitted. This is used for
356 example, in the optional BF field in the comparison instructions. The
357 assembler must count the number of operands remaining on the line,
358 and the number of operands remaining for the opcode, and decide
359 whether this operand is present or not. The disassembler should
360 print this operand out only if it is not zero. */
361#define PPC_OPERAND_OPTIONAL (0x400)
362
363/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
364 is omitted, then for the next operand use this operand value plus
365 1, ignoring the next operand field for the opcode. This wretched
366 hack is needed because the Power rotate instructions can take
367 either 4 or 5 operands. The disassembler should print this operand
368 out regardless of the PPC_OPERAND_OPTIONAL field. */
369#define PPC_OPERAND_NEXT (0x800)
370
371/* This operand should be regarded as a negative number for the
372 purposes of overflow checking (i.e., the normal most negative
373 number is disallowed and one more than the normal most positive
374 number is allowed). This flag will only be set for a signed
375 operand. */
376#define PPC_OPERAND_NEGATIVE (0x1000)
377
378/* This operand names a vector unit register. The disassembler
379 prints these with a leading 'v'. */
380#define PPC_OPERAND_VR (0x2000)
381
382/* This operand is for the DS field in a DS form instruction. */
383#define PPC_OPERAND_DS (0x4000)
384
385/* This operand is for the DQ field in a DQ form instruction. */
386#define PPC_OPERAND_DQ (0x8000)
387
388/* Valid range of operand is 0..n rather than 0..n-1. */
389#define PPC_OPERAND_PLUS1 (0x10000)
390
391/* Xilinx APU and FSL related operands */
392#define PPC_OPERAND_FSL (0x20000)
393#define PPC_OPERAND_FCR (0x40000)
394#define PPC_OPERAND_UDI (0x80000)
395
396/* This operand names a vector-scalar unit register. The disassembler
397 prints these with a leading 'vs'. */
398#define PPC_OPERAND_VSR (0x100000)
399
400/* This is a CR FIELD that does not use symbolic names. */
401#define PPC_OPERAND_CR_REG (0x200000)
402
403/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
404 is omitted, then the value it should use for the operand is stored
405 in the SHIFT field of the immediatly following operand field. */
406#define PPC_OPERAND_OPTIONAL_VALUE (0x400000)
407
408/* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is
409 only optional when generating 32-bit code. */
410#define PPC_OPERAND_OPTIONAL32 (0x800000)
411
412/* The POWER and PowerPC assemblers use a few macros. We keep them
413 with the operands table for simplicity. The macro table is an
414 array of struct powerpc_macro. */
415
416struct powerpc_macro
417{
418 /* The macro name. */
419 const char *name;
420
421 /* The number of operands the macro takes. */
422 unsigned int operands;
423
424 /* One bit flags for the opcode. These are used to indicate which
425 specific processors support the instructions. The values are the
426 same as those for the struct powerpc_opcode flags field. */
427 ppc_cpu_t flags;
428
429 /* A format string to turn the macro into a normal instruction.
430 Each %N in the string is replaced with operand number N (zero
431 based). */
432 const char *format;
433};
434
435extern const struct powerpc_macro powerpc_macros[];
436extern const int powerpc_num_macros;
437
438static inline long
439ppc_optional_operand_value (const struct powerpc_operand *operand)
440{
441 if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)
442 return (operand+1)->shift;
443 return 0;
444}
445
446#ifdef __cplusplus
447}
448#endif
449
450#endif /* PPC_H */