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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/* *********************************************************************
3 * SB1250 Board Support Package
4 *
5 * Memory Controller constants File: sb1250_mc.h
6 *
7 * This module contains constants and macros useful for
8 * programming the memory controller.
9 *
10 * SB1250 specification level: User's manual 1/02/02
11 *
12 *********************************************************************
13 *
14 * Copyright 2000, 2001, 2002, 2003
15 * Broadcom Corporation. All rights reserved.
16 *
17 ********************************************************************* */
18
19
20#ifndef _SB1250_MC_H
21#define _SB1250_MC_H
22
23#include <asm/sibyte/sb1250_defs.h>
24
25/*
26 * Memory Channel Config Register (table 6-14)
27 */
28
29#define S_MC_RESERVED0 0
30#define M_MC_RESERVED0 _SB_MAKEMASK(8, S_MC_RESERVED0)
31
32#define S_MC_CHANNEL_SEL 8
33#define M_MC_CHANNEL_SEL _SB_MAKEMASK(8, S_MC_CHANNEL_SEL)
34#define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x, S_MC_CHANNEL_SEL)
35#define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x, S_MC_CHANNEL_SEL, M_MC_CHANNEL_SEL)
36
37#define S_MC_BANK0_MAP 16
38#define M_MC_BANK0_MAP _SB_MAKEMASK(4, S_MC_BANK0_MAP)
39#define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK0_MAP)
40#define G_MC_BANK0_MAP(x) _SB_GETVALUE(x, S_MC_BANK0_MAP, M_MC_BANK0_MAP)
41
42#define K_MC_BANK0_MAP_DEFAULT 0x00
43#define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT)
44
45#define S_MC_BANK1_MAP 20
46#define M_MC_BANK1_MAP _SB_MAKEMASK(4, S_MC_BANK1_MAP)
47#define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK1_MAP)
48#define G_MC_BANK1_MAP(x) _SB_GETVALUE(x, S_MC_BANK1_MAP, M_MC_BANK1_MAP)
49
50#define K_MC_BANK1_MAP_DEFAULT 0x08
51#define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT)
52
53#define S_MC_BANK2_MAP 24
54#define M_MC_BANK2_MAP _SB_MAKEMASK(4, S_MC_BANK2_MAP)
55#define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK2_MAP)
56#define G_MC_BANK2_MAP(x) _SB_GETVALUE(x, S_MC_BANK2_MAP, M_MC_BANK2_MAP)
57
58#define K_MC_BANK2_MAP_DEFAULT 0x09
59#define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT)
60
61#define S_MC_BANK3_MAP 28
62#define M_MC_BANK3_MAP _SB_MAKEMASK(4, S_MC_BANK3_MAP)
63#define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK3_MAP)
64#define G_MC_BANK3_MAP(x) _SB_GETVALUE(x, S_MC_BANK3_MAP, M_MC_BANK3_MAP)
65
66#define K_MC_BANK3_MAP_DEFAULT 0x0C
67#define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT)
68
69#define M_MC_RESERVED1 _SB_MAKEMASK(8, 32)
70
71#define S_MC_QUEUE_SIZE 40
72#define M_MC_QUEUE_SIZE _SB_MAKEMASK(4, S_MC_QUEUE_SIZE)
73#define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x, S_MC_QUEUE_SIZE)
74#define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x, S_MC_QUEUE_SIZE, M_MC_QUEUE_SIZE)
75#define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A)
76
77#define S_MC_AGE_LIMIT 44
78#define M_MC_AGE_LIMIT _SB_MAKEMASK(4, S_MC_AGE_LIMIT)
79#define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x, S_MC_AGE_LIMIT)
80#define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x, S_MC_AGE_LIMIT, M_MC_AGE_LIMIT)
81#define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8)
82
83#define S_MC_WR_LIMIT 48
84#define M_MC_WR_LIMIT _SB_MAKEMASK(4, S_MC_WR_LIMIT)
85#define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x, S_MC_WR_LIMIT)
86#define G_MC_WR_LIMIT(x) _SB_GETVALUE(x, S_MC_WR_LIMIT, M_MC_WR_LIMIT)
87#define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5)
88
89#define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52)
90
91#define M_MC_RESERVED2 _SB_MAKEMASK(3, 53)
92
93#define S_MC_CS_MODE 56
94#define M_MC_CS_MODE _SB_MAKEMASK(4, S_MC_CS_MODE)
95#define V_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_MC_CS_MODE)
96#define G_MC_CS_MODE(x) _SB_GETVALUE(x, S_MC_CS_MODE, M_MC_CS_MODE)
97
98#define K_MC_CS_MODE_MSB_CS 0
99#define K_MC_CS_MODE_INTLV_CS 15
100#define K_MC_CS_MODE_MIXED_CS_10 12
101#define K_MC_CS_MODE_MIXED_CS_30 6
102#define K_MC_CS_MODE_MIXED_CS_32 3
103
104#define V_MC_CS_MODE_MSB_CS V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS)
105#define V_MC_CS_MODE_INTLV_CS V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS)
106#define V_MC_CS_MODE_MIXED_CS_10 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10)
107#define V_MC_CS_MODE_MIXED_CS_30 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30)
108#define V_MC_CS_MODE_MIXED_CS_32 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32)
109
110#define M_MC_ECC_DISABLE _SB_MAKEMASK1(60)
111#define M_MC_BERR_DISABLE _SB_MAKEMASK1(61)
112#define M_MC_FORCE_SEQ _SB_MAKEMASK1(62)
113#define M_MC_DEBUG _SB_MAKEMASK1(63)
114
115#define V_MC_CONFIG_DEFAULT V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \
116 V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT | \
117 V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | V_MC_CHANNEL_SEL(0) | \
118 M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT
119
120
121/*
122 * Memory clock config register (Table 6-15)
123 *
124 * Note: this field has been updated to be consistent with the errata to 0.2
125 */
126
127#define S_MC_CLK_RATIO 0
128#define M_MC_CLK_RATIO _SB_MAKEMASK(4, S_MC_CLK_RATIO)
129#define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_MC_CLK_RATIO)
130#define G_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_MC_CLK_RATIO, M_MC_CLK_RATIO)
131
132#define K_MC_CLK_RATIO_2X 4
133#define K_MC_CLK_RATIO_25X 5
134#define K_MC_CLK_RATIO_3X 6
135#define K_MC_CLK_RATIO_35X 7
136#define K_MC_CLK_RATIO_4X 8
137#define K_MC_CLK_RATIO_45X 9
138
139#define V_MC_CLK_RATIO_2X V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X)
140#define V_MC_CLK_RATIO_25X V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X)
141#define V_MC_CLK_RATIO_3X V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X)
142#define V_MC_CLK_RATIO_35X V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X)
143#define V_MC_CLK_RATIO_4X V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X)
144#define V_MC_CLK_RATIO_45X V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X)
145#define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X
146
147#define S_MC_REF_RATE 8
148#define M_MC_REF_RATE _SB_MAKEMASK(8, S_MC_REF_RATE)
149#define V_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_MC_REF_RATE)
150#define G_MC_REF_RATE(x) _SB_GETVALUE(x, S_MC_REF_RATE, M_MC_REF_RATE)
151
152#define K_MC_REF_RATE_100MHz 0x62
153#define K_MC_REF_RATE_133MHz 0x81
154#define K_MC_REF_RATE_200MHz 0xC4
155
156#define V_MC_REF_RATE_100MHz V_MC_REF_RATE(K_MC_REF_RATE_100MHz)
157#define V_MC_REF_RATE_133MHz V_MC_REF_RATE(K_MC_REF_RATE_133MHz)
158#define V_MC_REF_RATE_200MHz V_MC_REF_RATE(K_MC_REF_RATE_200MHz)
159#define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz
160
161#define S_MC_CLOCK_DRIVE 16
162#define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4, S_MC_CLOCK_DRIVE)
163#define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x, S_MC_CLOCK_DRIVE)
164#define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x, S_MC_CLOCK_DRIVE, M_MC_CLOCK_DRIVE)
165#define V_MC_CLOCK_DRIVE_DEFAULT V_MC_CLOCK_DRIVE(0xF)
166
167#define S_MC_DATA_DRIVE 20
168#define M_MC_DATA_DRIVE _SB_MAKEMASK(4, S_MC_DATA_DRIVE)
169#define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x, S_MC_DATA_DRIVE)
170#define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x, S_MC_DATA_DRIVE, M_MC_DATA_DRIVE)
171#define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0)
172
173#define S_MC_ADDR_DRIVE 24
174#define M_MC_ADDR_DRIVE _SB_MAKEMASK(4, S_MC_ADDR_DRIVE)
175#define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x, S_MC_ADDR_DRIVE)
176#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x, S_MC_ADDR_DRIVE, M_MC_ADDR_DRIVE)
177#define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0)
178
179#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
180#define M_MC_REF_DISABLE _SB_MAKEMASK1(30)
181#endif /* 1250 PASS3 || 112x PASS1 */
182
183#define M_MC_DLL_BYPASS _SB_MAKEMASK1(31)
184
185#define S_MC_DQI_SKEW 32
186#define M_MC_DQI_SKEW _SB_MAKEMASK(8, S_MC_DQI_SKEW)
187#define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQI_SKEW)
188#define G_MC_DQI_SKEW(x) _SB_GETVALUE(x, S_MC_DQI_SKEW, M_MC_DQI_SKEW)
189#define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0)
190
191#define S_MC_DQO_SKEW 40
192#define M_MC_DQO_SKEW _SB_MAKEMASK(8, S_MC_DQO_SKEW)
193#define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQO_SKEW)
194#define G_MC_DQO_SKEW(x) _SB_GETVALUE(x, S_MC_DQO_SKEW, M_MC_DQO_SKEW)
195#define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0)
196
197#define S_MC_ADDR_SKEW 48
198#define M_MC_ADDR_SKEW _SB_MAKEMASK(8, S_MC_ADDR_SKEW)
199#define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x, S_MC_ADDR_SKEW)
200#define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x, S_MC_ADDR_SKEW, M_MC_ADDR_SKEW)
201#define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F)
202
203#define S_MC_DLL_DEFAULT 56
204#define M_MC_DLL_DEFAULT _SB_MAKEMASK(8, S_MC_DLL_DEFAULT)
205#define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_MC_DLL_DEFAULT)
206#define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_MC_DLL_DEFAULT, M_MC_DLL_DEFAULT)
207#define V_MC_DLL_DEFAULT_DEFAULT V_MC_DLL_DEFAULT(0x10)
208
209#define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT | \
210 V_MC_ADDR_SKEW_DEFAULT | \
211 V_MC_DQO_SKEW_DEFAULT | \
212 V_MC_DQI_SKEW_DEFAULT | \
213 V_MC_ADDR_DRIVE_DEFAULT | \
214 V_MC_DATA_DRIVE_DEFAULT | \
215 V_MC_CLOCK_DRIVE_DEFAULT | \
216 V_MC_REF_RATE_DEFAULT
217
218
219
220/*
221 * DRAM Command Register (Table 6-13)
222 */
223
224#define S_MC_COMMAND 0
225#define M_MC_COMMAND _SB_MAKEMASK(4, S_MC_COMMAND)
226#define V_MC_COMMAND(x) _SB_MAKEVALUE(x, S_MC_COMMAND)
227#define G_MC_COMMAND(x) _SB_GETVALUE(x, S_MC_COMMAND, M_MC_COMMAND)
228
229#define K_MC_COMMAND_EMRS 0
230#define K_MC_COMMAND_MRS 1
231#define K_MC_COMMAND_PRE 2
232#define K_MC_COMMAND_AR 3
233#define K_MC_COMMAND_SETRFSH 4
234#define K_MC_COMMAND_CLRRFSH 5
235#define K_MC_COMMAND_SETPWRDN 6
236#define K_MC_COMMAND_CLRPWRDN 7
237
238#define V_MC_COMMAND_EMRS V_MC_COMMAND(K_MC_COMMAND_EMRS)
239#define V_MC_COMMAND_MRS V_MC_COMMAND(K_MC_COMMAND_MRS)
240#define V_MC_COMMAND_PRE V_MC_COMMAND(K_MC_COMMAND_PRE)
241#define V_MC_COMMAND_AR V_MC_COMMAND(K_MC_COMMAND_AR)
242#define V_MC_COMMAND_SETRFSH V_MC_COMMAND(K_MC_COMMAND_SETRFSH)
243#define V_MC_COMMAND_CLRRFSH V_MC_COMMAND(K_MC_COMMAND_CLRRFSH)
244#define V_MC_COMMAND_SETPWRDN V_MC_COMMAND(K_MC_COMMAND_SETPWRDN)
245#define V_MC_COMMAND_CLRPWRDN V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN)
246
247#define M_MC_CS0 _SB_MAKEMASK1(4)
248#define M_MC_CS1 _SB_MAKEMASK1(5)
249#define M_MC_CS2 _SB_MAKEMASK1(6)
250#define M_MC_CS3 _SB_MAKEMASK1(7)
251
252/*
253 * DRAM Mode Register (Table 6-14)
254 */
255
256#define S_MC_EMODE 0
257#define M_MC_EMODE _SB_MAKEMASK(15, S_MC_EMODE)
258#define V_MC_EMODE(x) _SB_MAKEVALUE(x, S_MC_EMODE)
259#define G_MC_EMODE(x) _SB_GETVALUE(x, S_MC_EMODE, M_MC_EMODE)
260#define V_MC_EMODE_DEFAULT V_MC_EMODE(0)
261
262#define S_MC_MODE 16
263#define M_MC_MODE _SB_MAKEMASK(15, S_MC_MODE)
264#define V_MC_MODE(x) _SB_MAKEVALUE(x, S_MC_MODE)
265#define G_MC_MODE(x) _SB_GETVALUE(x, S_MC_MODE, M_MC_MODE)
266#define V_MC_MODE_DEFAULT V_MC_MODE(0x22)
267
268#define S_MC_DRAM_TYPE 32
269#define M_MC_DRAM_TYPE _SB_MAKEMASK(3, S_MC_DRAM_TYPE)
270#define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_MC_DRAM_TYPE)
271#define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_MC_DRAM_TYPE, M_MC_DRAM_TYPE)
272
273#define K_MC_DRAM_TYPE_JEDEC 0
274#define K_MC_DRAM_TYPE_FCRAM 1
275#define K_MC_DRAM_TYPE_SGRAM 2
276
277#define V_MC_DRAM_TYPE_JEDEC V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC)
278#define V_MC_DRAM_TYPE_FCRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM)
279#define V_MC_DRAM_TYPE_SGRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM)
280
281#define M_MC_EXTERNALDECODE _SB_MAKEMASK1(35)
282
283#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
284#define M_MC_PRE_ON_A8 _SB_MAKEMASK1(36)
285#define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(37)
286#endif /* 1250 PASS3 || 112x PASS1 */
287
288
289
290/*
291 * SDRAM Timing Register (Table 6-15)
292 */
293
294#define M_MC_w2rIDLE_TWOCYCLES _SB_MAKEMASK1(60)
295#define M_MC_r2wIDLE_TWOCYCLES _SB_MAKEMASK1(61)
296#define M_MC_r2rIDLE_TWOCYCLES _SB_MAKEMASK1(62)
297
298#define S_MC_tFIFO 56
299#define M_MC_tFIFO _SB_MAKEMASK(4, S_MC_tFIFO)
300#define V_MC_tFIFO(x) _SB_MAKEVALUE(x, S_MC_tFIFO)
301#define G_MC_tFIFO(x) _SB_GETVALUE(x, S_MC_tFIFO, M_MC_tFIFO)
302#define K_MC_tFIFO_DEFAULT 1
303#define V_MC_tFIFO_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT)
304
305#define S_MC_tRFC 52
306#define M_MC_tRFC _SB_MAKEMASK(4, S_MC_tRFC)
307#define V_MC_tRFC(x) _SB_MAKEVALUE(x, S_MC_tRFC)
308#define G_MC_tRFC(x) _SB_GETVALUE(x, S_MC_tRFC, M_MC_tRFC)
309#define K_MC_tRFC_DEFAULT 12
310#define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT)
311
312#if SIBYTE_HDR_FEATURE(1250, PASS3)
313#define M_MC_tRFC_PLUS16 _SB_MAKEMASK1(51) /* 1250C3 and later. */
314#endif
315
316#define S_MC_tCwCr 40
317#define M_MC_tCwCr _SB_MAKEMASK(4, S_MC_tCwCr)
318#define V_MC_tCwCr(x) _SB_MAKEVALUE(x, S_MC_tCwCr)
319#define G_MC_tCwCr(x) _SB_GETVALUE(x, S_MC_tCwCr, M_MC_tCwCr)
320#define K_MC_tCwCr_DEFAULT 4
321#define V_MC_tCwCr_DEFAULT V_MC_tCwCr(K_MC_tCwCr_DEFAULT)
322
323#define S_MC_tRCr 28
324#define M_MC_tRCr _SB_MAKEMASK(4, S_MC_tRCr)
325#define V_MC_tRCr(x) _SB_MAKEVALUE(x, S_MC_tRCr)
326#define G_MC_tRCr(x) _SB_GETVALUE(x, S_MC_tRCr, M_MC_tRCr)
327#define K_MC_tRCr_DEFAULT 9
328#define V_MC_tRCr_DEFAULT V_MC_tRCr(K_MC_tRCr_DEFAULT)
329
330#define S_MC_tRCw 24
331#define M_MC_tRCw _SB_MAKEMASK(4, S_MC_tRCw)
332#define V_MC_tRCw(x) _SB_MAKEVALUE(x, S_MC_tRCw)
333#define G_MC_tRCw(x) _SB_GETVALUE(x, S_MC_tRCw, M_MC_tRCw)
334#define K_MC_tRCw_DEFAULT 10
335#define V_MC_tRCw_DEFAULT V_MC_tRCw(K_MC_tRCw_DEFAULT)
336
337#define S_MC_tRRD 20
338#define M_MC_tRRD _SB_MAKEMASK(4, S_MC_tRRD)
339#define V_MC_tRRD(x) _SB_MAKEVALUE(x, S_MC_tRRD)
340#define G_MC_tRRD(x) _SB_GETVALUE(x, S_MC_tRRD, M_MC_tRRD)
341#define K_MC_tRRD_DEFAULT 2
342#define V_MC_tRRD_DEFAULT V_MC_tRRD(K_MC_tRRD_DEFAULT)
343
344#define S_MC_tRP 16
345#define M_MC_tRP _SB_MAKEMASK(4, S_MC_tRP)
346#define V_MC_tRP(x) _SB_MAKEVALUE(x, S_MC_tRP)
347#define G_MC_tRP(x) _SB_GETVALUE(x, S_MC_tRP, M_MC_tRP)
348#define K_MC_tRP_DEFAULT 4
349#define V_MC_tRP_DEFAULT V_MC_tRP(K_MC_tRP_DEFAULT)
350
351#define S_MC_tCwD 8
352#define M_MC_tCwD _SB_MAKEMASK(4, S_MC_tCwD)
353#define V_MC_tCwD(x) _SB_MAKEVALUE(x, S_MC_tCwD)
354#define G_MC_tCwD(x) _SB_GETVALUE(x, S_MC_tCwD, M_MC_tCwD)
355#define K_MC_tCwD_DEFAULT 1
356#define V_MC_tCwD_DEFAULT V_MC_tCwD(K_MC_tCwD_DEFAULT)
357
358#define M_tCrDh _SB_MAKEMASK1(7)
359#define M_MC_tCrDh M_tCrDh
360
361#define S_MC_tCrD 4
362#define M_MC_tCrD _SB_MAKEMASK(3, S_MC_tCrD)
363#define V_MC_tCrD(x) _SB_MAKEVALUE(x, S_MC_tCrD)
364#define G_MC_tCrD(x) _SB_GETVALUE(x, S_MC_tCrD, M_MC_tCrD)
365#define K_MC_tCrD_DEFAULT 2
366#define V_MC_tCrD_DEFAULT V_MC_tCrD(K_MC_tCrD_DEFAULT)
367
368#define S_MC_tRCD 0
369#define M_MC_tRCD _SB_MAKEMASK(4, S_MC_tRCD)
370#define V_MC_tRCD(x) _SB_MAKEVALUE(x, S_MC_tRCD)
371#define G_MC_tRCD(x) _SB_GETVALUE(x, S_MC_tRCD, M_MC_tRCD)
372#define K_MC_tRCD_DEFAULT 3
373#define V_MC_tRCD_DEFAULT V_MC_tRCD(K_MC_tRCD_DEFAULT)
374
375#define V_MC_TIMING_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \
376 V_MC_tRFC(K_MC_tRFC_DEFAULT) | \
377 V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \
378 V_MC_tRCr(K_MC_tRCr_DEFAULT) | \
379 V_MC_tRCw(K_MC_tRCw_DEFAULT) | \
380 V_MC_tRRD(K_MC_tRRD_DEFAULT) | \
381 V_MC_tRP(K_MC_tRP_DEFAULT) | \
382 V_MC_tCwD(K_MC_tCwD_DEFAULT) | \
383 V_MC_tCrD(K_MC_tCrD_DEFAULT) | \
384 V_MC_tRCD(K_MC_tRCD_DEFAULT) | \
385 M_MC_r2rIDLE_TWOCYCLES
386
387/*
388 * Errata says these are not the default
389 * M_MC_w2rIDLE_TWOCYCLES | \
390 * M_MC_r2wIDLE_TWOCYCLES | \
391 */
392
393
394/*
395 * Chip Select Start Address Register (Table 6-17)
396 */
397
398#define S_MC_CS0_START 0
399#define M_MC_CS0_START _SB_MAKEMASK(16, S_MC_CS0_START)
400#define V_MC_CS0_START(x) _SB_MAKEVALUE(x, S_MC_CS0_START)
401#define G_MC_CS0_START(x) _SB_GETVALUE(x, S_MC_CS0_START, M_MC_CS0_START)
402
403#define S_MC_CS1_START 16
404#define M_MC_CS1_START _SB_MAKEMASK(16, S_MC_CS1_START)
405#define V_MC_CS1_START(x) _SB_MAKEVALUE(x, S_MC_CS1_START)
406#define G_MC_CS1_START(x) _SB_GETVALUE(x, S_MC_CS1_START, M_MC_CS1_START)
407
408#define S_MC_CS2_START 32
409#define M_MC_CS2_START _SB_MAKEMASK(16, S_MC_CS2_START)
410#define V_MC_CS2_START(x) _SB_MAKEVALUE(x, S_MC_CS2_START)
411#define G_MC_CS2_START(x) _SB_GETVALUE(x, S_MC_CS2_START, M_MC_CS2_START)
412
413#define S_MC_CS3_START 48
414#define M_MC_CS3_START _SB_MAKEMASK(16, S_MC_CS3_START)
415#define V_MC_CS3_START(x) _SB_MAKEVALUE(x, S_MC_CS3_START)
416#define G_MC_CS3_START(x) _SB_GETVALUE(x, S_MC_CS3_START, M_MC_CS3_START)
417
418/*
419 * Chip Select End Address Register (Table 6-18)
420 */
421
422#define S_MC_CS0_END 0
423#define M_MC_CS0_END _SB_MAKEMASK(16, S_MC_CS0_END)
424#define V_MC_CS0_END(x) _SB_MAKEVALUE(x, S_MC_CS0_END)
425#define G_MC_CS0_END(x) _SB_GETVALUE(x, S_MC_CS0_END, M_MC_CS0_END)
426
427#define S_MC_CS1_END 16
428#define M_MC_CS1_END _SB_MAKEMASK(16, S_MC_CS1_END)
429#define V_MC_CS1_END(x) _SB_MAKEVALUE(x, S_MC_CS1_END)
430#define G_MC_CS1_END(x) _SB_GETVALUE(x, S_MC_CS1_END, M_MC_CS1_END)
431
432#define S_MC_CS2_END 32
433#define M_MC_CS2_END _SB_MAKEMASK(16, S_MC_CS2_END)
434#define V_MC_CS2_END(x) _SB_MAKEVALUE(x, S_MC_CS2_END)
435#define G_MC_CS2_END(x) _SB_GETVALUE(x, S_MC_CS2_END, M_MC_CS2_END)
436
437#define S_MC_CS3_END 48
438#define M_MC_CS3_END _SB_MAKEMASK(16, S_MC_CS3_END)
439#define V_MC_CS3_END(x) _SB_MAKEVALUE(x, S_MC_CS3_END)
440#define G_MC_CS3_END(x) _SB_GETVALUE(x, S_MC_CS3_END, M_MC_CS3_END)
441
442/*
443 * Chip Select Interleave Register (Table 6-19)
444 */
445
446#define S_MC_INTLV_RESERVED 0
447#define M_MC_INTLV_RESERVED _SB_MAKEMASK(5, S_MC_INTLV_RESERVED)
448
449#define S_MC_INTERLEAVE 7
450#define M_MC_INTERLEAVE _SB_MAKEMASK(18, S_MC_INTERLEAVE)
451#define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x, S_MC_INTERLEAVE)
452
453#define S_MC_INTLV_MBZ 25
454#define M_MC_INTLV_MBZ _SB_MAKEMASK(39, S_MC_INTLV_MBZ)
455
456/*
457 * Row Address Bits Register (Table 6-20)
458 */
459
460#define S_MC_RAS_RESERVED 0
461#define M_MC_RAS_RESERVED _SB_MAKEMASK(5, S_MC_RAS_RESERVED)
462
463#define S_MC_RAS_SELECT 12
464#define M_MC_RAS_SELECT _SB_MAKEMASK(25, S_MC_RAS_SELECT)
465#define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_RAS_SELECT)
466
467#define S_MC_RAS_MBZ 37
468#define M_MC_RAS_MBZ _SB_MAKEMASK(27, S_MC_RAS_MBZ)
469
470
471/*
472 * Column Address Bits Register (Table 6-21)
473 */
474
475#define S_MC_CAS_RESERVED 0
476#define M_MC_CAS_RESERVED _SB_MAKEMASK(5, S_MC_CAS_RESERVED)
477
478#define S_MC_CAS_SELECT 5
479#define M_MC_CAS_SELECT _SB_MAKEMASK(18, S_MC_CAS_SELECT)
480#define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_CAS_SELECT)
481
482#define S_MC_CAS_MBZ 23
483#define M_MC_CAS_MBZ _SB_MAKEMASK(41, S_MC_CAS_MBZ)
484
485
486/*
487 * Bank Address Bits Register (Table 6-22)
488 */
489
490#define S_MC_BA_RESERVED 0
491#define M_MC_BA_RESERVED _SB_MAKEMASK(5, S_MC_BA_RESERVED)
492
493#define S_MC_BA_SELECT 5
494#define M_MC_BA_SELECT _SB_MAKEMASK(20, S_MC_BA_SELECT)
495#define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x, S_MC_BA_SELECT)
496
497#define S_MC_BA_MBZ 25
498#define M_MC_BA_MBZ _SB_MAKEMASK(39, S_MC_BA_MBZ)
499
500/*
501 * Chip Select Attribute Register (Table 6-23)
502 */
503
504#define K_MC_CS_ATTR_CLOSED 0
505#define K_MC_CS_ATTR_CASCHECK 1
506#define K_MC_CS_ATTR_HINT 2
507#define K_MC_CS_ATTR_OPEN 3
508
509#define S_MC_CS0_PAGE 0
510#define M_MC_CS0_PAGE _SB_MAKEMASK(2, S_MC_CS0_PAGE)
511#define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS0_PAGE)
512#define G_MC_CS0_PAGE(x) _SB_GETVALUE(x, S_MC_CS0_PAGE, M_MC_CS0_PAGE)
513
514#define S_MC_CS1_PAGE 16
515#define M_MC_CS1_PAGE _SB_MAKEMASK(2, S_MC_CS1_PAGE)
516#define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS1_PAGE)
517#define G_MC_CS1_PAGE(x) _SB_GETVALUE(x, S_MC_CS1_PAGE, M_MC_CS1_PAGE)
518
519#define S_MC_CS2_PAGE 32
520#define M_MC_CS2_PAGE _SB_MAKEMASK(2, S_MC_CS2_PAGE)
521#define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS2_PAGE)
522#define G_MC_CS2_PAGE(x) _SB_GETVALUE(x, S_MC_CS2_PAGE, M_MC_CS2_PAGE)
523
524#define S_MC_CS3_PAGE 48
525#define M_MC_CS3_PAGE _SB_MAKEMASK(2, S_MC_CS3_PAGE)
526#define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS3_PAGE)
527#define G_MC_CS3_PAGE(x) _SB_GETVALUE(x, S_MC_CS3_PAGE, M_MC_CS3_PAGE)
528
529/*
530 * ECC Test ECC Register (Table 6-25)
531 */
532
533#define S_MC_ECC_INVERT 0
534#define M_MC_ECC_INVERT _SB_MAKEMASK(8, S_MC_ECC_INVERT)
535
536
537#endif
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/* *********************************************************************
3 * SB1250 Board Support Package
4 *
5 * Memory Controller constants File: sb1250_mc.h
6 *
7 * This module contains constants and macros useful for
8 * programming the memory controller.
9 *
10 * SB1250 specification level: User's manual 1/02/02
11 *
12 *********************************************************************
13 *
14 * Copyright 2000, 2001, 2002, 2003
15 * Broadcom Corporation. All rights reserved.
16 *
17 ********************************************************************* */
18
19
20#ifndef _SB1250_MC_H
21#define _SB1250_MC_H
22
23#include <asm/sibyte/sb1250_defs.h>
24
25/*
26 * Memory Channel Config Register (table 6-14)
27 */
28
29#define S_MC_RESERVED0 0
30#define M_MC_RESERVED0 _SB_MAKEMASK(8, S_MC_RESERVED0)
31
32#define S_MC_CHANNEL_SEL 8
33#define M_MC_CHANNEL_SEL _SB_MAKEMASK(8, S_MC_CHANNEL_SEL)
34#define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x, S_MC_CHANNEL_SEL)
35#define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x, S_MC_CHANNEL_SEL, M_MC_CHANNEL_SEL)
36
37#define S_MC_BANK0_MAP 16
38#define M_MC_BANK0_MAP _SB_MAKEMASK(4, S_MC_BANK0_MAP)
39#define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK0_MAP)
40#define G_MC_BANK0_MAP(x) _SB_GETVALUE(x, S_MC_BANK0_MAP, M_MC_BANK0_MAP)
41
42#define K_MC_BANK0_MAP_DEFAULT 0x00
43#define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT)
44
45#define S_MC_BANK1_MAP 20
46#define M_MC_BANK1_MAP _SB_MAKEMASK(4, S_MC_BANK1_MAP)
47#define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK1_MAP)
48#define G_MC_BANK1_MAP(x) _SB_GETVALUE(x, S_MC_BANK1_MAP, M_MC_BANK1_MAP)
49
50#define K_MC_BANK1_MAP_DEFAULT 0x08
51#define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT)
52
53#define S_MC_BANK2_MAP 24
54#define M_MC_BANK2_MAP _SB_MAKEMASK(4, S_MC_BANK2_MAP)
55#define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK2_MAP)
56#define G_MC_BANK2_MAP(x) _SB_GETVALUE(x, S_MC_BANK2_MAP, M_MC_BANK2_MAP)
57
58#define K_MC_BANK2_MAP_DEFAULT 0x09
59#define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT)
60
61#define S_MC_BANK3_MAP 28
62#define M_MC_BANK3_MAP _SB_MAKEMASK(4, S_MC_BANK3_MAP)
63#define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK3_MAP)
64#define G_MC_BANK3_MAP(x) _SB_GETVALUE(x, S_MC_BANK3_MAP, M_MC_BANK3_MAP)
65
66#define K_MC_BANK3_MAP_DEFAULT 0x0C
67#define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT)
68
69#define M_MC_RESERVED1 _SB_MAKEMASK(8, 32)
70
71#define S_MC_QUEUE_SIZE 40
72#define M_MC_QUEUE_SIZE _SB_MAKEMASK(4, S_MC_QUEUE_SIZE)
73#define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x, S_MC_QUEUE_SIZE)
74#define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x, S_MC_QUEUE_SIZE, M_MC_QUEUE_SIZE)
75#define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A)
76
77#define S_MC_AGE_LIMIT 44
78#define M_MC_AGE_LIMIT _SB_MAKEMASK(4, S_MC_AGE_LIMIT)
79#define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x, S_MC_AGE_LIMIT)
80#define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x, S_MC_AGE_LIMIT, M_MC_AGE_LIMIT)
81#define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8)
82
83#define S_MC_WR_LIMIT 48
84#define M_MC_WR_LIMIT _SB_MAKEMASK(4, S_MC_WR_LIMIT)
85#define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x, S_MC_WR_LIMIT)
86#define G_MC_WR_LIMIT(x) _SB_GETVALUE(x, S_MC_WR_LIMIT, M_MC_WR_LIMIT)
87#define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5)
88
89#define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52)
90
91#define M_MC_RESERVED2 _SB_MAKEMASK(3, 53)
92
93#define S_MC_CS_MODE 56
94#define M_MC_CS_MODE _SB_MAKEMASK(4, S_MC_CS_MODE)
95#define V_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_MC_CS_MODE)
96#define G_MC_CS_MODE(x) _SB_GETVALUE(x, S_MC_CS_MODE, M_MC_CS_MODE)
97
98#define K_MC_CS_MODE_MSB_CS 0
99#define K_MC_CS_MODE_INTLV_CS 15
100#define K_MC_CS_MODE_MIXED_CS_10 12
101#define K_MC_CS_MODE_MIXED_CS_30 6
102#define K_MC_CS_MODE_MIXED_CS_32 3
103
104#define V_MC_CS_MODE_MSB_CS V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS)
105#define V_MC_CS_MODE_INTLV_CS V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS)
106#define V_MC_CS_MODE_MIXED_CS_10 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10)
107#define V_MC_CS_MODE_MIXED_CS_30 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30)
108#define V_MC_CS_MODE_MIXED_CS_32 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32)
109
110#define M_MC_ECC_DISABLE _SB_MAKEMASK1(60)
111#define M_MC_BERR_DISABLE _SB_MAKEMASK1(61)
112#define M_MC_FORCE_SEQ _SB_MAKEMASK1(62)
113#define M_MC_DEBUG _SB_MAKEMASK1(63)
114
115#define V_MC_CONFIG_DEFAULT V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \
116 V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT | \
117 V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | V_MC_CHANNEL_SEL(0) | \
118 M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT
119
120
121/*
122 * Memory clock config register (Table 6-15)
123 *
124 * Note: this field has been updated to be consistent with the errata to 0.2
125 */
126
127#define S_MC_CLK_RATIO 0
128#define M_MC_CLK_RATIO _SB_MAKEMASK(4, S_MC_CLK_RATIO)
129#define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_MC_CLK_RATIO)
130#define G_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_MC_CLK_RATIO, M_MC_CLK_RATIO)
131
132#define K_MC_CLK_RATIO_2X 4
133#define K_MC_CLK_RATIO_25X 5
134#define K_MC_CLK_RATIO_3X 6
135#define K_MC_CLK_RATIO_35X 7
136#define K_MC_CLK_RATIO_4X 8
137#define K_MC_CLK_RATIO_45X 9
138
139#define V_MC_CLK_RATIO_2X V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X)
140#define V_MC_CLK_RATIO_25X V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X)
141#define V_MC_CLK_RATIO_3X V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X)
142#define V_MC_CLK_RATIO_35X V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X)
143#define V_MC_CLK_RATIO_4X V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X)
144#define V_MC_CLK_RATIO_45X V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X)
145#define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X
146
147#define S_MC_REF_RATE 8
148#define M_MC_REF_RATE _SB_MAKEMASK(8, S_MC_REF_RATE)
149#define V_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_MC_REF_RATE)
150#define G_MC_REF_RATE(x) _SB_GETVALUE(x, S_MC_REF_RATE, M_MC_REF_RATE)
151
152#define K_MC_REF_RATE_100MHz 0x62
153#define K_MC_REF_RATE_133MHz 0x81
154#define K_MC_REF_RATE_200MHz 0xC4
155
156#define V_MC_REF_RATE_100MHz V_MC_REF_RATE(K_MC_REF_RATE_100MHz)
157#define V_MC_REF_RATE_133MHz V_MC_REF_RATE(K_MC_REF_RATE_133MHz)
158#define V_MC_REF_RATE_200MHz V_MC_REF_RATE(K_MC_REF_RATE_200MHz)
159#define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz
160
161#define S_MC_CLOCK_DRIVE 16
162#define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4, S_MC_CLOCK_DRIVE)
163#define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x, S_MC_CLOCK_DRIVE)
164#define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x, S_MC_CLOCK_DRIVE, M_MC_CLOCK_DRIVE)
165#define V_MC_CLOCK_DRIVE_DEFAULT V_MC_CLOCK_DRIVE(0xF)
166
167#define S_MC_DATA_DRIVE 20
168#define M_MC_DATA_DRIVE _SB_MAKEMASK(4, S_MC_DATA_DRIVE)
169#define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x, S_MC_DATA_DRIVE)
170#define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x, S_MC_DATA_DRIVE, M_MC_DATA_DRIVE)
171#define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0)
172
173#define S_MC_ADDR_DRIVE 24
174#define M_MC_ADDR_DRIVE _SB_MAKEMASK(4, S_MC_ADDR_DRIVE)
175#define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x, S_MC_ADDR_DRIVE)
176#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x, S_MC_ADDR_DRIVE, M_MC_ADDR_DRIVE)
177#define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0)
178
179#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
180#define M_MC_REF_DISABLE _SB_MAKEMASK1(30)
181#endif /* 1250 PASS3 || 112x PASS1 */
182
183#define M_MC_DLL_BYPASS _SB_MAKEMASK1(31)
184
185#define S_MC_DQI_SKEW 32
186#define M_MC_DQI_SKEW _SB_MAKEMASK(8, S_MC_DQI_SKEW)
187#define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQI_SKEW)
188#define G_MC_DQI_SKEW(x) _SB_GETVALUE(x, S_MC_DQI_SKEW, M_MC_DQI_SKEW)
189#define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0)
190
191#define S_MC_DQO_SKEW 40
192#define M_MC_DQO_SKEW _SB_MAKEMASK(8, S_MC_DQO_SKEW)
193#define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQO_SKEW)
194#define G_MC_DQO_SKEW(x) _SB_GETVALUE(x, S_MC_DQO_SKEW, M_MC_DQO_SKEW)
195#define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0)
196
197#define S_MC_ADDR_SKEW 48
198#define M_MC_ADDR_SKEW _SB_MAKEMASK(8, S_MC_ADDR_SKEW)
199#define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x, S_MC_ADDR_SKEW)
200#define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x, S_MC_ADDR_SKEW, M_MC_ADDR_SKEW)
201#define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F)
202
203#define S_MC_DLL_DEFAULT 56
204#define M_MC_DLL_DEFAULT _SB_MAKEMASK(8, S_MC_DLL_DEFAULT)
205#define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_MC_DLL_DEFAULT)
206#define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_MC_DLL_DEFAULT, M_MC_DLL_DEFAULT)
207#define V_MC_DLL_DEFAULT_DEFAULT V_MC_DLL_DEFAULT(0x10)
208
209#define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT | \
210 V_MC_ADDR_SKEW_DEFAULT | \
211 V_MC_DQO_SKEW_DEFAULT | \
212 V_MC_DQI_SKEW_DEFAULT | \
213 V_MC_ADDR_DRIVE_DEFAULT | \
214 V_MC_DATA_DRIVE_DEFAULT | \
215 V_MC_CLOCK_DRIVE_DEFAULT | \
216 V_MC_REF_RATE_DEFAULT
217
218
219
220/*
221 * DRAM Command Register (Table 6-13)
222 */
223
224#define S_MC_COMMAND 0
225#define M_MC_COMMAND _SB_MAKEMASK(4, S_MC_COMMAND)
226#define V_MC_COMMAND(x) _SB_MAKEVALUE(x, S_MC_COMMAND)
227#define G_MC_COMMAND(x) _SB_GETVALUE(x, S_MC_COMMAND, M_MC_COMMAND)
228
229#define K_MC_COMMAND_EMRS 0
230#define K_MC_COMMAND_MRS 1
231#define K_MC_COMMAND_PRE 2
232#define K_MC_COMMAND_AR 3
233#define K_MC_COMMAND_SETRFSH 4
234#define K_MC_COMMAND_CLRRFSH 5
235#define K_MC_COMMAND_SETPWRDN 6
236#define K_MC_COMMAND_CLRPWRDN 7
237
238#define V_MC_COMMAND_EMRS V_MC_COMMAND(K_MC_COMMAND_EMRS)
239#define V_MC_COMMAND_MRS V_MC_COMMAND(K_MC_COMMAND_MRS)
240#define V_MC_COMMAND_PRE V_MC_COMMAND(K_MC_COMMAND_PRE)
241#define V_MC_COMMAND_AR V_MC_COMMAND(K_MC_COMMAND_AR)
242#define V_MC_COMMAND_SETRFSH V_MC_COMMAND(K_MC_COMMAND_SETRFSH)
243#define V_MC_COMMAND_CLRRFSH V_MC_COMMAND(K_MC_COMMAND_CLRRFSH)
244#define V_MC_COMMAND_SETPWRDN V_MC_COMMAND(K_MC_COMMAND_SETPWRDN)
245#define V_MC_COMMAND_CLRPWRDN V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN)
246
247#define M_MC_CS0 _SB_MAKEMASK1(4)
248#define M_MC_CS1 _SB_MAKEMASK1(5)
249#define M_MC_CS2 _SB_MAKEMASK1(6)
250#define M_MC_CS3 _SB_MAKEMASK1(7)
251
252/*
253 * DRAM Mode Register (Table 6-14)
254 */
255
256#define S_MC_EMODE 0
257#define M_MC_EMODE _SB_MAKEMASK(15, S_MC_EMODE)
258#define V_MC_EMODE(x) _SB_MAKEVALUE(x, S_MC_EMODE)
259#define G_MC_EMODE(x) _SB_GETVALUE(x, S_MC_EMODE, M_MC_EMODE)
260#define V_MC_EMODE_DEFAULT V_MC_EMODE(0)
261
262#define S_MC_MODE 16
263#define M_MC_MODE _SB_MAKEMASK(15, S_MC_MODE)
264#define V_MC_MODE(x) _SB_MAKEVALUE(x, S_MC_MODE)
265#define G_MC_MODE(x) _SB_GETVALUE(x, S_MC_MODE, M_MC_MODE)
266#define V_MC_MODE_DEFAULT V_MC_MODE(0x22)
267
268#define S_MC_DRAM_TYPE 32
269#define M_MC_DRAM_TYPE _SB_MAKEMASK(3, S_MC_DRAM_TYPE)
270#define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_MC_DRAM_TYPE)
271#define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_MC_DRAM_TYPE, M_MC_DRAM_TYPE)
272
273#define K_MC_DRAM_TYPE_JEDEC 0
274#define K_MC_DRAM_TYPE_FCRAM 1
275#define K_MC_DRAM_TYPE_SGRAM 2
276
277#define V_MC_DRAM_TYPE_JEDEC V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC)
278#define V_MC_DRAM_TYPE_FCRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM)
279#define V_MC_DRAM_TYPE_SGRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM)
280
281#define M_MC_EXTERNALDECODE _SB_MAKEMASK1(35)
282
283#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
284#define M_MC_PRE_ON_A8 _SB_MAKEMASK1(36)
285#define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(37)
286#endif /* 1250 PASS3 || 112x PASS1 */
287
288
289
290/*
291 * SDRAM Timing Register (Table 6-15)
292 */
293
294#define M_MC_w2rIDLE_TWOCYCLES _SB_MAKEMASK1(60)
295#define M_MC_r2wIDLE_TWOCYCLES _SB_MAKEMASK1(61)
296#define M_MC_r2rIDLE_TWOCYCLES _SB_MAKEMASK1(62)
297
298#define S_MC_tFIFO 56
299#define M_MC_tFIFO _SB_MAKEMASK(4, S_MC_tFIFO)
300#define V_MC_tFIFO(x) _SB_MAKEVALUE(x, S_MC_tFIFO)
301#define G_MC_tFIFO(x) _SB_GETVALUE(x, S_MC_tFIFO, M_MC_tFIFO)
302#define K_MC_tFIFO_DEFAULT 1
303#define V_MC_tFIFO_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT)
304
305#define S_MC_tRFC 52
306#define M_MC_tRFC _SB_MAKEMASK(4, S_MC_tRFC)
307#define V_MC_tRFC(x) _SB_MAKEVALUE(x, S_MC_tRFC)
308#define G_MC_tRFC(x) _SB_GETVALUE(x, S_MC_tRFC, M_MC_tRFC)
309#define K_MC_tRFC_DEFAULT 12
310#define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT)
311
312#if SIBYTE_HDR_FEATURE(1250, PASS3)
313#define M_MC_tRFC_PLUS16 _SB_MAKEMASK1(51) /* 1250C3 and later. */
314#endif
315
316#define S_MC_tCwCr 40
317#define M_MC_tCwCr _SB_MAKEMASK(4, S_MC_tCwCr)
318#define V_MC_tCwCr(x) _SB_MAKEVALUE(x, S_MC_tCwCr)
319#define G_MC_tCwCr(x) _SB_GETVALUE(x, S_MC_tCwCr, M_MC_tCwCr)
320#define K_MC_tCwCr_DEFAULT 4
321#define V_MC_tCwCr_DEFAULT V_MC_tCwCr(K_MC_tCwCr_DEFAULT)
322
323#define S_MC_tRCr 28
324#define M_MC_tRCr _SB_MAKEMASK(4, S_MC_tRCr)
325#define V_MC_tRCr(x) _SB_MAKEVALUE(x, S_MC_tRCr)
326#define G_MC_tRCr(x) _SB_GETVALUE(x, S_MC_tRCr, M_MC_tRCr)
327#define K_MC_tRCr_DEFAULT 9
328#define V_MC_tRCr_DEFAULT V_MC_tRCr(K_MC_tRCr_DEFAULT)
329
330#define S_MC_tRCw 24
331#define M_MC_tRCw _SB_MAKEMASK(4, S_MC_tRCw)
332#define V_MC_tRCw(x) _SB_MAKEVALUE(x, S_MC_tRCw)
333#define G_MC_tRCw(x) _SB_GETVALUE(x, S_MC_tRCw, M_MC_tRCw)
334#define K_MC_tRCw_DEFAULT 10
335#define V_MC_tRCw_DEFAULT V_MC_tRCw(K_MC_tRCw_DEFAULT)
336
337#define S_MC_tRRD 20
338#define M_MC_tRRD _SB_MAKEMASK(4, S_MC_tRRD)
339#define V_MC_tRRD(x) _SB_MAKEVALUE(x, S_MC_tRRD)
340#define G_MC_tRRD(x) _SB_GETVALUE(x, S_MC_tRRD, M_MC_tRRD)
341#define K_MC_tRRD_DEFAULT 2
342#define V_MC_tRRD_DEFAULT V_MC_tRRD(K_MC_tRRD_DEFAULT)
343
344#define S_MC_tRP 16
345#define M_MC_tRP _SB_MAKEMASK(4, S_MC_tRP)
346#define V_MC_tRP(x) _SB_MAKEVALUE(x, S_MC_tRP)
347#define G_MC_tRP(x) _SB_GETVALUE(x, S_MC_tRP, M_MC_tRP)
348#define K_MC_tRP_DEFAULT 4
349#define V_MC_tRP_DEFAULT V_MC_tRP(K_MC_tRP_DEFAULT)
350
351#define S_MC_tCwD 8
352#define M_MC_tCwD _SB_MAKEMASK(4, S_MC_tCwD)
353#define V_MC_tCwD(x) _SB_MAKEVALUE(x, S_MC_tCwD)
354#define G_MC_tCwD(x) _SB_GETVALUE(x, S_MC_tCwD, M_MC_tCwD)
355#define K_MC_tCwD_DEFAULT 1
356#define V_MC_tCwD_DEFAULT V_MC_tCwD(K_MC_tCwD_DEFAULT)
357
358#define M_tCrDh _SB_MAKEMASK1(7)
359#define M_MC_tCrDh M_tCrDh
360
361#define S_MC_tCrD 4
362#define M_MC_tCrD _SB_MAKEMASK(3, S_MC_tCrD)
363#define V_MC_tCrD(x) _SB_MAKEVALUE(x, S_MC_tCrD)
364#define G_MC_tCrD(x) _SB_GETVALUE(x, S_MC_tCrD, M_MC_tCrD)
365#define K_MC_tCrD_DEFAULT 2
366#define V_MC_tCrD_DEFAULT V_MC_tCrD(K_MC_tCrD_DEFAULT)
367
368#define S_MC_tRCD 0
369#define M_MC_tRCD _SB_MAKEMASK(4, S_MC_tRCD)
370#define V_MC_tRCD(x) _SB_MAKEVALUE(x, S_MC_tRCD)
371#define G_MC_tRCD(x) _SB_GETVALUE(x, S_MC_tRCD, M_MC_tRCD)
372#define K_MC_tRCD_DEFAULT 3
373#define V_MC_tRCD_DEFAULT V_MC_tRCD(K_MC_tRCD_DEFAULT)
374
375#define V_MC_TIMING_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \
376 V_MC_tRFC(K_MC_tRFC_DEFAULT) | \
377 V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \
378 V_MC_tRCr(K_MC_tRCr_DEFAULT) | \
379 V_MC_tRCw(K_MC_tRCw_DEFAULT) | \
380 V_MC_tRRD(K_MC_tRRD_DEFAULT) | \
381 V_MC_tRP(K_MC_tRP_DEFAULT) | \
382 V_MC_tCwD(K_MC_tCwD_DEFAULT) | \
383 V_MC_tCrD(K_MC_tCrD_DEFAULT) | \
384 V_MC_tRCD(K_MC_tRCD_DEFAULT) | \
385 M_MC_r2rIDLE_TWOCYCLES
386
387/*
388 * Errata says these are not the default
389 * M_MC_w2rIDLE_TWOCYCLES | \
390 * M_MC_r2wIDLE_TWOCYCLES | \
391 */
392
393
394/*
395 * Chip Select Start Address Register (Table 6-17)
396 */
397
398#define S_MC_CS0_START 0
399#define M_MC_CS0_START _SB_MAKEMASK(16, S_MC_CS0_START)
400#define V_MC_CS0_START(x) _SB_MAKEVALUE(x, S_MC_CS0_START)
401#define G_MC_CS0_START(x) _SB_GETVALUE(x, S_MC_CS0_START, M_MC_CS0_START)
402
403#define S_MC_CS1_START 16
404#define M_MC_CS1_START _SB_MAKEMASK(16, S_MC_CS1_START)
405#define V_MC_CS1_START(x) _SB_MAKEVALUE(x, S_MC_CS1_START)
406#define G_MC_CS1_START(x) _SB_GETVALUE(x, S_MC_CS1_START, M_MC_CS1_START)
407
408#define S_MC_CS2_START 32
409#define M_MC_CS2_START _SB_MAKEMASK(16, S_MC_CS2_START)
410#define V_MC_CS2_START(x) _SB_MAKEVALUE(x, S_MC_CS2_START)
411#define G_MC_CS2_START(x) _SB_GETVALUE(x, S_MC_CS2_START, M_MC_CS2_START)
412
413#define S_MC_CS3_START 48
414#define M_MC_CS3_START _SB_MAKEMASK(16, S_MC_CS3_START)
415#define V_MC_CS3_START(x) _SB_MAKEVALUE(x, S_MC_CS3_START)
416#define G_MC_CS3_START(x) _SB_GETVALUE(x, S_MC_CS3_START, M_MC_CS3_START)
417
418/*
419 * Chip Select End Address Register (Table 6-18)
420 */
421
422#define S_MC_CS0_END 0
423#define M_MC_CS0_END _SB_MAKEMASK(16, S_MC_CS0_END)
424#define V_MC_CS0_END(x) _SB_MAKEVALUE(x, S_MC_CS0_END)
425#define G_MC_CS0_END(x) _SB_GETVALUE(x, S_MC_CS0_END, M_MC_CS0_END)
426
427#define S_MC_CS1_END 16
428#define M_MC_CS1_END _SB_MAKEMASK(16, S_MC_CS1_END)
429#define V_MC_CS1_END(x) _SB_MAKEVALUE(x, S_MC_CS1_END)
430#define G_MC_CS1_END(x) _SB_GETVALUE(x, S_MC_CS1_END, M_MC_CS1_END)
431
432#define S_MC_CS2_END 32
433#define M_MC_CS2_END _SB_MAKEMASK(16, S_MC_CS2_END)
434#define V_MC_CS2_END(x) _SB_MAKEVALUE(x, S_MC_CS2_END)
435#define G_MC_CS2_END(x) _SB_GETVALUE(x, S_MC_CS2_END, M_MC_CS2_END)
436
437#define S_MC_CS3_END 48
438#define M_MC_CS3_END _SB_MAKEMASK(16, S_MC_CS3_END)
439#define V_MC_CS3_END(x) _SB_MAKEVALUE(x, S_MC_CS3_END)
440#define G_MC_CS3_END(x) _SB_GETVALUE(x, S_MC_CS3_END, M_MC_CS3_END)
441
442/*
443 * Chip Select Interleave Register (Table 6-19)
444 */
445
446#define S_MC_INTLV_RESERVED 0
447#define M_MC_INTLV_RESERVED _SB_MAKEMASK(5, S_MC_INTLV_RESERVED)
448
449#define S_MC_INTERLEAVE 7
450#define M_MC_INTERLEAVE _SB_MAKEMASK(18, S_MC_INTERLEAVE)
451#define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x, S_MC_INTERLEAVE)
452
453#define S_MC_INTLV_MBZ 25
454#define M_MC_INTLV_MBZ _SB_MAKEMASK(39, S_MC_INTLV_MBZ)
455
456/*
457 * Row Address Bits Register (Table 6-20)
458 */
459
460#define S_MC_RAS_RESERVED 0
461#define M_MC_RAS_RESERVED _SB_MAKEMASK(5, S_MC_RAS_RESERVED)
462
463#define S_MC_RAS_SELECT 12
464#define M_MC_RAS_SELECT _SB_MAKEMASK(25, S_MC_RAS_SELECT)
465#define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_RAS_SELECT)
466
467#define S_MC_RAS_MBZ 37
468#define M_MC_RAS_MBZ _SB_MAKEMASK(27, S_MC_RAS_MBZ)
469
470
471/*
472 * Column Address Bits Register (Table 6-21)
473 */
474
475#define S_MC_CAS_RESERVED 0
476#define M_MC_CAS_RESERVED _SB_MAKEMASK(5, S_MC_CAS_RESERVED)
477
478#define S_MC_CAS_SELECT 5
479#define M_MC_CAS_SELECT _SB_MAKEMASK(18, S_MC_CAS_SELECT)
480#define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_CAS_SELECT)
481
482#define S_MC_CAS_MBZ 23
483#define M_MC_CAS_MBZ _SB_MAKEMASK(41, S_MC_CAS_MBZ)
484
485
486/*
487 * Bank Address Bits Register (Table 6-22)
488 */
489
490#define S_MC_BA_RESERVED 0
491#define M_MC_BA_RESERVED _SB_MAKEMASK(5, S_MC_BA_RESERVED)
492
493#define S_MC_BA_SELECT 5
494#define M_MC_BA_SELECT _SB_MAKEMASK(20, S_MC_BA_SELECT)
495#define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x, S_MC_BA_SELECT)
496
497#define S_MC_BA_MBZ 25
498#define M_MC_BA_MBZ _SB_MAKEMASK(39, S_MC_BA_MBZ)
499
500/*
501 * Chip Select Attribute Register (Table 6-23)
502 */
503
504#define K_MC_CS_ATTR_CLOSED 0
505#define K_MC_CS_ATTR_CASCHECK 1
506#define K_MC_CS_ATTR_HINT 2
507#define K_MC_CS_ATTR_OPEN 3
508
509#define S_MC_CS0_PAGE 0
510#define M_MC_CS0_PAGE _SB_MAKEMASK(2, S_MC_CS0_PAGE)
511#define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS0_PAGE)
512#define G_MC_CS0_PAGE(x) _SB_GETVALUE(x, S_MC_CS0_PAGE, M_MC_CS0_PAGE)
513
514#define S_MC_CS1_PAGE 16
515#define M_MC_CS1_PAGE _SB_MAKEMASK(2, S_MC_CS1_PAGE)
516#define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS1_PAGE)
517#define G_MC_CS1_PAGE(x) _SB_GETVALUE(x, S_MC_CS1_PAGE, M_MC_CS1_PAGE)
518
519#define S_MC_CS2_PAGE 32
520#define M_MC_CS2_PAGE _SB_MAKEMASK(2, S_MC_CS2_PAGE)
521#define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS2_PAGE)
522#define G_MC_CS2_PAGE(x) _SB_GETVALUE(x, S_MC_CS2_PAGE, M_MC_CS2_PAGE)
523
524#define S_MC_CS3_PAGE 48
525#define M_MC_CS3_PAGE _SB_MAKEMASK(2, S_MC_CS3_PAGE)
526#define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS3_PAGE)
527#define G_MC_CS3_PAGE(x) _SB_GETVALUE(x, S_MC_CS3_PAGE, M_MC_CS3_PAGE)
528
529/*
530 * ECC Test ECC Register (Table 6-25)
531 */
532
533#define S_MC_ECC_INVERT 0
534#define M_MC_ECC_INVERT _SB_MAKEMASK(8, S_MC_ECC_INVERT)
535
536
537#endif