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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
8 */
9
10#include <linux/init.h>
11#include <linux/bitops.h>
12#include <linux/memblock.h>
13#include <linux/ioport.h>
14#include <linux/kernel.h>
15#include <linux/io.h>
16#include <linux/of.h>
17#include <linux/of_clk.h>
18#include <linux/of_fdt.h>
19#include <linux/libfdt.h>
20#include <linux/smp.h>
21#include <asm/addrspace.h>
22#include <asm/bmips.h>
23#include <asm/bootinfo.h>
24#include <asm/cpu-type.h>
25#include <asm/mipsregs.h>
26#include <asm/prom.h>
27#include <asm/smp-ops.h>
28#include <asm/time.h>
29#include <asm/traps.h>
30#include <asm/fw/cfe/cfe_api.h>
31
32#define RELO_NORMAL_VEC BIT(18)
33
34#define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))
35#define BCM6328_TP1_DISABLED BIT(9)
36
37extern bool bmips_rac_flush_disable;
38
39static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
40
41struct bmips_quirk {
42 const char *compatible;
43 void (*quirk_fn)(void);
44};
45
46static void kbase_setup(void)
47{
48 __raw_writel(kbase | RELO_NORMAL_VEC,
49 BMIPS_GET_CBR() + BMIPS_RELO_VECTOR_CONTROL_1);
50 ebase = kbase;
51}
52
53static void bcm3384_viper_quirks(void)
54{
55 /*
56 * Some experimental CM boxes are set up to let CM own the Viper TP0
57 * and let Linux own TP1. This requires moving the kernel
58 * load address to a non-conflicting region (e.g. via
59 * CONFIG_PHYSICAL_START) and supplying an alternate DTB.
60 * If we detect this condition, we need to move the MIPS exception
61 * vectors up to an area that we own.
62 *
63 * This is distinct from the OTHER special case mentioned in
64 * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our
65 * logical CPU#1). For the Viper TP1 case, SMP is off limits.
66 *
67 * Also note that many BMIPS435x CPUs do not have a
68 * BMIPS_RELO_VECTOR_CONTROL_1 register, so it isn't safe to just
69 * write VMLINUX_LOAD_ADDRESS into that register on every SoC.
70 */
71 board_ebase_setup = &kbase_setup;
72 bmips_smp_enabled = 0;
73}
74
75static void bcm63xx_fixup_cpu1(void)
76{
77 /*
78 * The bootloader has set up the CPU1 reset vector at
79 * 0xa000_0200.
80 * This conflicts with the special interrupt vector (IV).
81 * The bootloader has also set up CPU1 to respond to the wrong
82 * IPI interrupt.
83 * Here we will start up CPU1 in the background and ask it to
84 * reconfigure itself then go back to sleep.
85 */
86 memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
87 __sync();
88 set_c0_cause(C_SW0);
89 cpumask_set_cpu(1, &bmips_booted_mask);
90}
91
92static void bcm6328_quirks(void)
93{
94 /* Check CPU1 status in OTP (it is usually disabled) */
95 if (__raw_readl(REG_BCM6328_OTP) & BCM6328_TP1_DISABLED)
96 bmips_smp_enabled = 0;
97 else
98 bcm63xx_fixup_cpu1();
99}
100
101static void bcm6358_quirks(void)
102{
103 /*
104 * BCM3368/BCM6358 need special handling for their shared TLB, so
105 * disable SMP for now
106 */
107 bmips_smp_enabled = 0;
108
109 /*
110 * RAC flush causes kernel panics on BCM6358 when booting from TP1
111 * because the bootloader is not initializing it properly.
112 */
113 bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31));
114}
115
116static void bcm6368_quirks(void)
117{
118 bcm63xx_fixup_cpu1();
119}
120
121static const struct bmips_quirk bmips_quirk_list[] = {
122 { "brcm,bcm3368", &bcm6358_quirks },
123 { "brcm,bcm3384-viper", &bcm3384_viper_quirks },
124 { "brcm,bcm33843-viper", &bcm3384_viper_quirks },
125 { "brcm,bcm6328", &bcm6328_quirks },
126 { "brcm,bcm6358", &bcm6358_quirks },
127 { "brcm,bcm6362", &bcm6368_quirks },
128 { "brcm,bcm6368", &bcm6368_quirks },
129 { "brcm,bcm63168", &bcm6368_quirks },
130 { "brcm,bcm63268", &bcm6368_quirks },
131 { },
132};
133
134static void __init bmips_init_cfe(void)
135{
136 cfe_seal = fw_arg3;
137
138 if (cfe_seal != CFE_EPTSEAL)
139 return;
140
141 cfe_init(fw_arg0, fw_arg2);
142}
143
144void __init prom_init(void)
145{
146 bmips_init_cfe();
147 bmips_cpu_setup();
148 register_bmips_smp_ops();
149}
150
151const char *get_system_type(void)
152{
153 return "Generic BMIPS kernel";
154}
155
156void __init plat_time_init(void)
157{
158 struct device_node *np;
159 u32 freq;
160
161 np = of_find_node_by_name(NULL, "cpus");
162 if (!np)
163 panic("missing 'cpus' DT node");
164 if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
165 panic("missing 'mips-hpt-frequency' property");
166 of_node_put(np);
167
168 mips_hpt_frequency = freq;
169}
170
171void __init plat_mem_setup(void)
172{
173 void *dtb;
174 const struct bmips_quirk *q;
175
176 set_io_port_base(0);
177 ioport_resource.start = 0;
178 ioport_resource.end = ~0;
179
180 /*
181 * intended to somewhat resemble ARM; see
182 * Documentation/arch/arm/booting.rst
183 */
184 if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
185 dtb = phys_to_virt(fw_arg2);
186 else
187 dtb = get_fdt();
188
189 if (!dtb)
190 cfe_die("no dtb found");
191
192 __dt_setup_arch(dtb);
193
194 for (q = bmips_quirk_list; q->quirk_fn; q++) {
195 if (of_flat_dt_is_compatible(of_get_flat_dt_root(),
196 q->compatible)) {
197 q->quirk_fn();
198 }
199 }
200}
201
202void __init device_tree_init(void)
203{
204 struct device_node *np;
205
206 unflatten_and_copy_device_tree();
207
208 /* Disable SMP boot unless both CPUs are listed in DT and !disabled */
209 np = of_find_node_by_name(NULL, "cpus");
210 if (np && of_get_available_child_count(np) <= 1)
211 bmips_smp_enabled = 0;
212 of_node_put(np);
213}
214
215static int __init plat_dev_init(void)
216{
217 of_clk_init(NULL);
218 return 0;
219}
220
221arch_initcall(plat_dev_init);
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
8 */
9
10#include <linux/init.h>
11#include <linux/bitops.h>
12#include <linux/memblock.h>
13#include <linux/ioport.h>
14#include <linux/kernel.h>
15#include <linux/io.h>
16#include <linux/of.h>
17#include <linux/of_clk.h>
18#include <linux/of_fdt.h>
19#include <linux/of_platform.h>
20#include <linux/libfdt.h>
21#include <linux/smp.h>
22#include <asm/addrspace.h>
23#include <asm/bmips.h>
24#include <asm/bootinfo.h>
25#include <asm/cpu-type.h>
26#include <asm/mipsregs.h>
27#include <asm/prom.h>
28#include <asm/smp-ops.h>
29#include <asm/time.h>
30#include <asm/traps.h>
31#include <asm/fw/cfe/cfe_api.h>
32
33#define RELO_NORMAL_VEC BIT(18)
34
35#define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))
36#define BCM6328_TP1_DISABLED BIT(9)
37
38static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
39
40struct bmips_quirk {
41 const char *compatible;
42 void (*quirk_fn)(void);
43};
44
45static void kbase_setup(void)
46{
47 __raw_writel(kbase | RELO_NORMAL_VEC,
48 BMIPS_GET_CBR() + BMIPS_RELO_VECTOR_CONTROL_1);
49 ebase = kbase;
50}
51
52static void bcm3384_viper_quirks(void)
53{
54 /*
55 * Some experimental CM boxes are set up to let CM own the Viper TP0
56 * and let Linux own TP1. This requires moving the kernel
57 * load address to a non-conflicting region (e.g. via
58 * CONFIG_PHYSICAL_START) and supplying an alternate DTB.
59 * If we detect this condition, we need to move the MIPS exception
60 * vectors up to an area that we own.
61 *
62 * This is distinct from the OTHER special case mentioned in
63 * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our
64 * logical CPU#1). For the Viper TP1 case, SMP is off limits.
65 *
66 * Also note that many BMIPS435x CPUs do not have a
67 * BMIPS_RELO_VECTOR_CONTROL_1 register, so it isn't safe to just
68 * write VMLINUX_LOAD_ADDRESS into that register on every SoC.
69 */
70 board_ebase_setup = &kbase_setup;
71 bmips_smp_enabled = 0;
72}
73
74static void bcm63xx_fixup_cpu1(void)
75{
76 /*
77 * The bootloader has set up the CPU1 reset vector at
78 * 0xa000_0200.
79 * This conflicts with the special interrupt vector (IV).
80 * The bootloader has also set up CPU1 to respond to the wrong
81 * IPI interrupt.
82 * Here we will start up CPU1 in the background and ask it to
83 * reconfigure itself then go back to sleep.
84 */
85 memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
86 __sync();
87 set_c0_cause(C_SW0);
88 cpumask_set_cpu(1, &bmips_booted_mask);
89}
90
91static void bcm6328_quirks(void)
92{
93 /* Check CPU1 status in OTP (it is usually disabled) */
94 if (__raw_readl(REG_BCM6328_OTP) & BCM6328_TP1_DISABLED)
95 bmips_smp_enabled = 0;
96 else
97 bcm63xx_fixup_cpu1();
98}
99
100static void bcm6358_quirks(void)
101{
102 /*
103 * BCM3368/BCM6358 need special handling for their shared TLB, so
104 * disable SMP for now
105 */
106 bmips_smp_enabled = 0;
107}
108
109static void bcm6368_quirks(void)
110{
111 bcm63xx_fixup_cpu1();
112}
113
114static const struct bmips_quirk bmips_quirk_list[] = {
115 { "brcm,bcm3368", &bcm6358_quirks },
116 { "brcm,bcm3384-viper", &bcm3384_viper_quirks },
117 { "brcm,bcm33843-viper", &bcm3384_viper_quirks },
118 { "brcm,bcm6328", &bcm6328_quirks },
119 { "brcm,bcm6358", &bcm6358_quirks },
120 { "brcm,bcm6362", &bcm6368_quirks },
121 { "brcm,bcm6368", &bcm6368_quirks },
122 { "brcm,bcm63168", &bcm6368_quirks },
123 { "brcm,bcm63268", &bcm6368_quirks },
124 { },
125};
126
127static void __init bmips_init_cfe(void)
128{
129 cfe_seal = fw_arg3;
130
131 if (cfe_seal != CFE_EPTSEAL)
132 return;
133
134 cfe_init(fw_arg0, fw_arg2);
135}
136
137void __init prom_init(void)
138{
139 bmips_init_cfe();
140 bmips_cpu_setup();
141 register_bmips_smp_ops();
142}
143
144const char *get_system_type(void)
145{
146 return "Generic BMIPS kernel";
147}
148
149void __init plat_time_init(void)
150{
151 struct device_node *np;
152 u32 freq;
153
154 np = of_find_node_by_name(NULL, "cpus");
155 if (!np)
156 panic("missing 'cpus' DT node");
157 if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
158 panic("missing 'mips-hpt-frequency' property");
159 of_node_put(np);
160
161 mips_hpt_frequency = freq;
162}
163
164void __init plat_mem_setup(void)
165{
166 void *dtb;
167 const struct bmips_quirk *q;
168
169 set_io_port_base(0);
170 ioport_resource.start = 0;
171 ioport_resource.end = ~0;
172
173 /* intended to somewhat resemble ARM; see Documentation/arm/booting.rst */
174 if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
175 dtb = phys_to_virt(fw_arg2);
176 else
177 dtb = get_fdt();
178
179 if (!dtb)
180 cfe_die("no dtb found");
181
182 __dt_setup_arch(dtb);
183
184 for (q = bmips_quirk_list; q->quirk_fn; q++) {
185 if (of_flat_dt_is_compatible(of_get_flat_dt_root(),
186 q->compatible)) {
187 q->quirk_fn();
188 }
189 }
190}
191
192void __init device_tree_init(void)
193{
194 struct device_node *np;
195
196 unflatten_and_copy_device_tree();
197
198 /* Disable SMP boot unless both CPUs are listed in DT and !disabled */
199 np = of_find_node_by_name(NULL, "cpus");
200 if (np && of_get_available_child_count(np) <= 1)
201 bmips_smp_enabled = 0;
202 of_node_put(np);
203}
204
205static int __init plat_dev_init(void)
206{
207 of_clk_init(NULL);
208 return 0;
209}
210
211arch_initcall(plat_dev_init);