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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Thunderbolt driver - NHI driver
4 *
5 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
6 * Copyright (C) 2018, Intel Corporation
7 */
8
9#ifndef DSL3510_H_
10#define DSL3510_H_
11
12#include <linux/thunderbolt.h>
13
14enum nhi_fw_mode {
15 NHI_FW_SAFE_MODE,
16 NHI_FW_AUTH_MODE,
17 NHI_FW_EP_MODE,
18 NHI_FW_CM_MODE,
19};
20
21enum nhi_mailbox_cmd {
22 NHI_MAILBOX_SAVE_DEVS = 0x05,
23 NHI_MAILBOX_DISCONNECT_PCIE_PATHS = 0x06,
24 NHI_MAILBOX_DRV_UNLOADS = 0x07,
25 NHI_MAILBOX_DISCONNECT_PA = 0x10,
26 NHI_MAILBOX_DISCONNECT_PB = 0x11,
27 NHI_MAILBOX_ALLOW_ALL_DEVS = 0x23,
28};
29
30int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data);
31enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi);
32
33/**
34 * struct tb_nhi_ops - NHI specific optional operations
35 * @init: NHI specific initialization
36 * @suspend_noirq: NHI specific suspend_noirq hook
37 * @resume_noirq: NHI specific resume_noirq hook
38 * @runtime_suspend: NHI specific runtime_suspend hook
39 * @runtime_resume: NHI specific runtime_resume hook
40 * @shutdown: NHI specific shutdown
41 */
42struct tb_nhi_ops {
43 int (*init)(struct tb_nhi *nhi);
44 int (*suspend_noirq)(struct tb_nhi *nhi, bool wakeup);
45 int (*resume_noirq)(struct tb_nhi *nhi);
46 int (*runtime_suspend)(struct tb_nhi *nhi);
47 int (*runtime_resume)(struct tb_nhi *nhi);
48 void (*shutdown)(struct tb_nhi *nhi);
49};
50
51extern const struct tb_nhi_ops icl_nhi_ops;
52
53/*
54 * PCI IDs used in this driver from Win Ridge forward. There is no
55 * need for the PCI quirk anymore as we will use ICM also on Apple
56 * hardware.
57 */
58#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_2C_NHI 0x1134
59#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_4C_NHI 0x1137
60#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_NHI 0x157d
61#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE 0x157e
62#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI 0x15bf
63#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE 0x15c0
64#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI 0x15d2
65#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE 0x15d3
66#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI 0x15d9
67#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE 0x15da
68#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI 0x15dc
69#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI 0x15dd
70#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI 0x15de
71#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_BRIDGE 0x15e7
72#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI 0x15e8
73#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_BRIDGE 0x15ea
74#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI 0x15eb
75#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE 0x15ef
76#define PCI_DEVICE_ID_INTEL_ADL_NHI0 0x463e
77#define PCI_DEVICE_ID_INTEL_ADL_NHI1 0x466d
78#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_80G_NHI 0x5781
79#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_40G_NHI 0x5784
80#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_80G_BRIDGE 0x5786
81#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_40G_BRIDGE 0x57a4
82#define PCI_DEVICE_ID_INTEL_MTL_M_NHI0 0x7eb2
83#define PCI_DEVICE_ID_INTEL_MTL_P_NHI0 0x7ec2
84#define PCI_DEVICE_ID_INTEL_MTL_P_NHI1 0x7ec3
85#define PCI_DEVICE_ID_INTEL_ICL_NHI1 0x8a0d
86#define PCI_DEVICE_ID_INTEL_ICL_NHI0 0x8a17
87#define PCI_DEVICE_ID_INTEL_TGL_NHI0 0x9a1b
88#define PCI_DEVICE_ID_INTEL_TGL_NHI1 0x9a1d
89#define PCI_DEVICE_ID_INTEL_TGL_H_NHI0 0x9a1f
90#define PCI_DEVICE_ID_INTEL_TGL_H_NHI1 0x9a21
91#define PCI_DEVICE_ID_INTEL_RPL_NHI0 0xa73e
92#define PCI_DEVICE_ID_INTEL_RPL_NHI1 0xa76d
93#define PCI_DEVICE_ID_INTEL_LNL_NHI0 0xa833
94#define PCI_DEVICE_ID_INTEL_LNL_NHI1 0xa834
95
96#define PCI_CLASS_SERIAL_USB_USB4 0x0c0340
97
98#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Thunderbolt driver - NHI driver
4 *
5 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
6 * Copyright (C) 2018, Intel Corporation
7 */
8
9#ifndef DSL3510_H_
10#define DSL3510_H_
11
12#include <linux/thunderbolt.h>
13
14enum nhi_fw_mode {
15 NHI_FW_SAFE_MODE,
16 NHI_FW_AUTH_MODE,
17 NHI_FW_EP_MODE,
18 NHI_FW_CM_MODE,
19};
20
21enum nhi_mailbox_cmd {
22 NHI_MAILBOX_SAVE_DEVS = 0x05,
23 NHI_MAILBOX_DISCONNECT_PCIE_PATHS = 0x06,
24 NHI_MAILBOX_DRV_UNLOADS = 0x07,
25 NHI_MAILBOX_DISCONNECT_PA = 0x10,
26 NHI_MAILBOX_DISCONNECT_PB = 0x11,
27 NHI_MAILBOX_ALLOW_ALL_DEVS = 0x23,
28};
29
30int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data);
31enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi);
32
33/**
34 * struct tb_nhi_ops - NHI specific optional operations
35 * @init: NHI specific initialization
36 * @suspend_noirq: NHI specific suspend_noirq hook
37 * @resume_noirq: NHI specific resume_noirq hook
38 * @runtime_suspend: NHI specific runtime_suspend hook
39 * @runtime_resume: NHI specific runtime_resume hook
40 * @shutdown: NHI specific shutdown
41 */
42struct tb_nhi_ops {
43 int (*init)(struct tb_nhi *nhi);
44 int (*suspend_noirq)(struct tb_nhi *nhi, bool wakeup);
45 int (*resume_noirq)(struct tb_nhi *nhi);
46 int (*runtime_suspend)(struct tb_nhi *nhi);
47 int (*runtime_resume)(struct tb_nhi *nhi);
48 void (*shutdown)(struct tb_nhi *nhi);
49};
50
51extern const struct tb_nhi_ops icl_nhi_ops;
52
53/*
54 * PCI IDs used in this driver from Win Ridge forward. There is no
55 * need for the PCI quirk anymore as we will use ICM also on Apple
56 * hardware.
57 */
58#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_2C_NHI 0x1134
59#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_4C_NHI 0x1137
60#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_NHI 0x157d
61#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE 0x157e
62#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI 0x15bf
63#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE 0x15c0
64#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI 0x15d2
65#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE 0x15d3
66#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI 0x15d9
67#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE 0x15da
68#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI 0x15dc
69#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI 0x15dd
70#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI 0x15de
71#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_BRIDGE 0x15e7
72#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI 0x15e8
73#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_BRIDGE 0x15ea
74#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI 0x15eb
75#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE 0x15ef
76#define PCI_DEVICE_ID_INTEL_ADL_NHI0 0x463e
77#define PCI_DEVICE_ID_INTEL_ADL_NHI1 0x466d
78#define PCI_DEVICE_ID_INTEL_MTL_M_NHI0 0x7eb2
79#define PCI_DEVICE_ID_INTEL_MTL_P_NHI0 0x7ec2
80#define PCI_DEVICE_ID_INTEL_MTL_P_NHI1 0x7ec3
81#define PCI_DEVICE_ID_INTEL_ICL_NHI1 0x8a0d
82#define PCI_DEVICE_ID_INTEL_ICL_NHI0 0x8a17
83#define PCI_DEVICE_ID_INTEL_TGL_NHI0 0x9a1b
84#define PCI_DEVICE_ID_INTEL_TGL_NHI1 0x9a1d
85#define PCI_DEVICE_ID_INTEL_TGL_H_NHI0 0x9a1f
86#define PCI_DEVICE_ID_INTEL_TGL_H_NHI1 0x9a21
87#define PCI_DEVICE_ID_INTEL_RPL_NHI0 0xa73e
88#define PCI_DEVICE_ID_INTEL_RPL_NHI1 0xa76d
89
90#define PCI_CLASS_SERIAL_USB_USB4 0x0c0340
91
92#endif