1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Qualcomm self-authenticating modem subsystem remoteproc driver
   4 *
   5 * Copyright (C) 2016 Linaro Ltd.
   6 * Copyright (C) 2014 Sony Mobile Communications AB
   7 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
   8 */
   9
  10#include <linux/clk.h>
  11#include <linux/delay.h>
  12#include <linux/devcoredump.h>
 
  13#include <linux/dma-mapping.h>
  14#include <linux/interrupt.h>
  15#include <linux/kernel.h>
  16#include <linux/mfd/syscon.h>
  17#include <linux/module.h>
  18#include <linux/of.h>
  19#include <linux/of_reserved_mem.h>
  20#include <linux/of_platform.h>
  21#include <linux/platform_device.h>
  22#include <linux/pm_domain.h>
  23#include <linux/pm_runtime.h>
  24#include <linux/regmap.h>
  25#include <linux/regulator/consumer.h>
  26#include <linux/remoteproc.h>
  27#include <linux/reset.h>
  28#include <linux/soc/qcom/mdt_loader.h>
  29#include <linux/iopoll.h>
  30#include <linux/slab.h>
  31
  32#include "remoteproc_internal.h"
  33#include "qcom_common.h"
  34#include "qcom_pil_info.h"
  35#include "qcom_q6v5.h"
  36
  37#include <linux/firmware/qcom/qcom_scm.h>
  38
  39#define MPSS_CRASH_REASON_SMEM		421
  40
  41#define MBA_LOG_SIZE			SZ_4K
  42
  43#define MPSS_PAS_ID			5
  44
  45/* RMB Status Register Values */
  46#define RMB_PBL_SUCCESS			0x1
  47
  48#define RMB_MBA_XPU_UNLOCKED		0x1
  49#define RMB_MBA_XPU_UNLOCKED_SCRIBBLED	0x2
  50#define RMB_MBA_META_DATA_AUTH_SUCCESS	0x3
  51#define RMB_MBA_AUTH_COMPLETE		0x4
  52
  53/* PBL/MBA interface registers */
  54#define RMB_MBA_IMAGE_REG		0x00
  55#define RMB_PBL_STATUS_REG		0x04
  56#define RMB_MBA_COMMAND_REG		0x08
  57#define RMB_MBA_STATUS_REG		0x0C
  58#define RMB_PMI_META_DATA_REG		0x10
  59#define RMB_PMI_CODE_START_REG		0x14
  60#define RMB_PMI_CODE_LENGTH_REG		0x18
  61#define RMB_MBA_MSS_STATUS		0x40
  62#define RMB_MBA_ALT_RESET		0x44
  63
  64#define RMB_CMD_META_DATA_READY		0x1
  65#define RMB_CMD_LOAD_READY		0x2
  66
  67/* QDSP6SS Register Offsets */
  68#define QDSP6SS_RESET_REG		0x014
  69#define QDSP6SS_GFMUX_CTL_REG		0x020
  70#define QDSP6SS_PWR_CTL_REG		0x030
  71#define QDSP6SS_MEM_PWR_CTL		0x0B0
  72#define QDSP6V6SS_MEM_PWR_CTL		0x034
  73#define QDSP6SS_STRAP_ACC		0x110
  74#define QDSP6V62SS_BHS_STATUS		0x0C4
  75
  76/* AXI Halt Register Offsets */
  77#define AXI_HALTREQ_REG			0x0
  78#define AXI_HALTACK_REG			0x4
  79#define AXI_IDLE_REG			0x8
  80#define AXI_GATING_VALID_OVERRIDE	BIT(0)
  81
  82#define HALT_ACK_TIMEOUT_US		100000
  83
  84/* QACCEPT Register Offsets */
  85#define QACCEPT_ACCEPT_REG		0x0
  86#define QACCEPT_ACTIVE_REG		0x4
  87#define QACCEPT_DENY_REG		0x8
  88#define QACCEPT_REQ_REG			0xC
  89
  90#define QACCEPT_TIMEOUT_US		50
  91
  92/* QDSP6SS_RESET */
  93#define Q6SS_STOP_CORE			BIT(0)
  94#define Q6SS_CORE_ARES			BIT(1)
  95#define Q6SS_BUS_ARES_ENABLE		BIT(2)
  96
  97/* QDSP6SS CBCR */
  98#define Q6SS_CBCR_CLKEN			BIT(0)
  99#define Q6SS_CBCR_CLKOFF		BIT(31)
 100#define Q6SS_CBCR_TIMEOUT_US		200
 101
 102/* QDSP6SS_GFMUX_CTL */
 103#define Q6SS_CLK_ENABLE			BIT(1)
 104
 105/* QDSP6SS_PWR_CTL */
 106#define Q6SS_L2DATA_SLP_NRET_N_0	BIT(0)
 107#define Q6SS_L2DATA_SLP_NRET_N_1	BIT(1)
 108#define Q6SS_L2DATA_SLP_NRET_N_2	BIT(2)
 109#define Q6SS_L2TAG_SLP_NRET_N		BIT(16)
 110#define Q6SS_ETB_SLP_NRET_N		BIT(17)
 111#define Q6SS_L2DATA_STBY_N		BIT(18)
 112#define Q6SS_SLP_RET_N			BIT(19)
 113#define Q6SS_CLAMP_IO			BIT(20)
 114#define QDSS_BHS_ON			BIT(21)
 115#define QDSS_LDO_BYP			BIT(22)
 116
 117/* QDSP6v55 parameters */
 118#define QDSP6V55_MEM_BITS		GENMASK(16, 8)
 119
 120/* QDSP6v56 parameters */
 121#define QDSP6v56_LDO_BYP		BIT(25)
 122#define QDSP6v56_BHS_ON		BIT(24)
 123#define QDSP6v56_CLAMP_WL		BIT(21)
 124#define QDSP6v56_CLAMP_QMC_MEM		BIT(22)
 125#define QDSP6SS_XO_CBCR		0x0038
 126#define QDSP6SS_ACC_OVERRIDE_VAL		0x20
 127#define QDSP6v55_BHS_EN_REST_ACK	BIT(0)
 128
 129/* QDSP6v65 parameters */
 130#define QDSP6SS_CORE_CBCR		0x20
 131#define QDSP6SS_SLEEP                   0x3C
 132#define QDSP6SS_BOOT_CORE_START         0x400
 133#define QDSP6SS_BOOT_CMD                0x404
 134#define BOOT_FSM_TIMEOUT                10000
 135#define BHS_CHECK_MAX_LOOPS             200
 136
 137struct reg_info {
 138	struct regulator *reg;
 139	int uV;
 140	int uA;
 141};
 142
 143struct qcom_mss_reg_res {
 144	const char *supply;
 145	int uV;
 146	int uA;
 147};
 148
 149struct rproc_hexagon_res {
 150	const char *hexagon_mba_image;
 151	struct qcom_mss_reg_res *proxy_supply;
 152	struct qcom_mss_reg_res *fallback_proxy_supply;
 153	struct qcom_mss_reg_res *active_supply;
 154	char **proxy_clk_names;
 155	char **reset_clk_names;
 156	char **active_clk_names;
 157	char **proxy_pd_names;
 158	int version;
 159	bool need_mem_protection;
 160	bool has_alt_reset;
 161	bool has_mba_logs;
 162	bool has_spare_reg;
 163	bool has_qaccept_regs;
 164	bool has_ext_cntl_regs;
 165	bool has_vq6;
 166};
 167
 168struct q6v5 {
 169	struct device *dev;
 170	struct rproc *rproc;
 171
 172	void __iomem *reg_base;
 173	void __iomem *rmb_base;
 174
 175	struct regmap *halt_map;
 176	struct regmap *conn_map;
 177
 178	u32 halt_q6;
 179	u32 halt_modem;
 180	u32 halt_nc;
 181	u32 halt_vq6;
 182	u32 conn_box;
 183
 184	u32 qaccept_mdm;
 185	u32 qaccept_cx;
 186	u32 qaccept_axi;
 187
 188	u32 axim1_clk_off;
 189	u32 crypto_clk_off;
 190	u32 force_clk_on;
 191	u32 rscc_disable;
 192
 193	struct reset_control *mss_restart;
 194	struct reset_control *pdc_reset;
 195
 196	struct qcom_q6v5 q6v5;
 197
 198	struct clk *active_clks[8];
 199	struct clk *reset_clks[4];
 200	struct clk *proxy_clks[4];
 201	struct device *proxy_pds[3];
 202	int active_clk_count;
 203	int reset_clk_count;
 204	int proxy_clk_count;
 205	int proxy_pd_count;
 206
 207	struct reg_info active_regs[1];
 208	struct reg_info proxy_regs[1];
 209	struct reg_info fallback_proxy_regs[2];
 210	int active_reg_count;
 211	int proxy_reg_count;
 212	int fallback_proxy_reg_count;
 213
 214	bool dump_mba_loaded;
 215	size_t current_dump_size;
 216	size_t total_dump_size;
 217
 218	phys_addr_t mba_phys;
 219	size_t mba_size;
 220	size_t dp_size;
 221
 222	phys_addr_t mdata_phys;
 223	size_t mdata_size;
 224
 225	phys_addr_t mpss_phys;
 226	phys_addr_t mpss_reloc;
 227	size_t mpss_size;
 228
 229	struct qcom_rproc_glink glink_subdev;
 230	struct qcom_rproc_subdev smd_subdev;
 231	struct qcom_rproc_ssr ssr_subdev;
 232	struct qcom_sysmon *sysmon;
 233	struct platform_device *bam_dmux;
 234	bool need_mem_protection;
 235	bool has_alt_reset;
 236	bool has_mba_logs;
 237	bool has_spare_reg;
 238	bool has_qaccept_regs;
 239	bool has_ext_cntl_regs;
 240	bool has_vq6;
 241	u64 mpss_perm;
 242	u64 mba_perm;
 243	const char *hexagon_mdt_image;
 244	int version;
 245};
 246
 247enum {
 248	MSS_MSM8909,
 249	MSS_MSM8916,
 250	MSS_MSM8953,
 251	MSS_MSM8974,
 252	MSS_MSM8996,
 253	MSS_MSM8998,
 254	MSS_SC7180,
 255	MSS_SC7280,
 256	MSS_SDM660,
 257	MSS_SDM845,
 258};
 259
 260static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
 261			       const struct qcom_mss_reg_res *reg_res)
 262{
 263	int rc;
 264	int i;
 265
 266	if (!reg_res)
 267		return 0;
 268
 269	for (i = 0; reg_res[i].supply; i++) {
 270		regs[i].reg = devm_regulator_get(dev, reg_res[i].supply);
 271		if (IS_ERR(regs[i].reg)) {
 272			rc = PTR_ERR(regs[i].reg);
 273			if (rc != -EPROBE_DEFER)
 274				dev_err(dev, "Failed to get %s\n regulator",
 275					reg_res[i].supply);
 276			return rc;
 277		}
 278
 279		regs[i].uV = reg_res[i].uV;
 280		regs[i].uA = reg_res[i].uA;
 281	}
 282
 283	return i;
 284}
 285
 286static int q6v5_regulator_enable(struct q6v5 *qproc,
 287				 struct reg_info *regs, int count)
 288{
 289	int ret;
 290	int i;
 291
 292	for (i = 0; i < count; i++) {
 293		if (regs[i].uV > 0) {
 294			ret = regulator_set_voltage(regs[i].reg,
 295					regs[i].uV, INT_MAX);
 296			if (ret) {
 297				dev_err(qproc->dev,
 298					"Failed to request voltage for %d.\n",
 299						i);
 300				goto err;
 301			}
 302		}
 303
 304		if (regs[i].uA > 0) {
 305			ret = regulator_set_load(regs[i].reg,
 306						 regs[i].uA);
 307			if (ret < 0) {
 308				dev_err(qproc->dev,
 309					"Failed to set regulator mode\n");
 310				goto err;
 311			}
 312		}
 313
 314		ret = regulator_enable(regs[i].reg);
 315		if (ret) {
 316			dev_err(qproc->dev, "Regulator enable failed\n");
 317			goto err;
 318		}
 319	}
 320
 321	return 0;
 322err:
 323	for (; i >= 0; i--) {
 324		if (regs[i].uV > 0)
 325			regulator_set_voltage(regs[i].reg, 0, INT_MAX);
 326
 327		if (regs[i].uA > 0)
 328			regulator_set_load(regs[i].reg, 0);
 329
 330		regulator_disable(regs[i].reg);
 331	}
 332
 333	return ret;
 334}
 335
 336static void q6v5_regulator_disable(struct q6v5 *qproc,
 337				   struct reg_info *regs, int count)
 338{
 339	int i;
 340
 341	for (i = 0; i < count; i++) {
 342		if (regs[i].uV > 0)
 343			regulator_set_voltage(regs[i].reg, 0, INT_MAX);
 344
 345		if (regs[i].uA > 0)
 346			regulator_set_load(regs[i].reg, 0);
 347
 348		regulator_disable(regs[i].reg);
 349	}
 350}
 351
 352static int q6v5_clk_enable(struct device *dev,
 353			   struct clk **clks, int count)
 354{
 355	int rc;
 356	int i;
 357
 358	for (i = 0; i < count; i++) {
 359		rc = clk_prepare_enable(clks[i]);
 360		if (rc) {
 361			dev_err(dev, "Clock enable failed\n");
 362			goto err;
 363		}
 364	}
 365
 366	return 0;
 367err:
 368	for (i--; i >= 0; i--)
 369		clk_disable_unprepare(clks[i]);
 370
 371	return rc;
 372}
 373
 374static void q6v5_clk_disable(struct device *dev,
 375			     struct clk **clks, int count)
 376{
 377	int i;
 378
 379	for (i = 0; i < count; i++)
 380		clk_disable_unprepare(clks[i]);
 381}
 382
 383static int q6v5_pds_enable(struct q6v5 *qproc, struct device **pds,
 384			   size_t pd_count)
 385{
 386	int ret;
 387	int i;
 388
 389	for (i = 0; i < pd_count; i++) {
 390		dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
 391		ret = pm_runtime_get_sync(pds[i]);
 392		if (ret < 0) {
 393			pm_runtime_put_noidle(pds[i]);
 394			dev_pm_genpd_set_performance_state(pds[i], 0);
 395			goto unroll_pd_votes;
 396		}
 397	}
 398
 399	return 0;
 400
 401unroll_pd_votes:
 402	for (i--; i >= 0; i--) {
 403		dev_pm_genpd_set_performance_state(pds[i], 0);
 404		pm_runtime_put(pds[i]);
 405	}
 406
 407	return ret;
 408}
 409
 410static void q6v5_pds_disable(struct q6v5 *qproc, struct device **pds,
 411			     size_t pd_count)
 412{
 413	int i;
 414
 415	for (i = 0; i < pd_count; i++) {
 416		dev_pm_genpd_set_performance_state(pds[i], 0);
 417		pm_runtime_put(pds[i]);
 418	}
 419}
 420
 421static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, u64 *current_perm,
 422				   bool local, bool remote, phys_addr_t addr,
 423				   size_t size)
 424{
 425	struct qcom_scm_vmperm next[2];
 426	int perms = 0;
 427
 428	if (!qproc->need_mem_protection)
 429		return 0;
 430
 431	if (local == !!(*current_perm & BIT(QCOM_SCM_VMID_HLOS)) &&
 432	    remote == !!(*current_perm & BIT(QCOM_SCM_VMID_MSS_MSA)))
 433		return 0;
 434
 435	if (local) {
 436		next[perms].vmid = QCOM_SCM_VMID_HLOS;
 437		next[perms].perm = QCOM_SCM_PERM_RWX;
 438		perms++;
 439	}
 440
 441	if (remote) {
 442		next[perms].vmid = QCOM_SCM_VMID_MSS_MSA;
 443		next[perms].perm = QCOM_SCM_PERM_RW;
 444		perms++;
 445	}
 446
 447	return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K),
 448				   current_perm, next, perms);
 449}
 450
 451static void q6v5_debug_policy_load(struct q6v5 *qproc, void *mba_region)
 452{
 453	const struct firmware *dp_fw;
 454
 455	if (request_firmware_direct(&dp_fw, "msadp", qproc->dev))
 456		return;
 457
 458	if (SZ_1M + dp_fw->size <= qproc->mba_size) {
 459		memcpy(mba_region + SZ_1M, dp_fw->data, dp_fw->size);
 460		qproc->dp_size = dp_fw->size;
 461	}
 462
 463	release_firmware(dp_fw);
 464}
 465
 466static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
 467{
 468	struct q6v5 *qproc = rproc->priv;
 469	void *mba_region;
 470
 471	/* MBA is restricted to a maximum size of 1M */
 472	if (fw->size > qproc->mba_size || fw->size > SZ_1M) {
 473		dev_err(qproc->dev, "MBA firmware load failed\n");
 474		return -EINVAL;
 475	}
 476
 477	mba_region = memremap(qproc->mba_phys, qproc->mba_size, MEMREMAP_WC);
 478	if (!mba_region) {
 479		dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
 480			&qproc->mba_phys, qproc->mba_size);
 481		return -EBUSY;
 482	}
 483
 484	memcpy(mba_region, fw->data, fw->size);
 485	q6v5_debug_policy_load(qproc, mba_region);
 486	memunmap(mba_region);
 487
 488	return 0;
 489}
 490
 491static int q6v5_reset_assert(struct q6v5 *qproc)
 492{
 493	int ret;
 494
 495	if (qproc->has_alt_reset) {
 496		reset_control_assert(qproc->pdc_reset);
 497		ret = reset_control_reset(qproc->mss_restart);
 498		reset_control_deassert(qproc->pdc_reset);
 499	} else if (qproc->has_spare_reg) {
 500		/*
 501		 * When the AXI pipeline is being reset with the Q6 modem partly
 502		 * operational there is possibility of AXI valid signal to
 503		 * glitch, leading to spurious transactions and Q6 hangs. A work
 504		 * around is employed by asserting the AXI_GATING_VALID_OVERRIDE
 505		 * BIT before triggering Q6 MSS reset. AXI_GATING_VALID_OVERRIDE
 506		 * is withdrawn post MSS assert followed by a MSS deassert,
 507		 * while holding the PDC reset.
 508		 */
 509		reset_control_assert(qproc->pdc_reset);
 510		regmap_update_bits(qproc->conn_map, qproc->conn_box,
 511				   AXI_GATING_VALID_OVERRIDE, 1);
 512		reset_control_assert(qproc->mss_restart);
 513		reset_control_deassert(qproc->pdc_reset);
 514		regmap_update_bits(qproc->conn_map, qproc->conn_box,
 515				   AXI_GATING_VALID_OVERRIDE, 0);
 516		ret = reset_control_deassert(qproc->mss_restart);
 517	} else if (qproc->has_ext_cntl_regs) {
 518		regmap_write(qproc->conn_map, qproc->rscc_disable, 0);
 519		reset_control_assert(qproc->pdc_reset);
 520		reset_control_assert(qproc->mss_restart);
 521		reset_control_deassert(qproc->pdc_reset);
 522		ret = reset_control_deassert(qproc->mss_restart);
 523	} else {
 524		ret = reset_control_assert(qproc->mss_restart);
 525	}
 526
 527	return ret;
 528}
 529
 530static int q6v5_reset_deassert(struct q6v5 *qproc)
 531{
 532	int ret;
 533
 534	if (qproc->has_alt_reset) {
 535		reset_control_assert(qproc->pdc_reset);
 536		writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
 537		ret = reset_control_reset(qproc->mss_restart);
 538		writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
 539		reset_control_deassert(qproc->pdc_reset);
 540	} else if (qproc->has_spare_reg || qproc->has_ext_cntl_regs) {
 541		ret = reset_control_reset(qproc->mss_restart);
 542	} else {
 543		ret = reset_control_deassert(qproc->mss_restart);
 544	}
 545
 546	return ret;
 547}
 548
 549static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
 550{
 551	unsigned long timeout;
 552	s32 val;
 553
 554	timeout = jiffies + msecs_to_jiffies(ms);
 555	for (;;) {
 556		val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
 557		if (val)
 558			break;
 559
 560		if (time_after(jiffies, timeout))
 561			return -ETIMEDOUT;
 562
 563		msleep(1);
 564	}
 565
 566	return val;
 567}
 568
 569static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
 570{
 571
 572	unsigned long timeout;
 573	s32 val;
 574
 575	timeout = jiffies + msecs_to_jiffies(ms);
 576	for (;;) {
 577		val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
 578		if (val < 0)
 579			break;
 580
 581		if (!status && val)
 582			break;
 583		else if (status && val == status)
 584			break;
 585
 586		if (time_after(jiffies, timeout))
 587			return -ETIMEDOUT;
 588
 589		msleep(1);
 590	}
 591
 592	return val;
 593}
 594
 595static void q6v5_dump_mba_logs(struct q6v5 *qproc)
 596{
 597	struct rproc *rproc = qproc->rproc;
 598	void *data;
 599	void *mba_region;
 600
 601	if (!qproc->has_mba_logs)
 602		return;
 603
 604	if (q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false, qproc->mba_phys,
 605				    qproc->mba_size))
 606		return;
 607
 608	mba_region = memremap(qproc->mba_phys, qproc->mba_size, MEMREMAP_WC);
 609	if (!mba_region)
 610		return;
 611
 612	data = vmalloc(MBA_LOG_SIZE);
 613	if (data) {
 614		memcpy(data, mba_region, MBA_LOG_SIZE);
 615		dev_coredumpv(&rproc->dev, data, MBA_LOG_SIZE, GFP_KERNEL);
 616	}
 617	memunmap(mba_region);
 618}
 619
 620static int q6v5proc_reset(struct q6v5 *qproc)
 621{
 622	u32 val;
 623	int ret;
 624	int i;
 625
 626	if (qproc->version == MSS_SDM845) {
 627		val = readl(qproc->reg_base + QDSP6SS_SLEEP);
 628		val |= Q6SS_CBCR_CLKEN;
 629		writel(val, qproc->reg_base + QDSP6SS_SLEEP);
 630
 631		ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
 632					 val, !(val & Q6SS_CBCR_CLKOFF), 1,
 633					 Q6SS_CBCR_TIMEOUT_US);
 634		if (ret) {
 635			dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
 636			return -ETIMEDOUT;
 637		}
 638
 639		/* De-assert QDSP6 stop core */
 640		writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
 641		/* Trigger boot FSM */
 642		writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
 643
 644		ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
 645				val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
 646		if (ret) {
 647			dev_err(qproc->dev, "Boot FSM failed to complete.\n");
 648			/* Reset the modem so that boot FSM is in reset state */
 649			q6v5_reset_deassert(qproc);
 650			return ret;
 651		}
 652
 653		goto pbl_wait;
 654	} else if (qproc->version == MSS_SC7180 || qproc->version == MSS_SC7280) {
 655		val = readl(qproc->reg_base + QDSP6SS_SLEEP);
 656		val |= Q6SS_CBCR_CLKEN;
 657		writel(val, qproc->reg_base + QDSP6SS_SLEEP);
 658
 659		ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
 660					 val, !(val & Q6SS_CBCR_CLKOFF), 1,
 661					 Q6SS_CBCR_TIMEOUT_US);
 662		if (ret) {
 663			dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
 664			return -ETIMEDOUT;
 665		}
 666
 667		/* Turn on the XO clock needed for PLL setup */
 668		val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
 669		val |= Q6SS_CBCR_CLKEN;
 670		writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
 671
 672		ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
 673					 val, !(val & Q6SS_CBCR_CLKOFF), 1,
 674					 Q6SS_CBCR_TIMEOUT_US);
 675		if (ret) {
 676			dev_err(qproc->dev, "QDSP6SS XO clock timed out\n");
 677			return -ETIMEDOUT;
 678		}
 679
 680		/* Configure Q6 core CBCR to auto-enable after reset sequence */
 681		val = readl(qproc->reg_base + QDSP6SS_CORE_CBCR);
 682		val |= Q6SS_CBCR_CLKEN;
 683		writel(val, qproc->reg_base + QDSP6SS_CORE_CBCR);
 684
 685		/* De-assert the Q6 stop core signal */
 686		writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
 687
 688		/* Wait for 10 us for any staggering logic to settle */
 689		usleep_range(10, 20);
 690
 691		/* Trigger the boot FSM to start the Q6 out-of-reset sequence */
 692		writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
 693
 694		/* Poll the MSS_STATUS for FSM completion */
 695		ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
 696					 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
 697		if (ret) {
 698			dev_err(qproc->dev, "Boot FSM failed to complete.\n");
 699			/* Reset the modem so that boot FSM is in reset state */
 700			q6v5_reset_deassert(qproc);
 701			return ret;
 702		}
 703		goto pbl_wait;
 704	} else if (qproc->version == MSS_MSM8909 ||
 705		   qproc->version == MSS_MSM8953 ||
 706		   qproc->version == MSS_MSM8996 ||
 707		   qproc->version == MSS_MSM8998 ||
 708		   qproc->version == MSS_SDM660) {
 709
 710		if (qproc->version != MSS_MSM8909 &&
 711		    qproc->version != MSS_MSM8953)
 712			/* Override the ACC value if required */
 713			writel(QDSP6SS_ACC_OVERRIDE_VAL,
 714			       qproc->reg_base + QDSP6SS_STRAP_ACC);
 715
 716		/* Assert resets, stop core */
 717		val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 718		val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
 719		writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 720
 721		/* BHS require xo cbcr to be enabled */
 722		val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
 723		val |= Q6SS_CBCR_CLKEN;
 724		writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
 725
 726		/* Read CLKOFF bit to go low indicating CLK is enabled */
 727		ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
 728					 val, !(val & Q6SS_CBCR_CLKOFF), 1,
 729					 Q6SS_CBCR_TIMEOUT_US);
 730		if (ret) {
 731			dev_err(qproc->dev,
 732				"xo cbcr enabling timed out (rc:%d)\n", ret);
 733			return ret;
 734		}
 735		/* Enable power block headswitch and wait for it to stabilize */
 736		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 737		val |= QDSP6v56_BHS_ON;
 738		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 739		val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 740		udelay(1);
 741
 742		if (qproc->version == MSS_SDM660) {
 743			ret = readl_relaxed_poll_timeout(qproc->reg_base + QDSP6V62SS_BHS_STATUS,
 744							 i, (i & QDSP6v55_BHS_EN_REST_ACK),
 745							 1, BHS_CHECK_MAX_LOOPS);
 746			if (ret == -ETIMEDOUT) {
 747				dev_err(qproc->dev, "BHS_EN_REST_ACK not set!\n");
 748				return -ETIMEDOUT;
 749			}
 750		}
 751
 752		/* Put LDO in bypass mode */
 753		val |= QDSP6v56_LDO_BYP;
 754		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 755
 756		if (qproc->version != MSS_MSM8909) {
 757			int mem_pwr_ctl;
 
 
 758
 759			/* Deassert QDSP6 compiler memory clamp */
 760			val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 761			val &= ~QDSP6v56_CLAMP_QMC_MEM;
 762			writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 763
 764			/* Deassert memory peripheral sleep and L2 memory standby */
 765			val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
 766			writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 767
 768			/* Turn on L1, L2, ETB and JU memories 1 at a time */
 769			if (qproc->version == MSS_MSM8953 ||
 770			    qproc->version == MSS_MSM8996) {
 771				mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL;
 772				i = 19;
 773			} else {
 774				/* MSS_MSM8998, MSS_SDM660 */
 775				mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL;
 776				i = 28;
 777			}
 778			val = readl(qproc->reg_base + mem_pwr_ctl);
 779			for (; i >= 0; i--) {
 780				val |= BIT(i);
 781				writel(val, qproc->reg_base + mem_pwr_ctl);
 782				/*
 783				 * Read back value to ensure the write is done then
 784				 * wait for 1us for both memory peripheral and data
 785				 * array to turn on.
 786				 */
 787				val |= readl(qproc->reg_base + mem_pwr_ctl);
 788				udelay(1);
 789			}
 790		} else {
 791			/* Turn on memories */
 792			val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 793			val |= Q6SS_SLP_RET_N | Q6SS_L2DATA_STBY_N |
 794			       Q6SS_ETB_SLP_NRET_N | QDSP6V55_MEM_BITS;
 795			writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 796
 797			/* Turn on L2 banks 1 at a time */
 798			for (i = 0; i <= 7; i++) {
 799				val |= BIT(i);
 800				writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 801			}
 
 
 
 
 802		}
 803
 804		/* Remove word line clamp */
 805		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 806		val &= ~QDSP6v56_CLAMP_WL;
 807		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 808	} else {
 809		/* Assert resets, stop core */
 810		val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 811		val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
 812		writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 813
 814		/* Enable power block headswitch and wait for it to stabilize */
 815		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 816		val |= QDSS_BHS_ON | QDSS_LDO_BYP;
 817		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 818		val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 819		udelay(1);
 820		/*
 821		 * Turn on memories. L2 banks should be done individually
 822		 * to minimize inrush current.
 823		 */
 824		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 825		val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
 826			Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
 827		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 828		val |= Q6SS_L2DATA_SLP_NRET_N_2;
 829		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 830		val |= Q6SS_L2DATA_SLP_NRET_N_1;
 831		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 832		val |= Q6SS_L2DATA_SLP_NRET_N_0;
 833		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 834	}
 835	/* Remove IO clamp */
 836	val &= ~Q6SS_CLAMP_IO;
 837	writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 838
 839	/* Bring core out of reset */
 840	val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 841	val &= ~Q6SS_CORE_ARES;
 842	writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 843
 844	/* Turn on core clock */
 845	val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
 846	val |= Q6SS_CLK_ENABLE;
 847	writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
 848
 849	/* Start core execution */
 850	val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 851	val &= ~Q6SS_STOP_CORE;
 852	writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 853
 854pbl_wait:
 855	/* Wait for PBL status */
 856	ret = q6v5_rmb_pbl_wait(qproc, 1000);
 857	if (ret == -ETIMEDOUT) {
 858		dev_err(qproc->dev, "PBL boot timed out\n");
 859	} else if (ret != RMB_PBL_SUCCESS) {
 860		dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret);
 861		ret = -EINVAL;
 862	} else {
 863		ret = 0;
 864	}
 865
 866	return ret;
 867}
 868
 869static int q6v5proc_enable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset)
 870{
 871	unsigned int val;
 872	int ret;
 873
 874	if (!qproc->has_qaccept_regs)
 875		return 0;
 876
 877	if (qproc->has_ext_cntl_regs) {
 878		regmap_write(qproc->conn_map, qproc->rscc_disable, 0);
 879		regmap_write(qproc->conn_map, qproc->force_clk_on, 1);
 880
 881		ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val,
 882					       !val, 1, Q6SS_CBCR_TIMEOUT_US);
 883		if (ret) {
 884			dev_err(qproc->dev, "failed to enable axim1 clock\n");
 885			return -ETIMEDOUT;
 886		}
 887	}
 888
 889	regmap_write(map, offset + QACCEPT_REQ_REG, 1);
 890
 891	/* Wait for accept */
 892	ret = regmap_read_poll_timeout(map, offset + QACCEPT_ACCEPT_REG, val, val, 5,
 893				       QACCEPT_TIMEOUT_US);
 894	if (ret) {
 895		dev_err(qproc->dev, "qchannel enable failed\n");
 896		return -ETIMEDOUT;
 897	}
 898
 899	return 0;
 900}
 901
 902static void q6v5proc_disable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset)
 903{
 904	int ret;
 905	unsigned int val, retry;
 906	unsigned int nretry = 10;
 907	bool takedown_complete = false;
 908
 909	if (!qproc->has_qaccept_regs)
 910		return;
 911
 912	while (!takedown_complete && nretry) {
 913		nretry--;
 914
 915		/* Wait for active transactions to complete */
 916		regmap_read_poll_timeout(map, offset + QACCEPT_ACTIVE_REG, val, !val, 5,
 917					 QACCEPT_TIMEOUT_US);
 918
 919		/* Request Q-channel transaction takedown */
 920		regmap_write(map, offset + QACCEPT_REQ_REG, 0);
 921
 922		/*
 923		 * If the request is denied, reset the Q-channel takedown request,
 924		 * wait for active transactions to complete and retry takedown.
 925		 */
 926		retry = 10;
 927		while (retry) {
 928			usleep_range(5, 10);
 929			retry--;
 930			ret = regmap_read(map, offset + QACCEPT_DENY_REG, &val);
 931			if (!ret && val) {
 932				regmap_write(map, offset + QACCEPT_REQ_REG, 1);
 933				break;
 934			}
 935
 936			ret = regmap_read(map, offset + QACCEPT_ACCEPT_REG, &val);
 937			if (!ret && !val) {
 938				takedown_complete = true;
 939				break;
 940			}
 941		}
 942
 943		if (!retry)
 944			break;
 945	}
 946
 947	/* Rely on mss_restart to clear out pending transactions on takedown failure */
 948	if (!takedown_complete)
 949		dev_err(qproc->dev, "qchannel takedown failed\n");
 950}
 951
 952static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
 953				   struct regmap *halt_map,
 954				   u32 offset)
 955{
 956	unsigned int val;
 957	int ret;
 958
 959	/* Check if we're already idle */
 960	ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
 961	if (!ret && val)
 962		return;
 963
 964	/* Assert halt request */
 965	regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
 966
 967	/* Wait for halt */
 968	regmap_read_poll_timeout(halt_map, offset + AXI_HALTACK_REG, val,
 969				 val, 1000, HALT_ACK_TIMEOUT_US);
 970
 971	ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
 972	if (ret || !val)
 973		dev_err(qproc->dev, "port failed halt\n");
 974
 975	/* Clear halt request (port will remain halted until reset) */
 976	regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
 977}
 978
 979static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw,
 980				const char *fw_name)
 981{
 982	unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
 
 
 
 983	dma_addr_t phys;
 984	void *metadata;
 985	u64 mdata_perm;
 986	int xferop_ret;
 987	size_t size;
 988	void *ptr;
 
 989	int ret;
 
 990
 991	metadata = qcom_mdt_read_metadata(fw, &size, fw_name, qproc->dev);
 992	if (IS_ERR(metadata))
 993		return PTR_ERR(metadata);
 994
 995	if (qproc->mdata_phys) {
 996		if (size > qproc->mdata_size) {
 997			ret = -EINVAL;
 998			dev_err(qproc->dev, "metadata size outside memory range\n");
 999			goto free_metadata;
1000		}
1001
1002		phys = qproc->mdata_phys;
1003		ptr = memremap(qproc->mdata_phys, size, MEMREMAP_WC);
1004		if (!ptr) {
1005			ret = -EBUSY;
1006			dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
1007				&qproc->mdata_phys, size);
1008			goto free_metadata;
1009		}
1010	} else {
1011		ptr = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs);
1012		if (!ptr) {
1013			ret = -ENOMEM;
1014			dev_err(qproc->dev, "failed to allocate mdt buffer\n");
1015			goto free_metadata;
1016		}
1017	}
1018
1019	memcpy(ptr, metadata, size);
 
1020
1021	if (qproc->mdata_phys)
1022		memunmap(ptr);
 
 
 
 
 
 
 
 
 
1023
1024	/* Hypervisor mapping to access metadata by modem */
1025	mdata_perm = BIT(QCOM_SCM_VMID_HLOS);
1026	ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, false, true,
1027				      phys, size);
1028	if (ret) {
1029		dev_err(qproc->dev,
1030			"assigning Q6 access to metadata failed: %d\n", ret);
1031		ret = -EAGAIN;
1032		goto free_dma_attrs;
1033	}
1034
1035	writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
1036	writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
1037
1038	ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000);
1039	if (ret == -ETIMEDOUT)
1040		dev_err(qproc->dev, "MPSS header authentication timed out\n");
1041	else if (ret < 0)
1042		dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret);
1043
1044	/* Metadata authentication done, remove modem access */
1045	xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, true, false,
1046					     phys, size);
1047	if (xferop_ret)
1048		dev_warn(qproc->dev,
1049			 "mdt buffer not reclaimed system may become unstable\n");
1050
1051free_dma_attrs:
1052	if (!qproc->mdata_phys)
1053		dma_free_attrs(qproc->dev, size, ptr, phys, dma_attrs);
1054free_metadata:
1055	kfree(metadata);
1056
1057	return ret < 0 ? ret : 0;
1058}
1059
1060static bool q6v5_phdr_valid(const struct elf32_phdr *phdr)
1061{
1062	if (phdr->p_type != PT_LOAD)
1063		return false;
1064
1065	if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH)
1066		return false;
1067
1068	if (!phdr->p_memsz)
1069		return false;
1070
1071	return true;
1072}
1073
1074static int q6v5_mba_load(struct q6v5 *qproc)
1075{
1076	int ret;
1077	int xfermemop_ret;
1078	bool mba_load_err = false;
1079
1080	ret = qcom_q6v5_prepare(&qproc->q6v5);
1081	if (ret)
1082		return ret;
1083
1084	ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1085	if (ret < 0) {
1086		dev_err(qproc->dev, "failed to enable proxy power domains\n");
1087		goto disable_irqs;
1088	}
1089
1090	ret = q6v5_regulator_enable(qproc, qproc->fallback_proxy_regs,
1091				    qproc->fallback_proxy_reg_count);
1092	if (ret) {
1093		dev_err(qproc->dev, "failed to enable fallback proxy supplies\n");
1094		goto disable_proxy_pds;
1095	}
1096
1097	ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
1098				    qproc->proxy_reg_count);
1099	if (ret) {
1100		dev_err(qproc->dev, "failed to enable proxy supplies\n");
1101		goto disable_fallback_proxy_reg;
1102	}
1103
1104	ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
1105			      qproc->proxy_clk_count);
1106	if (ret) {
1107		dev_err(qproc->dev, "failed to enable proxy clocks\n");
1108		goto disable_proxy_reg;
1109	}
1110
1111	ret = q6v5_regulator_enable(qproc, qproc->active_regs,
1112				    qproc->active_reg_count);
1113	if (ret) {
1114		dev_err(qproc->dev, "failed to enable supplies\n");
1115		goto disable_proxy_clk;
1116	}
1117
1118	ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
1119			      qproc->reset_clk_count);
1120	if (ret) {
1121		dev_err(qproc->dev, "failed to enable reset clocks\n");
1122		goto disable_vdd;
1123	}
1124
1125	ret = q6v5_reset_deassert(qproc);
1126	if (ret) {
1127		dev_err(qproc->dev, "failed to deassert mss restart\n");
1128		goto disable_reset_clks;
1129	}
1130
1131	ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
1132			      qproc->active_clk_count);
1133	if (ret) {
1134		dev_err(qproc->dev, "failed to enable clocks\n");
1135		goto assert_reset;
1136	}
1137
1138	ret = q6v5proc_enable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
1139	if (ret) {
1140		dev_err(qproc->dev, "failed to enable axi bridge\n");
1141		goto disable_active_clks;
1142	}
1143
1144	/*
1145	 * Some versions of the MBA firmware will upon boot wipe the MPSS region as well, so provide
1146	 * the Q6 access to this region.
1147	 */
1148	ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
1149				      qproc->mpss_phys, qproc->mpss_size);
1150	if (ret) {
1151		dev_err(qproc->dev, "assigning Q6 access to mpss memory failed: %d\n", ret);
1152		goto disable_active_clks;
1153	}
1154
1155	/* Assign MBA image access in DDR to q6 */
1156	ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, true,
1157				      qproc->mba_phys, qproc->mba_size);
1158	if (ret) {
1159		dev_err(qproc->dev,
1160			"assigning Q6 access to mba memory failed: %d\n", ret);
1161		goto disable_active_clks;
1162	}
1163
1164	writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
1165	if (qproc->dp_size) {
1166		writel(qproc->mba_phys + SZ_1M, qproc->rmb_base + RMB_PMI_CODE_START_REG);
1167		writel(qproc->dp_size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1168	}
1169
1170	ret = q6v5proc_reset(qproc);
1171	if (ret)
1172		goto reclaim_mba;
1173
1174	if (qproc->has_mba_logs)
1175		qcom_pil_info_store("mba", qproc->mba_phys, MBA_LOG_SIZE);
1176
1177	ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
1178	if (ret == -ETIMEDOUT) {
1179		dev_err(qproc->dev, "MBA boot timed out\n");
1180		goto halt_axi_ports;
1181	} else if (ret != RMB_MBA_XPU_UNLOCKED &&
1182		   ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
1183		dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
1184		ret = -EINVAL;
1185		goto halt_axi_ports;
1186	}
1187
1188	qproc->dump_mba_loaded = true;
1189	return 0;
1190
1191halt_axi_ports:
1192	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
1193	if (qproc->has_vq6)
1194		q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6);
1195	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
1196	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
1197	q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm);
1198	q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx);
1199	q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
1200	mba_load_err = true;
1201reclaim_mba:
1202	xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
1203						false, qproc->mba_phys,
1204						qproc->mba_size);
1205	if (xfermemop_ret) {
1206		dev_err(qproc->dev,
1207			"Failed to reclaim mba buffer, system may become unstable\n");
1208	} else if (mba_load_err) {
1209		q6v5_dump_mba_logs(qproc);
1210	}
1211
1212disable_active_clks:
1213	q6v5_clk_disable(qproc->dev, qproc->active_clks,
1214			 qproc->active_clk_count);
1215assert_reset:
1216	q6v5_reset_assert(qproc);
1217disable_reset_clks:
1218	q6v5_clk_disable(qproc->dev, qproc->reset_clks,
1219			 qproc->reset_clk_count);
1220disable_vdd:
1221	q6v5_regulator_disable(qproc, qproc->active_regs,
1222			       qproc->active_reg_count);
1223disable_proxy_clk:
1224	q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1225			 qproc->proxy_clk_count);
1226disable_proxy_reg:
1227	q6v5_regulator_disable(qproc, qproc->proxy_regs,
1228			       qproc->proxy_reg_count);
1229disable_fallback_proxy_reg:
1230	q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs,
1231			       qproc->fallback_proxy_reg_count);
1232disable_proxy_pds:
1233	q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1234disable_irqs:
1235	qcom_q6v5_unprepare(&qproc->q6v5);
1236
1237	return ret;
1238}
1239
1240static void q6v5_mba_reclaim(struct q6v5 *qproc)
1241{
1242	int ret;
1243	u32 val;
1244
1245	qproc->dump_mba_loaded = false;
1246	qproc->dp_size = 0;
1247
1248	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
1249	if (qproc->has_vq6)
1250		q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6);
1251	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
1252	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
1253	if (qproc->version == MSS_MSM8996) {
1254		/*
1255		 * To avoid high MX current during LPASS/MSS restart.
1256		 */
1257		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1258		val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL |
1259			QDSP6v56_CLAMP_QMC_MEM;
1260		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1261	}
1262
1263	if (qproc->has_ext_cntl_regs) {
1264		regmap_write(qproc->conn_map, qproc->rscc_disable, 1);
1265
1266		ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val,
1267					       !val, 1, Q6SS_CBCR_TIMEOUT_US);
1268		if (ret)
1269			dev_err(qproc->dev, "failed to enable axim1 clock\n");
1270
1271		ret = regmap_read_poll_timeout(qproc->halt_map, qproc->crypto_clk_off, val,
1272					       !val, 1, Q6SS_CBCR_TIMEOUT_US);
1273		if (ret)
1274			dev_err(qproc->dev, "failed to enable crypto clock\n");
1275	}
1276
1277	q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm);
1278	q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx);
1279	q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
1280
1281	q6v5_reset_assert(qproc);
1282
1283	q6v5_clk_disable(qproc->dev, qproc->reset_clks,
1284			 qproc->reset_clk_count);
1285	q6v5_clk_disable(qproc->dev, qproc->active_clks,
1286			 qproc->active_clk_count);
1287	q6v5_regulator_disable(qproc, qproc->active_regs,
1288			       qproc->active_reg_count);
1289
1290	/* In case of failure or coredump scenario where reclaiming MBA memory
1291	 * could not happen reclaim it here.
1292	 */
1293	ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false,
1294				      qproc->mba_phys,
1295				      qproc->mba_size);
1296	WARN_ON(ret);
1297
1298	ret = qcom_q6v5_unprepare(&qproc->q6v5);
1299	if (ret) {
1300		q6v5_pds_disable(qproc, qproc->proxy_pds,
1301				 qproc->proxy_pd_count);
1302		q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1303				 qproc->proxy_clk_count);
1304		q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs,
1305				       qproc->fallback_proxy_reg_count);
1306		q6v5_regulator_disable(qproc, qproc->proxy_regs,
1307				       qproc->proxy_reg_count);
1308	}
1309}
1310
1311static int q6v5_reload_mba(struct rproc *rproc)
1312{
1313	struct q6v5 *qproc = rproc->priv;
1314	const struct firmware *fw;
1315	int ret;
1316
1317	ret = request_firmware(&fw, rproc->firmware, qproc->dev);
1318	if (ret < 0)
1319		return ret;
1320
1321	q6v5_load(rproc, fw);
1322	ret = q6v5_mba_load(qproc);
1323	release_firmware(fw);
1324
1325	return ret;
1326}
1327
1328static int q6v5_mpss_load(struct q6v5 *qproc)
1329{
1330	const struct elf32_phdr *phdrs;
1331	const struct elf32_phdr *phdr;
1332	const struct firmware *seg_fw;
1333	const struct firmware *fw;
1334	struct elf32_hdr *ehdr;
1335	phys_addr_t mpss_reloc;
1336	phys_addr_t boot_addr;
1337	phys_addr_t min_addr = PHYS_ADDR_MAX;
1338	phys_addr_t max_addr = 0;
1339	u32 code_length;
1340	bool relocate = false;
1341	char *fw_name;
1342	size_t fw_name_len;
1343	ssize_t offset;
1344	size_t size = 0;
1345	void *ptr;
1346	int ret;
1347	int i;
1348
1349	fw_name_len = strlen(qproc->hexagon_mdt_image);
1350	if (fw_name_len <= 4)
1351		return -EINVAL;
1352
1353	fw_name = kstrdup(qproc->hexagon_mdt_image, GFP_KERNEL);
1354	if (!fw_name)
1355		return -ENOMEM;
1356
1357	ret = request_firmware(&fw, fw_name, qproc->dev);
1358	if (ret < 0) {
1359		dev_err(qproc->dev, "unable to load %s\n", fw_name);
1360		goto out;
1361	}
1362
1363	/* Initialize the RMB validator */
1364	writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1365
1366	ret = q6v5_mpss_init_image(qproc, fw, qproc->hexagon_mdt_image);
1367	if (ret)
1368		goto release_firmware;
1369
1370	ehdr = (struct elf32_hdr *)fw->data;
1371	phdrs = (struct elf32_phdr *)(ehdr + 1);
1372
1373	for (i = 0; i < ehdr->e_phnum; i++) {
1374		phdr = &phdrs[i];
1375
1376		if (!q6v5_phdr_valid(phdr))
1377			continue;
1378
1379		if (phdr->p_flags & QCOM_MDT_RELOCATABLE)
1380			relocate = true;
1381
1382		if (phdr->p_paddr < min_addr)
1383			min_addr = phdr->p_paddr;
1384
1385		if (phdr->p_paddr + phdr->p_memsz > max_addr)
1386			max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);
1387	}
1388
1389	if (qproc->version == MSS_MSM8953) {
1390		ret = qcom_scm_pas_mem_setup(MPSS_PAS_ID, qproc->mpss_phys, qproc->mpss_size);
1391		if (ret) {
1392			dev_err(qproc->dev,
1393				"setting up mpss memory failed: %d\n", ret);
1394			goto release_firmware;
1395		}
1396	}
1397
1398	/*
1399	 * In case of a modem subsystem restart on secure devices, the modem
1400	 * memory can be reclaimed only after MBA is loaded.
1401	 */
1402	q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, false,
1403				qproc->mpss_phys, qproc->mpss_size);
1404
1405	/* Share ownership between Linux and MSS, during segment loading */
1406	ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, true,
1407				      qproc->mpss_phys, qproc->mpss_size);
1408	if (ret) {
1409		dev_err(qproc->dev,
1410			"assigning Q6 access to mpss memory failed: %d\n", ret);
1411		ret = -EAGAIN;
1412		goto release_firmware;
1413	}
1414
1415	mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
1416	qproc->mpss_reloc = mpss_reloc;
1417	/* Load firmware segments */
1418	for (i = 0; i < ehdr->e_phnum; i++) {
1419		phdr = &phdrs[i];
1420
1421		if (!q6v5_phdr_valid(phdr))
1422			continue;
1423
1424		offset = phdr->p_paddr - mpss_reloc;
1425		if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) {
1426			dev_err(qproc->dev, "segment outside memory range\n");
1427			ret = -EINVAL;
1428			goto release_firmware;
1429		}
1430
1431		if (phdr->p_filesz > phdr->p_memsz) {
1432			dev_err(qproc->dev,
1433				"refusing to load segment %d with p_filesz > p_memsz\n",
1434				i);
1435			ret = -EINVAL;
1436			goto release_firmware;
1437		}
1438
1439		ptr = memremap(qproc->mpss_phys + offset, phdr->p_memsz, MEMREMAP_WC);
1440		if (!ptr) {
1441			dev_err(qproc->dev,
1442				"unable to map memory region: %pa+%zx-%x\n",
1443				&qproc->mpss_phys, offset, phdr->p_memsz);
1444			goto release_firmware;
1445		}
1446
1447		if (phdr->p_filesz && phdr->p_offset < fw->size) {
1448			/* Firmware is large enough to be non-split */
1449			if (phdr->p_offset + phdr->p_filesz > fw->size) {
1450				dev_err(qproc->dev,
1451					"failed to load segment %d from truncated file %s\n",
1452					i, fw_name);
1453				ret = -EINVAL;
1454				memunmap(ptr);
1455				goto release_firmware;
1456			}
1457
1458			memcpy(ptr, fw->data + phdr->p_offset, phdr->p_filesz);
1459		} else if (phdr->p_filesz) {
1460			/* Replace "xxx.xxx" with "xxx.bxx" */
1461			sprintf(fw_name + fw_name_len - 3, "b%02d", i);
1462			ret = request_firmware_into_buf(&seg_fw, fw_name, qproc->dev,
1463							ptr, phdr->p_filesz);
1464			if (ret) {
1465				dev_err(qproc->dev, "failed to load %s\n", fw_name);
1466				memunmap(ptr);
1467				goto release_firmware;
1468			}
1469
1470			if (seg_fw->size != phdr->p_filesz) {
1471				dev_err(qproc->dev,
1472					"failed to load segment %d from truncated file %s\n",
1473					i, fw_name);
1474				ret = -EINVAL;
1475				release_firmware(seg_fw);
1476				memunmap(ptr);
1477				goto release_firmware;
1478			}
1479
1480			release_firmware(seg_fw);
1481		}
1482
1483		if (phdr->p_memsz > phdr->p_filesz) {
1484			memset(ptr + phdr->p_filesz, 0,
1485			       phdr->p_memsz - phdr->p_filesz);
1486		}
1487		memunmap(ptr);
1488		size += phdr->p_memsz;
1489
1490		code_length = readl(qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1491		if (!code_length) {
1492			boot_addr = relocate ? qproc->mpss_phys : min_addr;
1493			writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
1494			writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
1495		}
1496		writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1497
1498		ret = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
1499		if (ret < 0) {
1500			dev_err(qproc->dev, "MPSS authentication failed: %d\n",
1501				ret);
1502			goto release_firmware;
1503		}
1504	}
1505
1506	/* Transfer ownership of modem ddr region to q6 */
1507	ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
1508				      qproc->mpss_phys, qproc->mpss_size);
1509	if (ret) {
1510		dev_err(qproc->dev,
1511			"assigning Q6 access to mpss memory failed: %d\n", ret);
1512		ret = -EAGAIN;
1513		goto release_firmware;
1514	}
1515
1516	ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000);
1517	if (ret == -ETIMEDOUT)
1518		dev_err(qproc->dev, "MPSS authentication timed out\n");
1519	else if (ret < 0)
1520		dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret);
1521
1522	qcom_pil_info_store("modem", qproc->mpss_phys, qproc->mpss_size);
1523
1524release_firmware:
1525	release_firmware(fw);
1526out:
1527	kfree(fw_name);
1528
1529	return ret < 0 ? ret : 0;
1530}
1531
1532static void qcom_q6v5_dump_segment(struct rproc *rproc,
1533				   struct rproc_dump_segment *segment,
1534				   void *dest, size_t cp_offset, size_t size)
1535{
1536	int ret = 0;
1537	struct q6v5 *qproc = rproc->priv;
1538	int offset = segment->da - qproc->mpss_reloc;
1539	void *ptr = NULL;
1540
1541	/* Unlock mba before copying segments */
1542	if (!qproc->dump_mba_loaded) {
1543		ret = q6v5_reload_mba(rproc);
1544		if (!ret) {
1545			/* Reset ownership back to Linux to copy segments */
1546			ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1547						      true, false,
1548						      qproc->mpss_phys,
1549						      qproc->mpss_size);
1550		}
1551	}
1552
1553	if (!ret)
1554		ptr = memremap(qproc->mpss_phys + offset + cp_offset, size, MEMREMAP_WC);
1555
1556	if (ptr) {
1557		memcpy(dest, ptr, size);
1558		memunmap(ptr);
1559	} else {
1560		memset(dest, 0xff, size);
1561	}
1562
1563	qproc->current_dump_size += size;
1564
1565	/* Reclaim mba after copying segments */
1566	if (qproc->current_dump_size == qproc->total_dump_size) {
1567		if (qproc->dump_mba_loaded) {
1568			/* Try to reset ownership back to Q6 */
1569			q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1570						false, true,
1571						qproc->mpss_phys,
1572						qproc->mpss_size);
1573			q6v5_mba_reclaim(qproc);
1574		}
1575	}
1576}
1577
1578static int q6v5_start(struct rproc *rproc)
1579{
1580	struct q6v5 *qproc = rproc->priv;
1581	int xfermemop_ret;
1582	int ret;
1583
1584	ret = q6v5_mba_load(qproc);
1585	if (ret)
1586		return ret;
1587
1588	dev_info(qproc->dev, "MBA booted with%s debug policy, loading mpss\n",
1589		 qproc->dp_size ? "" : "out");
1590
1591	ret = q6v5_mpss_load(qproc);
1592	if (ret)
1593		goto reclaim_mpss;
1594
1595	ret = qcom_q6v5_wait_for_start(&qproc->q6v5, msecs_to_jiffies(5000));
1596	if (ret == -ETIMEDOUT) {
1597		dev_err(qproc->dev, "start timed out\n");
1598		goto reclaim_mpss;
1599	}
1600
1601	xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
1602						false, qproc->mba_phys,
1603						qproc->mba_size);
1604	if (xfermemop_ret)
1605		dev_err(qproc->dev,
1606			"Failed to reclaim mba buffer system may become unstable\n");
1607
1608	/* Reset Dump Segment Mask */
1609	qproc->current_dump_size = 0;
1610
1611	return 0;
1612
1613reclaim_mpss:
1614	q6v5_mba_reclaim(qproc);
1615	q6v5_dump_mba_logs(qproc);
1616
1617	return ret;
1618}
1619
1620static int q6v5_stop(struct rproc *rproc)
1621{
1622	struct q6v5 *qproc = rproc->priv;
1623	int ret;
1624
1625	ret = qcom_q6v5_request_stop(&qproc->q6v5, qproc->sysmon);
1626	if (ret == -ETIMEDOUT)
1627		dev_err(qproc->dev, "timed out on wait\n");
1628
1629	q6v5_mba_reclaim(qproc);
1630
1631	return 0;
1632}
1633
1634static int qcom_q6v5_register_dump_segments(struct rproc *rproc,
1635					    const struct firmware *mba_fw)
1636{
1637	const struct firmware *fw;
1638	const struct elf32_phdr *phdrs;
1639	const struct elf32_phdr *phdr;
1640	const struct elf32_hdr *ehdr;
1641	struct q6v5 *qproc = rproc->priv;
1642	unsigned long i;
1643	int ret;
1644
1645	ret = request_firmware(&fw, qproc->hexagon_mdt_image, qproc->dev);
1646	if (ret < 0) {
1647		dev_err(qproc->dev, "unable to load %s\n",
1648			qproc->hexagon_mdt_image);
1649		return ret;
1650	}
1651
1652	rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
1653
1654	ehdr = (struct elf32_hdr *)fw->data;
1655	phdrs = (struct elf32_phdr *)(ehdr + 1);
1656	qproc->total_dump_size = 0;
1657
1658	for (i = 0; i < ehdr->e_phnum; i++) {
1659		phdr = &phdrs[i];
1660
1661		if (!q6v5_phdr_valid(phdr))
1662			continue;
1663
1664		ret = rproc_coredump_add_custom_segment(rproc, phdr->p_paddr,
1665							phdr->p_memsz,
1666							qcom_q6v5_dump_segment,
1667							NULL);
1668		if (ret)
1669			break;
1670
1671		qproc->total_dump_size += phdr->p_memsz;
1672	}
1673
1674	release_firmware(fw);
1675	return ret;
1676}
1677
1678static unsigned long q6v5_panic(struct rproc *rproc)
1679{
1680	struct q6v5 *qproc = rproc->priv;
1681
1682	return qcom_q6v5_panic(&qproc->q6v5);
1683}
1684
1685static const struct rproc_ops q6v5_ops = {
1686	.start = q6v5_start,
1687	.stop = q6v5_stop,
1688	.parse_fw = qcom_q6v5_register_dump_segments,
1689	.load = q6v5_load,
1690	.panic = q6v5_panic,
1691};
1692
1693static void qcom_msa_handover(struct qcom_q6v5 *q6v5)
1694{
1695	struct q6v5 *qproc = container_of(q6v5, struct q6v5, q6v5);
1696
1697	q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1698			 qproc->proxy_clk_count);
1699	q6v5_regulator_disable(qproc, qproc->proxy_regs,
1700			       qproc->proxy_reg_count);
1701	q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs,
1702			       qproc->fallback_proxy_reg_count);
1703	q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1704}
1705
1706static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
1707{
1708	struct of_phandle_args args;
1709	int halt_cell_cnt = 3;
1710	int ret;
1711
1712	qproc->reg_base = devm_platform_ioremap_resource_byname(pdev, "qdsp6");
1713	if (IS_ERR(qproc->reg_base))
1714		return PTR_ERR(qproc->reg_base);
1715
1716	qproc->rmb_base = devm_platform_ioremap_resource_byname(pdev, "rmb");
1717	if (IS_ERR(qproc->rmb_base))
1718		return PTR_ERR(qproc->rmb_base);
1719
1720	if (qproc->has_vq6)
1721		halt_cell_cnt++;
1722
1723	ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1724					       "qcom,halt-regs", halt_cell_cnt, 0, &args);
1725	if (ret < 0) {
1726		dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
1727		return -EINVAL;
1728	}
1729
1730	qproc->halt_map = syscon_node_to_regmap(args.np);
1731	of_node_put(args.np);
1732	if (IS_ERR(qproc->halt_map))
1733		return PTR_ERR(qproc->halt_map);
1734
1735	qproc->halt_q6 = args.args[0];
1736	qproc->halt_modem = args.args[1];
1737	qproc->halt_nc = args.args[2];
1738
1739	if (qproc->has_vq6)
1740		qproc->halt_vq6 = args.args[3];
1741
1742	if (qproc->has_qaccept_regs) {
1743		ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1744						       "qcom,qaccept-regs",
1745						       3, 0, &args);
1746		if (ret < 0) {
1747			dev_err(&pdev->dev, "failed to parse qaccept-regs\n");
1748			return -EINVAL;
1749		}
1750
1751		qproc->qaccept_mdm = args.args[0];
1752		qproc->qaccept_cx = args.args[1];
1753		qproc->qaccept_axi = args.args[2];
1754	}
1755
1756	if (qproc->has_ext_cntl_regs) {
1757		ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1758						       "qcom,ext-regs",
1759						       2, 0, &args);
1760		if (ret < 0) {
1761			dev_err(&pdev->dev, "failed to parse ext-regs index 0\n");
1762			return -EINVAL;
1763		}
1764
1765		qproc->conn_map = syscon_node_to_regmap(args.np);
1766		of_node_put(args.np);
1767		if (IS_ERR(qproc->conn_map))
1768			return PTR_ERR(qproc->conn_map);
1769
1770		qproc->force_clk_on = args.args[0];
1771		qproc->rscc_disable = args.args[1];
1772
1773		ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1774						       "qcom,ext-regs",
1775						       2, 1, &args);
1776		if (ret < 0) {
1777			dev_err(&pdev->dev, "failed to parse ext-regs index 1\n");
1778			return -EINVAL;
1779		}
1780
1781		qproc->axim1_clk_off = args.args[0];
1782		qproc->crypto_clk_off = args.args[1];
1783	}
1784
1785	if (qproc->has_spare_reg) {
1786		ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1787						       "qcom,spare-regs",
1788						       1, 0, &args);
1789		if (ret < 0) {
1790			dev_err(&pdev->dev, "failed to parse spare-regs\n");
1791			return -EINVAL;
1792		}
1793
1794		qproc->conn_map = syscon_node_to_regmap(args.np);
1795		of_node_put(args.np);
1796		if (IS_ERR(qproc->conn_map))
1797			return PTR_ERR(qproc->conn_map);
1798
1799		qproc->conn_box = args.args[0];
1800	}
1801
1802	return 0;
1803}
1804
1805static int q6v5_init_clocks(struct device *dev, struct clk **clks,
1806		char **clk_names)
1807{
1808	int i;
1809
1810	if (!clk_names)
1811		return 0;
1812
1813	for (i = 0; clk_names[i]; i++) {
1814		clks[i] = devm_clk_get(dev, clk_names[i]);
1815		if (IS_ERR(clks[i])) {
1816			int rc = PTR_ERR(clks[i]);
1817
1818			if (rc != -EPROBE_DEFER)
1819				dev_err(dev, "Failed to get %s clock\n",
1820					clk_names[i]);
1821			return rc;
1822		}
1823	}
1824
1825	return i;
1826}
1827
1828static int q6v5_pds_attach(struct device *dev, struct device **devs,
1829			   char **pd_names)
1830{
1831	size_t num_pds = 0;
1832	int ret;
1833	int i;
1834
1835	if (!pd_names)
1836		return 0;
1837
1838	while (pd_names[num_pds])
1839		num_pds++;
1840
1841	for (i = 0; i < num_pds; i++) {
1842		devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
1843		if (IS_ERR_OR_NULL(devs[i])) {
1844			ret = PTR_ERR(devs[i]) ? : -ENODATA;
1845			goto unroll_attach;
1846		}
1847	}
1848
1849	return num_pds;
1850
1851unroll_attach:
1852	for (i--; i >= 0; i--)
1853		dev_pm_domain_detach(devs[i], false);
1854
1855	return ret;
1856}
1857
1858static void q6v5_pds_detach(struct q6v5 *qproc, struct device **pds,
1859			    size_t pd_count)
1860{
1861	int i;
1862
1863	for (i = 0; i < pd_count; i++)
1864		dev_pm_domain_detach(pds[i], false);
1865}
1866
1867static int q6v5_init_reset(struct q6v5 *qproc)
1868{
1869	qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
1870							      "mss_restart");
1871	if (IS_ERR(qproc->mss_restart)) {
1872		dev_err(qproc->dev, "failed to acquire mss restart\n");
1873		return PTR_ERR(qproc->mss_restart);
1874	}
1875
1876	if (qproc->has_alt_reset || qproc->has_spare_reg || qproc->has_ext_cntl_regs) {
1877		qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
1878								    "pdc_reset");
1879		if (IS_ERR(qproc->pdc_reset)) {
1880			dev_err(qproc->dev, "failed to acquire pdc reset\n");
1881			return PTR_ERR(qproc->pdc_reset);
1882		}
1883	}
1884
1885	return 0;
1886}
1887
1888static int q6v5_alloc_memory_region(struct q6v5 *qproc)
1889{
1890	struct device_node *child;
1891	struct reserved_mem *rmem;
1892	struct device_node *node;
 
 
1893
1894	/*
1895	 * In the absence of mba/mpss sub-child, extract the mba and mpss
1896	 * reserved memory regions from device's memory-region property.
1897	 */
1898	child = of_get_child_by_name(qproc->dev->of_node, "mba");
1899	if (!child) {
1900		node = of_parse_phandle(qproc->dev->of_node,
1901					"memory-region", 0);
1902	} else {
1903		node = of_parse_phandle(child, "memory-region", 0);
1904		of_node_put(child);
1905	}
1906
1907	if (!node) {
1908		dev_err(qproc->dev, "no mba memory-region specified\n");
1909		return -EINVAL;
1910	}
1911
1912	rmem = of_reserved_mem_lookup(node);
1913	of_node_put(node);
1914	if (!rmem) {
1915		dev_err(qproc->dev, "unable to resolve mba region\n");
1916		return -EINVAL;
1917	}
1918
1919	qproc->mba_phys = rmem->base;
1920	qproc->mba_size = rmem->size;
1921
1922	if (!child) {
1923		node = of_parse_phandle(qproc->dev->of_node,
1924					"memory-region", 1);
1925	} else {
1926		child = of_get_child_by_name(qproc->dev->of_node, "mpss");
1927		node = of_parse_phandle(child, "memory-region", 0);
1928		of_node_put(child);
1929	}
1930
1931	if (!node) {
1932		dev_err(qproc->dev, "no mpss memory-region specified\n");
1933		return -EINVAL;
1934	}
1935
1936	rmem = of_reserved_mem_lookup(node);
1937	of_node_put(node);
1938	if (!rmem) {
1939		dev_err(qproc->dev, "unable to resolve mpss region\n");
1940		return -EINVAL;
1941	}
1942
1943	qproc->mpss_phys = qproc->mpss_reloc = rmem->base;
1944	qproc->mpss_size = rmem->size;
1945
1946	if (!child) {
1947		node = of_parse_phandle(qproc->dev->of_node, "memory-region", 2);
1948	} else {
1949		child = of_get_child_by_name(qproc->dev->of_node, "metadata");
1950		node = of_parse_phandle(child, "memory-region", 0);
1951		of_node_put(child);
1952	}
1953
1954	if (!node)
1955		return 0;
1956
1957	rmem = of_reserved_mem_lookup(node);
1958	if (!rmem) {
1959		dev_err(qproc->dev, "unable to resolve metadata region\n");
1960		return -EINVAL;
1961	}
1962
1963	qproc->mdata_phys = rmem->base;
1964	qproc->mdata_size = rmem->size;
1965
1966	return 0;
1967}
1968
1969static int q6v5_probe(struct platform_device *pdev)
1970{
1971	const struct rproc_hexagon_res *desc;
1972	struct device_node *node;
1973	struct q6v5 *qproc;
1974	struct rproc *rproc;
1975	const char *mba_image;
1976	int ret;
1977
1978	desc = of_device_get_match_data(&pdev->dev);
1979	if (!desc)
1980		return -EINVAL;
1981
1982	if (desc->need_mem_protection && !qcom_scm_is_available())
1983		return -EPROBE_DEFER;
1984
1985	mba_image = desc->hexagon_mba_image;
1986	ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
1987					    0, &mba_image);
1988	if (ret < 0 && ret != -EINVAL) {
1989		dev_err(&pdev->dev, "unable to read mba firmware-name\n");
1990		return ret;
1991	}
1992
1993	rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
1994			    mba_image, sizeof(*qproc));
1995	if (!rproc) {
1996		dev_err(&pdev->dev, "failed to allocate rproc\n");
1997		return -ENOMEM;
1998	}
1999
2000	rproc->auto_boot = false;
2001	rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
2002
2003	qproc = rproc->priv;
2004	qproc->dev = &pdev->dev;
2005	qproc->rproc = rproc;
2006	qproc->hexagon_mdt_image = "modem.mdt";
2007	ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
2008					    1, &qproc->hexagon_mdt_image);
2009	if (ret < 0 && ret != -EINVAL) {
2010		dev_err(&pdev->dev, "unable to read mpss firmware-name\n");
2011		goto free_rproc;
2012	}
2013
2014	platform_set_drvdata(pdev, qproc);
2015
2016	qproc->has_qaccept_regs = desc->has_qaccept_regs;
2017	qproc->has_ext_cntl_regs = desc->has_ext_cntl_regs;
2018	qproc->has_vq6 = desc->has_vq6;
2019	qproc->has_spare_reg = desc->has_spare_reg;
2020	ret = q6v5_init_mem(qproc, pdev);
2021	if (ret)
2022		goto free_rproc;
2023
2024	ret = q6v5_alloc_memory_region(qproc);
2025	if (ret)
2026		goto free_rproc;
2027
2028	ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks,
2029			       desc->proxy_clk_names);
2030	if (ret < 0) {
2031		dev_err(&pdev->dev, "Failed to get proxy clocks.\n");
2032		goto free_rproc;
2033	}
2034	qproc->proxy_clk_count = ret;
2035
2036	ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
2037			       desc->reset_clk_names);
2038	if (ret < 0) {
2039		dev_err(&pdev->dev, "Failed to get reset clocks.\n");
2040		goto free_rproc;
2041	}
2042	qproc->reset_clk_count = ret;
2043
2044	ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
2045			       desc->active_clk_names);
2046	if (ret < 0) {
2047		dev_err(&pdev->dev, "Failed to get active clocks.\n");
2048		goto free_rproc;
2049	}
2050	qproc->active_clk_count = ret;
2051
2052	ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs,
2053				  desc->proxy_supply);
2054	if (ret < 0) {
2055		dev_err(&pdev->dev, "Failed to get proxy regulators.\n");
2056		goto free_rproc;
2057	}
2058	qproc->proxy_reg_count = ret;
2059
2060	ret = q6v5_regulator_init(&pdev->dev,  qproc->active_regs,
2061				  desc->active_supply);
2062	if (ret < 0) {
2063		dev_err(&pdev->dev, "Failed to get active regulators.\n");
2064		goto free_rproc;
2065	}
2066	qproc->active_reg_count = ret;
2067
2068	ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds,
2069			      desc->proxy_pd_names);
2070	/* Fallback to regulators for old device trees */
2071	if (ret == -ENODATA && desc->fallback_proxy_supply) {
2072		ret = q6v5_regulator_init(&pdev->dev,
2073					  qproc->fallback_proxy_regs,
2074					  desc->fallback_proxy_supply);
2075		if (ret < 0) {
2076			dev_err(&pdev->dev, "Failed to get fallback proxy regulators.\n");
2077			goto free_rproc;
2078		}
2079		qproc->fallback_proxy_reg_count = ret;
2080	} else if (ret < 0) {
2081		dev_err(&pdev->dev, "Failed to init power domains\n");
2082		goto free_rproc;
2083	} else {
2084		qproc->proxy_pd_count = ret;
2085	}
2086
2087	qproc->has_alt_reset = desc->has_alt_reset;
2088	ret = q6v5_init_reset(qproc);
2089	if (ret)
2090		goto detach_proxy_pds;
2091
2092	qproc->version = desc->version;
2093	qproc->need_mem_protection = desc->need_mem_protection;
2094	qproc->has_mba_logs = desc->has_mba_logs;
2095
2096	ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM, "modem",
2097			     qcom_msa_handover);
2098	if (ret)
2099		goto detach_proxy_pds;
2100
2101	qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
2102	qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
2103	qcom_add_glink_subdev(rproc, &qproc->glink_subdev, "mpss");
2104	qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
2105	qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
2106	qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
2107	if (IS_ERR(qproc->sysmon)) {
2108		ret = PTR_ERR(qproc->sysmon);
2109		goto remove_subdevs;
2110	}
2111
2112	ret = rproc_add(rproc);
2113	if (ret)
2114		goto remove_sysmon_subdev;
2115
2116	node = of_get_compatible_child(pdev->dev.of_node, "qcom,bam-dmux");
2117	qproc->bam_dmux = of_platform_device_create(node, NULL, &pdev->dev);
2118	of_node_put(node);
2119
2120	return 0;
2121
2122remove_sysmon_subdev:
2123	qcom_remove_sysmon_subdev(qproc->sysmon);
2124remove_subdevs:
2125	qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
2126	qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
2127	qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
2128detach_proxy_pds:
2129	q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
2130free_rproc:
2131	rproc_free(rproc);
2132
2133	return ret;
2134}
2135
2136static void q6v5_remove(struct platform_device *pdev)
2137{
2138	struct q6v5 *qproc = platform_get_drvdata(pdev);
2139	struct rproc *rproc = qproc->rproc;
2140
2141	if (qproc->bam_dmux)
2142		of_platform_device_destroy(&qproc->bam_dmux->dev, NULL);
2143	rproc_del(rproc);
2144
2145	qcom_q6v5_deinit(&qproc->q6v5);
2146	qcom_remove_sysmon_subdev(qproc->sysmon);
2147	qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
2148	qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
2149	qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
2150
2151	q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
2152
2153	rproc_free(rproc);
 
 
2154}
2155
2156static const struct rproc_hexagon_res sc7180_mss = {
2157	.hexagon_mba_image = "mba.mbn",
2158	.proxy_clk_names = (char*[]){
2159		"xo",
2160		NULL
2161	},
2162	.reset_clk_names = (char*[]){
2163		"iface",
2164		"bus",
2165		"snoc_axi",
2166		NULL
2167	},
2168	.active_clk_names = (char*[]){
2169		"mnoc_axi",
2170		"nav",
2171		NULL
2172	},
2173	.proxy_pd_names = (char*[]){
2174		"cx",
2175		"mx",
2176		"mss",
2177		NULL
2178	},
2179	.need_mem_protection = true,
2180	.has_alt_reset = false,
2181	.has_mba_logs = true,
2182	.has_spare_reg = true,
2183	.has_qaccept_regs = false,
2184	.has_ext_cntl_regs = false,
2185	.has_vq6 = false,
2186	.version = MSS_SC7180,
2187};
2188
2189static const struct rproc_hexagon_res sc7280_mss = {
2190	.hexagon_mba_image = "mba.mbn",
2191	.proxy_clk_names = (char*[]){
2192		"xo",
2193		"pka",
2194		NULL
2195	},
2196	.active_clk_names = (char*[]){
2197		"iface",
2198		"offline",
2199		"snoc_axi",
2200		NULL
2201	},
2202	.proxy_pd_names = (char*[]){
2203		"cx",
2204		"mss",
2205		NULL
2206	},
2207	.need_mem_protection = true,
2208	.has_alt_reset = false,
2209	.has_mba_logs = true,
2210	.has_spare_reg = false,
2211	.has_qaccept_regs = true,
2212	.has_ext_cntl_regs = true,
2213	.has_vq6 = true,
2214	.version = MSS_SC7280,
2215};
2216
2217static const struct rproc_hexagon_res sdm660_mss = {
2218	.hexagon_mba_image = "mba.mbn",
2219	.proxy_clk_names = (char*[]){
2220			"xo",
2221			"qdss",
2222			"mem",
2223			NULL
2224	},
2225	.active_clk_names = (char*[]){
2226			"iface",
2227			"bus",
2228			"gpll0_mss",
2229			"mnoc_axi",
2230			"snoc_axi",
2231			NULL
2232	},
2233	.proxy_pd_names = (char*[]){
2234			"cx",
2235			"mx",
2236			NULL
2237	},
2238	.need_mem_protection = true,
2239	.has_alt_reset = false,
2240	.has_mba_logs = false,
2241	.has_spare_reg = false,
2242	.has_qaccept_regs = false,
2243	.has_ext_cntl_regs = false,
2244	.has_vq6 = false,
2245	.version = MSS_SDM660,
2246};
2247
2248static const struct rproc_hexagon_res sdm845_mss = {
2249	.hexagon_mba_image = "mba.mbn",
2250	.proxy_clk_names = (char*[]){
2251			"xo",
2252			"prng",
2253			NULL
2254	},
2255	.reset_clk_names = (char*[]){
2256			"iface",
2257			"snoc_axi",
2258			NULL
2259	},
2260	.active_clk_names = (char*[]){
2261			"bus",
2262			"mem",
2263			"gpll0_mss",
2264			"mnoc_axi",
2265			NULL
2266	},
2267	.proxy_pd_names = (char*[]){
2268			"cx",
2269			"mx",
2270			"mss",
2271			NULL
2272	},
2273	.need_mem_protection = true,
2274	.has_alt_reset = true,
2275	.has_mba_logs = false,
2276	.has_spare_reg = false,
2277	.has_qaccept_regs = false,
2278	.has_ext_cntl_regs = false,
2279	.has_vq6 = false,
2280	.version = MSS_SDM845,
2281};
2282
2283static const struct rproc_hexagon_res msm8998_mss = {
2284	.hexagon_mba_image = "mba.mbn",
2285	.proxy_clk_names = (char*[]){
2286			"xo",
2287			"qdss",
2288			"mem",
2289			NULL
2290	},
2291	.active_clk_names = (char*[]){
2292			"iface",
2293			"bus",
2294			"gpll0_mss",
2295			"mnoc_axi",
2296			"snoc_axi",
2297			NULL
2298	},
2299	.proxy_pd_names = (char*[]){
2300			"cx",
2301			"mx",
2302			NULL
2303	},
2304	.need_mem_protection = true,
2305	.has_alt_reset = false,
2306	.has_mba_logs = false,
2307	.has_spare_reg = false,
2308	.has_qaccept_regs = false,
2309	.has_ext_cntl_regs = false,
2310	.has_vq6 = false,
2311	.version = MSS_MSM8998,
2312};
2313
2314static const struct rproc_hexagon_res msm8996_mss = {
2315	.hexagon_mba_image = "mba.mbn",
2316	.proxy_supply = (struct qcom_mss_reg_res[]) {
2317		{
2318			.supply = "pll",
2319			.uA = 100000,
2320		},
2321		{}
2322	},
2323	.proxy_clk_names = (char*[]){
2324			"xo",
 
2325			"qdss",
2326			NULL
2327	},
2328	.active_clk_names = (char*[]){
2329			"iface",
2330			"bus",
2331			"mem",
2332			"gpll0_mss",
2333			"snoc_axi",
2334			"mnoc_axi",
2335			NULL
2336	},
2337	.proxy_pd_names = (char*[]){
2338			"mx",
2339			"cx",
2340			NULL
2341	},
2342	.need_mem_protection = true,
2343	.has_alt_reset = false,
2344	.has_mba_logs = false,
2345	.has_spare_reg = false,
2346	.has_qaccept_regs = false,
2347	.has_ext_cntl_regs = false,
2348	.has_vq6 = false,
2349	.version = MSS_MSM8996,
2350};
2351
2352static const struct rproc_hexagon_res msm8909_mss = {
2353	.hexagon_mba_image = "mba.mbn",
2354	.proxy_supply = (struct qcom_mss_reg_res[]) {
2355		{
2356			.supply = "pll",
2357			.uA = 100000,
2358		},
2359		{}
2360	},
2361	.proxy_clk_names = (char*[]){
2362		"xo",
2363		NULL
2364	},
2365	.active_clk_names = (char*[]){
2366		"iface",
2367		"bus",
2368		"mem",
2369		NULL
2370	},
2371	.proxy_pd_names = (char*[]){
2372		"mx",
2373		"cx",
2374		NULL
2375	},
2376	.need_mem_protection = false,
2377	.has_alt_reset = false,
2378	.has_mba_logs = false,
2379	.has_spare_reg = false,
2380	.has_qaccept_regs = false,
2381	.has_ext_cntl_regs = false,
2382	.has_vq6 = false,
2383	.version = MSS_MSM8909,
2384};
2385
2386static const struct rproc_hexagon_res msm8916_mss = {
2387	.hexagon_mba_image = "mba.mbn",
2388	.proxy_supply = (struct qcom_mss_reg_res[]) {
2389		{
2390			.supply = "pll",
2391			.uA = 100000,
2392		},
2393		{}
2394	},
2395	.fallback_proxy_supply = (struct qcom_mss_reg_res[]) {
2396		{
2397			.supply = "mx",
2398			.uV = 1050000,
2399		},
2400		{
2401			.supply = "cx",
2402			.uA = 100000,
2403		},
2404		{}
2405	},
2406	.proxy_clk_names = (char*[]){
2407		"xo",
2408		NULL
2409	},
2410	.active_clk_names = (char*[]){
2411		"iface",
2412		"bus",
2413		"mem",
2414		NULL
2415	},
2416	.proxy_pd_names = (char*[]){
2417		"mx",
2418		"cx",
2419		NULL
2420	},
2421	.need_mem_protection = false,
2422	.has_alt_reset = false,
2423	.has_mba_logs = false,
2424	.has_spare_reg = false,
2425	.has_qaccept_regs = false,
2426	.has_ext_cntl_regs = false,
2427	.has_vq6 = false,
2428	.version = MSS_MSM8916,
2429};
2430
2431static const struct rproc_hexagon_res msm8953_mss = {
2432	.hexagon_mba_image = "mba.mbn",
2433	.proxy_supply = (struct qcom_mss_reg_res[]) {
2434		{
2435			.supply = "pll",
2436			.uA = 100000,
2437		},
2438		{}
2439	},
2440	.proxy_clk_names = (char*[]){
2441		"xo",
2442		NULL
2443	},
2444	.active_clk_names = (char*[]){
2445		"iface",
2446		"bus",
2447		"mem",
2448		NULL
2449	},
2450	.proxy_pd_names = (char*[]) {
2451		"cx",
2452		"mx",
2453		"mss",
2454		NULL
2455	},
2456	.need_mem_protection = false,
2457	.has_alt_reset = false,
2458	.has_mba_logs = false,
2459	.has_spare_reg = false,
2460	.has_qaccept_regs = false,
2461	.has_ext_cntl_regs = false,
2462	.has_vq6 = false,
2463	.version = MSS_MSM8953,
2464};
2465
2466static const struct rproc_hexagon_res msm8974_mss = {
2467	.hexagon_mba_image = "mba.b00",
2468	.proxy_supply = (struct qcom_mss_reg_res[]) {
2469		{
2470			.supply = "pll",
2471			.uA = 100000,
2472		},
2473		{}
2474	},
2475	.fallback_proxy_supply = (struct qcom_mss_reg_res[]) {
2476		{
2477			.supply = "mx",
2478			.uV = 1050000,
2479		},
2480		{
2481			.supply = "cx",
2482			.uA = 100000,
2483		},
2484		{}
2485	},
2486	.active_supply = (struct qcom_mss_reg_res[]) {
2487		{
2488			.supply = "mss",
2489			.uV = 1050000,
2490			.uA = 100000,
2491		},
2492		{}
2493	},
2494	.proxy_clk_names = (char*[]){
2495		"xo",
2496		NULL
2497	},
2498	.active_clk_names = (char*[]){
2499		"iface",
2500		"bus",
2501		"mem",
2502		NULL
2503	},
2504	.proxy_pd_names = (char*[]){
2505		"mx",
2506		"cx",
2507		NULL
2508	},
2509	.need_mem_protection = false,
2510	.has_alt_reset = false,
2511	.has_mba_logs = false,
2512	.has_spare_reg = false,
2513	.has_qaccept_regs = false,
2514	.has_ext_cntl_regs = false,
2515	.has_vq6 = false,
2516	.version = MSS_MSM8974,
2517};
2518
2519static const struct of_device_id q6v5_of_match[] = {
2520	{ .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
2521	{ .compatible = "qcom,msm8909-mss-pil", .data = &msm8909_mss},
2522	{ .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
2523	{ .compatible = "qcom,msm8953-mss-pil", .data = &msm8953_mss},
2524	{ .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
2525	{ .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
2526	{ .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss},
2527	{ .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss},
2528	{ .compatible = "qcom,sc7280-mss-pil", .data = &sc7280_mss},
2529	{ .compatible = "qcom,sdm660-mss-pil", .data = &sdm660_mss},
2530	{ .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
2531	{ },
2532};
2533MODULE_DEVICE_TABLE(of, q6v5_of_match);
2534
2535static struct platform_driver q6v5_driver = {
2536	.probe = q6v5_probe,
2537	.remove_new = q6v5_remove,
2538	.driver = {
2539		.name = "qcom-q6v5-mss",
2540		.of_match_table = q6v5_of_match,
2541	},
2542};
2543module_platform_driver(q6v5_driver);
2544
2545MODULE_DESCRIPTION("Qualcomm Self-authenticating modem remoteproc driver");
2546MODULE_LICENSE("GPL v2");