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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) STMicroelectronics 2016
4 *
5 * Author: Gerald Baeza <gerald.baeza@st.com>
6 *
7 * Inspired by timer-stm32.c from Maxime Coquelin
8 * pwm-atmel.c from Bo Shen
9 */
10
11#include <linux/bitfield.h>
12#include <linux/mfd/stm32-timers.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/pinctrl/consumer.h>
16#include <linux/platform_device.h>
17#include <linux/pwm.h>
18
19#define CCMR_CHANNEL_SHIFT 8
20#define CCMR_CHANNEL_MASK 0xFF
21#define MAX_BREAKINPUT 2
22
23struct stm32_breakinput {
24 u32 index;
25 u32 level;
26 u32 filter;
27};
28
29struct stm32_pwm {
30 struct pwm_chip chip;
31 struct mutex lock; /* protect pwm config/enable */
32 struct clk *clk;
33 struct regmap *regmap;
34 u32 max_arr;
35 bool have_complementary_output;
36 struct stm32_breakinput breakinputs[MAX_BREAKINPUT];
37 unsigned int num_breakinputs;
38 u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */
39};
40
41static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip)
42{
43 return container_of(chip, struct stm32_pwm, chip);
44}
45
46static u32 active_channels(struct stm32_pwm *dev)
47{
48 u32 ccer;
49
50 regmap_read(dev->regmap, TIM_CCER, &ccer);
51
52 return ccer & TIM_CCER_CCXE;
53}
54
55#define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P)
56#define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E)
57#define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P)
58#define TIM_CCER_CC34E (TIM_CCER_CC3E | TIM_CCER_CC4E)
59
60/*
61 * Capture using PWM input mode:
62 * ___ ___
63 * TI[1, 2, 3 or 4]: ........._| |________|
64 * ^0 ^1 ^2
65 * . . .
66 * . . XXXXX
67 * . . XXXXX |
68 * . XXXXX . |
69 * XXXXX . . |
70 * COUNTER: ______XXXXX . . . |_XXX
71 * start^ . . . ^stop
72 * . . . .
73 * v v . v
74 * v
75 * CCR1/CCR3: tx..........t0...........t2
76 * CCR2/CCR4: tx..............t1.........
77 *
78 * DMA burst transfer: | |
79 * v v
80 * DMA buffer: { t0, tx } { t2, t1 }
81 * DMA done: ^
82 *
83 * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
84 * + DMA transfer CCR[1/3] & CCR[2/4] values (t0, tx: doesn't care)
85 * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4
86 * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
87 * + DMA transfer CCR[1/3] & CCR[2/4] values (t2, t1)
88 *
89 * DMA done, compute:
90 * - Period = t2 - t0
91 * - Duty cycle = t1 - t0
92 */
93static int stm32_pwm_raw_capture(struct stm32_pwm *priv, struct pwm_device *pwm,
94 unsigned long tmo_ms, u32 *raw_prd,
95 u32 *raw_dty)
96{
97 struct device *parent = priv->chip.dev->parent;
98 enum stm32_timers_dmas dma_id;
99 u32 ccen, ccr;
100 int ret;
101
102 /* Ensure registers have been updated, enable counter and capture */
103 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
104 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
105
106 /* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */
107 dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3;
108 ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E;
109 ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3;
110 regmap_set_bits(priv->regmap, TIM_CCER, ccen);
111
112 /*
113 * Timer DMA burst mode. Request 2 registers, 2 bursts, to get both
114 * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event.
115 * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 }
116 * or { CCR3, CCR4 }, { CCR3, CCR4 }
117 */
118 ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2,
119 2, tmo_ms);
120 if (ret)
121 goto stop;
122
123 /* Period: t2 - t0 (take care of counter overflow) */
124 if (priv->capture[0] <= priv->capture[2])
125 *raw_prd = priv->capture[2] - priv->capture[0];
126 else
127 *raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2];
128
129 /* Duty cycle capture requires at least two capture units */
130 if (pwm->chip->npwm < 2)
131 *raw_dty = 0;
132 else if (priv->capture[0] <= priv->capture[3])
133 *raw_dty = priv->capture[3] - priv->capture[0];
134 else
135 *raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3];
136
137 if (*raw_dty > *raw_prd) {
138 /*
139 * Race beetween PWM input and DMA: it may happen
140 * falling edge triggers new capture on TI2/4 before DMA
141 * had a chance to read CCR2/4. It means capture[1]
142 * contains period + duty_cycle. So, subtract period.
143 */
144 *raw_dty -= *raw_prd;
145 }
146
147stop:
148 regmap_clear_bits(priv->regmap, TIM_CCER, ccen);
149 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
150
151 return ret;
152}
153
154static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
155 struct pwm_capture *result, unsigned long tmo_ms)
156{
157 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
158 unsigned long long prd, div, dty;
159 unsigned long rate;
160 unsigned int psc = 0, icpsc, scale;
161 u32 raw_prd = 0, raw_dty = 0;
162 int ret = 0;
163
164 mutex_lock(&priv->lock);
165
166 if (active_channels(priv)) {
167 ret = -EBUSY;
168 goto unlock;
169 }
170
171 ret = clk_enable(priv->clk);
172 if (ret) {
173 dev_err(priv->chip.dev, "failed to enable counter clock\n");
174 goto unlock;
175 }
176
177 rate = clk_get_rate(priv->clk);
178 if (!rate) {
179 ret = -EINVAL;
180 goto clk_dis;
181 }
182
183 /* prescaler: fit timeout window provided by upper layer */
184 div = (unsigned long long)rate * (unsigned long long)tmo_ms;
185 do_div(div, MSEC_PER_SEC);
186 prd = div;
187 while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) {
188 psc++;
189 div = prd;
190 do_div(div, psc + 1);
191 }
192 regmap_write(priv->regmap, TIM_ARR, priv->max_arr);
193 regmap_write(priv->regmap, TIM_PSC, psc);
194
195 /* Reset input selector to its default input and disable slave mode */
196 regmap_write(priv->regmap, TIM_TISEL, 0x0);
197 regmap_write(priv->regmap, TIM_SMCR, 0x0);
198
199 /* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */
200 regmap_update_bits(priv->regmap,
201 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
202 TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ?
203 TIM_CCMR_CC1S_TI2 | TIM_CCMR_CC2S_TI2 :
204 TIM_CCMR_CC1S_TI1 | TIM_CCMR_CC2S_TI1);
205
206 /* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */
207 regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ?
208 TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ?
209 TIM_CCER_CC2P : TIM_CCER_CC4P);
210
211 ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty);
212 if (ret)
213 goto stop;
214
215 /*
216 * Got a capture. Try to improve accuracy at high rates:
217 * - decrease counter clock prescaler, scale up to max rate.
218 * - use input prescaler, capture once every /2 /4 or /8 edges.
219 */
220 if (raw_prd) {
221 u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */
222
223 scale = max_arr / min(max_arr, raw_prd);
224 } else {
225 scale = priv->max_arr; /* bellow resolution, use max scale */
226 }
227
228 if (psc && scale > 1) {
229 /* 2nd measure with new scale */
230 psc /= scale;
231 regmap_write(priv->regmap, TIM_PSC, psc);
232 ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd,
233 &raw_dty);
234 if (ret)
235 goto stop;
236 }
237
238 /* Compute intermediate period not to exceed timeout at low rates */
239 prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
240 do_div(prd, rate);
241
242 for (icpsc = 0; icpsc < MAX_TIM_ICPSC ; icpsc++) {
243 /* input prescaler: also keep arbitrary margin */
244 if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1))
245 break;
246 if (prd >= (tmo_ms * NSEC_PER_MSEC) >> (icpsc + 2))
247 break;
248 }
249
250 if (!icpsc)
251 goto done;
252
253 /* Last chance to improve period accuracy, using input prescaler */
254 regmap_update_bits(priv->regmap,
255 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
256 TIM_CCMR_IC1PSC | TIM_CCMR_IC2PSC,
257 FIELD_PREP(TIM_CCMR_IC1PSC, icpsc) |
258 FIELD_PREP(TIM_CCMR_IC2PSC, icpsc));
259
260 ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty);
261 if (ret)
262 goto stop;
263
264 if (raw_dty >= (raw_prd >> icpsc)) {
265 /*
266 * We may fall here using input prescaler, when input
267 * capture starts on high side (before falling edge).
268 * Example with icpsc to capture on each 4 events:
269 *
270 * start 1st capture 2nd capture
271 * v v v
272 * ___ _____ _____ _____ _____ ____
273 * TI1..4 |__| |__| |__| |__| |__|
274 * v v . . . . . v v
275 * icpsc1/3: . 0 . 1 . 2 . 3 . 0
276 * icpsc2/4: 0 1 2 3 0
277 * v v v v
278 * CCR1/3 ......t0..............................t2
279 * CCR2/4 ..t1..............................t1'...
280 * . . .
281 * Capture0: .<----------------------------->.
282 * Capture1: .<-------------------------->. .
283 * . . .
284 * Period: .<------> . .
285 * Low side: .<>.
286 *
287 * Result:
288 * - Period = Capture0 / icpsc
289 * - Duty = Period - Low side = Period - (Capture0 - Capture1)
290 */
291 raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty);
292 }
293
294done:
295 prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
296 result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc);
297 dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC;
298 result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);
299stop:
300 regmap_write(priv->regmap, TIM_CCER, 0);
301 regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0);
302 regmap_write(priv->regmap, TIM_PSC, 0);
303clk_dis:
304 clk_disable(priv->clk);
305unlock:
306 mutex_unlock(&priv->lock);
307
308 return ret;
309}
310
311static int stm32_pwm_config(struct stm32_pwm *priv, unsigned int ch,
312 int duty_ns, int period_ns)
313{
314 unsigned long long prd, div, dty;
315 unsigned int prescaler = 0;
316 u32 ccmr, mask, shift;
317
318 /* Period and prescaler values depends on clock rate */
319 div = (unsigned long long)clk_get_rate(priv->clk) * period_ns;
320
321 do_div(div, NSEC_PER_SEC);
322 prd = div;
323
324 while (div > priv->max_arr) {
325 prescaler++;
326 div = prd;
327 do_div(div, prescaler + 1);
328 }
329
330 prd = div;
331
332 if (prescaler > MAX_TIM_PSC)
333 return -EINVAL;
334
335 /*
336 * All channels share the same prescaler and counter so when two
337 * channels are active at the same time we can't change them
338 */
339 if (active_channels(priv) & ~(1 << ch * 4)) {
340 u32 psc, arr;
341
342 regmap_read(priv->regmap, TIM_PSC, &psc);
343 regmap_read(priv->regmap, TIM_ARR, &arr);
344
345 if ((psc != prescaler) || (arr != prd - 1))
346 return -EBUSY;
347 }
348
349 regmap_write(priv->regmap, TIM_PSC, prescaler);
350 regmap_write(priv->regmap, TIM_ARR, prd - 1);
351 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
352
353 /* Calculate the duty cycles */
354 dty = prd * duty_ns;
355 do_div(dty, period_ns);
356
357 regmap_write(priv->regmap, TIM_CCR1 + 4 * ch, dty);
358
359 /* Configure output mode */
360 shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
361 ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
362 mask = CCMR_CHANNEL_MASK << shift;
363
364 if (ch < 2)
365 regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
366 else
367 regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
368
369 regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE);
370
371 return 0;
372}
373
374static int stm32_pwm_set_polarity(struct stm32_pwm *priv, unsigned int ch,
375 enum pwm_polarity polarity)
376{
377 u32 mask;
378
379 mask = TIM_CCER_CC1P << (ch * 4);
380 if (priv->have_complementary_output)
381 mask |= TIM_CCER_CC1NP << (ch * 4);
382
383 regmap_update_bits(priv->regmap, TIM_CCER, mask,
384 polarity == PWM_POLARITY_NORMAL ? 0 : mask);
385
386 return 0;
387}
388
389static int stm32_pwm_enable(struct stm32_pwm *priv, unsigned int ch)
390{
391 u32 mask;
392 int ret;
393
394 ret = clk_enable(priv->clk);
395 if (ret)
396 return ret;
397
398 /* Enable channel */
399 mask = TIM_CCER_CC1E << (ch * 4);
400 if (priv->have_complementary_output)
401 mask |= TIM_CCER_CC1NE << (ch * 4);
402
403 regmap_set_bits(priv->regmap, TIM_CCER, mask);
404
405 /* Make sure that registers are updated */
406 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
407
408 /* Enable controller */
409 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
410
411 return 0;
412}
413
414static void stm32_pwm_disable(struct stm32_pwm *priv, unsigned int ch)
415{
416 u32 mask;
417
418 /* Disable channel */
419 mask = TIM_CCER_CC1E << (ch * 4);
420 if (priv->have_complementary_output)
421 mask |= TIM_CCER_CC1NE << (ch * 4);
422
423 regmap_clear_bits(priv->regmap, TIM_CCER, mask);
424
425 /* When all channels are disabled, we can disable the controller */
426 if (!active_channels(priv))
427 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
428
429 clk_disable(priv->clk);
430}
431
432static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
433 const struct pwm_state *state)
434{
435 bool enabled;
436 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
437 int ret;
438
439 enabled = pwm->state.enabled;
440
441 if (enabled && !state->enabled) {
442 stm32_pwm_disable(priv, pwm->hwpwm);
443 return 0;
444 }
445
446 if (state->polarity != pwm->state.polarity)
447 stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity);
448
449 ret = stm32_pwm_config(priv, pwm->hwpwm,
450 state->duty_cycle, state->period);
451 if (ret)
452 return ret;
453
454 if (!enabled && state->enabled)
455 ret = stm32_pwm_enable(priv, pwm->hwpwm);
456
457 return ret;
458}
459
460static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm,
461 const struct pwm_state *state)
462{
463 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
464 int ret;
465
466 /* protect common prescaler for all active channels */
467 mutex_lock(&priv->lock);
468 ret = stm32_pwm_apply(chip, pwm, state);
469 mutex_unlock(&priv->lock);
470
471 return ret;
472}
473
474static int stm32_pwm_get_state(struct pwm_chip *chip,
475 struct pwm_device *pwm, struct pwm_state *state)
476{
477 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
478 int ch = pwm->hwpwm;
479 unsigned long rate;
480 u32 ccer, psc, arr, ccr;
481 u64 dty, prd;
482 int ret;
483
484 mutex_lock(&priv->lock);
485
486 ret = regmap_read(priv->regmap, TIM_CCER, &ccer);
487 if (ret)
488 goto out;
489
490 state->enabled = ccer & (TIM_CCER_CC1E << (ch * 4));
491 state->polarity = (ccer & (TIM_CCER_CC1P << (ch * 4))) ?
492 PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL;
493 ret = regmap_read(priv->regmap, TIM_PSC, &psc);
494 if (ret)
495 goto out;
496 ret = regmap_read(priv->regmap, TIM_ARR, &arr);
497 if (ret)
498 goto out;
499 ret = regmap_read(priv->regmap, TIM_CCR1 + 4 * ch, &ccr);
500 if (ret)
501 goto out;
502
503 rate = clk_get_rate(priv->clk);
504
505 prd = (u64)NSEC_PER_SEC * (psc + 1) * (arr + 1);
506 state->period = DIV_ROUND_UP_ULL(prd, rate);
507 dty = (u64)NSEC_PER_SEC * (psc + 1) * ccr;
508 state->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);
509
510out:
511 mutex_unlock(&priv->lock);
512 return ret;
513}
514
515static const struct pwm_ops stm32pwm_ops = {
516 .apply = stm32_pwm_apply_locked,
517 .get_state = stm32_pwm_get_state,
518 .capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,
519};
520
521static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
522 const struct stm32_breakinput *bi)
523{
524 u32 shift = TIM_BDTR_BKF_SHIFT(bi->index);
525 u32 bke = TIM_BDTR_BKE(bi->index);
526 u32 bkp = TIM_BDTR_BKP(bi->index);
527 u32 bkf = TIM_BDTR_BKF(bi->index);
528 u32 mask = bkf | bkp | bke;
529 u32 bdtr;
530
531 bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke;
532
533 if (bi->level)
534 bdtr |= bkp;
535
536 regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);
537
538 regmap_read(priv->regmap, TIM_BDTR, &bdtr);
539
540 return (bdtr & bke) ? 0 : -EINVAL;
541}
542
543static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv)
544{
545 unsigned int i;
546 int ret;
547
548 for (i = 0; i < priv->num_breakinputs; i++) {
549 ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]);
550 if (ret < 0)
551 return ret;
552 }
553
554 return 0;
555}
556
557static int stm32_pwm_probe_breakinputs(struct stm32_pwm *priv,
558 struct device_node *np)
559{
560 int nb, ret, array_size;
561 unsigned int i;
562
563 nb = of_property_count_elems_of_size(np, "st,breakinput",
564 sizeof(struct stm32_breakinput));
565
566 /*
567 * Because "st,breakinput" parameter is optional do not make probe
568 * failed if it doesn't exist.
569 */
570 if (nb <= 0)
571 return 0;
572
573 if (nb > MAX_BREAKINPUT)
574 return -EINVAL;
575
576 priv->num_breakinputs = nb;
577 array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32);
578 ret = of_property_read_u32_array(np, "st,breakinput",
579 (u32 *)priv->breakinputs, array_size);
580 if (ret)
581 return ret;
582
583 for (i = 0; i < priv->num_breakinputs; i++) {
584 if (priv->breakinputs[i].index > 1 ||
585 priv->breakinputs[i].level > 1 ||
586 priv->breakinputs[i].filter > 15)
587 return -EINVAL;
588 }
589
590 return stm32_pwm_apply_breakinputs(priv);
591}
592
593static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
594{
595 u32 ccer;
596
597 /*
598 * If complementary bit doesn't exist writing 1 will have no
599 * effect so we can detect it.
600 */
601 regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
602 regmap_read(priv->regmap, TIM_CCER, &ccer);
603 regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
604
605 priv->have_complementary_output = (ccer != 0);
606}
607
608static unsigned int stm32_pwm_detect_channels(struct stm32_pwm *priv,
609 unsigned int *num_enabled)
610{
611 u32 ccer, ccer_backup;
612
613 /*
614 * If channels enable bits don't exist writing 1 will have no
615 * effect so we can detect and count them.
616 */
617 regmap_read(priv->regmap, TIM_CCER, &ccer_backup);
618 regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE);
619 regmap_read(priv->regmap, TIM_CCER, &ccer);
620 regmap_write(priv->regmap, TIM_CCER, ccer_backup);
621
622 *num_enabled = hweight32(ccer_backup & TIM_CCER_CCXE);
623
624 return hweight32(ccer & TIM_CCER_CCXE);
625}
626
627static int stm32_pwm_probe(struct platform_device *pdev)
628{
629 struct device *dev = &pdev->dev;
630 struct device_node *np = dev->of_node;
631 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
632 struct stm32_pwm *priv;
633 unsigned int num_enabled;
634 unsigned int i;
635 int ret;
636
637 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
638 if (!priv)
639 return -ENOMEM;
640
641 mutex_init(&priv->lock);
642 priv->regmap = ddata->regmap;
643 priv->clk = ddata->clk;
644 priv->max_arr = ddata->max_arr;
645
646 if (!priv->regmap || !priv->clk)
647 return -EINVAL;
648
649 ret = stm32_pwm_probe_breakinputs(priv, np);
650 if (ret)
651 return ret;
652
653 stm32_pwm_detect_complementary(priv);
654
655 priv->chip.dev = dev;
656 priv->chip.ops = &stm32pwm_ops;
657 priv->chip.npwm = stm32_pwm_detect_channels(priv, &num_enabled);
658
659 /* Initialize clock refcount to number of enabled PWM channels. */
660 for (i = 0; i < num_enabled; i++)
661 clk_enable(priv->clk);
662
663 ret = devm_pwmchip_add(dev, &priv->chip);
664 if (ret < 0)
665 return ret;
666
667 platform_set_drvdata(pdev, priv);
668
669 return 0;
670}
671
672static int stm32_pwm_suspend(struct device *dev)
673{
674 struct stm32_pwm *priv = dev_get_drvdata(dev);
675 unsigned int i;
676 u32 ccer, mask;
677
678 /* Look for active channels */
679 ccer = active_channels(priv);
680
681 for (i = 0; i < priv->chip.npwm; i++) {
682 mask = TIM_CCER_CC1E << (i * 4);
683 if (ccer & mask) {
684 dev_err(dev, "PWM %u still in use by consumer %s\n",
685 i, priv->chip.pwms[i].label);
686 return -EBUSY;
687 }
688 }
689
690 return pinctrl_pm_select_sleep_state(dev);
691}
692
693static int stm32_pwm_resume(struct device *dev)
694{
695 struct stm32_pwm *priv = dev_get_drvdata(dev);
696 int ret;
697
698 ret = pinctrl_pm_select_default_state(dev);
699 if (ret)
700 return ret;
701
702 /* restore breakinput registers that may have been lost in low power */
703 return stm32_pwm_apply_breakinputs(priv);
704}
705
706static DEFINE_SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume);
707
708static const struct of_device_id stm32_pwm_of_match[] = {
709 { .compatible = "st,stm32-pwm", },
710 { /* end node */ },
711};
712MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);
713
714static struct platform_driver stm32_pwm_driver = {
715 .probe = stm32_pwm_probe,
716 .driver = {
717 .name = "stm32-pwm",
718 .of_match_table = stm32_pwm_of_match,
719 .pm = pm_ptr(&stm32_pwm_pm_ops),
720 },
721};
722module_platform_driver(stm32_pwm_driver);
723
724MODULE_ALIAS("platform:stm32-pwm");
725MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
726MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) STMicroelectronics 2016
4 *
5 * Author: Gerald Baeza <gerald.baeza@st.com>
6 *
7 * Inspired by timer-stm32.c from Maxime Coquelin
8 * pwm-atmel.c from Bo Shen
9 */
10
11#include <linux/bitfield.h>
12#include <linux/mfd/stm32-timers.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/pinctrl/consumer.h>
16#include <linux/platform_device.h>
17#include <linux/pwm.h>
18
19#define CCMR_CHANNEL_SHIFT 8
20#define CCMR_CHANNEL_MASK 0xFF
21#define MAX_BREAKINPUT 2
22
23struct stm32_breakinput {
24 u32 index;
25 u32 level;
26 u32 filter;
27};
28
29struct stm32_pwm {
30 struct pwm_chip chip;
31 struct mutex lock; /* protect pwm config/enable */
32 struct clk *clk;
33 struct regmap *regmap;
34 u32 max_arr;
35 bool have_complementary_output;
36 struct stm32_breakinput breakinputs[MAX_BREAKINPUT];
37 unsigned int num_breakinputs;
38 u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */
39};
40
41static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip)
42{
43 return container_of(chip, struct stm32_pwm, chip);
44}
45
46static u32 active_channels(struct stm32_pwm *dev)
47{
48 u32 ccer;
49
50 regmap_read(dev->regmap, TIM_CCER, &ccer);
51
52 return ccer & TIM_CCER_CCXE;
53}
54
55static int write_ccrx(struct stm32_pwm *dev, int ch, u32 value)
56{
57 switch (ch) {
58 case 0:
59 return regmap_write(dev->regmap, TIM_CCR1, value);
60 case 1:
61 return regmap_write(dev->regmap, TIM_CCR2, value);
62 case 2:
63 return regmap_write(dev->regmap, TIM_CCR3, value);
64 case 3:
65 return regmap_write(dev->regmap, TIM_CCR4, value);
66 }
67 return -EINVAL;
68}
69
70#define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P)
71#define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E)
72#define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P)
73#define TIM_CCER_CC34E (TIM_CCER_CC3E | TIM_CCER_CC4E)
74
75/*
76 * Capture using PWM input mode:
77 * ___ ___
78 * TI[1, 2, 3 or 4]: ........._| |________|
79 * ^0 ^1 ^2
80 * . . .
81 * . . XXXXX
82 * . . XXXXX |
83 * . XXXXX . |
84 * XXXXX . . |
85 * COUNTER: ______XXXXX . . . |_XXX
86 * start^ . . . ^stop
87 * . . . .
88 * v v . v
89 * v
90 * CCR1/CCR3: tx..........t0...........t2
91 * CCR2/CCR4: tx..............t1.........
92 *
93 * DMA burst transfer: | |
94 * v v
95 * DMA buffer: { t0, tx } { t2, t1 }
96 * DMA done: ^
97 *
98 * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
99 * + DMA transfer CCR[1/3] & CCR[2/4] values (t0, tx: doesn't care)
100 * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4
101 * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
102 * + DMA transfer CCR[1/3] & CCR[2/4] values (t2, t1)
103 *
104 * DMA done, compute:
105 * - Period = t2 - t0
106 * - Duty cycle = t1 - t0
107 */
108static int stm32_pwm_raw_capture(struct stm32_pwm *priv, struct pwm_device *pwm,
109 unsigned long tmo_ms, u32 *raw_prd,
110 u32 *raw_dty)
111{
112 struct device *parent = priv->chip.dev->parent;
113 enum stm32_timers_dmas dma_id;
114 u32 ccen, ccr;
115 int ret;
116
117 /* Ensure registers have been updated, enable counter and capture */
118 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
119 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
120
121 /* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */
122 dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3;
123 ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E;
124 ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3;
125 regmap_set_bits(priv->regmap, TIM_CCER, ccen);
126
127 /*
128 * Timer DMA burst mode. Request 2 registers, 2 bursts, to get both
129 * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event.
130 * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 }
131 * or { CCR3, CCR4 }, { CCR3, CCR4 }
132 */
133 ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2,
134 2, tmo_ms);
135 if (ret)
136 goto stop;
137
138 /* Period: t2 - t0 (take care of counter overflow) */
139 if (priv->capture[0] <= priv->capture[2])
140 *raw_prd = priv->capture[2] - priv->capture[0];
141 else
142 *raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2];
143
144 /* Duty cycle capture requires at least two capture units */
145 if (pwm->chip->npwm < 2)
146 *raw_dty = 0;
147 else if (priv->capture[0] <= priv->capture[3])
148 *raw_dty = priv->capture[3] - priv->capture[0];
149 else
150 *raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3];
151
152 if (*raw_dty > *raw_prd) {
153 /*
154 * Race beetween PWM input and DMA: it may happen
155 * falling edge triggers new capture on TI2/4 before DMA
156 * had a chance to read CCR2/4. It means capture[1]
157 * contains period + duty_cycle. So, subtract period.
158 */
159 *raw_dty -= *raw_prd;
160 }
161
162stop:
163 regmap_clear_bits(priv->regmap, TIM_CCER, ccen);
164 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
165
166 return ret;
167}
168
169static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
170 struct pwm_capture *result, unsigned long tmo_ms)
171{
172 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
173 unsigned long long prd, div, dty;
174 unsigned long rate;
175 unsigned int psc = 0, icpsc, scale;
176 u32 raw_prd = 0, raw_dty = 0;
177 int ret = 0;
178
179 mutex_lock(&priv->lock);
180
181 if (active_channels(priv)) {
182 ret = -EBUSY;
183 goto unlock;
184 }
185
186 ret = clk_enable(priv->clk);
187 if (ret) {
188 dev_err(priv->chip.dev, "failed to enable counter clock\n");
189 goto unlock;
190 }
191
192 rate = clk_get_rate(priv->clk);
193 if (!rate) {
194 ret = -EINVAL;
195 goto clk_dis;
196 }
197
198 /* prescaler: fit timeout window provided by upper layer */
199 div = (unsigned long long)rate * (unsigned long long)tmo_ms;
200 do_div(div, MSEC_PER_SEC);
201 prd = div;
202 while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) {
203 psc++;
204 div = prd;
205 do_div(div, psc + 1);
206 }
207 regmap_write(priv->regmap, TIM_ARR, priv->max_arr);
208 regmap_write(priv->regmap, TIM_PSC, psc);
209
210 /* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */
211 regmap_update_bits(priv->regmap,
212 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
213 TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ?
214 TIM_CCMR_CC1S_TI2 | TIM_CCMR_CC2S_TI2 :
215 TIM_CCMR_CC1S_TI1 | TIM_CCMR_CC2S_TI1);
216
217 /* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */
218 regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ?
219 TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ?
220 TIM_CCER_CC2P : TIM_CCER_CC4P);
221
222 ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty);
223 if (ret)
224 goto stop;
225
226 /*
227 * Got a capture. Try to improve accuracy at high rates:
228 * - decrease counter clock prescaler, scale up to max rate.
229 * - use input prescaler, capture once every /2 /4 or /8 edges.
230 */
231 if (raw_prd) {
232 u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */
233
234 scale = max_arr / min(max_arr, raw_prd);
235 } else {
236 scale = priv->max_arr; /* bellow resolution, use max scale */
237 }
238
239 if (psc && scale > 1) {
240 /* 2nd measure with new scale */
241 psc /= scale;
242 regmap_write(priv->regmap, TIM_PSC, psc);
243 ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd,
244 &raw_dty);
245 if (ret)
246 goto stop;
247 }
248
249 /* Compute intermediate period not to exceed timeout at low rates */
250 prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
251 do_div(prd, rate);
252
253 for (icpsc = 0; icpsc < MAX_TIM_ICPSC ; icpsc++) {
254 /* input prescaler: also keep arbitrary margin */
255 if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1))
256 break;
257 if (prd >= (tmo_ms * NSEC_PER_MSEC) >> (icpsc + 2))
258 break;
259 }
260
261 if (!icpsc)
262 goto done;
263
264 /* Last chance to improve period accuracy, using input prescaler */
265 regmap_update_bits(priv->regmap,
266 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
267 TIM_CCMR_IC1PSC | TIM_CCMR_IC2PSC,
268 FIELD_PREP(TIM_CCMR_IC1PSC, icpsc) |
269 FIELD_PREP(TIM_CCMR_IC2PSC, icpsc));
270
271 ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty);
272 if (ret)
273 goto stop;
274
275 if (raw_dty >= (raw_prd >> icpsc)) {
276 /*
277 * We may fall here using input prescaler, when input
278 * capture starts on high side (before falling edge).
279 * Example with icpsc to capture on each 4 events:
280 *
281 * start 1st capture 2nd capture
282 * v v v
283 * ___ _____ _____ _____ _____ ____
284 * TI1..4 |__| |__| |__| |__| |__|
285 * v v . . . . . v v
286 * icpsc1/3: . 0 . 1 . 2 . 3 . 0
287 * icpsc2/4: 0 1 2 3 0
288 * v v v v
289 * CCR1/3 ......t0..............................t2
290 * CCR2/4 ..t1..............................t1'...
291 * . . .
292 * Capture0: .<----------------------------->.
293 * Capture1: .<-------------------------->. .
294 * . . .
295 * Period: .<------> . .
296 * Low side: .<>.
297 *
298 * Result:
299 * - Period = Capture0 / icpsc
300 * - Duty = Period - Low side = Period - (Capture0 - Capture1)
301 */
302 raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty);
303 }
304
305done:
306 prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
307 result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc);
308 dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC;
309 result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);
310stop:
311 regmap_write(priv->regmap, TIM_CCER, 0);
312 regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0);
313 regmap_write(priv->regmap, TIM_PSC, 0);
314clk_dis:
315 clk_disable(priv->clk);
316unlock:
317 mutex_unlock(&priv->lock);
318
319 return ret;
320}
321
322static int stm32_pwm_config(struct stm32_pwm *priv, int ch,
323 int duty_ns, int period_ns)
324{
325 unsigned long long prd, div, dty;
326 unsigned int prescaler = 0;
327 u32 ccmr, mask, shift;
328
329 /* Period and prescaler values depends on clock rate */
330 div = (unsigned long long)clk_get_rate(priv->clk) * period_ns;
331
332 do_div(div, NSEC_PER_SEC);
333 prd = div;
334
335 while (div > priv->max_arr) {
336 prescaler++;
337 div = prd;
338 do_div(div, prescaler + 1);
339 }
340
341 prd = div;
342
343 if (prescaler > MAX_TIM_PSC)
344 return -EINVAL;
345
346 /*
347 * All channels share the same prescaler and counter so when two
348 * channels are active at the same time we can't change them
349 */
350 if (active_channels(priv) & ~(1 << ch * 4)) {
351 u32 psc, arr;
352
353 regmap_read(priv->regmap, TIM_PSC, &psc);
354 regmap_read(priv->regmap, TIM_ARR, &arr);
355
356 if ((psc != prescaler) || (arr != prd - 1))
357 return -EBUSY;
358 }
359
360 regmap_write(priv->regmap, TIM_PSC, prescaler);
361 regmap_write(priv->regmap, TIM_ARR, prd - 1);
362 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
363
364 /* Calculate the duty cycles */
365 dty = prd * duty_ns;
366 do_div(dty, period_ns);
367
368 write_ccrx(priv, ch, dty);
369
370 /* Configure output mode */
371 shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
372 ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
373 mask = CCMR_CHANNEL_MASK << shift;
374
375 if (ch < 2)
376 regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
377 else
378 regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
379
380 regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE);
381
382 return 0;
383}
384
385static int stm32_pwm_set_polarity(struct stm32_pwm *priv, int ch,
386 enum pwm_polarity polarity)
387{
388 u32 mask;
389
390 mask = TIM_CCER_CC1P << (ch * 4);
391 if (priv->have_complementary_output)
392 mask |= TIM_CCER_CC1NP << (ch * 4);
393
394 regmap_update_bits(priv->regmap, TIM_CCER, mask,
395 polarity == PWM_POLARITY_NORMAL ? 0 : mask);
396
397 return 0;
398}
399
400static int stm32_pwm_enable(struct stm32_pwm *priv, int ch)
401{
402 u32 mask;
403 int ret;
404
405 ret = clk_enable(priv->clk);
406 if (ret)
407 return ret;
408
409 /* Enable channel */
410 mask = TIM_CCER_CC1E << (ch * 4);
411 if (priv->have_complementary_output)
412 mask |= TIM_CCER_CC1NE << (ch * 4);
413
414 regmap_set_bits(priv->regmap, TIM_CCER, mask);
415
416 /* Make sure that registers are updated */
417 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
418
419 /* Enable controller */
420 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
421
422 return 0;
423}
424
425static void stm32_pwm_disable(struct stm32_pwm *priv, int ch)
426{
427 u32 mask;
428
429 /* Disable channel */
430 mask = TIM_CCER_CC1E << (ch * 4);
431 if (priv->have_complementary_output)
432 mask |= TIM_CCER_CC1NE << (ch * 4);
433
434 regmap_clear_bits(priv->regmap, TIM_CCER, mask);
435
436 /* When all channels are disabled, we can disable the controller */
437 if (!active_channels(priv))
438 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
439
440 clk_disable(priv->clk);
441}
442
443static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
444 const struct pwm_state *state)
445{
446 bool enabled;
447 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
448 int ret;
449
450 enabled = pwm->state.enabled;
451
452 if (enabled && !state->enabled) {
453 stm32_pwm_disable(priv, pwm->hwpwm);
454 return 0;
455 }
456
457 if (state->polarity != pwm->state.polarity)
458 stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity);
459
460 ret = stm32_pwm_config(priv, pwm->hwpwm,
461 state->duty_cycle, state->period);
462 if (ret)
463 return ret;
464
465 if (!enabled && state->enabled)
466 ret = stm32_pwm_enable(priv, pwm->hwpwm);
467
468 return ret;
469}
470
471static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm,
472 const struct pwm_state *state)
473{
474 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
475 int ret;
476
477 /* protect common prescaler for all active channels */
478 mutex_lock(&priv->lock);
479 ret = stm32_pwm_apply(chip, pwm, state);
480 mutex_unlock(&priv->lock);
481
482 return ret;
483}
484
485static const struct pwm_ops stm32pwm_ops = {
486 .owner = THIS_MODULE,
487 .apply = stm32_pwm_apply_locked,
488 .capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,
489};
490
491static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
492 const struct stm32_breakinput *bi)
493{
494 u32 shift = TIM_BDTR_BKF_SHIFT(bi->index);
495 u32 bke = TIM_BDTR_BKE(bi->index);
496 u32 bkp = TIM_BDTR_BKP(bi->index);
497 u32 bkf = TIM_BDTR_BKF(bi->index);
498 u32 mask = bkf | bkp | bke;
499 u32 bdtr;
500
501 bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke;
502
503 if (bi->level)
504 bdtr |= bkp;
505
506 regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);
507
508 regmap_read(priv->regmap, TIM_BDTR, &bdtr);
509
510 return (bdtr & bke) ? 0 : -EINVAL;
511}
512
513static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv)
514{
515 unsigned int i;
516 int ret;
517
518 for (i = 0; i < priv->num_breakinputs; i++) {
519 ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]);
520 if (ret < 0)
521 return ret;
522 }
523
524 return 0;
525}
526
527static int stm32_pwm_probe_breakinputs(struct stm32_pwm *priv,
528 struct device_node *np)
529{
530 int nb, ret, array_size;
531 unsigned int i;
532
533 nb = of_property_count_elems_of_size(np, "st,breakinput",
534 sizeof(struct stm32_breakinput));
535
536 /*
537 * Because "st,breakinput" parameter is optional do not make probe
538 * failed if it doesn't exist.
539 */
540 if (nb <= 0)
541 return 0;
542
543 if (nb > MAX_BREAKINPUT)
544 return -EINVAL;
545
546 priv->num_breakinputs = nb;
547 array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32);
548 ret = of_property_read_u32_array(np, "st,breakinput",
549 (u32 *)priv->breakinputs, array_size);
550 if (ret)
551 return ret;
552
553 for (i = 0; i < priv->num_breakinputs; i++) {
554 if (priv->breakinputs[i].index > 1 ||
555 priv->breakinputs[i].level > 1 ||
556 priv->breakinputs[i].filter > 15)
557 return -EINVAL;
558 }
559
560 return stm32_pwm_apply_breakinputs(priv);
561}
562
563static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
564{
565 u32 ccer;
566
567 /*
568 * If complementary bit doesn't exist writing 1 will have no
569 * effect so we can detect it.
570 */
571 regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
572 regmap_read(priv->regmap, TIM_CCER, &ccer);
573 regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
574
575 priv->have_complementary_output = (ccer != 0);
576}
577
578static int stm32_pwm_detect_channels(struct stm32_pwm *priv)
579{
580 u32 ccer;
581 int npwm = 0;
582
583 /*
584 * If channels enable bits don't exist writing 1 will have no
585 * effect so we can detect and count them.
586 */
587 regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE);
588 regmap_read(priv->regmap, TIM_CCER, &ccer);
589 regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE);
590
591 if (ccer & TIM_CCER_CC1E)
592 npwm++;
593
594 if (ccer & TIM_CCER_CC2E)
595 npwm++;
596
597 if (ccer & TIM_CCER_CC3E)
598 npwm++;
599
600 if (ccer & TIM_CCER_CC4E)
601 npwm++;
602
603 return npwm;
604}
605
606static int stm32_pwm_probe(struct platform_device *pdev)
607{
608 struct device *dev = &pdev->dev;
609 struct device_node *np = dev->of_node;
610 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
611 struct stm32_pwm *priv;
612 int ret;
613
614 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
615 if (!priv)
616 return -ENOMEM;
617
618 mutex_init(&priv->lock);
619 priv->regmap = ddata->regmap;
620 priv->clk = ddata->clk;
621 priv->max_arr = ddata->max_arr;
622
623 if (!priv->regmap || !priv->clk)
624 return -EINVAL;
625
626 ret = stm32_pwm_probe_breakinputs(priv, np);
627 if (ret)
628 return ret;
629
630 stm32_pwm_detect_complementary(priv);
631
632 priv->chip.dev = dev;
633 priv->chip.ops = &stm32pwm_ops;
634 priv->chip.npwm = stm32_pwm_detect_channels(priv);
635
636 ret = pwmchip_add(&priv->chip);
637 if (ret < 0)
638 return ret;
639
640 platform_set_drvdata(pdev, priv);
641
642 return 0;
643}
644
645static int stm32_pwm_remove(struct platform_device *pdev)
646{
647 struct stm32_pwm *priv = platform_get_drvdata(pdev);
648 unsigned int i;
649
650 for (i = 0; i < priv->chip.npwm; i++)
651 pwm_disable(&priv->chip.pwms[i]);
652
653 pwmchip_remove(&priv->chip);
654
655 return 0;
656}
657
658static int __maybe_unused stm32_pwm_suspend(struct device *dev)
659{
660 struct stm32_pwm *priv = dev_get_drvdata(dev);
661 unsigned int i;
662 u32 ccer, mask;
663
664 /* Look for active channels */
665 ccer = active_channels(priv);
666
667 for (i = 0; i < priv->chip.npwm; i++) {
668 mask = TIM_CCER_CC1E << (i * 4);
669 if (ccer & mask) {
670 dev_err(dev, "PWM %u still in use by consumer %s\n",
671 i, priv->chip.pwms[i].label);
672 return -EBUSY;
673 }
674 }
675
676 return pinctrl_pm_select_sleep_state(dev);
677}
678
679static int __maybe_unused stm32_pwm_resume(struct device *dev)
680{
681 struct stm32_pwm *priv = dev_get_drvdata(dev);
682 int ret;
683
684 ret = pinctrl_pm_select_default_state(dev);
685 if (ret)
686 return ret;
687
688 /* restore breakinput registers that may have been lost in low power */
689 return stm32_pwm_apply_breakinputs(priv);
690}
691
692static SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume);
693
694static const struct of_device_id stm32_pwm_of_match[] = {
695 { .compatible = "st,stm32-pwm", },
696 { /* end node */ },
697};
698MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);
699
700static struct platform_driver stm32_pwm_driver = {
701 .probe = stm32_pwm_probe,
702 .remove = stm32_pwm_remove,
703 .driver = {
704 .name = "stm32-pwm",
705 .of_match_table = stm32_pwm_of_match,
706 .pm = &stm32_pwm_pm_ops,
707 },
708};
709module_platform_driver(stm32_pwm_driver);
710
711MODULE_ALIAS("platform:stm32-pwm");
712MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
713MODULE_LICENSE("GPL v2");