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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
5 *
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/interrupt.h>
12#include <linux/irq.h>
13#include <linux/irqdomain.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/msi.h>
17#include <linux/of_address.h>
18#include <linux/of_pci.h>
19#include <linux/of_platform.h>
20#include <linux/pci.h>
21#include <linux/pci-ecam.h>
22#include <linux/platform_device.h>
23#include <linux/irqchip/chained_irq.h>
24
25#include "../pci.h"
26
27/* Bridge core config registers */
28#define BRCFG_PCIE_RX0 0x00000000
29#define BRCFG_PCIE_RX1 0x00000004
30#define BRCFG_INTERRUPT 0x00000010
31#define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
32
33/* Egress - Bridge translation registers */
34#define E_BREG_CAPABILITIES 0x00000200
35#define E_BREG_CONTROL 0x00000208
36#define E_BREG_BASE_LO 0x00000210
37#define E_BREG_BASE_HI 0x00000214
38#define E_ECAM_CAPABILITIES 0x00000220
39#define E_ECAM_CONTROL 0x00000228
40#define E_ECAM_BASE_LO 0x00000230
41#define E_ECAM_BASE_HI 0x00000234
42
43/* Ingress - address translations */
44#define I_MSII_CAPABILITIES 0x00000300
45#define I_MSII_CONTROL 0x00000308
46#define I_MSII_BASE_LO 0x00000310
47#define I_MSII_BASE_HI 0x00000314
48
49#define I_ISUB_CONTROL 0x000003E8
50#define SET_ISUB_CONTROL BIT(0)
51/* Rxed msg fifo - Interrupt status registers */
52#define MSGF_MISC_STATUS 0x00000400
53#define MSGF_MISC_MASK 0x00000404
54#define MSGF_LEG_STATUS 0x00000420
55#define MSGF_LEG_MASK 0x00000424
56#define MSGF_MSI_STATUS_LO 0x00000440
57#define MSGF_MSI_STATUS_HI 0x00000444
58#define MSGF_MSI_MASK_LO 0x00000448
59#define MSGF_MSI_MASK_HI 0x0000044C
60
61/* Msg filter mask bits */
62#define CFG_ENABLE_PM_MSG_FWD BIT(1)
63#define CFG_ENABLE_INT_MSG_FWD BIT(2)
64#define CFG_ENABLE_ERR_MSG_FWD BIT(3)
65#define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \
66 CFG_ENABLE_INT_MSG_FWD | \
67 CFG_ENABLE_ERR_MSG_FWD)
68
69/* Misc interrupt status mask bits */
70#define MSGF_MISC_SR_RXMSG_AVAIL BIT(0)
71#define MSGF_MISC_SR_RXMSG_OVER BIT(1)
72#define MSGF_MISC_SR_SLAVE_ERR BIT(4)
73#define MSGF_MISC_SR_MASTER_ERR BIT(5)
74#define MSGF_MISC_SR_I_ADDR_ERR BIT(6)
75#define MSGF_MISC_SR_E_ADDR_ERR BIT(7)
76#define MSGF_MISC_SR_FATAL_AER BIT(16)
77#define MSGF_MISC_SR_NON_FATAL_AER BIT(17)
78#define MSGF_MISC_SR_CORR_AER BIT(18)
79#define MSGF_MISC_SR_UR_DETECT BIT(20)
80#define MSGF_MISC_SR_NON_FATAL_DEV BIT(22)
81#define MSGF_MISC_SR_FATAL_DEV BIT(23)
82#define MSGF_MISC_SR_LINK_DOWN BIT(24)
83#define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25)
84#define MSGF_MSIC_SR_LINK_BWIDTH BIT(26)
85
86#define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \
87 MSGF_MISC_SR_RXMSG_OVER | \
88 MSGF_MISC_SR_SLAVE_ERR | \
89 MSGF_MISC_SR_MASTER_ERR | \
90 MSGF_MISC_SR_I_ADDR_ERR | \
91 MSGF_MISC_SR_E_ADDR_ERR | \
92 MSGF_MISC_SR_FATAL_AER | \
93 MSGF_MISC_SR_NON_FATAL_AER | \
94 MSGF_MISC_SR_CORR_AER | \
95 MSGF_MISC_SR_UR_DETECT | \
96 MSGF_MISC_SR_NON_FATAL_DEV | \
97 MSGF_MISC_SR_FATAL_DEV | \
98 MSGF_MISC_SR_LINK_DOWN | \
99 MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \
100 MSGF_MSIC_SR_LINK_BWIDTH)
101
102/* Legacy interrupt status mask bits */
103#define MSGF_LEG_SR_INTA BIT(0)
104#define MSGF_LEG_SR_INTB BIT(1)
105#define MSGF_LEG_SR_INTC BIT(2)
106#define MSGF_LEG_SR_INTD BIT(3)
107#define MSGF_LEG_SR_MASKALL (MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \
108 MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
109
110/* MSI interrupt status mask bits */
111#define MSGF_MSI_SR_LO_MASK GENMASK(31, 0)
112#define MSGF_MSI_SR_HI_MASK GENMASK(31, 0)
113
114#define MSII_PRESENT BIT(0)
115#define MSII_ENABLE BIT(0)
116#define MSII_STATUS_ENABLE BIT(15)
117
118/* Bridge config interrupt mask */
119#define BRCFG_INTERRUPT_MASK BIT(0)
120#define BREG_PRESENT BIT(0)
121#define BREG_ENABLE BIT(0)
122#define BREG_ENABLE_FORCE BIT(1)
123
124/* E_ECAM status mask bits */
125#define E_ECAM_PRESENT BIT(0)
126#define E_ECAM_CR_ENABLE BIT(0)
127#define E_ECAM_SIZE_LOC GENMASK(20, 16)
128#define E_ECAM_SIZE_SHIFT 16
129#define NWL_ECAM_MAX_SIZE 16
130
131#define CFG_DMA_REG_BAR GENMASK(2, 0)
132#define CFG_PCIE_CACHE GENMASK(7, 0)
133
134#define INT_PCI_MSI_NR (2 * 32)
135
136/* Readin the PS_LINKUP */
137#define PS_LINKUP_OFFSET 0x00000238
138#define PCIE_PHY_LINKUP_BIT BIT(0)
139#define PHY_RDY_LINKUP_BIT BIT(1)
140
141/* Parameters for the waiting for link up routine */
142#define LINK_WAIT_MAX_RETRIES 10
143#define LINK_WAIT_USLEEP_MIN 90000
144#define LINK_WAIT_USLEEP_MAX 100000
145
146struct nwl_msi { /* MSI information */
147 struct irq_domain *msi_domain;
148 DECLARE_BITMAP(bitmap, INT_PCI_MSI_NR);
149 struct irq_domain *dev_domain;
150 struct mutex lock; /* protect bitmap variable */
151 int irq_msi0;
152 int irq_msi1;
153};
154
155struct nwl_pcie {
156 struct device *dev;
157 void __iomem *breg_base;
158 void __iomem *pcireg_base;
159 void __iomem *ecam_base;
160 phys_addr_t phys_breg_base; /* Physical Bridge Register Base */
161 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
162 phys_addr_t phys_ecam_base; /* Physical Configuration Base */
163 u32 breg_size;
164 u32 pcie_reg_size;
165 u32 ecam_size;
166 int irq_intx;
167 int irq_misc;
168 struct nwl_msi msi;
169 struct irq_domain *intx_irq_domain;
170 struct clk *clk;
171 raw_spinlock_t leg_mask_lock;
172};
173
174static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
175{
176 return readl(pcie->breg_base + off);
177}
178
179static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
180{
181 writel(val, pcie->breg_base + off);
182}
183
184static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
185{
186 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
187 return true;
188 return false;
189}
190
191static bool nwl_phy_link_up(struct nwl_pcie *pcie)
192{
193 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
194 return true;
195 return false;
196}
197
198static int nwl_wait_for_link(struct nwl_pcie *pcie)
199{
200 struct device *dev = pcie->dev;
201 int retries;
202
203 /* check if the link is up or not */
204 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
205 if (nwl_phy_link_up(pcie))
206 return 0;
207 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
208 }
209
210 dev_err(dev, "PHY link never came up\n");
211 return -ETIMEDOUT;
212}
213
214static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
215{
216 struct nwl_pcie *pcie = bus->sysdata;
217
218 /* Check link before accessing downstream ports */
219 if (!pci_is_root_bus(bus)) {
220 if (!nwl_pcie_link_up(pcie))
221 return false;
222 } else if (devfn > 0)
223 /* Only one device down on each root port */
224 return false;
225
226 return true;
227}
228
229/**
230 * nwl_pcie_map_bus - Get configuration base
231 *
232 * @bus: Bus structure of current bus
233 * @devfn: Device/function
234 * @where: Offset from base
235 *
236 * Return: Base address of the configuration space needed to be
237 * accessed.
238 */
239static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
240 int where)
241{
242 struct nwl_pcie *pcie = bus->sysdata;
243
244 if (!nwl_pcie_valid_device(bus, devfn))
245 return NULL;
246
247 return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
248}
249
250/* PCIe operations */
251static struct pci_ops nwl_pcie_ops = {
252 .map_bus = nwl_pcie_map_bus,
253 .read = pci_generic_config_read,
254 .write = pci_generic_config_write,
255};
256
257static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
258{
259 struct nwl_pcie *pcie = data;
260 struct device *dev = pcie->dev;
261 u32 misc_stat;
262
263 /* Checking for misc interrupts */
264 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
265 MSGF_MISC_SR_MASKALL;
266 if (!misc_stat)
267 return IRQ_NONE;
268
269 if (misc_stat & MSGF_MISC_SR_RXMSG_OVER)
270 dev_err(dev, "Received Message FIFO Overflow\n");
271
272 if (misc_stat & MSGF_MISC_SR_SLAVE_ERR)
273 dev_err(dev, "Slave error\n");
274
275 if (misc_stat & MSGF_MISC_SR_MASTER_ERR)
276 dev_err(dev, "Master error\n");
277
278 if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR)
279 dev_err(dev, "In Misc Ingress address translation error\n");
280
281 if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR)
282 dev_err(dev, "In Misc Egress address translation error\n");
283
284 if (misc_stat & MSGF_MISC_SR_FATAL_AER)
285 dev_err(dev, "Fatal Error in AER Capability\n");
286
287 if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER)
288 dev_err(dev, "Non-Fatal Error in AER Capability\n");
289
290 if (misc_stat & MSGF_MISC_SR_CORR_AER)
291 dev_err(dev, "Correctable Error in AER Capability\n");
292
293 if (misc_stat & MSGF_MISC_SR_UR_DETECT)
294 dev_err(dev, "Unsupported request Detected\n");
295
296 if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV)
297 dev_err(dev, "Non-Fatal Error Detected\n");
298
299 if (misc_stat & MSGF_MISC_SR_FATAL_DEV)
300 dev_err(dev, "Fatal Error Detected\n");
301
302 if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH)
303 dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n");
304
305 if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH)
306 dev_info(dev, "Link Bandwidth Management Status bit set\n");
307
308 /* Clear misc interrupt status */
309 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);
310
311 return IRQ_HANDLED;
312}
313
314static void nwl_pcie_leg_handler(struct irq_desc *desc)
315{
316 struct irq_chip *chip = irq_desc_get_chip(desc);
317 struct nwl_pcie *pcie;
318 unsigned long status;
319 u32 bit;
320
321 chained_irq_enter(chip, desc);
322 pcie = irq_desc_get_handler_data(desc);
323
324 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
325 MSGF_LEG_SR_MASKALL) != 0) {
326 for_each_set_bit(bit, &status, PCI_NUM_INTX)
327 generic_handle_domain_irq(pcie->intx_irq_domain, bit);
328 }
329
330 chained_irq_exit(chip, desc);
331}
332
333static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)
334{
335 struct nwl_msi *msi = &pcie->msi;
336 unsigned long status;
337 u32 bit;
338
339 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {
340 for_each_set_bit(bit, &status, 32) {
341 nwl_bridge_writel(pcie, 1 << bit, status_reg);
342 generic_handle_domain_irq(msi->dev_domain, bit);
343 }
344 }
345}
346
347static void nwl_pcie_msi_handler_high(struct irq_desc *desc)
348{
349 struct irq_chip *chip = irq_desc_get_chip(desc);
350 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
351
352 chained_irq_enter(chip, desc);
353 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);
354 chained_irq_exit(chip, desc);
355}
356
357static void nwl_pcie_msi_handler_low(struct irq_desc *desc)
358{
359 struct irq_chip *chip = irq_desc_get_chip(desc);
360 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
361
362 chained_irq_enter(chip, desc);
363 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);
364 chained_irq_exit(chip, desc);
365}
366
367static void nwl_mask_intx_irq(struct irq_data *data)
368{
369 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
370 unsigned long flags;
371 u32 mask;
372 u32 val;
373
374 mask = 1 << (data->hwirq - 1);
375 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
376 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
377 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);
378 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
379}
380
381static void nwl_unmask_intx_irq(struct irq_data *data)
382{
383 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
384 unsigned long flags;
385 u32 mask;
386 u32 val;
387
388 mask = 1 << (data->hwirq - 1);
389 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
390 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
391 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);
392 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
393}
394
395static struct irq_chip nwl_intx_irq_chip = {
396 .name = "nwl_pcie:legacy",
397 .irq_enable = nwl_unmask_intx_irq,
398 .irq_disable = nwl_mask_intx_irq,
399 .irq_mask = nwl_mask_intx_irq,
400 .irq_unmask = nwl_unmask_intx_irq,
401};
402
403static int nwl_intx_map(struct irq_domain *domain, unsigned int irq,
404 irq_hw_number_t hwirq)
405{
406 irq_set_chip_and_handler(irq, &nwl_intx_irq_chip, handle_level_irq);
407 irq_set_chip_data(irq, domain->host_data);
408 irq_set_status_flags(irq, IRQ_LEVEL);
409
410 return 0;
411}
412
413static const struct irq_domain_ops intx_domain_ops = {
414 .map = nwl_intx_map,
415 .xlate = pci_irqd_intx_xlate,
416};
417
418#ifdef CONFIG_PCI_MSI
419static struct irq_chip nwl_msi_irq_chip = {
420 .name = "nwl_pcie:msi",
421 .irq_enable = pci_msi_unmask_irq,
422 .irq_disable = pci_msi_mask_irq,
423 .irq_mask = pci_msi_mask_irq,
424 .irq_unmask = pci_msi_unmask_irq,
425};
426
427static struct msi_domain_info nwl_msi_domain_info = {
428 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
429 MSI_FLAG_MULTI_PCI_MSI),
430 .chip = &nwl_msi_irq_chip,
431};
432#endif
433
434static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
435{
436 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
437 phys_addr_t msi_addr = pcie->phys_pcie_reg_base;
438
439 msg->address_lo = lower_32_bits(msi_addr);
440 msg->address_hi = upper_32_bits(msi_addr);
441 msg->data = data->hwirq;
442}
443
444static int nwl_msi_set_affinity(struct irq_data *irq_data,
445 const struct cpumask *mask, bool force)
446{
447 return -EINVAL;
448}
449
450static struct irq_chip nwl_irq_chip = {
451 .name = "Xilinx MSI",
452 .irq_compose_msi_msg = nwl_compose_msi_msg,
453 .irq_set_affinity = nwl_msi_set_affinity,
454};
455
456static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
457 unsigned int nr_irqs, void *args)
458{
459 struct nwl_pcie *pcie = domain->host_data;
460 struct nwl_msi *msi = &pcie->msi;
461 int bit;
462 int i;
463
464 mutex_lock(&msi->lock);
465 bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR,
466 get_count_order(nr_irqs));
467 if (bit < 0) {
468 mutex_unlock(&msi->lock);
469 return -ENOSPC;
470 }
471
472 for (i = 0; i < nr_irqs; i++) {
473 irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip,
474 domain->host_data, handle_simple_irq,
475 NULL, NULL);
476 }
477 mutex_unlock(&msi->lock);
478 return 0;
479}
480
481static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq,
482 unsigned int nr_irqs)
483{
484 struct irq_data *data = irq_domain_get_irq_data(domain, virq);
485 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
486 struct nwl_msi *msi = &pcie->msi;
487
488 mutex_lock(&msi->lock);
489 bitmap_release_region(msi->bitmap, data->hwirq,
490 get_count_order(nr_irqs));
491 mutex_unlock(&msi->lock);
492}
493
494static const struct irq_domain_ops dev_msi_domain_ops = {
495 .alloc = nwl_irq_domain_alloc,
496 .free = nwl_irq_domain_free,
497};
498
499static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
500{
501#ifdef CONFIG_PCI_MSI
502 struct device *dev = pcie->dev;
503 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
504 struct nwl_msi *msi = &pcie->msi;
505
506 msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR,
507 &dev_msi_domain_ops, pcie);
508 if (!msi->dev_domain) {
509 dev_err(dev, "failed to create dev IRQ domain\n");
510 return -ENOMEM;
511 }
512 msi->msi_domain = pci_msi_create_irq_domain(fwnode,
513 &nwl_msi_domain_info,
514 msi->dev_domain);
515 if (!msi->msi_domain) {
516 dev_err(dev, "failed to create msi IRQ domain\n");
517 irq_domain_remove(msi->dev_domain);
518 return -ENOMEM;
519 }
520#endif
521 return 0;
522}
523
524static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
525{
526 struct device *dev = pcie->dev;
527 struct device_node *node = dev->of_node;
528 struct device_node *intc_node;
529
530 intc_node = of_get_next_child(node, NULL);
531 if (!intc_node) {
532 dev_err(dev, "No legacy intc node found\n");
533 return -EINVAL;
534 }
535
536 pcie->intx_irq_domain = irq_domain_add_linear(intc_node,
537 PCI_NUM_INTX,
538 &intx_domain_ops,
539 pcie);
540 of_node_put(intc_node);
541 if (!pcie->intx_irq_domain) {
542 dev_err(dev, "failed to create IRQ domain\n");
543 return -ENOMEM;
544 }
545
546 raw_spin_lock_init(&pcie->leg_mask_lock);
547 nwl_pcie_init_msi_irq_domain(pcie);
548 return 0;
549}
550
551static int nwl_pcie_enable_msi(struct nwl_pcie *pcie)
552{
553 struct device *dev = pcie->dev;
554 struct platform_device *pdev = to_platform_device(dev);
555 struct nwl_msi *msi = &pcie->msi;
556 unsigned long base;
557 int ret;
558
559 mutex_init(&msi->lock);
560
561 /* Get msi_1 IRQ number */
562 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1");
563 if (msi->irq_msi1 < 0)
564 return -EINVAL;
565
566 irq_set_chained_handler_and_data(msi->irq_msi1,
567 nwl_pcie_msi_handler_high, pcie);
568
569 /* Get msi_0 IRQ number */
570 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0");
571 if (msi->irq_msi0 < 0)
572 return -EINVAL;
573
574 irq_set_chained_handler_and_data(msi->irq_msi0,
575 nwl_pcie_msi_handler_low, pcie);
576
577 /* Check for msii_present bit */
578 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
579 if (!ret) {
580 dev_err(dev, "MSI not present\n");
581 return -EIO;
582 }
583
584 /* Enable MSII */
585 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
586 MSII_ENABLE, I_MSII_CONTROL);
587
588 /* Enable MSII status */
589 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
590 MSII_STATUS_ENABLE, I_MSII_CONTROL);
591
592 /* setup AFI/FPCI range */
593 base = pcie->phys_pcie_reg_base;
594 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
595 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
596
597 /*
598 * For high range MSI interrupts: disable, clear any pending,
599 * and enable
600 */
601 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI);
602
603 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) &
604 MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI);
605
606 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
607
608 /*
609 * For low range MSI interrupts: disable, clear any pending,
610 * and enable
611 */
612 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO);
613
614 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &
615 MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO);
616
617 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
618
619 return 0;
620}
621
622static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
623{
624 struct device *dev = pcie->dev;
625 struct platform_device *pdev = to_platform_device(dev);
626 u32 breg_val, ecam_val;
627 int err;
628
629 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
630 if (!breg_val) {
631 dev_err(dev, "BREG is not present\n");
632 return breg_val;
633 }
634
635 /* Write bridge_off to breg base */
636 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),
637 E_BREG_BASE_LO);
638 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),
639 E_BREG_BASE_HI);
640
641 /* Enable BREG */
642 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
643 E_BREG_CONTROL);
644
645 /* Disable DMA channel registers */
646 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |
647 CFG_DMA_REG_BAR, BRCFG_PCIE_RX0);
648
649 /* Enable Ingress subtractive decode translation */
650 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);
651
652 /* Enable msg filtering details */
653 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
654 BRCFG_PCIE_RX_MSG_FILTER);
655
656 /* This routes the PCIe DMA traffic to go through CCI path */
657 if (of_dma_is_coherent(dev->of_node))
658 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) |
659 CFG_PCIE_CACHE, BRCFG_PCIE_RX1);
660
661 err = nwl_wait_for_link(pcie);
662 if (err)
663 return err;
664
665 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
666 if (!ecam_val) {
667 dev_err(dev, "ECAM is not present\n");
668 return ecam_val;
669 }
670
671 /* Enable ECAM */
672 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
673 E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
674
675 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
676 (NWL_ECAM_MAX_SIZE << E_ECAM_SIZE_SHIFT),
677 E_ECAM_CONTROL);
678
679 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
680 E_ECAM_BASE_LO);
681 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
682 E_ECAM_BASE_HI);
683
684 if (nwl_pcie_link_up(pcie))
685 dev_info(dev, "Link is UP\n");
686 else
687 dev_info(dev, "Link is DOWN\n");
688
689 /* Get misc IRQ number */
690 pcie->irq_misc = platform_get_irq_byname(pdev, "misc");
691 if (pcie->irq_misc < 0)
692 return -EINVAL;
693
694 err = devm_request_irq(dev, pcie->irq_misc,
695 nwl_pcie_misc_handler, IRQF_SHARED,
696 "nwl_pcie:misc", pcie);
697 if (err) {
698 dev_err(dev, "fail to register misc IRQ#%d\n",
699 pcie->irq_misc);
700 return err;
701 }
702
703 /* Disable all misc interrupts */
704 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
705
706 /* Clear pending misc interrupts */
707 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
708 MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS);
709
710 /* Enable all misc interrupts */
711 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
712
713 /* Disable all INTX interrupts */
714 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
715
716 /* Clear pending INTX interrupts */
717 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
718 MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);
719
720 /* Enable all INTX interrupts */
721 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
722
723 /* Enable the bridge config interrupt */
724 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |
725 BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT);
726
727 return 0;
728}
729
730static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
731 struct platform_device *pdev)
732{
733 struct device *dev = pcie->dev;
734 struct resource *res;
735
736 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
737 pcie->breg_base = devm_ioremap_resource(dev, res);
738 if (IS_ERR(pcie->breg_base))
739 return PTR_ERR(pcie->breg_base);
740 pcie->phys_breg_base = res->start;
741
742 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg");
743 pcie->pcireg_base = devm_ioremap_resource(dev, res);
744 if (IS_ERR(pcie->pcireg_base))
745 return PTR_ERR(pcie->pcireg_base);
746 pcie->phys_pcie_reg_base = res->start;
747
748 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
749 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res);
750 if (IS_ERR(pcie->ecam_base))
751 return PTR_ERR(pcie->ecam_base);
752 pcie->phys_ecam_base = res->start;
753
754 /* Get intx IRQ number */
755 pcie->irq_intx = platform_get_irq_byname(pdev, "intx");
756 if (pcie->irq_intx < 0)
757 return pcie->irq_intx;
758
759 irq_set_chained_handler_and_data(pcie->irq_intx,
760 nwl_pcie_leg_handler, pcie);
761
762 return 0;
763}
764
765static const struct of_device_id nwl_pcie_of_match[] = {
766 { .compatible = "xlnx,nwl-pcie-2.11", },
767 {}
768};
769
770static int nwl_pcie_probe(struct platform_device *pdev)
771{
772 struct device *dev = &pdev->dev;
773 struct nwl_pcie *pcie;
774 struct pci_host_bridge *bridge;
775 int err;
776
777 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
778 if (!bridge)
779 return -ENODEV;
780
781 pcie = pci_host_bridge_priv(bridge);
782
783 pcie->dev = dev;
784
785 err = nwl_pcie_parse_dt(pcie, pdev);
786 if (err) {
787 dev_err(dev, "Parsing DT failed\n");
788 return err;
789 }
790
791 pcie->clk = devm_clk_get(dev, NULL);
792 if (IS_ERR(pcie->clk))
793 return PTR_ERR(pcie->clk);
794
795 err = clk_prepare_enable(pcie->clk);
796 if (err) {
797 dev_err(dev, "can't enable PCIe ref clock\n");
798 return err;
799 }
800
801 err = nwl_pcie_bridge_init(pcie);
802 if (err) {
803 dev_err(dev, "HW Initialization failed\n");
804 return err;
805 }
806
807 err = nwl_pcie_init_irq_domain(pcie);
808 if (err) {
809 dev_err(dev, "Failed creating IRQ Domain\n");
810 return err;
811 }
812
813 bridge->sysdata = pcie;
814 bridge->ops = &nwl_pcie_ops;
815
816 if (IS_ENABLED(CONFIG_PCI_MSI)) {
817 err = nwl_pcie_enable_msi(pcie);
818 if (err < 0) {
819 dev_err(dev, "failed to enable MSI support: %d\n", err);
820 return err;
821 }
822 }
823
824 return pci_host_probe(bridge);
825}
826
827static struct platform_driver nwl_pcie_driver = {
828 .driver = {
829 .name = "nwl-pcie",
830 .suppress_bind_attrs = true,
831 .of_match_table = nwl_pcie_of_match,
832 },
833 .probe = nwl_pcie_probe,
834};
835builtin_platform_driver(nwl_pcie_driver);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
5 *
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/interrupt.h>
12#include <linux/irq.h>
13#include <linux/irqdomain.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/msi.h>
17#include <linux/of_address.h>
18#include <linux/of_pci.h>
19#include <linux/of_platform.h>
20#include <linux/pci.h>
21#include <linux/pci-ecam.h>
22#include <linux/platform_device.h>
23#include <linux/irqchip/chained_irq.h>
24
25#include "../pci.h"
26
27/* Bridge core config registers */
28#define BRCFG_PCIE_RX0 0x00000000
29#define BRCFG_PCIE_RX1 0x00000004
30#define BRCFG_INTERRUPT 0x00000010
31#define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
32
33/* Egress - Bridge translation registers */
34#define E_BREG_CAPABILITIES 0x00000200
35#define E_BREG_CONTROL 0x00000208
36#define E_BREG_BASE_LO 0x00000210
37#define E_BREG_BASE_HI 0x00000214
38#define E_ECAM_CAPABILITIES 0x00000220
39#define E_ECAM_CONTROL 0x00000228
40#define E_ECAM_BASE_LO 0x00000230
41#define E_ECAM_BASE_HI 0x00000234
42
43/* Ingress - address translations */
44#define I_MSII_CAPABILITIES 0x00000300
45#define I_MSII_CONTROL 0x00000308
46#define I_MSII_BASE_LO 0x00000310
47#define I_MSII_BASE_HI 0x00000314
48
49#define I_ISUB_CONTROL 0x000003E8
50#define SET_ISUB_CONTROL BIT(0)
51/* Rxed msg fifo - Interrupt status registers */
52#define MSGF_MISC_STATUS 0x00000400
53#define MSGF_MISC_MASK 0x00000404
54#define MSGF_LEG_STATUS 0x00000420
55#define MSGF_LEG_MASK 0x00000424
56#define MSGF_MSI_STATUS_LO 0x00000440
57#define MSGF_MSI_STATUS_HI 0x00000444
58#define MSGF_MSI_MASK_LO 0x00000448
59#define MSGF_MSI_MASK_HI 0x0000044C
60
61/* Msg filter mask bits */
62#define CFG_ENABLE_PM_MSG_FWD BIT(1)
63#define CFG_ENABLE_INT_MSG_FWD BIT(2)
64#define CFG_ENABLE_ERR_MSG_FWD BIT(3)
65#define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \
66 CFG_ENABLE_INT_MSG_FWD | \
67 CFG_ENABLE_ERR_MSG_FWD)
68
69/* Misc interrupt status mask bits */
70#define MSGF_MISC_SR_RXMSG_AVAIL BIT(0)
71#define MSGF_MISC_SR_RXMSG_OVER BIT(1)
72#define MSGF_MISC_SR_SLAVE_ERR BIT(4)
73#define MSGF_MISC_SR_MASTER_ERR BIT(5)
74#define MSGF_MISC_SR_I_ADDR_ERR BIT(6)
75#define MSGF_MISC_SR_E_ADDR_ERR BIT(7)
76#define MSGF_MISC_SR_FATAL_AER BIT(16)
77#define MSGF_MISC_SR_NON_FATAL_AER BIT(17)
78#define MSGF_MISC_SR_CORR_AER BIT(18)
79#define MSGF_MISC_SR_UR_DETECT BIT(20)
80#define MSGF_MISC_SR_NON_FATAL_DEV BIT(22)
81#define MSGF_MISC_SR_FATAL_DEV BIT(23)
82#define MSGF_MISC_SR_LINK_DOWN BIT(24)
83#define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25)
84#define MSGF_MSIC_SR_LINK_BWIDTH BIT(26)
85
86#define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \
87 MSGF_MISC_SR_RXMSG_OVER | \
88 MSGF_MISC_SR_SLAVE_ERR | \
89 MSGF_MISC_SR_MASTER_ERR | \
90 MSGF_MISC_SR_I_ADDR_ERR | \
91 MSGF_MISC_SR_E_ADDR_ERR | \
92 MSGF_MISC_SR_FATAL_AER | \
93 MSGF_MISC_SR_NON_FATAL_AER | \
94 MSGF_MISC_SR_CORR_AER | \
95 MSGF_MISC_SR_UR_DETECT | \
96 MSGF_MISC_SR_NON_FATAL_DEV | \
97 MSGF_MISC_SR_FATAL_DEV | \
98 MSGF_MISC_SR_LINK_DOWN | \
99 MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \
100 MSGF_MSIC_SR_LINK_BWIDTH)
101
102/* Legacy interrupt status mask bits */
103#define MSGF_LEG_SR_INTA BIT(0)
104#define MSGF_LEG_SR_INTB BIT(1)
105#define MSGF_LEG_SR_INTC BIT(2)
106#define MSGF_LEG_SR_INTD BIT(3)
107#define MSGF_LEG_SR_MASKALL (MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \
108 MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
109
110/* MSI interrupt status mask bits */
111#define MSGF_MSI_SR_LO_MASK GENMASK(31, 0)
112#define MSGF_MSI_SR_HI_MASK GENMASK(31, 0)
113
114#define MSII_PRESENT BIT(0)
115#define MSII_ENABLE BIT(0)
116#define MSII_STATUS_ENABLE BIT(15)
117
118/* Bridge config interrupt mask */
119#define BRCFG_INTERRUPT_MASK BIT(0)
120#define BREG_PRESENT BIT(0)
121#define BREG_ENABLE BIT(0)
122#define BREG_ENABLE_FORCE BIT(1)
123
124/* E_ECAM status mask bits */
125#define E_ECAM_PRESENT BIT(0)
126#define E_ECAM_CR_ENABLE BIT(0)
127#define E_ECAM_SIZE_LOC GENMASK(20, 16)
128#define E_ECAM_SIZE_SHIFT 16
129#define NWL_ECAM_VALUE_DEFAULT 12
130
131#define CFG_DMA_REG_BAR GENMASK(2, 0)
132#define CFG_PCIE_CACHE GENMASK(7, 0)
133
134#define INT_PCI_MSI_NR (2 * 32)
135
136/* Readin the PS_LINKUP */
137#define PS_LINKUP_OFFSET 0x00000238
138#define PCIE_PHY_LINKUP_BIT BIT(0)
139#define PHY_RDY_LINKUP_BIT BIT(1)
140
141/* Parameters for the waiting for link up routine */
142#define LINK_WAIT_MAX_RETRIES 10
143#define LINK_WAIT_USLEEP_MIN 90000
144#define LINK_WAIT_USLEEP_MAX 100000
145
146struct nwl_msi { /* MSI information */
147 struct irq_domain *msi_domain;
148 DECLARE_BITMAP(bitmap, INT_PCI_MSI_NR);
149 struct irq_domain *dev_domain;
150 struct mutex lock; /* protect bitmap variable */
151 int irq_msi0;
152 int irq_msi1;
153};
154
155struct nwl_pcie {
156 struct device *dev;
157 void __iomem *breg_base;
158 void __iomem *pcireg_base;
159 void __iomem *ecam_base;
160 phys_addr_t phys_breg_base; /* Physical Bridge Register Base */
161 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
162 phys_addr_t phys_ecam_base; /* Physical Configuration Base */
163 u32 breg_size;
164 u32 pcie_reg_size;
165 u32 ecam_size;
166 int irq_intx;
167 int irq_misc;
168 u32 ecam_value;
169 u8 last_busno;
170 struct nwl_msi msi;
171 struct irq_domain *legacy_irq_domain;
172 struct clk *clk;
173 raw_spinlock_t leg_mask_lock;
174};
175
176static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
177{
178 return readl(pcie->breg_base + off);
179}
180
181static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
182{
183 writel(val, pcie->breg_base + off);
184}
185
186static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
187{
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
189 return true;
190 return false;
191}
192
193static bool nwl_phy_link_up(struct nwl_pcie *pcie)
194{
195 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
196 return true;
197 return false;
198}
199
200static int nwl_wait_for_link(struct nwl_pcie *pcie)
201{
202 struct device *dev = pcie->dev;
203 int retries;
204
205 /* check if the link is up or not */
206 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
207 if (nwl_phy_link_up(pcie))
208 return 0;
209 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
210 }
211
212 dev_err(dev, "PHY link never came up\n");
213 return -ETIMEDOUT;
214}
215
216static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
217{
218 struct nwl_pcie *pcie = bus->sysdata;
219
220 /* Check link before accessing downstream ports */
221 if (!pci_is_root_bus(bus)) {
222 if (!nwl_pcie_link_up(pcie))
223 return false;
224 } else if (devfn > 0)
225 /* Only one device down on each root port */
226 return false;
227
228 return true;
229}
230
231/**
232 * nwl_pcie_map_bus - Get configuration base
233 *
234 * @bus: Bus structure of current bus
235 * @devfn: Device/function
236 * @where: Offset from base
237 *
238 * Return: Base address of the configuration space needed to be
239 * accessed.
240 */
241static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
242 int where)
243{
244 struct nwl_pcie *pcie = bus->sysdata;
245
246 if (!nwl_pcie_valid_device(bus, devfn))
247 return NULL;
248
249 return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
250}
251
252/* PCIe operations */
253static struct pci_ops nwl_pcie_ops = {
254 .map_bus = nwl_pcie_map_bus,
255 .read = pci_generic_config_read,
256 .write = pci_generic_config_write,
257};
258
259static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
260{
261 struct nwl_pcie *pcie = data;
262 struct device *dev = pcie->dev;
263 u32 misc_stat;
264
265 /* Checking for misc interrupts */
266 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
267 MSGF_MISC_SR_MASKALL;
268 if (!misc_stat)
269 return IRQ_NONE;
270
271 if (misc_stat & MSGF_MISC_SR_RXMSG_OVER)
272 dev_err(dev, "Received Message FIFO Overflow\n");
273
274 if (misc_stat & MSGF_MISC_SR_SLAVE_ERR)
275 dev_err(dev, "Slave error\n");
276
277 if (misc_stat & MSGF_MISC_SR_MASTER_ERR)
278 dev_err(dev, "Master error\n");
279
280 if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR)
281 dev_err(dev, "In Misc Ingress address translation error\n");
282
283 if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR)
284 dev_err(dev, "In Misc Egress address translation error\n");
285
286 if (misc_stat & MSGF_MISC_SR_FATAL_AER)
287 dev_err(dev, "Fatal Error in AER Capability\n");
288
289 if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER)
290 dev_err(dev, "Non-Fatal Error in AER Capability\n");
291
292 if (misc_stat & MSGF_MISC_SR_CORR_AER)
293 dev_err(dev, "Correctable Error in AER Capability\n");
294
295 if (misc_stat & MSGF_MISC_SR_UR_DETECT)
296 dev_err(dev, "Unsupported request Detected\n");
297
298 if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV)
299 dev_err(dev, "Non-Fatal Error Detected\n");
300
301 if (misc_stat & MSGF_MISC_SR_FATAL_DEV)
302 dev_err(dev, "Fatal Error Detected\n");
303
304 if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH)
305 dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n");
306
307 if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH)
308 dev_info(dev, "Link Bandwidth Management Status bit set\n");
309
310 /* Clear misc interrupt status */
311 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);
312
313 return IRQ_HANDLED;
314}
315
316static void nwl_pcie_leg_handler(struct irq_desc *desc)
317{
318 struct irq_chip *chip = irq_desc_get_chip(desc);
319 struct nwl_pcie *pcie;
320 unsigned long status;
321 u32 bit;
322
323 chained_irq_enter(chip, desc);
324 pcie = irq_desc_get_handler_data(desc);
325
326 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
327 MSGF_LEG_SR_MASKALL) != 0) {
328 for_each_set_bit(bit, &status, PCI_NUM_INTX)
329 generic_handle_domain_irq(pcie->legacy_irq_domain, bit);
330 }
331
332 chained_irq_exit(chip, desc);
333}
334
335static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)
336{
337 struct nwl_msi *msi = &pcie->msi;
338 unsigned long status;
339 u32 bit;
340
341 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {
342 for_each_set_bit(bit, &status, 32) {
343 nwl_bridge_writel(pcie, 1 << bit, status_reg);
344 generic_handle_domain_irq(msi->dev_domain, bit);
345 }
346 }
347}
348
349static void nwl_pcie_msi_handler_high(struct irq_desc *desc)
350{
351 struct irq_chip *chip = irq_desc_get_chip(desc);
352 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
353
354 chained_irq_enter(chip, desc);
355 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);
356 chained_irq_exit(chip, desc);
357}
358
359static void nwl_pcie_msi_handler_low(struct irq_desc *desc)
360{
361 struct irq_chip *chip = irq_desc_get_chip(desc);
362 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
363
364 chained_irq_enter(chip, desc);
365 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);
366 chained_irq_exit(chip, desc);
367}
368
369static void nwl_mask_leg_irq(struct irq_data *data)
370{
371 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
372 unsigned long flags;
373 u32 mask;
374 u32 val;
375
376 mask = 1 << (data->hwirq - 1);
377 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
378 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
379 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);
380 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
381}
382
383static void nwl_unmask_leg_irq(struct irq_data *data)
384{
385 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
386 unsigned long flags;
387 u32 mask;
388 u32 val;
389
390 mask = 1 << (data->hwirq - 1);
391 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
392 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
393 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);
394 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
395}
396
397static struct irq_chip nwl_leg_irq_chip = {
398 .name = "nwl_pcie:legacy",
399 .irq_enable = nwl_unmask_leg_irq,
400 .irq_disable = nwl_mask_leg_irq,
401 .irq_mask = nwl_mask_leg_irq,
402 .irq_unmask = nwl_unmask_leg_irq,
403};
404
405static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq,
406 irq_hw_number_t hwirq)
407{
408 irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_level_irq);
409 irq_set_chip_data(irq, domain->host_data);
410 irq_set_status_flags(irq, IRQ_LEVEL);
411
412 return 0;
413}
414
415static const struct irq_domain_ops legacy_domain_ops = {
416 .map = nwl_legacy_map,
417 .xlate = pci_irqd_intx_xlate,
418};
419
420#ifdef CONFIG_PCI_MSI
421static struct irq_chip nwl_msi_irq_chip = {
422 .name = "nwl_pcie:msi",
423 .irq_enable = pci_msi_unmask_irq,
424 .irq_disable = pci_msi_mask_irq,
425 .irq_mask = pci_msi_mask_irq,
426 .irq_unmask = pci_msi_unmask_irq,
427};
428
429static struct msi_domain_info nwl_msi_domain_info = {
430 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
431 MSI_FLAG_MULTI_PCI_MSI),
432 .chip = &nwl_msi_irq_chip,
433};
434#endif
435
436static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
437{
438 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
439 phys_addr_t msi_addr = pcie->phys_pcie_reg_base;
440
441 msg->address_lo = lower_32_bits(msi_addr);
442 msg->address_hi = upper_32_bits(msi_addr);
443 msg->data = data->hwirq;
444}
445
446static int nwl_msi_set_affinity(struct irq_data *irq_data,
447 const struct cpumask *mask, bool force)
448{
449 return -EINVAL;
450}
451
452static struct irq_chip nwl_irq_chip = {
453 .name = "Xilinx MSI",
454 .irq_compose_msi_msg = nwl_compose_msi_msg,
455 .irq_set_affinity = nwl_msi_set_affinity,
456};
457
458static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
459 unsigned int nr_irqs, void *args)
460{
461 struct nwl_pcie *pcie = domain->host_data;
462 struct nwl_msi *msi = &pcie->msi;
463 int bit;
464 int i;
465
466 mutex_lock(&msi->lock);
467 bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR,
468 get_count_order(nr_irqs));
469 if (bit < 0) {
470 mutex_unlock(&msi->lock);
471 return -ENOSPC;
472 }
473
474 for (i = 0; i < nr_irqs; i++) {
475 irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip,
476 domain->host_data, handle_simple_irq,
477 NULL, NULL);
478 }
479 mutex_unlock(&msi->lock);
480 return 0;
481}
482
483static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq,
484 unsigned int nr_irqs)
485{
486 struct irq_data *data = irq_domain_get_irq_data(domain, virq);
487 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
488 struct nwl_msi *msi = &pcie->msi;
489
490 mutex_lock(&msi->lock);
491 bitmap_release_region(msi->bitmap, data->hwirq,
492 get_count_order(nr_irqs));
493 mutex_unlock(&msi->lock);
494}
495
496static const struct irq_domain_ops dev_msi_domain_ops = {
497 .alloc = nwl_irq_domain_alloc,
498 .free = nwl_irq_domain_free,
499};
500
501static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
502{
503#ifdef CONFIG_PCI_MSI
504 struct device *dev = pcie->dev;
505 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
506 struct nwl_msi *msi = &pcie->msi;
507
508 msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR,
509 &dev_msi_domain_ops, pcie);
510 if (!msi->dev_domain) {
511 dev_err(dev, "failed to create dev IRQ domain\n");
512 return -ENOMEM;
513 }
514 msi->msi_domain = pci_msi_create_irq_domain(fwnode,
515 &nwl_msi_domain_info,
516 msi->dev_domain);
517 if (!msi->msi_domain) {
518 dev_err(dev, "failed to create msi IRQ domain\n");
519 irq_domain_remove(msi->dev_domain);
520 return -ENOMEM;
521 }
522#endif
523 return 0;
524}
525
526static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
527{
528 struct device *dev = pcie->dev;
529 struct device_node *node = dev->of_node;
530 struct device_node *legacy_intc_node;
531
532 legacy_intc_node = of_get_next_child(node, NULL);
533 if (!legacy_intc_node) {
534 dev_err(dev, "No legacy intc node found\n");
535 return -EINVAL;
536 }
537
538 pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node,
539 PCI_NUM_INTX,
540 &legacy_domain_ops,
541 pcie);
542 of_node_put(legacy_intc_node);
543 if (!pcie->legacy_irq_domain) {
544 dev_err(dev, "failed to create IRQ domain\n");
545 return -ENOMEM;
546 }
547
548 raw_spin_lock_init(&pcie->leg_mask_lock);
549 nwl_pcie_init_msi_irq_domain(pcie);
550 return 0;
551}
552
553static int nwl_pcie_enable_msi(struct nwl_pcie *pcie)
554{
555 struct device *dev = pcie->dev;
556 struct platform_device *pdev = to_platform_device(dev);
557 struct nwl_msi *msi = &pcie->msi;
558 unsigned long base;
559 int ret;
560
561 mutex_init(&msi->lock);
562
563 /* Get msi_1 IRQ number */
564 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1");
565 if (msi->irq_msi1 < 0)
566 return -EINVAL;
567
568 irq_set_chained_handler_and_data(msi->irq_msi1,
569 nwl_pcie_msi_handler_high, pcie);
570
571 /* Get msi_0 IRQ number */
572 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0");
573 if (msi->irq_msi0 < 0)
574 return -EINVAL;
575
576 irq_set_chained_handler_and_data(msi->irq_msi0,
577 nwl_pcie_msi_handler_low, pcie);
578
579 /* Check for msii_present bit */
580 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
581 if (!ret) {
582 dev_err(dev, "MSI not present\n");
583 return -EIO;
584 }
585
586 /* Enable MSII */
587 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
588 MSII_ENABLE, I_MSII_CONTROL);
589
590 /* Enable MSII status */
591 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
592 MSII_STATUS_ENABLE, I_MSII_CONTROL);
593
594 /* setup AFI/FPCI range */
595 base = pcie->phys_pcie_reg_base;
596 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
597 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
598
599 /*
600 * For high range MSI interrupts: disable, clear any pending,
601 * and enable
602 */
603 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI);
604
605 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) &
606 MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI);
607
608 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
609
610 /*
611 * For low range MSI interrupts: disable, clear any pending,
612 * and enable
613 */
614 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO);
615
616 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &
617 MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO);
618
619 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
620
621 return 0;
622}
623
624static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
625{
626 struct device *dev = pcie->dev;
627 struct platform_device *pdev = to_platform_device(dev);
628 u32 breg_val, ecam_val, first_busno = 0;
629 int err;
630
631 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
632 if (!breg_val) {
633 dev_err(dev, "BREG is not present\n");
634 return breg_val;
635 }
636
637 /* Write bridge_off to breg base */
638 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),
639 E_BREG_BASE_LO);
640 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),
641 E_BREG_BASE_HI);
642
643 /* Enable BREG */
644 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
645 E_BREG_CONTROL);
646
647 /* Disable DMA channel registers */
648 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |
649 CFG_DMA_REG_BAR, BRCFG_PCIE_RX0);
650
651 /* Enable Ingress subtractive decode translation */
652 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);
653
654 /* Enable msg filtering details */
655 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
656 BRCFG_PCIE_RX_MSG_FILTER);
657
658 /* This routes the PCIe DMA traffic to go through CCI path */
659 if (of_dma_is_coherent(dev->of_node))
660 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) |
661 CFG_PCIE_CACHE, BRCFG_PCIE_RX1);
662
663 err = nwl_wait_for_link(pcie);
664 if (err)
665 return err;
666
667 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
668 if (!ecam_val) {
669 dev_err(dev, "ECAM is not present\n");
670 return ecam_val;
671 }
672
673 /* Enable ECAM */
674 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
675 E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
676
677 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
678 (pcie->ecam_value << E_ECAM_SIZE_SHIFT),
679 E_ECAM_CONTROL);
680
681 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
682 E_ECAM_BASE_LO);
683 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
684 E_ECAM_BASE_HI);
685
686 /* Get bus range */
687 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);
688 pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;
689 /* Write primary, secondary and subordinate bus numbers */
690 ecam_val = first_busno;
691 ecam_val |= (first_busno + 1) << 8;
692 ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);
693 writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));
694
695 if (nwl_pcie_link_up(pcie))
696 dev_info(dev, "Link is UP\n");
697 else
698 dev_info(dev, "Link is DOWN\n");
699
700 /* Get misc IRQ number */
701 pcie->irq_misc = platform_get_irq_byname(pdev, "misc");
702 if (pcie->irq_misc < 0)
703 return -EINVAL;
704
705 err = devm_request_irq(dev, pcie->irq_misc,
706 nwl_pcie_misc_handler, IRQF_SHARED,
707 "nwl_pcie:misc", pcie);
708 if (err) {
709 dev_err(dev, "fail to register misc IRQ#%d\n",
710 pcie->irq_misc);
711 return err;
712 }
713
714 /* Disable all misc interrupts */
715 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
716
717 /* Clear pending misc interrupts */
718 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
719 MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS);
720
721 /* Enable all misc interrupts */
722 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
723
724 /* Disable all legacy interrupts */
725 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
726
727 /* Clear pending legacy interrupts */
728 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
729 MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);
730
731 /* Enable all legacy interrupts */
732 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
733
734 /* Enable the bridge config interrupt */
735 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |
736 BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT);
737
738 return 0;
739}
740
741static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
742 struct platform_device *pdev)
743{
744 struct device *dev = pcie->dev;
745 struct resource *res;
746
747 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
748 pcie->breg_base = devm_ioremap_resource(dev, res);
749 if (IS_ERR(pcie->breg_base))
750 return PTR_ERR(pcie->breg_base);
751 pcie->phys_breg_base = res->start;
752
753 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg");
754 pcie->pcireg_base = devm_ioremap_resource(dev, res);
755 if (IS_ERR(pcie->pcireg_base))
756 return PTR_ERR(pcie->pcireg_base);
757 pcie->phys_pcie_reg_base = res->start;
758
759 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
760 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res);
761 if (IS_ERR(pcie->ecam_base))
762 return PTR_ERR(pcie->ecam_base);
763 pcie->phys_ecam_base = res->start;
764
765 /* Get intx IRQ number */
766 pcie->irq_intx = platform_get_irq_byname(pdev, "intx");
767 if (pcie->irq_intx < 0)
768 return pcie->irq_intx;
769
770 irq_set_chained_handler_and_data(pcie->irq_intx,
771 nwl_pcie_leg_handler, pcie);
772
773 return 0;
774}
775
776static const struct of_device_id nwl_pcie_of_match[] = {
777 { .compatible = "xlnx,nwl-pcie-2.11", },
778 {}
779};
780
781static int nwl_pcie_probe(struct platform_device *pdev)
782{
783 struct device *dev = &pdev->dev;
784 struct nwl_pcie *pcie;
785 struct pci_host_bridge *bridge;
786 int err;
787
788 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
789 if (!bridge)
790 return -ENODEV;
791
792 pcie = pci_host_bridge_priv(bridge);
793
794 pcie->dev = dev;
795 pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
796
797 err = nwl_pcie_parse_dt(pcie, pdev);
798 if (err) {
799 dev_err(dev, "Parsing DT failed\n");
800 return err;
801 }
802
803 pcie->clk = devm_clk_get(dev, NULL);
804 if (IS_ERR(pcie->clk))
805 return PTR_ERR(pcie->clk);
806
807 err = clk_prepare_enable(pcie->clk);
808 if (err) {
809 dev_err(dev, "can't enable PCIe ref clock\n");
810 return err;
811 }
812
813 err = nwl_pcie_bridge_init(pcie);
814 if (err) {
815 dev_err(dev, "HW Initialization failed\n");
816 return err;
817 }
818
819 err = nwl_pcie_init_irq_domain(pcie);
820 if (err) {
821 dev_err(dev, "Failed creating IRQ Domain\n");
822 return err;
823 }
824
825 bridge->sysdata = pcie;
826 bridge->ops = &nwl_pcie_ops;
827
828 if (IS_ENABLED(CONFIG_PCI_MSI)) {
829 err = nwl_pcie_enable_msi(pcie);
830 if (err < 0) {
831 dev_err(dev, "failed to enable MSI support: %d\n", err);
832 return err;
833 }
834 }
835
836 return pci_host_probe(bridge);
837}
838
839static struct platform_driver nwl_pcie_driver = {
840 .driver = {
841 .name = "nwl-pcie",
842 .suppress_bind_attrs = true,
843 .of_match_table = nwl_pcie_of_match,
844 },
845 .probe = nwl_pcie_probe,
846};
847builtin_platform_driver(nwl_pcie_driver);