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1// SPDX-License-Identifier: GPL-2.0+
2/* Microchip Sparx5 Switch driver
3 *
4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
5 *
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
8 */
9#include <linux/module.h>
10#include <linux/device.h>
11#include <linux/netdevice.h>
12#include <linux/platform_device.h>
13#include <linux/interrupt.h>
14#include <linux/of.h>
15#include <linux/of_net.h>
16#include <linux/of_mdio.h>
17#include <net/switchdev.h>
18#include <linux/etherdevice.h>
19#include <linux/io.h>
20#include <linux/printk.h>
21#include <linux/iopoll.h>
22#include <linux/mfd/syscon.h>
23#include <linux/regmap.h>
24#include <linux/types.h>
25#include <linux/reset.h>
26
27#include "sparx5_main_regs.h"
28#include "sparx5_main.h"
29#include "sparx5_port.h"
30#include "sparx5_qos.h"
31
32#define QLIM_WM(fraction) \
33 ((SPX5_BUFFER_MEMORY / SPX5_BUFFER_CELL_SZ - 100) * (fraction) / 100)
34#define IO_RANGES 3
35
36struct initial_port_config {
37 u32 portno;
38 struct device_node *node;
39 struct sparx5_port_config conf;
40 struct phy *serdes;
41};
42
43struct sparx5_ram_config {
44 void __iomem *init_reg;
45 u32 init_val;
46};
47
48struct sparx5_main_io_resource {
49 enum sparx5_target id;
50 phys_addr_t offset;
51 int range;
52};
53
54static const struct sparx5_main_io_resource sparx5_main_iomap[] = {
55 { TARGET_CPU, 0, 0 }, /* 0x600000000 */
56 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */
57 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */
58 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */
59 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */
60 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */
61 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */
62 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */
63 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */
64 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */
65 { TARGET_DEV5G + 2, 0x10020000, 1 }, /* 0x610020000 */
66 { TARGET_PCS5G_BR + 2, 0x10024000, 1 }, /* 0x610024000 */
67 { TARGET_DEV2G5 + 6, 0x10028000, 1 }, /* 0x610028000 */
68 { TARGET_DEV5G + 6, 0x1002c000, 1 }, /* 0x61002c000 */
69 { TARGET_PCS5G_BR + 6, 0x10030000, 1 }, /* 0x610030000 */
70 { TARGET_DEV2G5 + 7, 0x10034000, 1 }, /* 0x610034000 */
71 { TARGET_DEV5G + 7, 0x10038000, 1 }, /* 0x610038000 */
72 { TARGET_PCS5G_BR + 7, 0x1003c000, 1 }, /* 0x61003c000 */
73 { TARGET_DEV2G5 + 8, 0x10040000, 1 }, /* 0x610040000 */
74 { TARGET_DEV5G + 8, 0x10044000, 1 }, /* 0x610044000 */
75 { TARGET_PCS5G_BR + 8, 0x10048000, 1 }, /* 0x610048000 */
76 { TARGET_DEV2G5 + 9, 0x1004c000, 1 }, /* 0x61004c000 */
77 { TARGET_DEV5G + 9, 0x10050000, 1 }, /* 0x610050000 */
78 { TARGET_PCS5G_BR + 9, 0x10054000, 1 }, /* 0x610054000 */
79 { TARGET_DEV2G5 + 10, 0x10058000, 1 }, /* 0x610058000 */
80 { TARGET_DEV5G + 10, 0x1005c000, 1 }, /* 0x61005c000 */
81 { TARGET_PCS5G_BR + 10, 0x10060000, 1 }, /* 0x610060000 */
82 { TARGET_DEV2G5 + 11, 0x10064000, 1 }, /* 0x610064000 */
83 { TARGET_DEV5G + 11, 0x10068000, 1 }, /* 0x610068000 */
84 { TARGET_PCS5G_BR + 11, 0x1006c000, 1 }, /* 0x61006c000 */
85 { TARGET_DEV2G5 + 12, 0x10070000, 1 }, /* 0x610070000 */
86 { TARGET_DEV10G, 0x10074000, 1 }, /* 0x610074000 */
87 { TARGET_PCS10G_BR, 0x10078000, 1 }, /* 0x610078000 */
88 { TARGET_DEV2G5 + 14, 0x1007c000, 1 }, /* 0x61007c000 */
89 { TARGET_DEV10G + 2, 0x10080000, 1 }, /* 0x610080000 */
90 { TARGET_PCS10G_BR + 2, 0x10084000, 1 }, /* 0x610084000 */
91 { TARGET_DEV2G5 + 15, 0x10088000, 1 }, /* 0x610088000 */
92 { TARGET_DEV10G + 3, 0x1008c000, 1 }, /* 0x61008c000 */
93 { TARGET_PCS10G_BR + 3, 0x10090000, 1 }, /* 0x610090000 */
94 { TARGET_DEV2G5 + 16, 0x10094000, 1 }, /* 0x610094000 */
95 { TARGET_DEV2G5 + 17, 0x10098000, 1 }, /* 0x610098000 */
96 { TARGET_DEV2G5 + 18, 0x1009c000, 1 }, /* 0x61009c000 */
97 { TARGET_DEV2G5 + 19, 0x100a0000, 1 }, /* 0x6100a0000 */
98 { TARGET_DEV2G5 + 20, 0x100a4000, 1 }, /* 0x6100a4000 */
99 { TARGET_DEV2G5 + 21, 0x100a8000, 1 }, /* 0x6100a8000 */
100 { TARGET_DEV2G5 + 22, 0x100ac000, 1 }, /* 0x6100ac000 */
101 { TARGET_DEV2G5 + 23, 0x100b0000, 1 }, /* 0x6100b0000 */
102 { TARGET_DEV2G5 + 32, 0x100b4000, 1 }, /* 0x6100b4000 */
103 { TARGET_DEV2G5 + 33, 0x100b8000, 1 }, /* 0x6100b8000 */
104 { TARGET_DEV2G5 + 34, 0x100bc000, 1 }, /* 0x6100bc000 */
105 { TARGET_DEV2G5 + 35, 0x100c0000, 1 }, /* 0x6100c0000 */
106 { TARGET_DEV2G5 + 36, 0x100c4000, 1 }, /* 0x6100c4000 */
107 { TARGET_DEV2G5 + 37, 0x100c8000, 1 }, /* 0x6100c8000 */
108 { TARGET_DEV2G5 + 38, 0x100cc000, 1 }, /* 0x6100cc000 */
109 { TARGET_DEV2G5 + 39, 0x100d0000, 1 }, /* 0x6100d0000 */
110 { TARGET_DEV2G5 + 40, 0x100d4000, 1 }, /* 0x6100d4000 */
111 { TARGET_DEV2G5 + 41, 0x100d8000, 1 }, /* 0x6100d8000 */
112 { TARGET_DEV2G5 + 42, 0x100dc000, 1 }, /* 0x6100dc000 */
113 { TARGET_DEV2G5 + 43, 0x100e0000, 1 }, /* 0x6100e0000 */
114 { TARGET_DEV2G5 + 44, 0x100e4000, 1 }, /* 0x6100e4000 */
115 { TARGET_DEV2G5 + 45, 0x100e8000, 1 }, /* 0x6100e8000 */
116 { TARGET_DEV2G5 + 46, 0x100ec000, 1 }, /* 0x6100ec000 */
117 { TARGET_DEV2G5 + 47, 0x100f0000, 1 }, /* 0x6100f0000 */
118 { TARGET_DEV2G5 + 57, 0x100f4000, 1 }, /* 0x6100f4000 */
119 { TARGET_DEV25G + 1, 0x100f8000, 1 }, /* 0x6100f8000 */
120 { TARGET_PCS25G_BR + 1, 0x100fc000, 1 }, /* 0x6100fc000 */
121 { TARGET_DEV2G5 + 59, 0x10104000, 1 }, /* 0x610104000 */
122 { TARGET_DEV25G + 3, 0x10108000, 1 }, /* 0x610108000 */
123 { TARGET_PCS25G_BR + 3, 0x1010c000, 1 }, /* 0x61010c000 */
124 { TARGET_DEV2G5 + 60, 0x10114000, 1 }, /* 0x610114000 */
125 { TARGET_DEV25G + 4, 0x10118000, 1 }, /* 0x610118000 */
126 { TARGET_PCS25G_BR + 4, 0x1011c000, 1 }, /* 0x61011c000 */
127 { TARGET_DEV2G5 + 64, 0x10124000, 1 }, /* 0x610124000 */
128 { TARGET_DEV5G + 12, 0x10128000, 1 }, /* 0x610128000 */
129 { TARGET_PCS5G_BR + 12, 0x1012c000, 1 }, /* 0x61012c000 */
130 { TARGET_PORT_CONF, 0x10130000, 1 }, /* 0x610130000 */
131 { TARGET_DEV2G5 + 3, 0x10404000, 1 }, /* 0x610404000 */
132 { TARGET_DEV5G + 3, 0x10408000, 1 }, /* 0x610408000 */
133 { TARGET_PCS5G_BR + 3, 0x1040c000, 1 }, /* 0x61040c000 */
134 { TARGET_DEV2G5 + 4, 0x10410000, 1 }, /* 0x610410000 */
135 { TARGET_DEV5G + 4, 0x10414000, 1 }, /* 0x610414000 */
136 { TARGET_PCS5G_BR + 4, 0x10418000, 1 }, /* 0x610418000 */
137 { TARGET_DEV2G5 + 5, 0x1041c000, 1 }, /* 0x61041c000 */
138 { TARGET_DEV5G + 5, 0x10420000, 1 }, /* 0x610420000 */
139 { TARGET_PCS5G_BR + 5, 0x10424000, 1 }, /* 0x610424000 */
140 { TARGET_DEV2G5 + 13, 0x10428000, 1 }, /* 0x610428000 */
141 { TARGET_DEV10G + 1, 0x1042c000, 1 }, /* 0x61042c000 */
142 { TARGET_PCS10G_BR + 1, 0x10430000, 1 }, /* 0x610430000 */
143 { TARGET_DEV2G5 + 24, 0x10434000, 1 }, /* 0x610434000 */
144 { TARGET_DEV2G5 + 25, 0x10438000, 1 }, /* 0x610438000 */
145 { TARGET_DEV2G5 + 26, 0x1043c000, 1 }, /* 0x61043c000 */
146 { TARGET_DEV2G5 + 27, 0x10440000, 1 }, /* 0x610440000 */
147 { TARGET_DEV2G5 + 28, 0x10444000, 1 }, /* 0x610444000 */
148 { TARGET_DEV2G5 + 29, 0x10448000, 1 }, /* 0x610448000 */
149 { TARGET_DEV2G5 + 30, 0x1044c000, 1 }, /* 0x61044c000 */
150 { TARGET_DEV2G5 + 31, 0x10450000, 1 }, /* 0x610450000 */
151 { TARGET_DEV2G5 + 48, 0x10454000, 1 }, /* 0x610454000 */
152 { TARGET_DEV10G + 4, 0x10458000, 1 }, /* 0x610458000 */
153 { TARGET_PCS10G_BR + 4, 0x1045c000, 1 }, /* 0x61045c000 */
154 { TARGET_DEV2G5 + 49, 0x10460000, 1 }, /* 0x610460000 */
155 { TARGET_DEV10G + 5, 0x10464000, 1 }, /* 0x610464000 */
156 { TARGET_PCS10G_BR + 5, 0x10468000, 1 }, /* 0x610468000 */
157 { TARGET_DEV2G5 + 50, 0x1046c000, 1 }, /* 0x61046c000 */
158 { TARGET_DEV10G + 6, 0x10470000, 1 }, /* 0x610470000 */
159 { TARGET_PCS10G_BR + 6, 0x10474000, 1 }, /* 0x610474000 */
160 { TARGET_DEV2G5 + 51, 0x10478000, 1 }, /* 0x610478000 */
161 { TARGET_DEV10G + 7, 0x1047c000, 1 }, /* 0x61047c000 */
162 { TARGET_PCS10G_BR + 7, 0x10480000, 1 }, /* 0x610480000 */
163 { TARGET_DEV2G5 + 52, 0x10484000, 1 }, /* 0x610484000 */
164 { TARGET_DEV10G + 8, 0x10488000, 1 }, /* 0x610488000 */
165 { TARGET_PCS10G_BR + 8, 0x1048c000, 1 }, /* 0x61048c000 */
166 { TARGET_DEV2G5 + 53, 0x10490000, 1 }, /* 0x610490000 */
167 { TARGET_DEV10G + 9, 0x10494000, 1 }, /* 0x610494000 */
168 { TARGET_PCS10G_BR + 9, 0x10498000, 1 }, /* 0x610498000 */
169 { TARGET_DEV2G5 + 54, 0x1049c000, 1 }, /* 0x61049c000 */
170 { TARGET_DEV10G + 10, 0x104a0000, 1 }, /* 0x6104a0000 */
171 { TARGET_PCS10G_BR + 10, 0x104a4000, 1 }, /* 0x6104a4000 */
172 { TARGET_DEV2G5 + 55, 0x104a8000, 1 }, /* 0x6104a8000 */
173 { TARGET_DEV10G + 11, 0x104ac000, 1 }, /* 0x6104ac000 */
174 { TARGET_PCS10G_BR + 11, 0x104b0000, 1 }, /* 0x6104b0000 */
175 { TARGET_DEV2G5 + 56, 0x104b4000, 1 }, /* 0x6104b4000 */
176 { TARGET_DEV25G, 0x104b8000, 1 }, /* 0x6104b8000 */
177 { TARGET_PCS25G_BR, 0x104bc000, 1 }, /* 0x6104bc000 */
178 { TARGET_DEV2G5 + 58, 0x104c4000, 1 }, /* 0x6104c4000 */
179 { TARGET_DEV25G + 2, 0x104c8000, 1 }, /* 0x6104c8000 */
180 { TARGET_PCS25G_BR + 2, 0x104cc000, 1 }, /* 0x6104cc000 */
181 { TARGET_DEV2G5 + 61, 0x104d4000, 1 }, /* 0x6104d4000 */
182 { TARGET_DEV25G + 5, 0x104d8000, 1 }, /* 0x6104d8000 */
183 { TARGET_PCS25G_BR + 5, 0x104dc000, 1 }, /* 0x6104dc000 */
184 { TARGET_DEV2G5 + 62, 0x104e4000, 1 }, /* 0x6104e4000 */
185 { TARGET_DEV25G + 6, 0x104e8000, 1 }, /* 0x6104e8000 */
186 { TARGET_PCS25G_BR + 6, 0x104ec000, 1 }, /* 0x6104ec000 */
187 { TARGET_DEV2G5 + 63, 0x104f4000, 1 }, /* 0x6104f4000 */
188 { TARGET_DEV25G + 7, 0x104f8000, 1 }, /* 0x6104f8000 */
189 { TARGET_PCS25G_BR + 7, 0x104fc000, 1 }, /* 0x6104fc000 */
190 { TARGET_DSM, 0x10504000, 1 }, /* 0x610504000 */
191 { TARGET_ASM, 0x10600000, 1 }, /* 0x610600000 */
192 { TARGET_GCB, 0x11010000, 2 }, /* 0x611010000 */
193 { TARGET_QS, 0x11030000, 2 }, /* 0x611030000 */
194 { TARGET_PTP, 0x11040000, 2 }, /* 0x611040000 */
195 { TARGET_ANA_ACL, 0x11050000, 2 }, /* 0x611050000 */
196 { TARGET_LRN, 0x11060000, 2 }, /* 0x611060000 */
197 { TARGET_VCAP_SUPER, 0x11080000, 2 }, /* 0x611080000 */
198 { TARGET_QSYS, 0x110a0000, 2 }, /* 0x6110a0000 */
199 { TARGET_QFWD, 0x110b0000, 2 }, /* 0x6110b0000 */
200 { TARGET_XQS, 0x110c0000, 2 }, /* 0x6110c0000 */
201 { TARGET_VCAP_ES2, 0x110d0000, 2 }, /* 0x6110d0000 */
202 { TARGET_VCAP_ES0, 0x110e0000, 2 }, /* 0x6110e0000 */
203 { TARGET_CLKGEN, 0x11100000, 2 }, /* 0x611100000 */
204 { TARGET_ANA_AC_POL, 0x11200000, 2 }, /* 0x611200000 */
205 { TARGET_QRES, 0x11280000, 2 }, /* 0x611280000 */
206 { TARGET_EACL, 0x112c0000, 2 }, /* 0x6112c0000 */
207 { TARGET_ANA_CL, 0x11400000, 2 }, /* 0x611400000 */
208 { TARGET_ANA_L3, 0x11480000, 2 }, /* 0x611480000 */
209 { TARGET_ANA_AC_SDLB, 0x11500000, 2 }, /* 0x611500000 */
210 { TARGET_HSCH, 0x11580000, 2 }, /* 0x611580000 */
211 { TARGET_REW, 0x11600000, 2 }, /* 0x611600000 */
212 { TARGET_ANA_L2, 0x11800000, 2 }, /* 0x611800000 */
213 { TARGET_ANA_AC, 0x11900000, 2 }, /* 0x611900000 */
214 { TARGET_VOP, 0x11a00000, 2 }, /* 0x611a00000 */
215};
216
217static int sparx5_create_targets(struct sparx5 *sparx5)
218{
219 struct resource *iores[IO_RANGES];
220 void __iomem *iomem[IO_RANGES];
221 void __iomem *begin[IO_RANGES];
222 int range_id[IO_RANGES];
223 int idx, jdx;
224
225 for (idx = 0, jdx = 0; jdx < ARRAY_SIZE(sparx5_main_iomap); jdx++) {
226 const struct sparx5_main_io_resource *iomap = &sparx5_main_iomap[jdx];
227
228 if (idx == iomap->range) {
229 range_id[idx] = jdx;
230 idx++;
231 }
232 }
233 for (idx = 0; idx < IO_RANGES; idx++) {
234 iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM,
235 idx);
236 if (!iores[idx]) {
237 dev_err(sparx5->dev, "Invalid resource\n");
238 return -EINVAL;
239 }
240 iomem[idx] = devm_ioremap(sparx5->dev,
241 iores[idx]->start,
242 resource_size(iores[idx]));
243 if (!iomem[idx]) {
244 dev_err(sparx5->dev, "Unable to get switch registers: %s\n",
245 iores[idx]->name);
246 return -ENOMEM;
247 }
248 begin[idx] = iomem[idx] - sparx5_main_iomap[range_id[idx]].offset;
249 }
250 for (jdx = 0; jdx < ARRAY_SIZE(sparx5_main_iomap); jdx++) {
251 const struct sparx5_main_io_resource *iomap = &sparx5_main_iomap[jdx];
252
253 sparx5->regs[iomap->id] = begin[iomap->range] + iomap->offset;
254 }
255 return 0;
256}
257
258static int sparx5_create_port(struct sparx5 *sparx5,
259 struct initial_port_config *config)
260{
261 struct sparx5_port *spx5_port;
262 struct net_device *ndev;
263 struct phylink *phylink;
264 int err;
265
266 ndev = sparx5_create_netdev(sparx5, config->portno);
267 if (IS_ERR(ndev)) {
268 dev_err(sparx5->dev, "Could not create net device: %02u\n",
269 config->portno);
270 return PTR_ERR(ndev);
271 }
272 spx5_port = netdev_priv(ndev);
273 spx5_port->of_node = config->node;
274 spx5_port->serdes = config->serdes;
275 spx5_port->pvid = NULL_VID;
276 spx5_port->signd_internal = true;
277 spx5_port->signd_active_high = true;
278 spx5_port->signd_enable = true;
279 spx5_port->max_vlan_tags = SPX5_PORT_MAX_TAGS_NONE;
280 spx5_port->vlan_type = SPX5_VLAN_PORT_TYPE_UNAWARE;
281 spx5_port->custom_etype = 0x8880; /* Vitesse */
282 spx5_port->phylink_pcs.poll = true;
283 spx5_port->phylink_pcs.ops = &sparx5_phylink_pcs_ops;
284 spx5_port->phylink_pcs.neg_mode = true;
285 spx5_port->is_mrouter = false;
286 INIT_LIST_HEAD(&spx5_port->tc_templates);
287 sparx5->ports[config->portno] = spx5_port;
288
289 err = sparx5_port_init(sparx5, spx5_port, &config->conf);
290 if (err) {
291 dev_err(sparx5->dev, "port init failed\n");
292 return err;
293 }
294 spx5_port->conf = config->conf;
295
296 /* Setup VLAN */
297 sparx5_vlan_port_setup(sparx5, spx5_port->portno);
298
299 /* Create a phylink for PHY management. Also handles SFPs */
300 spx5_port->phylink_config.dev = &spx5_port->ndev->dev;
301 spx5_port->phylink_config.type = PHYLINK_NETDEV;
302 spx5_port->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
303 MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD |
304 MAC_2500FD | MAC_5000FD | MAC_10000FD | MAC_25000FD;
305
306 __set_bit(PHY_INTERFACE_MODE_SGMII,
307 spx5_port->phylink_config.supported_interfaces);
308 __set_bit(PHY_INTERFACE_MODE_QSGMII,
309 spx5_port->phylink_config.supported_interfaces);
310 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
311 spx5_port->phylink_config.supported_interfaces);
312 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
313 spx5_port->phylink_config.supported_interfaces);
314
315 if (spx5_port->conf.bandwidth == SPEED_5000 ||
316 spx5_port->conf.bandwidth == SPEED_10000 ||
317 spx5_port->conf.bandwidth == SPEED_25000)
318 __set_bit(PHY_INTERFACE_MODE_5GBASER,
319 spx5_port->phylink_config.supported_interfaces);
320
321 if (spx5_port->conf.bandwidth == SPEED_10000 ||
322 spx5_port->conf.bandwidth == SPEED_25000)
323 __set_bit(PHY_INTERFACE_MODE_10GBASER,
324 spx5_port->phylink_config.supported_interfaces);
325
326 if (spx5_port->conf.bandwidth == SPEED_25000)
327 __set_bit(PHY_INTERFACE_MODE_25GBASER,
328 spx5_port->phylink_config.supported_interfaces);
329
330 phylink = phylink_create(&spx5_port->phylink_config,
331 of_fwnode_handle(config->node),
332 config->conf.phy_mode,
333 &sparx5_phylink_mac_ops);
334 if (IS_ERR(phylink))
335 return PTR_ERR(phylink);
336
337 spx5_port->phylink = phylink;
338
339 return 0;
340}
341
342static int sparx5_init_ram(struct sparx5 *s5)
343{
344 const struct sparx5_ram_config spx5_ram_cfg[] = {
345 {spx5_reg_get(s5, ANA_AC_STAT_RESET), ANA_AC_STAT_RESET_RESET},
346 {spx5_reg_get(s5, ASM_STAT_CFG), ASM_STAT_CFG_STAT_CNT_CLR_SHOT},
347 {spx5_reg_get(s5, QSYS_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
348 {spx5_reg_get(s5, REW_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
349 {spx5_reg_get(s5, VOP_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
350 {spx5_reg_get(s5, ANA_AC_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
351 {spx5_reg_get(s5, ASM_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
352 {spx5_reg_get(s5, EACL_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
353 {spx5_reg_get(s5, VCAP_SUPER_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
354 {spx5_reg_get(s5, DSM_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}
355 };
356 const struct sparx5_ram_config *cfg;
357 u32 value, pending, jdx, idx;
358
359 for (jdx = 0; jdx < 10; jdx++) {
360 pending = ARRAY_SIZE(spx5_ram_cfg);
361 for (idx = 0; idx < ARRAY_SIZE(spx5_ram_cfg); idx++) {
362 cfg = &spx5_ram_cfg[idx];
363 if (jdx == 0) {
364 writel(cfg->init_val, cfg->init_reg);
365 } else {
366 value = readl(cfg->init_reg);
367 if ((value & cfg->init_val) != cfg->init_val)
368 pending--;
369 }
370 }
371 if (!pending)
372 break;
373 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
374 }
375
376 if (pending > 0) {
377 /* Still initializing, should be complete in
378 * less than 1ms
379 */
380 dev_err(s5->dev, "Memory initialization error\n");
381 return -EINVAL;
382 }
383 return 0;
384}
385
386static int sparx5_init_switchcore(struct sparx5 *sparx5)
387{
388 u32 value;
389 int err = 0;
390
391 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(1),
392 EACL_POL_EACL_CFG_EACL_FORCE_INIT,
393 sparx5,
394 EACL_POL_EACL_CFG);
395
396 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(0),
397 EACL_POL_EACL_CFG_EACL_FORCE_INIT,
398 sparx5,
399 EACL_POL_EACL_CFG);
400
401 /* Initialize memories, if not done already */
402 value = spx5_rd(sparx5, HSCH_RESET_CFG);
403 if (!(value & HSCH_RESET_CFG_CORE_ENA)) {
404 err = sparx5_init_ram(sparx5);
405 if (err)
406 return err;
407 }
408
409 /* Reset counters */
410 spx5_wr(ANA_AC_STAT_RESET_RESET_SET(1), sparx5, ANA_AC_STAT_RESET);
411 spx5_wr(ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(1), sparx5, ASM_STAT_CFG);
412
413 /* Enable switch-core and queue system */
414 spx5_wr(HSCH_RESET_CFG_CORE_ENA_SET(1), sparx5, HSCH_RESET_CFG);
415
416 return 0;
417}
418
419static int sparx5_init_coreclock(struct sparx5 *sparx5)
420{
421 enum sparx5_core_clockfreq freq = sparx5->coreclock;
422 u32 clk_div, clk_period, pol_upd_int, idx;
423
424 /* Verify if core clock frequency is supported on target.
425 * If 'VTSS_CORE_CLOCK_DEFAULT' then the highest supported
426 * freq. is used
427 */
428 switch (sparx5->target_ct) {
429 case SPX5_TARGET_CT_7546:
430 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
431 freq = SPX5_CORE_CLOCK_250MHZ;
432 else if (sparx5->coreclock != SPX5_CORE_CLOCK_250MHZ)
433 freq = 0; /* Not supported */
434 break;
435 case SPX5_TARGET_CT_7549:
436 case SPX5_TARGET_CT_7552:
437 case SPX5_TARGET_CT_7556:
438 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
439 freq = SPX5_CORE_CLOCK_500MHZ;
440 else if (sparx5->coreclock != SPX5_CORE_CLOCK_500MHZ)
441 freq = 0; /* Not supported */
442 break;
443 case SPX5_TARGET_CT_7558:
444 case SPX5_TARGET_CT_7558TSN:
445 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
446 freq = SPX5_CORE_CLOCK_625MHZ;
447 else if (sparx5->coreclock != SPX5_CORE_CLOCK_625MHZ)
448 freq = 0; /* Not supported */
449 break;
450 case SPX5_TARGET_CT_7546TSN:
451 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
452 freq = SPX5_CORE_CLOCK_625MHZ;
453 break;
454 case SPX5_TARGET_CT_7549TSN:
455 case SPX5_TARGET_CT_7552TSN:
456 case SPX5_TARGET_CT_7556TSN:
457 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
458 freq = SPX5_CORE_CLOCK_625MHZ;
459 else if (sparx5->coreclock == SPX5_CORE_CLOCK_250MHZ)
460 freq = 0; /* Not supported */
461 break;
462 default:
463 dev_err(sparx5->dev, "Target (%#04x) not supported\n",
464 sparx5->target_ct);
465 return -ENODEV;
466 }
467
468 switch (freq) {
469 case SPX5_CORE_CLOCK_250MHZ:
470 clk_div = 10;
471 pol_upd_int = 312;
472 break;
473 case SPX5_CORE_CLOCK_500MHZ:
474 clk_div = 5;
475 pol_upd_int = 624;
476 break;
477 case SPX5_CORE_CLOCK_625MHZ:
478 clk_div = 4;
479 pol_upd_int = 780;
480 break;
481 default:
482 dev_err(sparx5->dev, "%d coreclock not supported on (%#04x)\n",
483 sparx5->coreclock, sparx5->target_ct);
484 return -EINVAL;
485 }
486
487 /* Update state with chosen frequency */
488 sparx5->coreclock = freq;
489
490 /* Configure the LCPLL */
491 spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) |
492 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(0) |
493 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(0) |
494 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(0) |
495 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(0) |
496 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(1),
497 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV |
498 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV |
499 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR |
500 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL |
501 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA |
502 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA,
503 sparx5,
504 CLKGEN_LCPLL1_CORE_CLK_CFG);
505
506 clk_period = sparx5_clk_period(freq);
507
508 spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100),
509 HSCH_SYS_CLK_PER_100PS,
510 sparx5,
511 HSCH_SYS_CLK_PER);
512
513 spx5_rmw(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100),
514 ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS,
515 sparx5,
516 ANA_AC_POL_BDLB_DLB_CTRL);
517
518 spx5_rmw(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100),
519 ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS,
520 sparx5,
521 ANA_AC_POL_SLB_DLB_CTRL);
522
523 spx5_rmw(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(clk_period / 100),
524 LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS,
525 sparx5,
526 LRN_AUTOAGE_CFG_1);
527
528 for (idx = 0; idx < 3; idx++)
529 spx5_rmw(GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(clk_period / 100),
530 GCB_SIO_CLOCK_SYS_CLK_PERIOD,
531 sparx5,
532 GCB_SIO_CLOCK(idx));
533
534 spx5_rmw(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET
535 ((256 * 1000) / clk_period),
536 HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY,
537 sparx5,
538 HSCH_TAS_STATEMACHINE_CFG);
539
540 spx5_rmw(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(pol_upd_int),
541 ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT,
542 sparx5,
543 ANA_AC_POL_POL_UPD_INT_CFG);
544
545 return 0;
546}
547
548static int sparx5_qlim_set(struct sparx5 *sparx5)
549{
550 u32 res, dp, prio;
551
552 for (res = 0; res < 2; res++) {
553 for (prio = 0; prio < 8; prio++)
554 spx5_wr(0xFFF, sparx5,
555 QRES_RES_CFG(prio + 630 + res * 1024));
556
557 for (dp = 0; dp < 4; dp++)
558 spx5_wr(0xFFF, sparx5,
559 QRES_RES_CFG(dp + 638 + res * 1024));
560 }
561
562 /* Set 80,90,95,100% of memory size for top watermarks */
563 spx5_wr(QLIM_WM(80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0));
564 spx5_wr(QLIM_WM(90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0));
565 spx5_wr(QLIM_WM(95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0));
566 spx5_wr(QLIM_WM(100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0));
567
568 return 0;
569}
570
571/* Some boards needs to map the SGPIO for signal detect explicitly to the
572 * port module
573 */
574static void sparx5_board_init(struct sparx5 *sparx5)
575{
576 int idx;
577
578 if (!sparx5->sd_sgpio_remapping)
579 return;
580
581 /* Enable SGPIO Signal Detect remapping */
582 spx5_rmw(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL,
583 GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL,
584 sparx5,
585 GCB_HW_SGPIO_SD_CFG);
586
587 /* Refer to LOS SGPIO */
588 for (idx = 0; idx < SPX5_PORTS; idx++)
589 if (sparx5->ports[idx])
590 if (sparx5->ports[idx]->conf.sd_sgpio != ~0)
591 spx5_wr(sparx5->ports[idx]->conf.sd_sgpio,
592 sparx5,
593 GCB_HW_SGPIO_TO_SD_MAP_CFG(idx));
594}
595
596static int sparx5_start(struct sparx5 *sparx5)
597{
598 u8 broadcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
599 char queue_name[32];
600 u32 idx;
601 int err;
602
603 /* Setup own UPSIDs */
604 for (idx = 0; idx < 3; idx++) {
605 spx5_wr(idx, sparx5, ANA_AC_OWN_UPSID(idx));
606 spx5_wr(idx, sparx5, ANA_CL_OWN_UPSID(idx));
607 spx5_wr(idx, sparx5, ANA_L2_OWN_UPSID(idx));
608 spx5_wr(idx, sparx5, REW_OWN_UPSID(idx));
609 }
610
611 /* Enable CPU ports */
612 for (idx = SPX5_PORTS; idx < SPX5_PORTS_ALL; idx++)
613 spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1),
614 QFWD_SWITCH_PORT_MODE_PORT_ENA,
615 sparx5,
616 QFWD_SWITCH_PORT_MODE(idx));
617
618 /* Init masks */
619 sparx5_update_fwd(sparx5);
620
621 /* CPU copy CPU pgids */
622 spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1),
623 sparx5, ANA_AC_PGID_MISC_CFG(PGID_CPU));
624 spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1),
625 sparx5, ANA_AC_PGID_MISC_CFG(PGID_BCAST));
626
627 /* Recalc injected frame FCS */
628 for (idx = SPX5_PORT_CPU_0; idx <= SPX5_PORT_CPU_1; idx++)
629 spx5_rmw(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(1),
630 ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA,
631 sparx5, ANA_CL_FILTER_CTRL(idx));
632
633 /* Init MAC table, ageing */
634 sparx5_mact_init(sparx5);
635
636 /* Init PGID table arbitrator */
637 sparx5_pgid_init(sparx5);
638
639 /* Setup VLANs */
640 sparx5_vlan_init(sparx5);
641
642 /* Add host mode BC address (points only to CPU) */
643 sparx5_mact_learn(sparx5, PGID_CPU, broadcast, NULL_VID);
644
645 /* Enable queue limitation watermarks */
646 sparx5_qlim_set(sparx5);
647
648 err = sparx5_config_auto_calendar(sparx5);
649 if (err)
650 return err;
651
652 err = sparx5_config_dsm_calendar(sparx5);
653 if (err)
654 return err;
655
656 /* Init stats */
657 err = sparx_stats_init(sparx5);
658 if (err)
659 return err;
660
661 /* Init mact_sw struct */
662 mutex_init(&sparx5->mact_lock);
663 INIT_LIST_HEAD(&sparx5->mact_entries);
664 snprintf(queue_name, sizeof(queue_name), "%s-mact",
665 dev_name(sparx5->dev));
666 sparx5->mact_queue = create_singlethread_workqueue(queue_name);
667 if (!sparx5->mact_queue)
668 return -ENOMEM;
669
670 INIT_DELAYED_WORK(&sparx5->mact_work, sparx5_mact_pull_work);
671 queue_delayed_work(sparx5->mact_queue, &sparx5->mact_work,
672 SPX5_MACT_PULL_DELAY);
673
674 mutex_init(&sparx5->mdb_lock);
675 INIT_LIST_HEAD(&sparx5->mdb_entries);
676
677 err = sparx5_register_netdevs(sparx5);
678 if (err)
679 return err;
680
681 sparx5_board_init(sparx5);
682 err = sparx5_register_notifier_blocks(sparx5);
683 if (err)
684 return err;
685
686 err = sparx5_vcap_init(sparx5);
687 if (err) {
688 sparx5_unregister_notifier_blocks(sparx5);
689 return err;
690 }
691
692 /* Start Frame DMA with fallback to register based INJ/XTR */
693 err = -ENXIO;
694 if (sparx5->fdma_irq >= 0) {
695 if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0)
696 err = devm_request_threaded_irq(sparx5->dev,
697 sparx5->fdma_irq,
698 NULL,
699 sparx5_fdma_handler,
700 IRQF_ONESHOT,
701 "sparx5-fdma", sparx5);
702 if (!err)
703 err = sparx5_fdma_start(sparx5);
704 if (err)
705 sparx5->fdma_irq = -ENXIO;
706 } else {
707 sparx5->fdma_irq = -ENXIO;
708 }
709 if (err && sparx5->xtr_irq >= 0) {
710 err = devm_request_irq(sparx5->dev, sparx5->xtr_irq,
711 sparx5_xtr_handler, IRQF_SHARED,
712 "sparx5-xtr", sparx5);
713 if (!err)
714 err = sparx5_manual_injection_mode(sparx5);
715 if (err)
716 sparx5->xtr_irq = -ENXIO;
717 } else {
718 sparx5->xtr_irq = -ENXIO;
719 }
720
721 if (sparx5->ptp_irq >= 0) {
722 err = devm_request_threaded_irq(sparx5->dev, sparx5->ptp_irq,
723 NULL, sparx5_ptp_irq_handler,
724 IRQF_ONESHOT, "sparx5-ptp",
725 sparx5);
726 if (err)
727 sparx5->ptp_irq = -ENXIO;
728
729 sparx5->ptp = 1;
730 }
731
732 return err;
733}
734
735static void sparx5_cleanup_ports(struct sparx5 *sparx5)
736{
737 sparx5_unregister_netdevs(sparx5);
738 sparx5_destroy_netdevs(sparx5);
739}
740
741static int mchp_sparx5_probe(struct platform_device *pdev)
742{
743 struct initial_port_config *configs, *config;
744 struct device_node *np = pdev->dev.of_node;
745 struct device_node *ports, *portnp;
746 struct reset_control *reset;
747 struct sparx5 *sparx5;
748 int idx = 0, err = 0;
749
750 if (!np && !pdev->dev.platform_data)
751 return -ENODEV;
752
753 sparx5 = devm_kzalloc(&pdev->dev, sizeof(*sparx5), GFP_KERNEL);
754 if (!sparx5)
755 return -ENOMEM;
756
757 platform_set_drvdata(pdev, sparx5);
758 sparx5->pdev = pdev;
759 sparx5->dev = &pdev->dev;
760 spin_lock_init(&sparx5->tx_lock);
761
762 /* Do switch core reset if available */
763 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch");
764 if (IS_ERR(reset))
765 return dev_err_probe(&pdev->dev, PTR_ERR(reset),
766 "Failed to get switch reset controller.\n");
767 reset_control_reset(reset);
768
769 /* Default values, some from DT */
770 sparx5->coreclock = SPX5_CORE_CLOCK_DEFAULT;
771
772 sparx5->debugfs_root = debugfs_create_dir("sparx5", NULL);
773
774 ports = of_get_child_by_name(np, "ethernet-ports");
775 if (!ports) {
776 dev_err(sparx5->dev, "no ethernet-ports child node found\n");
777 return -ENODEV;
778 }
779 sparx5->port_count = of_get_child_count(ports);
780
781 configs = kcalloc(sparx5->port_count,
782 sizeof(struct initial_port_config), GFP_KERNEL);
783 if (!configs) {
784 err = -ENOMEM;
785 goto cleanup_pnode;
786 }
787
788 for_each_available_child_of_node(ports, portnp) {
789 struct sparx5_port_config *conf;
790 struct phy *serdes;
791 u32 portno;
792
793 err = of_property_read_u32(portnp, "reg", &portno);
794 if (err) {
795 dev_err(sparx5->dev, "port reg property error\n");
796 continue;
797 }
798 config = &configs[idx];
799 conf = &config->conf;
800 conf->speed = SPEED_UNKNOWN;
801 conf->bandwidth = SPEED_UNKNOWN;
802 err = of_get_phy_mode(portnp, &conf->phy_mode);
803 if (err) {
804 dev_err(sparx5->dev, "port %u: missing phy-mode\n",
805 portno);
806 continue;
807 }
808 err = of_property_read_u32(portnp, "microchip,bandwidth",
809 &conf->bandwidth);
810 if (err) {
811 dev_err(sparx5->dev, "port %u: missing bandwidth\n",
812 portno);
813 continue;
814 }
815 err = of_property_read_u32(portnp, "microchip,sd-sgpio", &conf->sd_sgpio);
816 if (err)
817 conf->sd_sgpio = ~0;
818 else
819 sparx5->sd_sgpio_remapping = true;
820 serdes = devm_of_phy_get(sparx5->dev, portnp, NULL);
821 if (IS_ERR(serdes)) {
822 err = dev_err_probe(sparx5->dev, PTR_ERR(serdes),
823 "port %u: missing serdes\n",
824 portno);
825 of_node_put(portnp);
826 goto cleanup_config;
827 }
828 config->portno = portno;
829 config->node = portnp;
830 config->serdes = serdes;
831
832 conf->media = PHY_MEDIA_DAC;
833 conf->serdes_reset = true;
834 conf->portmode = conf->phy_mode;
835 conf->power_down = true;
836 idx++;
837 }
838
839 err = sparx5_create_targets(sparx5);
840 if (err)
841 goto cleanup_config;
842
843 if (of_get_mac_address(np, sparx5->base_mac)) {
844 dev_info(sparx5->dev, "MAC addr was not set, use random MAC\n");
845 eth_random_addr(sparx5->base_mac);
846 sparx5->base_mac[5] = 0;
847 }
848
849 sparx5->fdma_irq = platform_get_irq_byname(sparx5->pdev, "fdma");
850 sparx5->xtr_irq = platform_get_irq_byname(sparx5->pdev, "xtr");
851 sparx5->ptp_irq = platform_get_irq_byname(sparx5->pdev, "ptp");
852
853 /* Read chip ID to check CPU interface */
854 sparx5->chip_id = spx5_rd(sparx5, GCB_CHIP_ID);
855
856 sparx5->target_ct = (enum spx5_target_chiptype)
857 GCB_CHIP_ID_PART_ID_GET(sparx5->chip_id);
858
859 /* Initialize Switchcore and internal RAMs */
860 err = sparx5_init_switchcore(sparx5);
861 if (err) {
862 dev_err(sparx5->dev, "Switchcore initialization error\n");
863 goto cleanup_config;
864 }
865
866 /* Initialize the LC-PLL (core clock) and set affected registers */
867 err = sparx5_init_coreclock(sparx5);
868 if (err) {
869 dev_err(sparx5->dev, "LC-PLL initialization error\n");
870 goto cleanup_config;
871 }
872
873 for (idx = 0; idx < sparx5->port_count; ++idx) {
874 config = &configs[idx];
875 if (!config->node)
876 continue;
877
878 err = sparx5_create_port(sparx5, config);
879 if (err) {
880 dev_err(sparx5->dev, "port create error\n");
881 goto cleanup_ports;
882 }
883 }
884
885 err = sparx5_start(sparx5);
886 if (err) {
887 dev_err(sparx5->dev, "Start failed\n");
888 goto cleanup_ports;
889 }
890
891 err = sparx5_qos_init(sparx5);
892 if (err) {
893 dev_err(sparx5->dev, "Failed to initialize QoS\n");
894 goto cleanup_ports;
895 }
896
897 err = sparx5_ptp_init(sparx5);
898 if (err) {
899 dev_err(sparx5->dev, "PTP failed\n");
900 goto cleanup_ports;
901 }
902 goto cleanup_config;
903
904cleanup_ports:
905 sparx5_cleanup_ports(sparx5);
906 if (sparx5->mact_queue)
907 destroy_workqueue(sparx5->mact_queue);
908cleanup_config:
909 kfree(configs);
910cleanup_pnode:
911 of_node_put(ports);
912 return err;
913}
914
915static void mchp_sparx5_remove(struct platform_device *pdev)
916{
917 struct sparx5 *sparx5 = platform_get_drvdata(pdev);
918
919 debugfs_remove_recursive(sparx5->debugfs_root);
920 if (sparx5->xtr_irq) {
921 disable_irq(sparx5->xtr_irq);
922 sparx5->xtr_irq = -ENXIO;
923 }
924 if (sparx5->fdma_irq) {
925 disable_irq(sparx5->fdma_irq);
926 sparx5->fdma_irq = -ENXIO;
927 }
928 sparx5_ptp_deinit(sparx5);
929 sparx5_fdma_stop(sparx5);
930 sparx5_cleanup_ports(sparx5);
931 sparx5_vcap_destroy(sparx5);
932 /* Unregister netdevs */
933 sparx5_unregister_notifier_blocks(sparx5);
934 destroy_workqueue(sparx5->mact_queue);
935}
936
937static const struct of_device_id mchp_sparx5_match[] = {
938 { .compatible = "microchip,sparx5-switch" },
939 { }
940};
941MODULE_DEVICE_TABLE(of, mchp_sparx5_match);
942
943static struct platform_driver mchp_sparx5_driver = {
944 .probe = mchp_sparx5_probe,
945 .remove_new = mchp_sparx5_remove,
946 .driver = {
947 .name = "sparx5-switch",
948 .of_match_table = mchp_sparx5_match,
949 },
950};
951
952module_platform_driver(mchp_sparx5_driver);
953
954MODULE_DESCRIPTION("Microchip Sparx5 switch driver");
955MODULE_AUTHOR("Steen Hegelund <steen.hegelund@microchip.com>");
956MODULE_LICENSE("Dual MIT/GPL");
1// SPDX-License-Identifier: GPL-2.0+
2/* Microchip Sparx5 Switch driver
3 *
4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
5 *
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
8 */
9#include <linux/module.h>
10#include <linux/device.h>
11#include <linux/netdevice.h>
12#include <linux/platform_device.h>
13#include <linux/interrupt.h>
14#include <linux/of.h>
15#include <linux/of_net.h>
16#include <linux/of_mdio.h>
17#include <net/switchdev.h>
18#include <linux/etherdevice.h>
19#include <linux/io.h>
20#include <linux/printk.h>
21#include <linux/iopoll.h>
22#include <linux/mfd/syscon.h>
23#include <linux/regmap.h>
24#include <linux/types.h>
25#include <linux/reset.h>
26
27#include "sparx5_main_regs.h"
28#include "sparx5_main.h"
29#include "sparx5_port.h"
30#include "sparx5_qos.h"
31
32#define QLIM_WM(fraction) \
33 ((SPX5_BUFFER_MEMORY / SPX5_BUFFER_CELL_SZ - 100) * (fraction) / 100)
34#define IO_RANGES 3
35
36struct initial_port_config {
37 u32 portno;
38 struct device_node *node;
39 struct sparx5_port_config conf;
40 struct phy *serdes;
41};
42
43struct sparx5_ram_config {
44 void __iomem *init_reg;
45 u32 init_val;
46};
47
48struct sparx5_main_io_resource {
49 enum sparx5_target id;
50 phys_addr_t offset;
51 int range;
52};
53
54static const struct sparx5_main_io_resource sparx5_main_iomap[] = {
55 { TARGET_CPU, 0, 0 }, /* 0x600000000 */
56 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */
57 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */
58 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */
59 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */
60 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */
61 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */
62 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */
63 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */
64 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */
65 { TARGET_DEV5G + 2, 0x10020000, 1 }, /* 0x610020000 */
66 { TARGET_PCS5G_BR + 2, 0x10024000, 1 }, /* 0x610024000 */
67 { TARGET_DEV2G5 + 6, 0x10028000, 1 }, /* 0x610028000 */
68 { TARGET_DEV5G + 6, 0x1002c000, 1 }, /* 0x61002c000 */
69 { TARGET_PCS5G_BR + 6, 0x10030000, 1 }, /* 0x610030000 */
70 { TARGET_DEV2G5 + 7, 0x10034000, 1 }, /* 0x610034000 */
71 { TARGET_DEV5G + 7, 0x10038000, 1 }, /* 0x610038000 */
72 { TARGET_PCS5G_BR + 7, 0x1003c000, 1 }, /* 0x61003c000 */
73 { TARGET_DEV2G5 + 8, 0x10040000, 1 }, /* 0x610040000 */
74 { TARGET_DEV5G + 8, 0x10044000, 1 }, /* 0x610044000 */
75 { TARGET_PCS5G_BR + 8, 0x10048000, 1 }, /* 0x610048000 */
76 { TARGET_DEV2G5 + 9, 0x1004c000, 1 }, /* 0x61004c000 */
77 { TARGET_DEV5G + 9, 0x10050000, 1 }, /* 0x610050000 */
78 { TARGET_PCS5G_BR + 9, 0x10054000, 1 }, /* 0x610054000 */
79 { TARGET_DEV2G5 + 10, 0x10058000, 1 }, /* 0x610058000 */
80 { TARGET_DEV5G + 10, 0x1005c000, 1 }, /* 0x61005c000 */
81 { TARGET_PCS5G_BR + 10, 0x10060000, 1 }, /* 0x610060000 */
82 { TARGET_DEV2G5 + 11, 0x10064000, 1 }, /* 0x610064000 */
83 { TARGET_DEV5G + 11, 0x10068000, 1 }, /* 0x610068000 */
84 { TARGET_PCS5G_BR + 11, 0x1006c000, 1 }, /* 0x61006c000 */
85 { TARGET_DEV2G5 + 12, 0x10070000, 1 }, /* 0x610070000 */
86 { TARGET_DEV10G, 0x10074000, 1 }, /* 0x610074000 */
87 { TARGET_PCS10G_BR, 0x10078000, 1 }, /* 0x610078000 */
88 { TARGET_DEV2G5 + 14, 0x1007c000, 1 }, /* 0x61007c000 */
89 { TARGET_DEV10G + 2, 0x10080000, 1 }, /* 0x610080000 */
90 { TARGET_PCS10G_BR + 2, 0x10084000, 1 }, /* 0x610084000 */
91 { TARGET_DEV2G5 + 15, 0x10088000, 1 }, /* 0x610088000 */
92 { TARGET_DEV10G + 3, 0x1008c000, 1 }, /* 0x61008c000 */
93 { TARGET_PCS10G_BR + 3, 0x10090000, 1 }, /* 0x610090000 */
94 { TARGET_DEV2G5 + 16, 0x10094000, 1 }, /* 0x610094000 */
95 { TARGET_DEV2G5 + 17, 0x10098000, 1 }, /* 0x610098000 */
96 { TARGET_DEV2G5 + 18, 0x1009c000, 1 }, /* 0x61009c000 */
97 { TARGET_DEV2G5 + 19, 0x100a0000, 1 }, /* 0x6100a0000 */
98 { TARGET_DEV2G5 + 20, 0x100a4000, 1 }, /* 0x6100a4000 */
99 { TARGET_DEV2G5 + 21, 0x100a8000, 1 }, /* 0x6100a8000 */
100 { TARGET_DEV2G5 + 22, 0x100ac000, 1 }, /* 0x6100ac000 */
101 { TARGET_DEV2G5 + 23, 0x100b0000, 1 }, /* 0x6100b0000 */
102 { TARGET_DEV2G5 + 32, 0x100b4000, 1 }, /* 0x6100b4000 */
103 { TARGET_DEV2G5 + 33, 0x100b8000, 1 }, /* 0x6100b8000 */
104 { TARGET_DEV2G5 + 34, 0x100bc000, 1 }, /* 0x6100bc000 */
105 { TARGET_DEV2G5 + 35, 0x100c0000, 1 }, /* 0x6100c0000 */
106 { TARGET_DEV2G5 + 36, 0x100c4000, 1 }, /* 0x6100c4000 */
107 { TARGET_DEV2G5 + 37, 0x100c8000, 1 }, /* 0x6100c8000 */
108 { TARGET_DEV2G5 + 38, 0x100cc000, 1 }, /* 0x6100cc000 */
109 { TARGET_DEV2G5 + 39, 0x100d0000, 1 }, /* 0x6100d0000 */
110 { TARGET_DEV2G5 + 40, 0x100d4000, 1 }, /* 0x6100d4000 */
111 { TARGET_DEV2G5 + 41, 0x100d8000, 1 }, /* 0x6100d8000 */
112 { TARGET_DEV2G5 + 42, 0x100dc000, 1 }, /* 0x6100dc000 */
113 { TARGET_DEV2G5 + 43, 0x100e0000, 1 }, /* 0x6100e0000 */
114 { TARGET_DEV2G5 + 44, 0x100e4000, 1 }, /* 0x6100e4000 */
115 { TARGET_DEV2G5 + 45, 0x100e8000, 1 }, /* 0x6100e8000 */
116 { TARGET_DEV2G5 + 46, 0x100ec000, 1 }, /* 0x6100ec000 */
117 { TARGET_DEV2G5 + 47, 0x100f0000, 1 }, /* 0x6100f0000 */
118 { TARGET_DEV2G5 + 57, 0x100f4000, 1 }, /* 0x6100f4000 */
119 { TARGET_DEV25G + 1, 0x100f8000, 1 }, /* 0x6100f8000 */
120 { TARGET_PCS25G_BR + 1, 0x100fc000, 1 }, /* 0x6100fc000 */
121 { TARGET_DEV2G5 + 59, 0x10104000, 1 }, /* 0x610104000 */
122 { TARGET_DEV25G + 3, 0x10108000, 1 }, /* 0x610108000 */
123 { TARGET_PCS25G_BR + 3, 0x1010c000, 1 }, /* 0x61010c000 */
124 { TARGET_DEV2G5 + 60, 0x10114000, 1 }, /* 0x610114000 */
125 { TARGET_DEV25G + 4, 0x10118000, 1 }, /* 0x610118000 */
126 { TARGET_PCS25G_BR + 4, 0x1011c000, 1 }, /* 0x61011c000 */
127 { TARGET_DEV2G5 + 64, 0x10124000, 1 }, /* 0x610124000 */
128 { TARGET_DEV5G + 12, 0x10128000, 1 }, /* 0x610128000 */
129 { TARGET_PCS5G_BR + 12, 0x1012c000, 1 }, /* 0x61012c000 */
130 { TARGET_PORT_CONF, 0x10130000, 1 }, /* 0x610130000 */
131 { TARGET_DEV2G5 + 3, 0x10404000, 1 }, /* 0x610404000 */
132 { TARGET_DEV5G + 3, 0x10408000, 1 }, /* 0x610408000 */
133 { TARGET_PCS5G_BR + 3, 0x1040c000, 1 }, /* 0x61040c000 */
134 { TARGET_DEV2G5 + 4, 0x10410000, 1 }, /* 0x610410000 */
135 { TARGET_DEV5G + 4, 0x10414000, 1 }, /* 0x610414000 */
136 { TARGET_PCS5G_BR + 4, 0x10418000, 1 }, /* 0x610418000 */
137 { TARGET_DEV2G5 + 5, 0x1041c000, 1 }, /* 0x61041c000 */
138 { TARGET_DEV5G + 5, 0x10420000, 1 }, /* 0x610420000 */
139 { TARGET_PCS5G_BR + 5, 0x10424000, 1 }, /* 0x610424000 */
140 { TARGET_DEV2G5 + 13, 0x10428000, 1 }, /* 0x610428000 */
141 { TARGET_DEV10G + 1, 0x1042c000, 1 }, /* 0x61042c000 */
142 { TARGET_PCS10G_BR + 1, 0x10430000, 1 }, /* 0x610430000 */
143 { TARGET_DEV2G5 + 24, 0x10434000, 1 }, /* 0x610434000 */
144 { TARGET_DEV2G5 + 25, 0x10438000, 1 }, /* 0x610438000 */
145 { TARGET_DEV2G5 + 26, 0x1043c000, 1 }, /* 0x61043c000 */
146 { TARGET_DEV2G5 + 27, 0x10440000, 1 }, /* 0x610440000 */
147 { TARGET_DEV2G5 + 28, 0x10444000, 1 }, /* 0x610444000 */
148 { TARGET_DEV2G5 + 29, 0x10448000, 1 }, /* 0x610448000 */
149 { TARGET_DEV2G5 + 30, 0x1044c000, 1 }, /* 0x61044c000 */
150 { TARGET_DEV2G5 + 31, 0x10450000, 1 }, /* 0x610450000 */
151 { TARGET_DEV2G5 + 48, 0x10454000, 1 }, /* 0x610454000 */
152 { TARGET_DEV10G + 4, 0x10458000, 1 }, /* 0x610458000 */
153 { TARGET_PCS10G_BR + 4, 0x1045c000, 1 }, /* 0x61045c000 */
154 { TARGET_DEV2G5 + 49, 0x10460000, 1 }, /* 0x610460000 */
155 { TARGET_DEV10G + 5, 0x10464000, 1 }, /* 0x610464000 */
156 { TARGET_PCS10G_BR + 5, 0x10468000, 1 }, /* 0x610468000 */
157 { TARGET_DEV2G5 + 50, 0x1046c000, 1 }, /* 0x61046c000 */
158 { TARGET_DEV10G + 6, 0x10470000, 1 }, /* 0x610470000 */
159 { TARGET_PCS10G_BR + 6, 0x10474000, 1 }, /* 0x610474000 */
160 { TARGET_DEV2G5 + 51, 0x10478000, 1 }, /* 0x610478000 */
161 { TARGET_DEV10G + 7, 0x1047c000, 1 }, /* 0x61047c000 */
162 { TARGET_PCS10G_BR + 7, 0x10480000, 1 }, /* 0x610480000 */
163 { TARGET_DEV2G5 + 52, 0x10484000, 1 }, /* 0x610484000 */
164 { TARGET_DEV10G + 8, 0x10488000, 1 }, /* 0x610488000 */
165 { TARGET_PCS10G_BR + 8, 0x1048c000, 1 }, /* 0x61048c000 */
166 { TARGET_DEV2G5 + 53, 0x10490000, 1 }, /* 0x610490000 */
167 { TARGET_DEV10G + 9, 0x10494000, 1 }, /* 0x610494000 */
168 { TARGET_PCS10G_BR + 9, 0x10498000, 1 }, /* 0x610498000 */
169 { TARGET_DEV2G5 + 54, 0x1049c000, 1 }, /* 0x61049c000 */
170 { TARGET_DEV10G + 10, 0x104a0000, 1 }, /* 0x6104a0000 */
171 { TARGET_PCS10G_BR + 10, 0x104a4000, 1 }, /* 0x6104a4000 */
172 { TARGET_DEV2G5 + 55, 0x104a8000, 1 }, /* 0x6104a8000 */
173 { TARGET_DEV10G + 11, 0x104ac000, 1 }, /* 0x6104ac000 */
174 { TARGET_PCS10G_BR + 11, 0x104b0000, 1 }, /* 0x6104b0000 */
175 { TARGET_DEV2G5 + 56, 0x104b4000, 1 }, /* 0x6104b4000 */
176 { TARGET_DEV25G, 0x104b8000, 1 }, /* 0x6104b8000 */
177 { TARGET_PCS25G_BR, 0x104bc000, 1 }, /* 0x6104bc000 */
178 { TARGET_DEV2G5 + 58, 0x104c4000, 1 }, /* 0x6104c4000 */
179 { TARGET_DEV25G + 2, 0x104c8000, 1 }, /* 0x6104c8000 */
180 { TARGET_PCS25G_BR + 2, 0x104cc000, 1 }, /* 0x6104cc000 */
181 { TARGET_DEV2G5 + 61, 0x104d4000, 1 }, /* 0x6104d4000 */
182 { TARGET_DEV25G + 5, 0x104d8000, 1 }, /* 0x6104d8000 */
183 { TARGET_PCS25G_BR + 5, 0x104dc000, 1 }, /* 0x6104dc000 */
184 { TARGET_DEV2G5 + 62, 0x104e4000, 1 }, /* 0x6104e4000 */
185 { TARGET_DEV25G + 6, 0x104e8000, 1 }, /* 0x6104e8000 */
186 { TARGET_PCS25G_BR + 6, 0x104ec000, 1 }, /* 0x6104ec000 */
187 { TARGET_DEV2G5 + 63, 0x104f4000, 1 }, /* 0x6104f4000 */
188 { TARGET_DEV25G + 7, 0x104f8000, 1 }, /* 0x6104f8000 */
189 { TARGET_PCS25G_BR + 7, 0x104fc000, 1 }, /* 0x6104fc000 */
190 { TARGET_DSM, 0x10504000, 1 }, /* 0x610504000 */
191 { TARGET_ASM, 0x10600000, 1 }, /* 0x610600000 */
192 { TARGET_GCB, 0x11010000, 2 }, /* 0x611010000 */
193 { TARGET_QS, 0x11030000, 2 }, /* 0x611030000 */
194 { TARGET_PTP, 0x11040000, 2 }, /* 0x611040000 */
195 { TARGET_ANA_ACL, 0x11050000, 2 }, /* 0x611050000 */
196 { TARGET_LRN, 0x11060000, 2 }, /* 0x611060000 */
197 { TARGET_VCAP_SUPER, 0x11080000, 2 }, /* 0x611080000 */
198 { TARGET_QSYS, 0x110a0000, 2 }, /* 0x6110a0000 */
199 { TARGET_QFWD, 0x110b0000, 2 }, /* 0x6110b0000 */
200 { TARGET_XQS, 0x110c0000, 2 }, /* 0x6110c0000 */
201 { TARGET_CLKGEN, 0x11100000, 2 }, /* 0x611100000 */
202 { TARGET_ANA_AC_POL, 0x11200000, 2 }, /* 0x611200000 */
203 { TARGET_QRES, 0x11280000, 2 }, /* 0x611280000 */
204 { TARGET_EACL, 0x112c0000, 2 }, /* 0x6112c0000 */
205 { TARGET_ANA_CL, 0x11400000, 2 }, /* 0x611400000 */
206 { TARGET_ANA_L3, 0x11480000, 2 }, /* 0x611480000 */
207 { TARGET_HSCH, 0x11580000, 2 }, /* 0x611580000 */
208 { TARGET_REW, 0x11600000, 2 }, /* 0x611600000 */
209 { TARGET_ANA_L2, 0x11800000, 2 }, /* 0x611800000 */
210 { TARGET_ANA_AC, 0x11900000, 2 }, /* 0x611900000 */
211 { TARGET_VOP, 0x11a00000, 2 }, /* 0x611a00000 */
212};
213
214static int sparx5_create_targets(struct sparx5 *sparx5)
215{
216 struct resource *iores[IO_RANGES];
217 void __iomem *iomem[IO_RANGES];
218 void __iomem *begin[IO_RANGES];
219 int range_id[IO_RANGES];
220 int idx, jdx;
221
222 for (idx = 0, jdx = 0; jdx < ARRAY_SIZE(sparx5_main_iomap); jdx++) {
223 const struct sparx5_main_io_resource *iomap = &sparx5_main_iomap[jdx];
224
225 if (idx == iomap->range) {
226 range_id[idx] = jdx;
227 idx++;
228 }
229 }
230 for (idx = 0; idx < IO_RANGES; idx++) {
231 iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM,
232 idx);
233 if (!iores[idx]) {
234 dev_err(sparx5->dev, "Invalid resource\n");
235 return -EINVAL;
236 }
237 iomem[idx] = devm_ioremap(sparx5->dev,
238 iores[idx]->start,
239 resource_size(iores[idx]));
240 if (!iomem[idx]) {
241 dev_err(sparx5->dev, "Unable to get switch registers: %s\n",
242 iores[idx]->name);
243 return -ENOMEM;
244 }
245 begin[idx] = iomem[idx] - sparx5_main_iomap[range_id[idx]].offset;
246 }
247 for (jdx = 0; jdx < ARRAY_SIZE(sparx5_main_iomap); jdx++) {
248 const struct sparx5_main_io_resource *iomap = &sparx5_main_iomap[jdx];
249
250 sparx5->regs[iomap->id] = begin[iomap->range] + iomap->offset;
251 }
252 return 0;
253}
254
255static int sparx5_create_port(struct sparx5 *sparx5,
256 struct initial_port_config *config)
257{
258 struct sparx5_port *spx5_port;
259 struct net_device *ndev;
260 struct phylink *phylink;
261 int err;
262
263 ndev = sparx5_create_netdev(sparx5, config->portno);
264 if (IS_ERR(ndev)) {
265 dev_err(sparx5->dev, "Could not create net device: %02u\n",
266 config->portno);
267 return PTR_ERR(ndev);
268 }
269 spx5_port = netdev_priv(ndev);
270 spx5_port->of_node = config->node;
271 spx5_port->serdes = config->serdes;
272 spx5_port->pvid = NULL_VID;
273 spx5_port->signd_internal = true;
274 spx5_port->signd_active_high = true;
275 spx5_port->signd_enable = true;
276 spx5_port->max_vlan_tags = SPX5_PORT_MAX_TAGS_NONE;
277 spx5_port->vlan_type = SPX5_VLAN_PORT_TYPE_UNAWARE;
278 spx5_port->custom_etype = 0x8880; /* Vitesse */
279 spx5_port->phylink_pcs.poll = true;
280 spx5_port->phylink_pcs.ops = &sparx5_phylink_pcs_ops;
281 spx5_port->is_mrouter = false;
282 sparx5->ports[config->portno] = spx5_port;
283
284 err = sparx5_port_init(sparx5, spx5_port, &config->conf);
285 if (err) {
286 dev_err(sparx5->dev, "port init failed\n");
287 return err;
288 }
289 spx5_port->conf = config->conf;
290
291 /* Setup VLAN */
292 sparx5_vlan_port_setup(sparx5, spx5_port->portno);
293
294 /* Create a phylink for PHY management. Also handles SFPs */
295 spx5_port->phylink_config.dev = &spx5_port->ndev->dev;
296 spx5_port->phylink_config.type = PHYLINK_NETDEV;
297 spx5_port->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
298 MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD |
299 MAC_2500FD | MAC_5000FD | MAC_10000FD | MAC_25000FD;
300
301 __set_bit(PHY_INTERFACE_MODE_SGMII,
302 spx5_port->phylink_config.supported_interfaces);
303 __set_bit(PHY_INTERFACE_MODE_QSGMII,
304 spx5_port->phylink_config.supported_interfaces);
305 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
306 spx5_port->phylink_config.supported_interfaces);
307 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
308 spx5_port->phylink_config.supported_interfaces);
309
310 if (spx5_port->conf.bandwidth == SPEED_5000 ||
311 spx5_port->conf.bandwidth == SPEED_10000 ||
312 spx5_port->conf.bandwidth == SPEED_25000)
313 __set_bit(PHY_INTERFACE_MODE_5GBASER,
314 spx5_port->phylink_config.supported_interfaces);
315
316 if (spx5_port->conf.bandwidth == SPEED_10000 ||
317 spx5_port->conf.bandwidth == SPEED_25000)
318 __set_bit(PHY_INTERFACE_MODE_10GBASER,
319 spx5_port->phylink_config.supported_interfaces);
320
321 if (spx5_port->conf.bandwidth == SPEED_25000)
322 __set_bit(PHY_INTERFACE_MODE_25GBASER,
323 spx5_port->phylink_config.supported_interfaces);
324
325 phylink = phylink_create(&spx5_port->phylink_config,
326 of_fwnode_handle(config->node),
327 config->conf.phy_mode,
328 &sparx5_phylink_mac_ops);
329 if (IS_ERR(phylink))
330 return PTR_ERR(phylink);
331
332 spx5_port->phylink = phylink;
333
334 return 0;
335}
336
337static int sparx5_init_ram(struct sparx5 *s5)
338{
339 const struct sparx5_ram_config spx5_ram_cfg[] = {
340 {spx5_reg_get(s5, ANA_AC_STAT_RESET), ANA_AC_STAT_RESET_RESET},
341 {spx5_reg_get(s5, ASM_STAT_CFG), ASM_STAT_CFG_STAT_CNT_CLR_SHOT},
342 {spx5_reg_get(s5, QSYS_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
343 {spx5_reg_get(s5, REW_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
344 {spx5_reg_get(s5, VOP_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
345 {spx5_reg_get(s5, ANA_AC_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
346 {spx5_reg_get(s5, ASM_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
347 {spx5_reg_get(s5, EACL_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
348 {spx5_reg_get(s5, VCAP_SUPER_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
349 {spx5_reg_get(s5, DSM_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}
350 };
351 const struct sparx5_ram_config *cfg;
352 u32 value, pending, jdx, idx;
353
354 for (jdx = 0; jdx < 10; jdx++) {
355 pending = ARRAY_SIZE(spx5_ram_cfg);
356 for (idx = 0; idx < ARRAY_SIZE(spx5_ram_cfg); idx++) {
357 cfg = &spx5_ram_cfg[idx];
358 if (jdx == 0) {
359 writel(cfg->init_val, cfg->init_reg);
360 } else {
361 value = readl(cfg->init_reg);
362 if ((value & cfg->init_val) != cfg->init_val)
363 pending--;
364 }
365 }
366 if (!pending)
367 break;
368 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
369 }
370
371 if (pending > 0) {
372 /* Still initializing, should be complete in
373 * less than 1ms
374 */
375 dev_err(s5->dev, "Memory initialization error\n");
376 return -EINVAL;
377 }
378 return 0;
379}
380
381static int sparx5_init_switchcore(struct sparx5 *sparx5)
382{
383 u32 value;
384 int err = 0;
385
386 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(1),
387 EACL_POL_EACL_CFG_EACL_FORCE_INIT,
388 sparx5,
389 EACL_POL_EACL_CFG);
390
391 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(0),
392 EACL_POL_EACL_CFG_EACL_FORCE_INIT,
393 sparx5,
394 EACL_POL_EACL_CFG);
395
396 /* Initialize memories, if not done already */
397 value = spx5_rd(sparx5, HSCH_RESET_CFG);
398 if (!(value & HSCH_RESET_CFG_CORE_ENA)) {
399 err = sparx5_init_ram(sparx5);
400 if (err)
401 return err;
402 }
403
404 /* Reset counters */
405 spx5_wr(ANA_AC_STAT_RESET_RESET_SET(1), sparx5, ANA_AC_STAT_RESET);
406 spx5_wr(ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(1), sparx5, ASM_STAT_CFG);
407
408 /* Enable switch-core and queue system */
409 spx5_wr(HSCH_RESET_CFG_CORE_ENA_SET(1), sparx5, HSCH_RESET_CFG);
410
411 return 0;
412}
413
414static int sparx5_init_coreclock(struct sparx5 *sparx5)
415{
416 enum sparx5_core_clockfreq freq = sparx5->coreclock;
417 u32 clk_div, clk_period, pol_upd_int, idx;
418
419 /* Verify if core clock frequency is supported on target.
420 * If 'VTSS_CORE_CLOCK_DEFAULT' then the highest supported
421 * freq. is used
422 */
423 switch (sparx5->target_ct) {
424 case SPX5_TARGET_CT_7546:
425 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
426 freq = SPX5_CORE_CLOCK_250MHZ;
427 else if (sparx5->coreclock != SPX5_CORE_CLOCK_250MHZ)
428 freq = 0; /* Not supported */
429 break;
430 case SPX5_TARGET_CT_7549:
431 case SPX5_TARGET_CT_7552:
432 case SPX5_TARGET_CT_7556:
433 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
434 freq = SPX5_CORE_CLOCK_500MHZ;
435 else if (sparx5->coreclock != SPX5_CORE_CLOCK_500MHZ)
436 freq = 0; /* Not supported */
437 break;
438 case SPX5_TARGET_CT_7558:
439 case SPX5_TARGET_CT_7558TSN:
440 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
441 freq = SPX5_CORE_CLOCK_625MHZ;
442 else if (sparx5->coreclock != SPX5_CORE_CLOCK_625MHZ)
443 freq = 0; /* Not supported */
444 break;
445 case SPX5_TARGET_CT_7546TSN:
446 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
447 freq = SPX5_CORE_CLOCK_625MHZ;
448 break;
449 case SPX5_TARGET_CT_7549TSN:
450 case SPX5_TARGET_CT_7552TSN:
451 case SPX5_TARGET_CT_7556TSN:
452 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
453 freq = SPX5_CORE_CLOCK_625MHZ;
454 else if (sparx5->coreclock == SPX5_CORE_CLOCK_250MHZ)
455 freq = 0; /* Not supported */
456 break;
457 default:
458 dev_err(sparx5->dev, "Target (%#04x) not supported\n",
459 sparx5->target_ct);
460 return -ENODEV;
461 }
462
463 switch (freq) {
464 case SPX5_CORE_CLOCK_250MHZ:
465 clk_div = 10;
466 pol_upd_int = 312;
467 break;
468 case SPX5_CORE_CLOCK_500MHZ:
469 clk_div = 5;
470 pol_upd_int = 624;
471 break;
472 case SPX5_CORE_CLOCK_625MHZ:
473 clk_div = 4;
474 pol_upd_int = 780;
475 break;
476 default:
477 dev_err(sparx5->dev, "%d coreclock not supported on (%#04x)\n",
478 sparx5->coreclock, sparx5->target_ct);
479 return -EINVAL;
480 }
481
482 /* Update state with chosen frequency */
483 sparx5->coreclock = freq;
484
485 /* Configure the LCPLL */
486 spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) |
487 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(0) |
488 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(0) |
489 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(0) |
490 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(0) |
491 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(1),
492 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV |
493 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV |
494 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR |
495 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL |
496 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA |
497 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA,
498 sparx5,
499 CLKGEN_LCPLL1_CORE_CLK_CFG);
500
501 clk_period = sparx5_clk_period(freq);
502
503 spx5_rmw(HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS_SET(clk_period / 100),
504 HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS,
505 sparx5,
506 HSCH_SYS_CLK_PER);
507
508 spx5_rmw(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100),
509 ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS,
510 sparx5,
511 ANA_AC_POL_BDLB_DLB_CTRL);
512
513 spx5_rmw(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100),
514 ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS,
515 sparx5,
516 ANA_AC_POL_SLB_DLB_CTRL);
517
518 spx5_rmw(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(clk_period / 100),
519 LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS,
520 sparx5,
521 LRN_AUTOAGE_CFG_1);
522
523 for (idx = 0; idx < 3; idx++)
524 spx5_rmw(GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(clk_period / 100),
525 GCB_SIO_CLOCK_SYS_CLK_PERIOD,
526 sparx5,
527 GCB_SIO_CLOCK(idx));
528
529 spx5_rmw(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET
530 ((256 * 1000) / clk_period),
531 HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY,
532 sparx5,
533 HSCH_TAS_STATEMACHINE_CFG);
534
535 spx5_rmw(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(pol_upd_int),
536 ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT,
537 sparx5,
538 ANA_AC_POL_POL_UPD_INT_CFG);
539
540 return 0;
541}
542
543static int sparx5_qlim_set(struct sparx5 *sparx5)
544{
545 u32 res, dp, prio;
546
547 for (res = 0; res < 2; res++) {
548 for (prio = 0; prio < 8; prio++)
549 spx5_wr(0xFFF, sparx5,
550 QRES_RES_CFG(prio + 630 + res * 1024));
551
552 for (dp = 0; dp < 4; dp++)
553 spx5_wr(0xFFF, sparx5,
554 QRES_RES_CFG(dp + 638 + res * 1024));
555 }
556
557 /* Set 80,90,95,100% of memory size for top watermarks */
558 spx5_wr(QLIM_WM(80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0));
559 spx5_wr(QLIM_WM(90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0));
560 spx5_wr(QLIM_WM(95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0));
561 spx5_wr(QLIM_WM(100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0));
562
563 return 0;
564}
565
566/* Some boards needs to map the SGPIO for signal detect explicitly to the
567 * port module
568 */
569static void sparx5_board_init(struct sparx5 *sparx5)
570{
571 int idx;
572
573 if (!sparx5->sd_sgpio_remapping)
574 return;
575
576 /* Enable SGPIO Signal Detect remapping */
577 spx5_rmw(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL,
578 GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL,
579 sparx5,
580 GCB_HW_SGPIO_SD_CFG);
581
582 /* Refer to LOS SGPIO */
583 for (idx = 0; idx < SPX5_PORTS; idx++)
584 if (sparx5->ports[idx])
585 if (sparx5->ports[idx]->conf.sd_sgpio != ~0)
586 spx5_wr(sparx5->ports[idx]->conf.sd_sgpio,
587 sparx5,
588 GCB_HW_SGPIO_TO_SD_MAP_CFG(idx));
589}
590
591static int sparx5_start(struct sparx5 *sparx5)
592{
593 u8 broadcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
594 char queue_name[32];
595 u32 idx;
596 int err;
597
598 /* Setup own UPSIDs */
599 for (idx = 0; idx < 3; idx++) {
600 spx5_wr(idx, sparx5, ANA_AC_OWN_UPSID(idx));
601 spx5_wr(idx, sparx5, ANA_CL_OWN_UPSID(idx));
602 spx5_wr(idx, sparx5, ANA_L2_OWN_UPSID(idx));
603 spx5_wr(idx, sparx5, REW_OWN_UPSID(idx));
604 }
605
606 /* Enable CPU ports */
607 for (idx = SPX5_PORTS; idx < SPX5_PORTS_ALL; idx++)
608 spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1),
609 QFWD_SWITCH_PORT_MODE_PORT_ENA,
610 sparx5,
611 QFWD_SWITCH_PORT_MODE(idx));
612
613 /* Init masks */
614 sparx5_update_fwd(sparx5);
615
616 /* CPU copy CPU pgids */
617 spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1),
618 sparx5, ANA_AC_PGID_MISC_CFG(PGID_CPU));
619 spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1),
620 sparx5, ANA_AC_PGID_MISC_CFG(PGID_BCAST));
621
622 /* Recalc injected frame FCS */
623 for (idx = SPX5_PORT_CPU_0; idx <= SPX5_PORT_CPU_1; idx++)
624 spx5_rmw(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(1),
625 ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA,
626 sparx5, ANA_CL_FILTER_CTRL(idx));
627
628 /* Init MAC table, ageing */
629 sparx5_mact_init(sparx5);
630
631 /* Init PGID table arbitrator */
632 sparx5_pgid_init(sparx5);
633
634 /* Setup VLANs */
635 sparx5_vlan_init(sparx5);
636
637 /* Add host mode BC address (points only to CPU) */
638 sparx5_mact_learn(sparx5, PGID_CPU, broadcast, NULL_VID);
639
640 /* Enable queue limitation watermarks */
641 sparx5_qlim_set(sparx5);
642
643 err = sparx5_config_auto_calendar(sparx5);
644 if (err)
645 return err;
646
647 err = sparx5_config_dsm_calendar(sparx5);
648 if (err)
649 return err;
650
651 /* Init stats */
652 err = sparx_stats_init(sparx5);
653 if (err)
654 return err;
655
656 /* Init mact_sw struct */
657 mutex_init(&sparx5->mact_lock);
658 INIT_LIST_HEAD(&sparx5->mact_entries);
659 snprintf(queue_name, sizeof(queue_name), "%s-mact",
660 dev_name(sparx5->dev));
661 sparx5->mact_queue = create_singlethread_workqueue(queue_name);
662 if (!sparx5->mact_queue)
663 return -ENOMEM;
664
665 INIT_DELAYED_WORK(&sparx5->mact_work, sparx5_mact_pull_work);
666 queue_delayed_work(sparx5->mact_queue, &sparx5->mact_work,
667 SPX5_MACT_PULL_DELAY);
668
669 mutex_init(&sparx5->mdb_lock);
670 INIT_LIST_HEAD(&sparx5->mdb_entries);
671
672 err = sparx5_register_netdevs(sparx5);
673 if (err)
674 return err;
675
676 sparx5_board_init(sparx5);
677 err = sparx5_register_notifier_blocks(sparx5);
678 if (err)
679 return err;
680
681 err = sparx5_vcap_init(sparx5);
682 if (err) {
683 sparx5_unregister_notifier_blocks(sparx5);
684 return err;
685 }
686
687 /* Start Frame DMA with fallback to register based INJ/XTR */
688 err = -ENXIO;
689 if (sparx5->fdma_irq >= 0) {
690 if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0)
691 err = devm_request_threaded_irq(sparx5->dev,
692 sparx5->fdma_irq,
693 NULL,
694 sparx5_fdma_handler,
695 IRQF_ONESHOT,
696 "sparx5-fdma", sparx5);
697 if (!err)
698 err = sparx5_fdma_start(sparx5);
699 if (err)
700 sparx5->fdma_irq = -ENXIO;
701 } else {
702 sparx5->fdma_irq = -ENXIO;
703 }
704 if (err && sparx5->xtr_irq >= 0) {
705 err = devm_request_irq(sparx5->dev, sparx5->xtr_irq,
706 sparx5_xtr_handler, IRQF_SHARED,
707 "sparx5-xtr", sparx5);
708 if (!err)
709 err = sparx5_manual_injection_mode(sparx5);
710 if (err)
711 sparx5->xtr_irq = -ENXIO;
712 } else {
713 sparx5->xtr_irq = -ENXIO;
714 }
715
716 if (sparx5->ptp_irq >= 0) {
717 err = devm_request_threaded_irq(sparx5->dev, sparx5->ptp_irq,
718 NULL, sparx5_ptp_irq_handler,
719 IRQF_ONESHOT, "sparx5-ptp",
720 sparx5);
721 if (err)
722 sparx5->ptp_irq = -ENXIO;
723
724 sparx5->ptp = 1;
725 }
726
727 return err;
728}
729
730static void sparx5_cleanup_ports(struct sparx5 *sparx5)
731{
732 sparx5_unregister_netdevs(sparx5);
733 sparx5_destroy_netdevs(sparx5);
734}
735
736static int mchp_sparx5_probe(struct platform_device *pdev)
737{
738 struct initial_port_config *configs, *config;
739 struct device_node *np = pdev->dev.of_node;
740 struct device_node *ports, *portnp;
741 struct reset_control *reset;
742 struct sparx5 *sparx5;
743 int idx = 0, err = 0;
744
745 if (!np && !pdev->dev.platform_data)
746 return -ENODEV;
747
748 sparx5 = devm_kzalloc(&pdev->dev, sizeof(*sparx5), GFP_KERNEL);
749 if (!sparx5)
750 return -ENOMEM;
751
752 platform_set_drvdata(pdev, sparx5);
753 sparx5->pdev = pdev;
754 sparx5->dev = &pdev->dev;
755
756 /* Do switch core reset if available */
757 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch");
758 if (IS_ERR(reset))
759 return dev_err_probe(&pdev->dev, PTR_ERR(reset),
760 "Failed to get switch reset controller.\n");
761 reset_control_reset(reset);
762
763 /* Default values, some from DT */
764 sparx5->coreclock = SPX5_CORE_CLOCK_DEFAULT;
765
766 sparx5->debugfs_root = debugfs_create_dir("sparx5", NULL);
767
768 ports = of_get_child_by_name(np, "ethernet-ports");
769 if (!ports) {
770 dev_err(sparx5->dev, "no ethernet-ports child node found\n");
771 return -ENODEV;
772 }
773 sparx5->port_count = of_get_child_count(ports);
774
775 configs = kcalloc(sparx5->port_count,
776 sizeof(struct initial_port_config), GFP_KERNEL);
777 if (!configs) {
778 err = -ENOMEM;
779 goto cleanup_pnode;
780 }
781
782 for_each_available_child_of_node(ports, portnp) {
783 struct sparx5_port_config *conf;
784 struct phy *serdes;
785 u32 portno;
786
787 err = of_property_read_u32(portnp, "reg", &portno);
788 if (err) {
789 dev_err(sparx5->dev, "port reg property error\n");
790 continue;
791 }
792 config = &configs[idx];
793 conf = &config->conf;
794 conf->speed = SPEED_UNKNOWN;
795 conf->bandwidth = SPEED_UNKNOWN;
796 err = of_get_phy_mode(portnp, &conf->phy_mode);
797 if (err) {
798 dev_err(sparx5->dev, "port %u: missing phy-mode\n",
799 portno);
800 continue;
801 }
802 err = of_property_read_u32(portnp, "microchip,bandwidth",
803 &conf->bandwidth);
804 if (err) {
805 dev_err(sparx5->dev, "port %u: missing bandwidth\n",
806 portno);
807 continue;
808 }
809 err = of_property_read_u32(portnp, "microchip,sd-sgpio", &conf->sd_sgpio);
810 if (err)
811 conf->sd_sgpio = ~0;
812 else
813 sparx5->sd_sgpio_remapping = true;
814 serdes = devm_of_phy_get(sparx5->dev, portnp, NULL);
815 if (IS_ERR(serdes)) {
816 err = dev_err_probe(sparx5->dev, PTR_ERR(serdes),
817 "port %u: missing serdes\n",
818 portno);
819 of_node_put(portnp);
820 goto cleanup_config;
821 }
822 config->portno = portno;
823 config->node = portnp;
824 config->serdes = serdes;
825
826 conf->media = PHY_MEDIA_DAC;
827 conf->serdes_reset = true;
828 conf->portmode = conf->phy_mode;
829 conf->power_down = true;
830 idx++;
831 }
832
833 err = sparx5_create_targets(sparx5);
834 if (err)
835 goto cleanup_config;
836
837 if (of_get_mac_address(np, sparx5->base_mac)) {
838 dev_info(sparx5->dev, "MAC addr was not set, use random MAC\n");
839 eth_random_addr(sparx5->base_mac);
840 sparx5->base_mac[5] = 0;
841 }
842
843 sparx5->fdma_irq = platform_get_irq_byname(sparx5->pdev, "fdma");
844 sparx5->xtr_irq = platform_get_irq_byname(sparx5->pdev, "xtr");
845 sparx5->ptp_irq = platform_get_irq_byname(sparx5->pdev, "ptp");
846
847 /* Read chip ID to check CPU interface */
848 sparx5->chip_id = spx5_rd(sparx5, GCB_CHIP_ID);
849
850 sparx5->target_ct = (enum spx5_target_chiptype)
851 GCB_CHIP_ID_PART_ID_GET(sparx5->chip_id);
852
853 /* Initialize Switchcore and internal RAMs */
854 err = sparx5_init_switchcore(sparx5);
855 if (err) {
856 dev_err(sparx5->dev, "Switchcore initialization error\n");
857 goto cleanup_config;
858 }
859
860 /* Initialize the LC-PLL (core clock) and set affected registers */
861 err = sparx5_init_coreclock(sparx5);
862 if (err) {
863 dev_err(sparx5->dev, "LC-PLL initialization error\n");
864 goto cleanup_config;
865 }
866
867 for (idx = 0; idx < sparx5->port_count; ++idx) {
868 config = &configs[idx];
869 if (!config->node)
870 continue;
871
872 err = sparx5_create_port(sparx5, config);
873 if (err) {
874 dev_err(sparx5->dev, "port create error\n");
875 goto cleanup_ports;
876 }
877 }
878
879 err = sparx5_start(sparx5);
880 if (err) {
881 dev_err(sparx5->dev, "Start failed\n");
882 goto cleanup_ports;
883 }
884
885 err = sparx5_qos_init(sparx5);
886 if (err) {
887 dev_err(sparx5->dev, "Failed to initialize QoS\n");
888 goto cleanup_ports;
889 }
890
891 err = sparx5_ptp_init(sparx5);
892 if (err) {
893 dev_err(sparx5->dev, "PTP failed\n");
894 goto cleanup_ports;
895 }
896 goto cleanup_config;
897
898cleanup_ports:
899 sparx5_cleanup_ports(sparx5);
900 if (sparx5->mact_queue)
901 destroy_workqueue(sparx5->mact_queue);
902cleanup_config:
903 kfree(configs);
904cleanup_pnode:
905 of_node_put(ports);
906 return err;
907}
908
909static int mchp_sparx5_remove(struct platform_device *pdev)
910{
911 struct sparx5 *sparx5 = platform_get_drvdata(pdev);
912
913 debugfs_remove_recursive(sparx5->debugfs_root);
914 if (sparx5->xtr_irq) {
915 disable_irq(sparx5->xtr_irq);
916 sparx5->xtr_irq = -ENXIO;
917 }
918 if (sparx5->fdma_irq) {
919 disable_irq(sparx5->fdma_irq);
920 sparx5->fdma_irq = -ENXIO;
921 }
922 sparx5_ptp_deinit(sparx5);
923 sparx5_fdma_stop(sparx5);
924 sparx5_cleanup_ports(sparx5);
925 sparx5_vcap_destroy(sparx5);
926 /* Unregister netdevs */
927 sparx5_unregister_notifier_blocks(sparx5);
928 destroy_workqueue(sparx5->mact_queue);
929
930 return 0;
931}
932
933static const struct of_device_id mchp_sparx5_match[] = {
934 { .compatible = "microchip,sparx5-switch" },
935 { }
936};
937MODULE_DEVICE_TABLE(of, mchp_sparx5_match);
938
939static struct platform_driver mchp_sparx5_driver = {
940 .probe = mchp_sparx5_probe,
941 .remove = mchp_sparx5_remove,
942 .driver = {
943 .name = "sparx5-switch",
944 .of_match_table = mchp_sparx5_match,
945 },
946};
947
948module_platform_driver(mchp_sparx5_driver);
949
950MODULE_DESCRIPTION("Microchip Sparx5 switch driver");
951MODULE_AUTHOR("Steen Hegelund <steen.hegelund@microchip.com>");
952MODULE_LICENSE("Dual MIT/GPL");