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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (C) 2021, Intel Corporation. */
3
4#include "ice.h"
5#include "ice_lib.h"
6#include "ice_trace.h"
7
8#define E810_OUT_PROP_DELAY_NS 1
9
10#define UNKNOWN_INCVAL_E82X 0x100000000ULL
11
12static const struct ptp_pin_desc ice_pin_desc_e810t[] = {
13 /* name idx func chan */
14 { "GNSS", GNSS, PTP_PF_EXTTS, 0, { 0, } },
15 { "SMA1", SMA1, PTP_PF_NONE, 1, { 0, } },
16 { "U.FL1", UFL1, PTP_PF_NONE, 1, { 0, } },
17 { "SMA2", SMA2, PTP_PF_NONE, 2, { 0, } },
18 { "U.FL2", UFL2, PTP_PF_NONE, 2, { 0, } },
19};
20
21/**
22 * ice_get_sma_config_e810t
23 * @hw: pointer to the hw struct
24 * @ptp_pins: pointer to the ptp_pin_desc struture
25 *
26 * Read the configuration of the SMA control logic and put it into the
27 * ptp_pin_desc structure
28 */
29static int
30ice_get_sma_config_e810t(struct ice_hw *hw, struct ptp_pin_desc *ptp_pins)
31{
32 u8 data, i;
33 int status;
34
35 /* Read initial pin state */
36 status = ice_read_sma_ctrl_e810t(hw, &data);
37 if (status)
38 return status;
39
40 /* initialize with defaults */
41 for (i = 0; i < NUM_PTP_PINS_E810T; i++) {
42 strscpy(ptp_pins[i].name, ice_pin_desc_e810t[i].name,
43 sizeof(ptp_pins[i].name));
44 ptp_pins[i].index = ice_pin_desc_e810t[i].index;
45 ptp_pins[i].func = ice_pin_desc_e810t[i].func;
46 ptp_pins[i].chan = ice_pin_desc_e810t[i].chan;
47 }
48
49 /* Parse SMA1/UFL1 */
50 switch (data & ICE_SMA1_MASK_E810T) {
51 case ICE_SMA1_MASK_E810T:
52 default:
53 ptp_pins[SMA1].func = PTP_PF_NONE;
54 ptp_pins[UFL1].func = PTP_PF_NONE;
55 break;
56 case ICE_SMA1_DIR_EN_E810T:
57 ptp_pins[SMA1].func = PTP_PF_PEROUT;
58 ptp_pins[UFL1].func = PTP_PF_NONE;
59 break;
60 case ICE_SMA1_TX_EN_E810T:
61 ptp_pins[SMA1].func = PTP_PF_EXTTS;
62 ptp_pins[UFL1].func = PTP_PF_NONE;
63 break;
64 case 0:
65 ptp_pins[SMA1].func = PTP_PF_EXTTS;
66 ptp_pins[UFL1].func = PTP_PF_PEROUT;
67 break;
68 }
69
70 /* Parse SMA2/UFL2 */
71 switch (data & ICE_SMA2_MASK_E810T) {
72 case ICE_SMA2_MASK_E810T:
73 default:
74 ptp_pins[SMA2].func = PTP_PF_NONE;
75 ptp_pins[UFL2].func = PTP_PF_NONE;
76 break;
77 case (ICE_SMA2_TX_EN_E810T | ICE_SMA2_UFL2_RX_DIS_E810T):
78 ptp_pins[SMA2].func = PTP_PF_EXTTS;
79 ptp_pins[UFL2].func = PTP_PF_NONE;
80 break;
81 case (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_UFL2_RX_DIS_E810T):
82 ptp_pins[SMA2].func = PTP_PF_PEROUT;
83 ptp_pins[UFL2].func = PTP_PF_NONE;
84 break;
85 case (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_TX_EN_E810T):
86 ptp_pins[SMA2].func = PTP_PF_NONE;
87 ptp_pins[UFL2].func = PTP_PF_EXTTS;
88 break;
89 case ICE_SMA2_DIR_EN_E810T:
90 ptp_pins[SMA2].func = PTP_PF_PEROUT;
91 ptp_pins[UFL2].func = PTP_PF_EXTTS;
92 break;
93 }
94
95 return 0;
96}
97
98/**
99 * ice_ptp_set_sma_config_e810t
100 * @hw: pointer to the hw struct
101 * @ptp_pins: pointer to the ptp_pin_desc struture
102 *
103 * Set the configuration of the SMA control logic based on the configuration in
104 * num_pins parameter
105 */
106static int
107ice_ptp_set_sma_config_e810t(struct ice_hw *hw,
108 const struct ptp_pin_desc *ptp_pins)
109{
110 int status;
111 u8 data;
112
113 /* SMA1 and UFL1 cannot be set to TX at the same time */
114 if (ptp_pins[SMA1].func == PTP_PF_PEROUT &&
115 ptp_pins[UFL1].func == PTP_PF_PEROUT)
116 return -EINVAL;
117
118 /* SMA2 and UFL2 cannot be set to RX at the same time */
119 if (ptp_pins[SMA2].func == PTP_PF_EXTTS &&
120 ptp_pins[UFL2].func == PTP_PF_EXTTS)
121 return -EINVAL;
122
123 /* Read initial pin state value */
124 status = ice_read_sma_ctrl_e810t(hw, &data);
125 if (status)
126 return status;
127
128 /* Set the right sate based on the desired configuration */
129 data &= ~ICE_SMA1_MASK_E810T;
130 if (ptp_pins[SMA1].func == PTP_PF_NONE &&
131 ptp_pins[UFL1].func == PTP_PF_NONE) {
132 dev_info(ice_hw_to_dev(hw), "SMA1 + U.FL1 disabled");
133 data |= ICE_SMA1_MASK_E810T;
134 } else if (ptp_pins[SMA1].func == PTP_PF_EXTTS &&
135 ptp_pins[UFL1].func == PTP_PF_NONE) {
136 dev_info(ice_hw_to_dev(hw), "SMA1 RX");
137 data |= ICE_SMA1_TX_EN_E810T;
138 } else if (ptp_pins[SMA1].func == PTP_PF_NONE &&
139 ptp_pins[UFL1].func == PTP_PF_PEROUT) {
140 /* U.FL 1 TX will always enable SMA 1 RX */
141 dev_info(ice_hw_to_dev(hw), "SMA1 RX + U.FL1 TX");
142 } else if (ptp_pins[SMA1].func == PTP_PF_EXTTS &&
143 ptp_pins[UFL1].func == PTP_PF_PEROUT) {
144 dev_info(ice_hw_to_dev(hw), "SMA1 RX + U.FL1 TX");
145 } else if (ptp_pins[SMA1].func == PTP_PF_PEROUT &&
146 ptp_pins[UFL1].func == PTP_PF_NONE) {
147 dev_info(ice_hw_to_dev(hw), "SMA1 TX");
148 data |= ICE_SMA1_DIR_EN_E810T;
149 }
150
151 data &= ~ICE_SMA2_MASK_E810T;
152 if (ptp_pins[SMA2].func == PTP_PF_NONE &&
153 ptp_pins[UFL2].func == PTP_PF_NONE) {
154 dev_info(ice_hw_to_dev(hw), "SMA2 + U.FL2 disabled");
155 data |= ICE_SMA2_MASK_E810T;
156 } else if (ptp_pins[SMA2].func == PTP_PF_EXTTS &&
157 ptp_pins[UFL2].func == PTP_PF_NONE) {
158 dev_info(ice_hw_to_dev(hw), "SMA2 RX");
159 data |= (ICE_SMA2_TX_EN_E810T |
160 ICE_SMA2_UFL2_RX_DIS_E810T);
161 } else if (ptp_pins[SMA2].func == PTP_PF_NONE &&
162 ptp_pins[UFL2].func == PTP_PF_EXTTS) {
163 dev_info(ice_hw_to_dev(hw), "UFL2 RX");
164 data |= (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_TX_EN_E810T);
165 } else if (ptp_pins[SMA2].func == PTP_PF_PEROUT &&
166 ptp_pins[UFL2].func == PTP_PF_NONE) {
167 dev_info(ice_hw_to_dev(hw), "SMA2 TX");
168 data |= (ICE_SMA2_DIR_EN_E810T |
169 ICE_SMA2_UFL2_RX_DIS_E810T);
170 } else if (ptp_pins[SMA2].func == PTP_PF_PEROUT &&
171 ptp_pins[UFL2].func == PTP_PF_EXTTS) {
172 dev_info(ice_hw_to_dev(hw), "SMA2 TX + U.FL2 RX");
173 data |= ICE_SMA2_DIR_EN_E810T;
174 }
175
176 return ice_write_sma_ctrl_e810t(hw, data);
177}
178
179/**
180 * ice_ptp_set_sma_e810t
181 * @info: the driver's PTP info structure
182 * @pin: pin index in kernel structure
183 * @func: Pin function to be set (PTP_PF_NONE, PTP_PF_EXTTS or PTP_PF_PEROUT)
184 *
185 * Set the configuration of a single SMA pin
186 */
187static int
188ice_ptp_set_sma_e810t(struct ptp_clock_info *info, unsigned int pin,
189 enum ptp_pin_function func)
190{
191 struct ptp_pin_desc ptp_pins[NUM_PTP_PINS_E810T];
192 struct ice_pf *pf = ptp_info_to_pf(info);
193 struct ice_hw *hw = &pf->hw;
194 int err;
195
196 if (pin < SMA1 || func > PTP_PF_PEROUT)
197 return -EOPNOTSUPP;
198
199 err = ice_get_sma_config_e810t(hw, ptp_pins);
200 if (err)
201 return err;
202
203 /* Disable the same function on the other pin sharing the channel */
204 if (pin == SMA1 && ptp_pins[UFL1].func == func)
205 ptp_pins[UFL1].func = PTP_PF_NONE;
206 if (pin == UFL1 && ptp_pins[SMA1].func == func)
207 ptp_pins[SMA1].func = PTP_PF_NONE;
208
209 if (pin == SMA2 && ptp_pins[UFL2].func == func)
210 ptp_pins[UFL2].func = PTP_PF_NONE;
211 if (pin == UFL2 && ptp_pins[SMA2].func == func)
212 ptp_pins[SMA2].func = PTP_PF_NONE;
213
214 /* Set up new pin function in the temp table */
215 ptp_pins[pin].func = func;
216
217 return ice_ptp_set_sma_config_e810t(hw, ptp_pins);
218}
219
220/**
221 * ice_verify_pin_e810t
222 * @info: the driver's PTP info structure
223 * @pin: Pin index
224 * @func: Assigned function
225 * @chan: Assigned channel
226 *
227 * Verify if pin supports requested pin function. If the Check pins consistency.
228 * Reconfigure the SMA logic attached to the given pin to enable its
229 * desired functionality
230 */
231static int
232ice_verify_pin_e810t(struct ptp_clock_info *info, unsigned int pin,
233 enum ptp_pin_function func, unsigned int chan)
234{
235 /* Don't allow channel reassignment */
236 if (chan != ice_pin_desc_e810t[pin].chan)
237 return -EOPNOTSUPP;
238
239 /* Check if functions are properly assigned */
240 switch (func) {
241 case PTP_PF_NONE:
242 break;
243 case PTP_PF_EXTTS:
244 if (pin == UFL1)
245 return -EOPNOTSUPP;
246 break;
247 case PTP_PF_PEROUT:
248 if (pin == UFL2 || pin == GNSS)
249 return -EOPNOTSUPP;
250 break;
251 case PTP_PF_PHYSYNC:
252 return -EOPNOTSUPP;
253 }
254
255 return ice_ptp_set_sma_e810t(info, pin, func);
256}
257
258/**
259 * ice_ptp_cfg_tx_interrupt - Configure Tx timestamp interrupt for the device
260 * @pf: Board private structure
261 *
262 * Program the device to respond appropriately to the Tx timestamp interrupt
263 * cause.
264 */
265static void ice_ptp_cfg_tx_interrupt(struct ice_pf *pf)
266{
267 struct ice_hw *hw = &pf->hw;
268 bool enable;
269 u32 val;
270
271 switch (pf->ptp.tx_interrupt_mode) {
272 case ICE_PTP_TX_INTERRUPT_ALL:
273 /* React to interrupts across all quads. */
274 wr32(hw, PFINT_TSYN_MSK + (0x4 * hw->pf_id), (u32)0x1f);
275 enable = true;
276 break;
277 case ICE_PTP_TX_INTERRUPT_NONE:
278 /* Do not react to interrupts on any quad. */
279 wr32(hw, PFINT_TSYN_MSK + (0x4 * hw->pf_id), (u32)0x0);
280 enable = false;
281 break;
282 case ICE_PTP_TX_INTERRUPT_SELF:
283 default:
284 enable = pf->ptp.tstamp_config.tx_type == HWTSTAMP_TX_ON;
285 break;
286 }
287
288 /* Configure the Tx timestamp interrupt */
289 val = rd32(hw, PFINT_OICR_ENA);
290 if (enable)
291 val |= PFINT_OICR_TSYN_TX_M;
292 else
293 val &= ~PFINT_OICR_TSYN_TX_M;
294 wr32(hw, PFINT_OICR_ENA, val);
295}
296
297/**
298 * ice_set_rx_tstamp - Enable or disable Rx timestamping
299 * @pf: The PF pointer to search in
300 * @on: bool value for whether timestamps are enabled or disabled
301 */
302static void ice_set_rx_tstamp(struct ice_pf *pf, bool on)
303{
304 struct ice_vsi *vsi;
305 u16 i;
306
307 vsi = ice_get_main_vsi(pf);
308 if (!vsi || !vsi->rx_rings)
309 return;
310
311 /* Set the timestamp flag for all the Rx rings */
312 ice_for_each_rxq(vsi, i) {
313 if (!vsi->rx_rings[i])
314 continue;
315 vsi->rx_rings[i]->ptp_rx = on;
316 }
317}
318
319/**
320 * ice_ptp_disable_timestamp_mode - Disable current timestamp mode
321 * @pf: Board private structure
322 *
323 * Called during preparation for reset to temporarily disable timestamping on
324 * the device. Called during remove to disable timestamping while cleaning up
325 * driver resources.
326 */
327static void ice_ptp_disable_timestamp_mode(struct ice_pf *pf)
328{
329 struct ice_hw *hw = &pf->hw;
330 u32 val;
331
332 val = rd32(hw, PFINT_OICR_ENA);
333 val &= ~PFINT_OICR_TSYN_TX_M;
334 wr32(hw, PFINT_OICR_ENA, val);
335
336 ice_set_rx_tstamp(pf, false);
337}
338
339/**
340 * ice_ptp_restore_timestamp_mode - Restore timestamp configuration
341 * @pf: Board private structure
342 *
343 * Called at the end of rebuild to restore timestamp configuration after
344 * a device reset.
345 */
346void ice_ptp_restore_timestamp_mode(struct ice_pf *pf)
347{
348 struct ice_hw *hw = &pf->hw;
349 bool enable_rx;
350
351 ice_ptp_cfg_tx_interrupt(pf);
352
353 enable_rx = pf->ptp.tstamp_config.rx_filter == HWTSTAMP_FILTER_ALL;
354 ice_set_rx_tstamp(pf, enable_rx);
355
356 /* Trigger an immediate software interrupt to ensure that timestamps
357 * which occurred during reset are handled now.
358 */
359 wr32(hw, PFINT_OICR, PFINT_OICR_TSYN_TX_M);
360 ice_flush(hw);
361}
362
363/**
364 * ice_ptp_read_src_clk_reg - Read the source clock register
365 * @pf: Board private structure
366 * @sts: Optional parameter for holding a pair of system timestamps from
367 * the system clock. Will be ignored if NULL is given.
368 */
369static u64
370ice_ptp_read_src_clk_reg(struct ice_pf *pf, struct ptp_system_timestamp *sts)
371{
372 struct ice_hw *hw = &pf->hw;
373 u32 hi, lo, lo2;
374 u8 tmr_idx;
375
376 tmr_idx = ice_get_ptp_src_clock_index(hw);
377 /* Read the system timestamp pre PHC read */
378 ptp_read_system_prets(sts);
379
380 lo = rd32(hw, GLTSYN_TIME_L(tmr_idx));
381
382 /* Read the system timestamp post PHC read */
383 ptp_read_system_postts(sts);
384
385 hi = rd32(hw, GLTSYN_TIME_H(tmr_idx));
386 lo2 = rd32(hw, GLTSYN_TIME_L(tmr_idx));
387
388 if (lo2 < lo) {
389 /* if TIME_L rolled over read TIME_L again and update
390 * system timestamps
391 */
392 ptp_read_system_prets(sts);
393 lo = rd32(hw, GLTSYN_TIME_L(tmr_idx));
394 ptp_read_system_postts(sts);
395 hi = rd32(hw, GLTSYN_TIME_H(tmr_idx));
396 }
397
398 return ((u64)hi << 32) | lo;
399}
400
401/**
402 * ice_ptp_extend_32b_ts - Convert a 32b nanoseconds timestamp to 64b
403 * @cached_phc_time: recently cached copy of PHC time
404 * @in_tstamp: Ingress/egress 32b nanoseconds timestamp value
405 *
406 * Hardware captures timestamps which contain only 32 bits of nominal
407 * nanoseconds, as opposed to the 64bit timestamps that the stack expects.
408 * Note that the captured timestamp values may be 40 bits, but the lower
409 * 8 bits are sub-nanoseconds and generally discarded.
410 *
411 * Extend the 32bit nanosecond timestamp using the following algorithm and
412 * assumptions:
413 *
414 * 1) have a recently cached copy of the PHC time
415 * 2) assume that the in_tstamp was captured 2^31 nanoseconds (~2.1
416 * seconds) before or after the PHC time was captured.
417 * 3) calculate the delta between the cached time and the timestamp
418 * 4) if the delta is smaller than 2^31 nanoseconds, then the timestamp was
419 * captured after the PHC time. In this case, the full timestamp is just
420 * the cached PHC time plus the delta.
421 * 5) otherwise, if the delta is larger than 2^31 nanoseconds, then the
422 * timestamp was captured *before* the PHC time, i.e. because the PHC
423 * cache was updated after the timestamp was captured by hardware. In this
424 * case, the full timestamp is the cached time minus the inverse delta.
425 *
426 * This algorithm works even if the PHC time was updated after a Tx timestamp
427 * was requested, but before the Tx timestamp event was reported from
428 * hardware.
429 *
430 * This calculation primarily relies on keeping the cached PHC time up to
431 * date. If the timestamp was captured more than 2^31 nanoseconds after the
432 * PHC time, it is possible that the lower 32bits of PHC time have
433 * overflowed more than once, and we might generate an incorrect timestamp.
434 *
435 * This is prevented by (a) periodically updating the cached PHC time once
436 * a second, and (b) discarding any Tx timestamp packet if it has waited for
437 * a timestamp for more than one second.
438 */
439static u64 ice_ptp_extend_32b_ts(u64 cached_phc_time, u32 in_tstamp)
440{
441 u32 delta, phc_time_lo;
442 u64 ns;
443
444 /* Extract the lower 32 bits of the PHC time */
445 phc_time_lo = (u32)cached_phc_time;
446
447 /* Calculate the delta between the lower 32bits of the cached PHC
448 * time and the in_tstamp value
449 */
450 delta = (in_tstamp - phc_time_lo);
451
452 /* Do not assume that the in_tstamp is always more recent than the
453 * cached PHC time. If the delta is large, it indicates that the
454 * in_tstamp was taken in the past, and should be converted
455 * forward.
456 */
457 if (delta > (U32_MAX / 2)) {
458 /* reverse the delta calculation here */
459 delta = (phc_time_lo - in_tstamp);
460 ns = cached_phc_time - delta;
461 } else {
462 ns = cached_phc_time + delta;
463 }
464
465 return ns;
466}
467
468/**
469 * ice_ptp_extend_40b_ts - Convert a 40b timestamp to 64b nanoseconds
470 * @pf: Board private structure
471 * @in_tstamp: Ingress/egress 40b timestamp value
472 *
473 * The Tx and Rx timestamps are 40 bits wide, including 32 bits of nominal
474 * nanoseconds, 7 bits of sub-nanoseconds, and a valid bit.
475 *
476 * *--------------------------------------------------------------*
477 * | 32 bits of nanoseconds | 7 high bits of sub ns underflow | v |
478 * *--------------------------------------------------------------*
479 *
480 * The low bit is an indicator of whether the timestamp is valid. The next
481 * 7 bits are a capture of the upper 7 bits of the sub-nanosecond underflow,
482 * and the remaining 32 bits are the lower 32 bits of the PHC timer.
483 *
484 * It is assumed that the caller verifies the timestamp is valid prior to
485 * calling this function.
486 *
487 * Extract the 32bit nominal nanoseconds and extend them. Use the cached PHC
488 * time stored in the device private PTP structure as the basis for timestamp
489 * extension.
490 *
491 * See ice_ptp_extend_32b_ts for a detailed explanation of the extension
492 * algorithm.
493 */
494static u64 ice_ptp_extend_40b_ts(struct ice_pf *pf, u64 in_tstamp)
495{
496 const u64 mask = GENMASK_ULL(31, 0);
497 unsigned long discard_time;
498
499 /* Discard the hardware timestamp if the cached PHC time is too old */
500 discard_time = pf->ptp.cached_phc_jiffies + msecs_to_jiffies(2000);
501 if (time_is_before_jiffies(discard_time)) {
502 pf->ptp.tx_hwtstamp_discarded++;
503 return 0;
504 }
505
506 return ice_ptp_extend_32b_ts(pf->ptp.cached_phc_time,
507 (in_tstamp >> 8) & mask);
508}
509
510/**
511 * ice_ptp_is_tx_tracker_up - Check if Tx tracker is ready for new timestamps
512 * @tx: the PTP Tx timestamp tracker to check
513 *
514 * Check that a given PTP Tx timestamp tracker is up, i.e. that it is ready
515 * to accept new timestamp requests.
516 *
517 * Assumes the tx->lock spinlock is already held.
518 */
519static bool
520ice_ptp_is_tx_tracker_up(struct ice_ptp_tx *tx)
521{
522 lockdep_assert_held(&tx->lock);
523
524 return tx->init && !tx->calibrating;
525}
526
527/**
528 * ice_ptp_req_tx_single_tstamp - Request Tx timestamp for a port from FW
529 * @tx: the PTP Tx timestamp tracker
530 * @idx: index of the timestamp to request
531 */
532void ice_ptp_req_tx_single_tstamp(struct ice_ptp_tx *tx, u8 idx)
533{
534 struct ice_ptp_port *ptp_port;
535 struct sk_buff *skb;
536 struct ice_pf *pf;
537
538 if (!tx->init)
539 return;
540
541 ptp_port = container_of(tx, struct ice_ptp_port, tx);
542 pf = ptp_port_to_pf(ptp_port);
543
544 /* Drop packets which have waited for more than 2 seconds */
545 if (time_is_before_jiffies(tx->tstamps[idx].start + 2 * HZ)) {
546 /* Count the number of Tx timestamps that timed out */
547 pf->ptp.tx_hwtstamp_timeouts++;
548
549 skb = tx->tstamps[idx].skb;
550 tx->tstamps[idx].skb = NULL;
551 clear_bit(idx, tx->in_use);
552
553 dev_kfree_skb_any(skb);
554 return;
555 }
556
557 ice_trace(tx_tstamp_fw_req, tx->tstamps[idx].skb, idx);
558
559 /* Write TS index to read to the PF register so the FW can read it */
560 wr32(&pf->hw, PF_SB_ATQBAL,
561 TS_LL_READ_TS_INTR | FIELD_PREP(TS_LL_READ_TS_IDX, idx) |
562 TS_LL_READ_TS);
563 tx->last_ll_ts_idx_read = idx;
564}
565
566/**
567 * ice_ptp_complete_tx_single_tstamp - Complete Tx timestamp for a port
568 * @tx: the PTP Tx timestamp tracker
569 */
570void ice_ptp_complete_tx_single_tstamp(struct ice_ptp_tx *tx)
571{
572 struct skb_shared_hwtstamps shhwtstamps = {};
573 u8 idx = tx->last_ll_ts_idx_read;
574 struct ice_ptp_port *ptp_port;
575 u64 raw_tstamp, tstamp;
576 bool drop_ts = false;
577 struct sk_buff *skb;
578 struct ice_pf *pf;
579 u32 val;
580
581 if (!tx->init || tx->last_ll_ts_idx_read < 0)
582 return;
583
584 ptp_port = container_of(tx, struct ice_ptp_port, tx);
585 pf = ptp_port_to_pf(ptp_port);
586
587 ice_trace(tx_tstamp_fw_done, tx->tstamps[idx].skb, idx);
588
589 val = rd32(&pf->hw, PF_SB_ATQBAL);
590
591 /* When the bit is cleared, the TS is ready in the register */
592 if (val & TS_LL_READ_TS) {
593 dev_err(ice_pf_to_dev(pf), "Failed to get the Tx tstamp - FW not ready");
594 return;
595 }
596
597 /* High 8 bit value of the TS is on the bits 16:23 */
598 raw_tstamp = FIELD_GET(TS_LL_READ_TS_HIGH, val);
599 raw_tstamp <<= 32;
600
601 /* Read the low 32 bit value */
602 raw_tstamp |= (u64)rd32(&pf->hw, PF_SB_ATQBAH);
603
604 /* For PHYs which don't implement a proper timestamp ready bitmap,
605 * verify that the timestamp value is different from the last cached
606 * timestamp. If it is not, skip this for now assuming it hasn't yet
607 * been captured by hardware.
608 */
609 if (!drop_ts && tx->verify_cached &&
610 raw_tstamp == tx->tstamps[idx].cached_tstamp)
611 return;
612
613 if (tx->verify_cached && raw_tstamp)
614 tx->tstamps[idx].cached_tstamp = raw_tstamp;
615 clear_bit(idx, tx->in_use);
616 skb = tx->tstamps[idx].skb;
617 tx->tstamps[idx].skb = NULL;
618 if (test_and_clear_bit(idx, tx->stale))
619 drop_ts = true;
620
621 if (!skb)
622 return;
623
624 if (drop_ts) {
625 dev_kfree_skb_any(skb);
626 return;
627 }
628
629 /* Extend the timestamp using cached PHC time */
630 tstamp = ice_ptp_extend_40b_ts(pf, raw_tstamp);
631 if (tstamp) {
632 shhwtstamps.hwtstamp = ns_to_ktime(tstamp);
633 ice_trace(tx_tstamp_complete, skb, idx);
634 }
635
636 skb_tstamp_tx(skb, &shhwtstamps);
637 dev_kfree_skb_any(skb);
638}
639
640/**
641 * ice_ptp_process_tx_tstamp - Process Tx timestamps for a port
642 * @tx: the PTP Tx timestamp tracker
643 *
644 * Process timestamps captured by the PHY associated with this port. To do
645 * this, loop over each index with a waiting skb.
646 *
647 * If a given index has a valid timestamp, perform the following steps:
648 *
649 * 1) check that the timestamp request is not stale
650 * 2) check that a timestamp is ready and available in the PHY memory bank
651 * 3) read and copy the timestamp out of the PHY register
652 * 4) unlock the index by clearing the associated in_use bit
653 * 5) check if the timestamp is stale, and discard if so
654 * 6) extend the 40 bit timestamp value to get a 64 bit timestamp value
655 * 7) send this 64 bit timestamp to the stack
656 *
657 * Note that we do not hold the tracking lock while reading the Tx timestamp.
658 * This is because reading the timestamp requires taking a mutex that might
659 * sleep.
660 *
661 * The only place where we set in_use is when a new timestamp is initiated
662 * with a slot index. This is only called in the hard xmit routine where an
663 * SKB has a request flag set. The only places where we clear this bit is this
664 * function, or during teardown when the Tx timestamp tracker is being
665 * removed. A timestamp index will never be re-used until the in_use bit for
666 * that index is cleared.
667 *
668 * If a Tx thread starts a new timestamp, we might not begin processing it
669 * right away but we will notice it at the end when we re-queue the task.
670 *
671 * If a Tx thread starts a new timestamp just after this function exits, the
672 * interrupt for that timestamp should re-trigger this function once
673 * a timestamp is ready.
674 *
675 * In cases where the PTP hardware clock was directly adjusted, some
676 * timestamps may not be able to safely use the timestamp extension math. In
677 * this case, software will set the stale bit for any outstanding Tx
678 * timestamps when the clock is adjusted. Then this function will discard
679 * those captured timestamps instead of sending them to the stack.
680 *
681 * If a Tx packet has been waiting for more than 2 seconds, it is not possible
682 * to correctly extend the timestamp using the cached PHC time. It is
683 * extremely unlikely that a packet will ever take this long to timestamp. If
684 * we detect a Tx timestamp request that has waited for this long we assume
685 * the packet will never be sent by hardware and discard it without reading
686 * the timestamp register.
687 */
688static void ice_ptp_process_tx_tstamp(struct ice_ptp_tx *tx)
689{
690 struct ice_ptp_port *ptp_port;
691 unsigned long flags;
692 struct ice_pf *pf;
693 struct ice_hw *hw;
694 u64 tstamp_ready;
695 bool link_up;
696 int err;
697 u8 idx;
698
699 ptp_port = container_of(tx, struct ice_ptp_port, tx);
700 pf = ptp_port_to_pf(ptp_port);
701 hw = &pf->hw;
702
703 /* Read the Tx ready status first */
704 err = ice_get_phy_tx_tstamp_ready(hw, tx->block, &tstamp_ready);
705 if (err)
706 return;
707
708 /* Drop packets if the link went down */
709 link_up = ptp_port->link_up;
710
711 for_each_set_bit(idx, tx->in_use, tx->len) {
712 struct skb_shared_hwtstamps shhwtstamps = {};
713 u8 phy_idx = idx + tx->offset;
714 u64 raw_tstamp = 0, tstamp;
715 bool drop_ts = !link_up;
716 struct sk_buff *skb;
717
718 /* Drop packets which have waited for more than 2 seconds */
719 if (time_is_before_jiffies(tx->tstamps[idx].start + 2 * HZ)) {
720 drop_ts = true;
721
722 /* Count the number of Tx timestamps that timed out */
723 pf->ptp.tx_hwtstamp_timeouts++;
724 }
725
726 /* Only read a timestamp from the PHY if its marked as ready
727 * by the tstamp_ready register. This avoids unnecessary
728 * reading of timestamps which are not yet valid. This is
729 * important as we must read all timestamps which are valid
730 * and only timestamps which are valid during each interrupt.
731 * If we do not, the hardware logic for generating a new
732 * interrupt can get stuck on some devices.
733 */
734 if (!(tstamp_ready & BIT_ULL(phy_idx))) {
735 if (drop_ts)
736 goto skip_ts_read;
737
738 continue;
739 }
740
741 ice_trace(tx_tstamp_fw_req, tx->tstamps[idx].skb, idx);
742
743 err = ice_read_phy_tstamp(hw, tx->block, phy_idx, &raw_tstamp);
744 if (err && !drop_ts)
745 continue;
746
747 ice_trace(tx_tstamp_fw_done, tx->tstamps[idx].skb, idx);
748
749 /* For PHYs which don't implement a proper timestamp ready
750 * bitmap, verify that the timestamp value is different
751 * from the last cached timestamp. If it is not, skip this for
752 * now assuming it hasn't yet been captured by hardware.
753 */
754 if (!drop_ts && tx->verify_cached &&
755 raw_tstamp == tx->tstamps[idx].cached_tstamp)
756 continue;
757
758 /* Discard any timestamp value without the valid bit set */
759 if (!(raw_tstamp & ICE_PTP_TS_VALID))
760 drop_ts = true;
761
762skip_ts_read:
763 spin_lock_irqsave(&tx->lock, flags);
764 if (tx->verify_cached && raw_tstamp)
765 tx->tstamps[idx].cached_tstamp = raw_tstamp;
766 clear_bit(idx, tx->in_use);
767 skb = tx->tstamps[idx].skb;
768 tx->tstamps[idx].skb = NULL;
769 if (test_and_clear_bit(idx, tx->stale))
770 drop_ts = true;
771 spin_unlock_irqrestore(&tx->lock, flags);
772
773 /* It is unlikely but possible that the SKB will have been
774 * flushed at this point due to link change or teardown.
775 */
776 if (!skb)
777 continue;
778
779 if (drop_ts) {
780 dev_kfree_skb_any(skb);
781 continue;
782 }
783
784 /* Extend the timestamp using cached PHC time */
785 tstamp = ice_ptp_extend_40b_ts(pf, raw_tstamp);
786 if (tstamp) {
787 shhwtstamps.hwtstamp = ns_to_ktime(tstamp);
788 ice_trace(tx_tstamp_complete, skb, idx);
789 }
790
791 skb_tstamp_tx(skb, &shhwtstamps);
792 dev_kfree_skb_any(skb);
793 }
794}
795
796/**
797 * ice_ptp_tx_tstamp_owner - Process Tx timestamps for all ports on the device
798 * @pf: Board private structure
799 */
800static enum ice_tx_tstamp_work ice_ptp_tx_tstamp_owner(struct ice_pf *pf)
801{
802 struct ice_ptp_port *port;
803 unsigned int i;
804
805 mutex_lock(&pf->ptp.ports_owner.lock);
806 list_for_each_entry(port, &pf->ptp.ports_owner.ports, list_member) {
807 struct ice_ptp_tx *tx = &port->tx;
808
809 if (!tx || !tx->init)
810 continue;
811
812 ice_ptp_process_tx_tstamp(tx);
813 }
814 mutex_unlock(&pf->ptp.ports_owner.lock);
815
816 for (i = 0; i < ICE_MAX_QUAD; i++) {
817 u64 tstamp_ready;
818 int err;
819
820 /* Read the Tx ready status first */
821 err = ice_get_phy_tx_tstamp_ready(&pf->hw, i, &tstamp_ready);
822 if (err)
823 break;
824 else if (tstamp_ready)
825 return ICE_TX_TSTAMP_WORK_PENDING;
826 }
827
828 return ICE_TX_TSTAMP_WORK_DONE;
829}
830
831/**
832 * ice_ptp_tx_tstamp - Process Tx timestamps for this function.
833 * @tx: Tx tracking structure to initialize
834 *
835 * Returns: ICE_TX_TSTAMP_WORK_PENDING if there are any outstanding incomplete
836 * Tx timestamps, or ICE_TX_TSTAMP_WORK_DONE otherwise.
837 */
838static enum ice_tx_tstamp_work ice_ptp_tx_tstamp(struct ice_ptp_tx *tx)
839{
840 bool more_timestamps;
841 unsigned long flags;
842
843 if (!tx->init)
844 return ICE_TX_TSTAMP_WORK_DONE;
845
846 /* Process the Tx timestamp tracker */
847 ice_ptp_process_tx_tstamp(tx);
848
849 /* Check if there are outstanding Tx timestamps */
850 spin_lock_irqsave(&tx->lock, flags);
851 more_timestamps = tx->init && !bitmap_empty(tx->in_use, tx->len);
852 spin_unlock_irqrestore(&tx->lock, flags);
853
854 if (more_timestamps)
855 return ICE_TX_TSTAMP_WORK_PENDING;
856
857 return ICE_TX_TSTAMP_WORK_DONE;
858}
859
860/**
861 * ice_ptp_alloc_tx_tracker - Initialize tracking for Tx timestamps
862 * @tx: Tx tracking structure to initialize
863 *
864 * Assumes that the length has already been initialized. Do not call directly,
865 * use the ice_ptp_init_tx_* instead.
866 */
867static int
868ice_ptp_alloc_tx_tracker(struct ice_ptp_tx *tx)
869{
870 unsigned long *in_use, *stale;
871 struct ice_tx_tstamp *tstamps;
872
873 tstamps = kcalloc(tx->len, sizeof(*tstamps), GFP_KERNEL);
874 in_use = bitmap_zalloc(tx->len, GFP_KERNEL);
875 stale = bitmap_zalloc(tx->len, GFP_KERNEL);
876
877 if (!tstamps || !in_use || !stale) {
878 kfree(tstamps);
879 bitmap_free(in_use);
880 bitmap_free(stale);
881
882 return -ENOMEM;
883 }
884
885 tx->tstamps = tstamps;
886 tx->in_use = in_use;
887 tx->stale = stale;
888 tx->init = 1;
889 tx->last_ll_ts_idx_read = -1;
890
891 spin_lock_init(&tx->lock);
892
893 return 0;
894}
895
896/**
897 * ice_ptp_flush_tx_tracker - Flush any remaining timestamps from the tracker
898 * @pf: Board private structure
899 * @tx: the tracker to flush
900 *
901 * Called during teardown when a Tx tracker is being removed.
902 */
903static void
904ice_ptp_flush_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx)
905{
906 struct ice_hw *hw = &pf->hw;
907 unsigned long flags;
908 u64 tstamp_ready;
909 int err;
910 u8 idx;
911
912 err = ice_get_phy_tx_tstamp_ready(hw, tx->block, &tstamp_ready);
913 if (err) {
914 dev_dbg(ice_pf_to_dev(pf), "Failed to get the Tx tstamp ready bitmap for block %u, err %d\n",
915 tx->block, err);
916
917 /* If we fail to read the Tx timestamp ready bitmap just
918 * skip clearing the PHY timestamps.
919 */
920 tstamp_ready = 0;
921 }
922
923 for_each_set_bit(idx, tx->in_use, tx->len) {
924 u8 phy_idx = idx + tx->offset;
925 struct sk_buff *skb;
926
927 /* In case this timestamp is ready, we need to clear it. */
928 if (!hw->reset_ongoing && (tstamp_ready & BIT_ULL(phy_idx)))
929 ice_clear_phy_tstamp(hw, tx->block, phy_idx);
930
931 spin_lock_irqsave(&tx->lock, flags);
932 skb = tx->tstamps[idx].skb;
933 tx->tstamps[idx].skb = NULL;
934 clear_bit(idx, tx->in_use);
935 clear_bit(idx, tx->stale);
936 spin_unlock_irqrestore(&tx->lock, flags);
937
938 /* Count the number of Tx timestamps flushed */
939 pf->ptp.tx_hwtstamp_flushed++;
940
941 /* Free the SKB after we've cleared the bit */
942 dev_kfree_skb_any(skb);
943 }
944}
945
946/**
947 * ice_ptp_mark_tx_tracker_stale - Mark unfinished timestamps as stale
948 * @tx: the tracker to mark
949 *
950 * Mark currently outstanding Tx timestamps as stale. This prevents sending
951 * their timestamp value to the stack. This is required to prevent extending
952 * the 40bit hardware timestamp incorrectly.
953 *
954 * This should be called when the PTP clock is modified such as after a set
955 * time request.
956 */
957static void
958ice_ptp_mark_tx_tracker_stale(struct ice_ptp_tx *tx)
959{
960 unsigned long flags;
961
962 spin_lock_irqsave(&tx->lock, flags);
963 bitmap_or(tx->stale, tx->stale, tx->in_use, tx->len);
964 spin_unlock_irqrestore(&tx->lock, flags);
965}
966
967/**
968 * ice_ptp_release_tx_tracker - Release allocated memory for Tx tracker
969 * @pf: Board private structure
970 * @tx: Tx tracking structure to release
971 *
972 * Free memory associated with the Tx timestamp tracker.
973 */
974static void
975ice_ptp_release_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx)
976{
977 unsigned long flags;
978
979 spin_lock_irqsave(&tx->lock, flags);
980 tx->init = 0;
981 spin_unlock_irqrestore(&tx->lock, flags);
982
983 /* wait for potentially outstanding interrupt to complete */
984 synchronize_irq(pf->oicr_irq.virq);
985
986 ice_ptp_flush_tx_tracker(pf, tx);
987
988 kfree(tx->tstamps);
989 tx->tstamps = NULL;
990
991 bitmap_free(tx->in_use);
992 tx->in_use = NULL;
993
994 bitmap_free(tx->stale);
995 tx->stale = NULL;
996
997 tx->len = 0;
998}
999
1000/**
1001 * ice_ptp_init_tx_e82x - Initialize tracking for Tx timestamps
1002 * @pf: Board private structure
1003 * @tx: the Tx tracking structure to initialize
1004 * @port: the port this structure tracks
1005 *
1006 * Initialize the Tx timestamp tracker for this port. For generic MAC devices,
1007 * the timestamp block is shared for all ports in the same quad. To avoid
1008 * ports using the same timestamp index, logically break the block of
1009 * registers into chunks based on the port number.
1010 */
1011static int
1012ice_ptp_init_tx_e82x(struct ice_pf *pf, struct ice_ptp_tx *tx, u8 port)
1013{
1014 tx->block = port / ICE_PORTS_PER_QUAD;
1015 tx->offset = (port % ICE_PORTS_PER_QUAD) * INDEX_PER_PORT_E82X;
1016 tx->len = INDEX_PER_PORT_E82X;
1017 tx->verify_cached = 0;
1018
1019 return ice_ptp_alloc_tx_tracker(tx);
1020}
1021
1022/**
1023 * ice_ptp_init_tx_e810 - Initialize tracking for Tx timestamps
1024 * @pf: Board private structure
1025 * @tx: the Tx tracking structure to initialize
1026 *
1027 * Initialize the Tx timestamp tracker for this PF. For E810 devices, each
1028 * port has its own block of timestamps, independent of the other ports.
1029 */
1030static int
1031ice_ptp_init_tx_e810(struct ice_pf *pf, struct ice_ptp_tx *tx)
1032{
1033 tx->block = pf->hw.port_info->lport;
1034 tx->offset = 0;
1035 tx->len = INDEX_PER_PORT_E810;
1036 /* The E810 PHY does not provide a timestamp ready bitmap. Instead,
1037 * verify new timestamps against cached copy of the last read
1038 * timestamp.
1039 */
1040 tx->verify_cached = 1;
1041
1042 return ice_ptp_alloc_tx_tracker(tx);
1043}
1044
1045/**
1046 * ice_ptp_update_cached_phctime - Update the cached PHC time values
1047 * @pf: Board specific private structure
1048 *
1049 * This function updates the system time values which are cached in the PF
1050 * structure and the Rx rings.
1051 *
1052 * This function must be called periodically to ensure that the cached value
1053 * is never more than 2 seconds old.
1054 *
1055 * Note that the cached copy in the PF PTP structure is always updated, even
1056 * if we can't update the copy in the Rx rings.
1057 *
1058 * Return:
1059 * * 0 - OK, successfully updated
1060 * * -EAGAIN - PF was busy, need to reschedule the update
1061 */
1062static int ice_ptp_update_cached_phctime(struct ice_pf *pf)
1063{
1064 struct device *dev = ice_pf_to_dev(pf);
1065 unsigned long update_before;
1066 u64 systime;
1067 int i;
1068
1069 update_before = pf->ptp.cached_phc_jiffies + msecs_to_jiffies(2000);
1070 if (pf->ptp.cached_phc_time &&
1071 time_is_before_jiffies(update_before)) {
1072 unsigned long time_taken = jiffies - pf->ptp.cached_phc_jiffies;
1073
1074 dev_warn(dev, "%u msecs passed between update to cached PHC time\n",
1075 jiffies_to_msecs(time_taken));
1076 pf->ptp.late_cached_phc_updates++;
1077 }
1078
1079 /* Read the current PHC time */
1080 systime = ice_ptp_read_src_clk_reg(pf, NULL);
1081
1082 /* Update the cached PHC time stored in the PF structure */
1083 WRITE_ONCE(pf->ptp.cached_phc_time, systime);
1084 WRITE_ONCE(pf->ptp.cached_phc_jiffies, jiffies);
1085
1086 if (test_and_set_bit(ICE_CFG_BUSY, pf->state))
1087 return -EAGAIN;
1088
1089 ice_for_each_vsi(pf, i) {
1090 struct ice_vsi *vsi = pf->vsi[i];
1091 int j;
1092
1093 if (!vsi)
1094 continue;
1095
1096 if (vsi->type != ICE_VSI_PF)
1097 continue;
1098
1099 ice_for_each_rxq(vsi, j) {
1100 if (!vsi->rx_rings[j])
1101 continue;
1102 WRITE_ONCE(vsi->rx_rings[j]->cached_phctime, systime);
1103 }
1104 }
1105 clear_bit(ICE_CFG_BUSY, pf->state);
1106
1107 return 0;
1108}
1109
1110/**
1111 * ice_ptp_reset_cached_phctime - Reset cached PHC time after an update
1112 * @pf: Board specific private structure
1113 *
1114 * This function must be called when the cached PHC time is no longer valid,
1115 * such as after a time adjustment. It marks any currently outstanding Tx
1116 * timestamps as stale and updates the cached PHC time for both the PF and Rx
1117 * rings.
1118 *
1119 * If updating the PHC time cannot be done immediately, a warning message is
1120 * logged and the work item is scheduled immediately to minimize the window
1121 * with a wrong cached timestamp.
1122 */
1123static void ice_ptp_reset_cached_phctime(struct ice_pf *pf)
1124{
1125 struct device *dev = ice_pf_to_dev(pf);
1126 int err;
1127
1128 /* Update the cached PHC time immediately if possible, otherwise
1129 * schedule the work item to execute soon.
1130 */
1131 err = ice_ptp_update_cached_phctime(pf);
1132 if (err) {
1133 /* If another thread is updating the Rx rings, we won't
1134 * properly reset them here. This could lead to reporting of
1135 * invalid timestamps, but there isn't much we can do.
1136 */
1137 dev_warn(dev, "%s: ICE_CFG_BUSY, unable to immediately update cached PHC time\n",
1138 __func__);
1139
1140 /* Queue the work item to update the Rx rings when possible */
1141 kthread_queue_delayed_work(pf->ptp.kworker, &pf->ptp.work,
1142 msecs_to_jiffies(10));
1143 }
1144
1145 /* Mark any outstanding timestamps as stale, since they might have
1146 * been captured in hardware before the time update. This could lead
1147 * to us extending them with the wrong cached value resulting in
1148 * incorrect timestamp values.
1149 */
1150 ice_ptp_mark_tx_tracker_stale(&pf->ptp.port.tx);
1151}
1152
1153/**
1154 * ice_ptp_read_time - Read the time from the device
1155 * @pf: Board private structure
1156 * @ts: timespec structure to hold the current time value
1157 * @sts: Optional parameter for holding a pair of system timestamps from
1158 * the system clock. Will be ignored if NULL is given.
1159 *
1160 * This function reads the source clock registers and stores them in a timespec.
1161 * However, since the registers are 64 bits of nanoseconds, we must convert the
1162 * result to a timespec before we can return.
1163 */
1164static void
1165ice_ptp_read_time(struct ice_pf *pf, struct timespec64 *ts,
1166 struct ptp_system_timestamp *sts)
1167{
1168 u64 time_ns = ice_ptp_read_src_clk_reg(pf, sts);
1169
1170 *ts = ns_to_timespec64(time_ns);
1171}
1172
1173/**
1174 * ice_ptp_write_init - Set PHC time to provided value
1175 * @pf: Board private structure
1176 * @ts: timespec structure that holds the new time value
1177 *
1178 * Set the PHC time to the specified time provided in the timespec.
1179 */
1180static int ice_ptp_write_init(struct ice_pf *pf, struct timespec64 *ts)
1181{
1182 u64 ns = timespec64_to_ns(ts);
1183 struct ice_hw *hw = &pf->hw;
1184
1185 return ice_ptp_init_time(hw, ns);
1186}
1187
1188/**
1189 * ice_ptp_write_adj - Adjust PHC clock time atomically
1190 * @pf: Board private structure
1191 * @adj: Adjustment in nanoseconds
1192 *
1193 * Perform an atomic adjustment of the PHC time by the specified number of
1194 * nanoseconds.
1195 */
1196static int ice_ptp_write_adj(struct ice_pf *pf, s32 adj)
1197{
1198 struct ice_hw *hw = &pf->hw;
1199
1200 return ice_ptp_adj_clock(hw, adj);
1201}
1202
1203/**
1204 * ice_base_incval - Get base timer increment value
1205 * @pf: Board private structure
1206 *
1207 * Look up the base timer increment value for this device. The base increment
1208 * value is used to define the nominal clock tick rate. This increment value
1209 * is programmed during device initialization. It is also used as the basis
1210 * for calculating adjustments using scaled_ppm.
1211 */
1212static u64 ice_base_incval(struct ice_pf *pf)
1213{
1214 struct ice_hw *hw = &pf->hw;
1215 u64 incval;
1216
1217 if (ice_is_e810(hw))
1218 incval = ICE_PTP_NOMINAL_INCVAL_E810;
1219 else if (ice_e82x_time_ref(hw) < NUM_ICE_TIME_REF_FREQ)
1220 incval = ice_e82x_nominal_incval(ice_e82x_time_ref(hw));
1221 else
1222 incval = UNKNOWN_INCVAL_E82X;
1223
1224 dev_dbg(ice_pf_to_dev(pf), "PTP: using base increment value of 0x%016llx\n",
1225 incval);
1226
1227 return incval;
1228}
1229
1230/**
1231 * ice_ptp_check_tx_fifo - Check whether Tx FIFO is in an OK state
1232 * @port: PTP port for which Tx FIFO is checked
1233 */
1234static int ice_ptp_check_tx_fifo(struct ice_ptp_port *port)
1235{
1236 int quad = port->port_num / ICE_PORTS_PER_QUAD;
1237 int offs = port->port_num % ICE_PORTS_PER_QUAD;
1238 struct ice_pf *pf;
1239 struct ice_hw *hw;
1240 u32 val, phy_sts;
1241 int err;
1242
1243 pf = ptp_port_to_pf(port);
1244 hw = &pf->hw;
1245
1246 if (port->tx_fifo_busy_cnt == FIFO_OK)
1247 return 0;
1248
1249 /* need to read FIFO state */
1250 if (offs == 0 || offs == 1)
1251 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_FIFO01_STATUS,
1252 &val);
1253 else
1254 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_FIFO23_STATUS,
1255 &val);
1256
1257 if (err) {
1258 dev_err(ice_pf_to_dev(pf), "PTP failed to check port %d Tx FIFO, err %d\n",
1259 port->port_num, err);
1260 return err;
1261 }
1262
1263 if (offs & 0x1)
1264 phy_sts = FIELD_GET(Q_REG_FIFO13_M, val);
1265 else
1266 phy_sts = FIELD_GET(Q_REG_FIFO02_M, val);
1267
1268 if (phy_sts & FIFO_EMPTY) {
1269 port->tx_fifo_busy_cnt = FIFO_OK;
1270 return 0;
1271 }
1272
1273 port->tx_fifo_busy_cnt++;
1274
1275 dev_dbg(ice_pf_to_dev(pf), "Try %d, port %d FIFO not empty\n",
1276 port->tx_fifo_busy_cnt, port->port_num);
1277
1278 if (port->tx_fifo_busy_cnt == ICE_PTP_FIFO_NUM_CHECKS) {
1279 dev_dbg(ice_pf_to_dev(pf),
1280 "Port %d Tx FIFO still not empty; resetting quad %d\n",
1281 port->port_num, quad);
1282 ice_ptp_reset_ts_memory_quad_e82x(hw, quad);
1283 port->tx_fifo_busy_cnt = FIFO_OK;
1284 return 0;
1285 }
1286
1287 return -EAGAIN;
1288}
1289
1290/**
1291 * ice_ptp_wait_for_offsets - Check for valid Tx and Rx offsets
1292 * @work: Pointer to the kthread_work structure for this task
1293 *
1294 * Check whether hardware has completed measuring the Tx and Rx offset values
1295 * used to configure and enable vernier timestamp calibration.
1296 *
1297 * Once the offset in either direction is measured, configure the associated
1298 * registers with the calibrated offset values and enable timestamping. The Tx
1299 * and Rx directions are configured independently as soon as their associated
1300 * offsets are known.
1301 *
1302 * This function reschedules itself until both Tx and Rx calibration have
1303 * completed.
1304 */
1305static void ice_ptp_wait_for_offsets(struct kthread_work *work)
1306{
1307 struct ice_ptp_port *port;
1308 struct ice_pf *pf;
1309 struct ice_hw *hw;
1310 int tx_err;
1311 int rx_err;
1312
1313 port = container_of(work, struct ice_ptp_port, ov_work.work);
1314 pf = ptp_port_to_pf(port);
1315 hw = &pf->hw;
1316
1317 if (ice_is_reset_in_progress(pf->state)) {
1318 /* wait for device driver to complete reset */
1319 kthread_queue_delayed_work(pf->ptp.kworker,
1320 &port->ov_work,
1321 msecs_to_jiffies(100));
1322 return;
1323 }
1324
1325 tx_err = ice_ptp_check_tx_fifo(port);
1326 if (!tx_err)
1327 tx_err = ice_phy_cfg_tx_offset_e82x(hw, port->port_num);
1328 rx_err = ice_phy_cfg_rx_offset_e82x(hw, port->port_num);
1329 if (tx_err || rx_err) {
1330 /* Tx and/or Rx offset not yet configured, try again later */
1331 kthread_queue_delayed_work(pf->ptp.kworker,
1332 &port->ov_work,
1333 msecs_to_jiffies(100));
1334 return;
1335 }
1336}
1337
1338/**
1339 * ice_ptp_port_phy_stop - Stop timestamping for a PHY port
1340 * @ptp_port: PTP port to stop
1341 */
1342static int
1343ice_ptp_port_phy_stop(struct ice_ptp_port *ptp_port)
1344{
1345 struct ice_pf *pf = ptp_port_to_pf(ptp_port);
1346 u8 port = ptp_port->port_num;
1347 struct ice_hw *hw = &pf->hw;
1348 int err;
1349
1350 if (ice_is_e810(hw))
1351 return 0;
1352
1353 mutex_lock(&ptp_port->ps_lock);
1354
1355 kthread_cancel_delayed_work_sync(&ptp_port->ov_work);
1356
1357 err = ice_stop_phy_timer_e82x(hw, port, true);
1358 if (err)
1359 dev_err(ice_pf_to_dev(pf), "PTP failed to set PHY port %d down, err %d\n",
1360 port, err);
1361
1362 mutex_unlock(&ptp_port->ps_lock);
1363
1364 return err;
1365}
1366
1367/**
1368 * ice_ptp_port_phy_restart - (Re)start and calibrate PHY timestamping
1369 * @ptp_port: PTP port for which the PHY start is set
1370 *
1371 * Start the PHY timestamping block, and initiate Vernier timestamping
1372 * calibration. If timestamping cannot be calibrated (such as if link is down)
1373 * then disable the timestamping block instead.
1374 */
1375static int
1376ice_ptp_port_phy_restart(struct ice_ptp_port *ptp_port)
1377{
1378 struct ice_pf *pf = ptp_port_to_pf(ptp_port);
1379 u8 port = ptp_port->port_num;
1380 struct ice_hw *hw = &pf->hw;
1381 unsigned long flags;
1382 int err;
1383
1384 if (ice_is_e810(hw))
1385 return 0;
1386
1387 if (!ptp_port->link_up)
1388 return ice_ptp_port_phy_stop(ptp_port);
1389
1390 mutex_lock(&ptp_port->ps_lock);
1391
1392 kthread_cancel_delayed_work_sync(&ptp_port->ov_work);
1393
1394 /* temporarily disable Tx timestamps while calibrating PHY offset */
1395 spin_lock_irqsave(&ptp_port->tx.lock, flags);
1396 ptp_port->tx.calibrating = true;
1397 spin_unlock_irqrestore(&ptp_port->tx.lock, flags);
1398 ptp_port->tx_fifo_busy_cnt = 0;
1399
1400 /* Start the PHY timer in Vernier mode */
1401 err = ice_start_phy_timer_e82x(hw, port);
1402 if (err)
1403 goto out_unlock;
1404
1405 /* Enable Tx timestamps right away */
1406 spin_lock_irqsave(&ptp_port->tx.lock, flags);
1407 ptp_port->tx.calibrating = false;
1408 spin_unlock_irqrestore(&ptp_port->tx.lock, flags);
1409
1410 kthread_queue_delayed_work(pf->ptp.kworker, &ptp_port->ov_work, 0);
1411
1412out_unlock:
1413 if (err)
1414 dev_err(ice_pf_to_dev(pf), "PTP failed to set PHY port %d up, err %d\n",
1415 port, err);
1416
1417 mutex_unlock(&ptp_port->ps_lock);
1418
1419 return err;
1420}
1421
1422/**
1423 * ice_ptp_link_change - Reconfigure PTP after link status change
1424 * @pf: Board private structure
1425 * @port: Port for which the PHY start is set
1426 * @linkup: Link is up or down
1427 */
1428void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup)
1429{
1430 struct ice_ptp_port *ptp_port;
1431 struct ice_hw *hw = &pf->hw;
1432
1433 if (!test_bit(ICE_FLAG_PTP, pf->flags))
1434 return;
1435
1436 if (WARN_ON_ONCE(port >= ICE_NUM_EXTERNAL_PORTS))
1437 return;
1438
1439 ptp_port = &pf->ptp.port;
1440 if (WARN_ON_ONCE(ptp_port->port_num != port))
1441 return;
1442
1443 /* Update cached link status for this port immediately */
1444 ptp_port->link_up = linkup;
1445
1446 switch (hw->phy_model) {
1447 case ICE_PHY_E810:
1448 /* Do not reconfigure E810 PHY */
1449 return;
1450 case ICE_PHY_E82X:
1451 ice_ptp_port_phy_restart(ptp_port);
1452 return;
1453 default:
1454 dev_warn(ice_pf_to_dev(pf), "%s: Unknown PHY type\n", __func__);
1455 }
1456}
1457
1458/**
1459 * ice_ptp_tx_ena_intr - Enable or disable the Tx timestamp interrupt
1460 * @pf: PF private structure
1461 * @ena: bool value to enable or disable interrupt
1462 * @threshold: Minimum number of packets at which intr is triggered
1463 *
1464 * Utility function to enable or disable Tx timestamp interrupt and threshold
1465 */
1466static int ice_ptp_tx_ena_intr(struct ice_pf *pf, bool ena, u32 threshold)
1467{
1468 struct ice_hw *hw = &pf->hw;
1469 int err = 0;
1470 int quad;
1471 u32 val;
1472
1473 ice_ptp_reset_ts_memory(hw);
1474
1475 for (quad = 0; quad < ICE_MAX_QUAD; quad++) {
1476 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG,
1477 &val);
1478 if (err)
1479 break;
1480
1481 if (ena) {
1482 val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
1483 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M;
1484 val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M,
1485 threshold);
1486 } else {
1487 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
1488 }
1489
1490 err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG,
1491 val);
1492 if (err)
1493 break;
1494 }
1495
1496 if (err)
1497 dev_err(ice_pf_to_dev(pf), "PTP failed in intr ena, err %d\n",
1498 err);
1499 return err;
1500}
1501
1502/**
1503 * ice_ptp_reset_phy_timestamping - Reset PHY timestamping block
1504 * @pf: Board private structure
1505 */
1506static void ice_ptp_reset_phy_timestamping(struct ice_pf *pf)
1507{
1508 ice_ptp_port_phy_restart(&pf->ptp.port);
1509}
1510
1511/**
1512 * ice_ptp_restart_all_phy - Restart all PHYs to recalibrate timestamping
1513 * @pf: Board private structure
1514 */
1515static void ice_ptp_restart_all_phy(struct ice_pf *pf)
1516{
1517 struct list_head *entry;
1518
1519 list_for_each(entry, &pf->ptp.ports_owner.ports) {
1520 struct ice_ptp_port *port = list_entry(entry,
1521 struct ice_ptp_port,
1522 list_member);
1523
1524 if (port->link_up)
1525 ice_ptp_port_phy_restart(port);
1526 }
1527}
1528
1529/**
1530 * ice_ptp_adjfine - Adjust clock increment rate
1531 * @info: the driver's PTP info structure
1532 * @scaled_ppm: Parts per million with 16-bit fractional field
1533 *
1534 * Adjust the frequency of the clock by the indicated scaled ppm from the
1535 * base frequency.
1536 */
1537static int ice_ptp_adjfine(struct ptp_clock_info *info, long scaled_ppm)
1538{
1539 struct ice_pf *pf = ptp_info_to_pf(info);
1540 struct ice_hw *hw = &pf->hw;
1541 u64 incval;
1542 int err;
1543
1544 incval = adjust_by_scaled_ppm(ice_base_incval(pf), scaled_ppm);
1545 err = ice_ptp_write_incval_locked(hw, incval);
1546 if (err) {
1547 dev_err(ice_pf_to_dev(pf), "PTP failed to set incval, err %d\n",
1548 err);
1549 return -EIO;
1550 }
1551
1552 return 0;
1553}
1554
1555/**
1556 * ice_ptp_extts_event - Process PTP external clock event
1557 * @pf: Board private structure
1558 */
1559void ice_ptp_extts_event(struct ice_pf *pf)
1560{
1561 struct ptp_clock_event event;
1562 struct ice_hw *hw = &pf->hw;
1563 u8 chan, tmr_idx;
1564 u32 hi, lo;
1565
1566 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
1567 /* Event time is captured by one of the two matched registers
1568 * GLTSYN_EVNT_L: 32 LSB of sampled time event
1569 * GLTSYN_EVNT_H: 32 MSB of sampled time event
1570 * Event is defined in GLTSYN_EVNT_0 register
1571 */
1572 for (chan = 0; chan < GLTSYN_EVNT_H_IDX_MAX; chan++) {
1573 /* Check if channel is enabled */
1574 if (pf->ptp.ext_ts_irq & (1 << chan)) {
1575 lo = rd32(hw, GLTSYN_EVNT_L(chan, tmr_idx));
1576 hi = rd32(hw, GLTSYN_EVNT_H(chan, tmr_idx));
1577 event.timestamp = (((u64)hi) << 32) | lo;
1578 event.type = PTP_CLOCK_EXTTS;
1579 event.index = chan;
1580
1581 /* Fire event */
1582 ptp_clock_event(pf->ptp.clock, &event);
1583 pf->ptp.ext_ts_irq &= ~(1 << chan);
1584 }
1585 }
1586}
1587
1588/**
1589 * ice_ptp_cfg_extts - Configure EXTTS pin and channel
1590 * @pf: Board private structure
1591 * @ena: true to enable; false to disable
1592 * @chan: GPIO channel (0-3)
1593 * @gpio_pin: GPIO pin
1594 * @extts_flags: request flags from the ptp_extts_request.flags
1595 */
1596static int
1597ice_ptp_cfg_extts(struct ice_pf *pf, bool ena, unsigned int chan, u32 gpio_pin,
1598 unsigned int extts_flags)
1599{
1600 u32 func, aux_reg, gpio_reg, irq_reg;
1601 struct ice_hw *hw = &pf->hw;
1602 u8 tmr_idx;
1603
1604 if (chan > (unsigned int)pf->ptp.info.n_ext_ts)
1605 return -EINVAL;
1606
1607 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
1608
1609 irq_reg = rd32(hw, PFINT_OICR_ENA);
1610
1611 if (ena) {
1612 /* Enable the interrupt */
1613 irq_reg |= PFINT_OICR_TSYN_EVNT_M;
1614 aux_reg = GLTSYN_AUX_IN_0_INT_ENA_M;
1615
1616#define GLTSYN_AUX_IN_0_EVNTLVL_RISING_EDGE BIT(0)
1617#define GLTSYN_AUX_IN_0_EVNTLVL_FALLING_EDGE BIT(1)
1618
1619 /* set event level to requested edge */
1620 if (extts_flags & PTP_FALLING_EDGE)
1621 aux_reg |= GLTSYN_AUX_IN_0_EVNTLVL_FALLING_EDGE;
1622 if (extts_flags & PTP_RISING_EDGE)
1623 aux_reg |= GLTSYN_AUX_IN_0_EVNTLVL_RISING_EDGE;
1624
1625 /* Write GPIO CTL reg.
1626 * 0x1 is input sampled by EVENT register(channel)
1627 * + num_in_channels * tmr_idx
1628 */
1629 func = 1 + chan + (tmr_idx * 3);
1630 gpio_reg = FIELD_PREP(GLGEN_GPIO_CTL_PIN_FUNC_M, func);
1631 pf->ptp.ext_ts_chan |= (1 << chan);
1632 } else {
1633 /* clear the values we set to reset defaults */
1634 aux_reg = 0;
1635 gpio_reg = 0;
1636 pf->ptp.ext_ts_chan &= ~(1 << chan);
1637 if (!pf->ptp.ext_ts_chan)
1638 irq_reg &= ~PFINT_OICR_TSYN_EVNT_M;
1639 }
1640
1641 wr32(hw, PFINT_OICR_ENA, irq_reg);
1642 wr32(hw, GLTSYN_AUX_IN(chan, tmr_idx), aux_reg);
1643 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), gpio_reg);
1644
1645 return 0;
1646}
1647
1648/**
1649 * ice_ptp_cfg_clkout - Configure clock to generate periodic wave
1650 * @pf: Board private structure
1651 * @chan: GPIO channel (0-3)
1652 * @config: desired periodic clk configuration. NULL will disable channel
1653 * @store: If set to true the values will be stored
1654 *
1655 * Configure the internal clock generator modules to generate the clock wave of
1656 * specified period.
1657 */
1658static int ice_ptp_cfg_clkout(struct ice_pf *pf, unsigned int chan,
1659 struct ice_perout_channel *config, bool store)
1660{
1661 u64 current_time, period, start_time, phase;
1662 struct ice_hw *hw = &pf->hw;
1663 u32 func, val, gpio_pin;
1664 u8 tmr_idx;
1665
1666 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
1667
1668 /* 0. Reset mode & out_en in AUX_OUT */
1669 wr32(hw, GLTSYN_AUX_OUT(chan, tmr_idx), 0);
1670
1671 /* If we're disabling the output, clear out CLKO and TGT and keep
1672 * output level low
1673 */
1674 if (!config || !config->ena) {
1675 wr32(hw, GLTSYN_CLKO(chan, tmr_idx), 0);
1676 wr32(hw, GLTSYN_TGT_L(chan, tmr_idx), 0);
1677 wr32(hw, GLTSYN_TGT_H(chan, tmr_idx), 0);
1678
1679 val = GLGEN_GPIO_CTL_PIN_DIR_M;
1680 gpio_pin = pf->ptp.perout_channels[chan].gpio_pin;
1681 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), val);
1682
1683 /* Store the value if requested */
1684 if (store)
1685 memset(&pf->ptp.perout_channels[chan], 0,
1686 sizeof(struct ice_perout_channel));
1687
1688 return 0;
1689 }
1690 period = config->period;
1691 start_time = config->start_time;
1692 div64_u64_rem(start_time, period, &phase);
1693 gpio_pin = config->gpio_pin;
1694
1695 /* 1. Write clkout with half of required period value */
1696 if (period & 0x1) {
1697 dev_err(ice_pf_to_dev(pf), "CLK Period must be an even value\n");
1698 goto err;
1699 }
1700
1701 period >>= 1;
1702
1703 /* For proper operation, the GLTSYN_CLKO must be larger than clock tick
1704 */
1705#define MIN_PULSE 3
1706 if (period <= MIN_PULSE || period > U32_MAX) {
1707 dev_err(ice_pf_to_dev(pf), "CLK Period must be > %d && < 2^33",
1708 MIN_PULSE * 2);
1709 goto err;
1710 }
1711
1712 wr32(hw, GLTSYN_CLKO(chan, tmr_idx), lower_32_bits(period));
1713
1714 /* Allow time for programming before start_time is hit */
1715 current_time = ice_ptp_read_src_clk_reg(pf, NULL);
1716
1717 /* if start time is in the past start the timer at the nearest second
1718 * maintaining phase
1719 */
1720 if (start_time < current_time)
1721 start_time = div64_u64(current_time + NSEC_PER_SEC - 1,
1722 NSEC_PER_SEC) * NSEC_PER_SEC + phase;
1723
1724 if (ice_is_e810(hw))
1725 start_time -= E810_OUT_PROP_DELAY_NS;
1726 else
1727 start_time -= ice_e82x_pps_delay(ice_e82x_time_ref(hw));
1728
1729 /* 2. Write TARGET time */
1730 wr32(hw, GLTSYN_TGT_L(chan, tmr_idx), lower_32_bits(start_time));
1731 wr32(hw, GLTSYN_TGT_H(chan, tmr_idx), upper_32_bits(start_time));
1732
1733 /* 3. Write AUX_OUT register */
1734 val = GLTSYN_AUX_OUT_0_OUT_ENA_M | GLTSYN_AUX_OUT_0_OUTMOD_M;
1735 wr32(hw, GLTSYN_AUX_OUT(chan, tmr_idx), val);
1736
1737 /* 4. write GPIO CTL reg */
1738 func = 8 + chan + (tmr_idx * 4);
1739 val = GLGEN_GPIO_CTL_PIN_DIR_M |
1740 FIELD_PREP(GLGEN_GPIO_CTL_PIN_FUNC_M, func);
1741 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), val);
1742
1743 /* Store the value if requested */
1744 if (store) {
1745 memcpy(&pf->ptp.perout_channels[chan], config,
1746 sizeof(struct ice_perout_channel));
1747 pf->ptp.perout_channels[chan].start_time = phase;
1748 }
1749
1750 return 0;
1751err:
1752 dev_err(ice_pf_to_dev(pf), "PTP failed to cfg per_clk\n");
1753 return -EFAULT;
1754}
1755
1756/**
1757 * ice_ptp_disable_all_clkout - Disable all currently configured outputs
1758 * @pf: pointer to the PF structure
1759 *
1760 * Disable all currently configured clock outputs. This is necessary before
1761 * certain changes to the PTP hardware clock. Use ice_ptp_enable_all_clkout to
1762 * re-enable the clocks again.
1763 */
1764static void ice_ptp_disable_all_clkout(struct ice_pf *pf)
1765{
1766 uint i;
1767
1768 for (i = 0; i < pf->ptp.info.n_per_out; i++)
1769 if (pf->ptp.perout_channels[i].ena)
1770 ice_ptp_cfg_clkout(pf, i, NULL, false);
1771}
1772
1773/**
1774 * ice_ptp_enable_all_clkout - Enable all configured periodic clock outputs
1775 * @pf: pointer to the PF structure
1776 *
1777 * Enable all currently configured clock outputs. Use this after
1778 * ice_ptp_disable_all_clkout to reconfigure the output signals according to
1779 * their configuration.
1780 */
1781static void ice_ptp_enable_all_clkout(struct ice_pf *pf)
1782{
1783 uint i;
1784
1785 for (i = 0; i < pf->ptp.info.n_per_out; i++)
1786 if (pf->ptp.perout_channels[i].ena)
1787 ice_ptp_cfg_clkout(pf, i, &pf->ptp.perout_channels[i],
1788 false);
1789}
1790
1791/**
1792 * ice_ptp_gpio_enable_e810 - Enable/disable ancillary features of PHC
1793 * @info: the driver's PTP info structure
1794 * @rq: The requested feature to change
1795 * @on: Enable/disable flag
1796 */
1797static int
1798ice_ptp_gpio_enable_e810(struct ptp_clock_info *info,
1799 struct ptp_clock_request *rq, int on)
1800{
1801 struct ice_pf *pf = ptp_info_to_pf(info);
1802 struct ice_perout_channel clk_cfg = {0};
1803 bool sma_pres = false;
1804 unsigned int chan;
1805 u32 gpio_pin;
1806 int err;
1807
1808 if (ice_is_feature_supported(pf, ICE_F_SMA_CTRL))
1809 sma_pres = true;
1810
1811 switch (rq->type) {
1812 case PTP_CLK_REQ_PEROUT:
1813 chan = rq->perout.index;
1814 if (sma_pres) {
1815 if (chan == ice_pin_desc_e810t[SMA1].chan)
1816 clk_cfg.gpio_pin = GPIO_20;
1817 else if (chan == ice_pin_desc_e810t[SMA2].chan)
1818 clk_cfg.gpio_pin = GPIO_22;
1819 else
1820 return -1;
1821 } else if (ice_is_e810t(&pf->hw)) {
1822 if (chan == 0)
1823 clk_cfg.gpio_pin = GPIO_20;
1824 else
1825 clk_cfg.gpio_pin = GPIO_22;
1826 } else if (chan == PPS_CLK_GEN_CHAN) {
1827 clk_cfg.gpio_pin = PPS_PIN_INDEX;
1828 } else {
1829 clk_cfg.gpio_pin = chan;
1830 }
1831
1832 clk_cfg.period = ((rq->perout.period.sec * NSEC_PER_SEC) +
1833 rq->perout.period.nsec);
1834 clk_cfg.start_time = ((rq->perout.start.sec * NSEC_PER_SEC) +
1835 rq->perout.start.nsec);
1836 clk_cfg.ena = !!on;
1837
1838 err = ice_ptp_cfg_clkout(pf, chan, &clk_cfg, true);
1839 break;
1840 case PTP_CLK_REQ_EXTTS:
1841 chan = rq->extts.index;
1842 if (sma_pres) {
1843 if (chan < ice_pin_desc_e810t[SMA2].chan)
1844 gpio_pin = GPIO_21;
1845 else
1846 gpio_pin = GPIO_23;
1847 } else if (ice_is_e810t(&pf->hw)) {
1848 if (chan == 0)
1849 gpio_pin = GPIO_21;
1850 else
1851 gpio_pin = GPIO_23;
1852 } else {
1853 gpio_pin = chan;
1854 }
1855
1856 err = ice_ptp_cfg_extts(pf, !!on, chan, gpio_pin,
1857 rq->extts.flags);
1858 break;
1859 default:
1860 return -EOPNOTSUPP;
1861 }
1862
1863 return err;
1864}
1865
1866/**
1867 * ice_ptp_gpio_enable_e823 - Enable/disable ancillary features of PHC
1868 * @info: the driver's PTP info structure
1869 * @rq: The requested feature to change
1870 * @on: Enable/disable flag
1871 */
1872static int ice_ptp_gpio_enable_e823(struct ptp_clock_info *info,
1873 struct ptp_clock_request *rq, int on)
1874{
1875 struct ice_pf *pf = ptp_info_to_pf(info);
1876 struct ice_perout_channel clk_cfg = {0};
1877 int err;
1878
1879 switch (rq->type) {
1880 case PTP_CLK_REQ_PPS:
1881 clk_cfg.gpio_pin = PPS_PIN_INDEX;
1882 clk_cfg.period = NSEC_PER_SEC;
1883 clk_cfg.ena = !!on;
1884
1885 err = ice_ptp_cfg_clkout(pf, PPS_CLK_GEN_CHAN, &clk_cfg, true);
1886 break;
1887 case PTP_CLK_REQ_EXTTS:
1888 err = ice_ptp_cfg_extts(pf, !!on, rq->extts.index,
1889 TIME_SYNC_PIN_INDEX, rq->extts.flags);
1890 break;
1891 default:
1892 return -EOPNOTSUPP;
1893 }
1894
1895 return err;
1896}
1897
1898/**
1899 * ice_ptp_gettimex64 - Get the time of the clock
1900 * @info: the driver's PTP info structure
1901 * @ts: timespec64 structure to hold the current time value
1902 * @sts: Optional parameter for holding a pair of system timestamps from
1903 * the system clock. Will be ignored if NULL is given.
1904 *
1905 * Read the device clock and return the correct value on ns, after converting it
1906 * into a timespec struct.
1907 */
1908static int
1909ice_ptp_gettimex64(struct ptp_clock_info *info, struct timespec64 *ts,
1910 struct ptp_system_timestamp *sts)
1911{
1912 struct ice_pf *pf = ptp_info_to_pf(info);
1913 struct ice_hw *hw = &pf->hw;
1914
1915 if (!ice_ptp_lock(hw)) {
1916 dev_err(ice_pf_to_dev(pf), "PTP failed to get time\n");
1917 return -EBUSY;
1918 }
1919
1920 ice_ptp_read_time(pf, ts, sts);
1921 ice_ptp_unlock(hw);
1922
1923 return 0;
1924}
1925
1926/**
1927 * ice_ptp_settime64 - Set the time of the clock
1928 * @info: the driver's PTP info structure
1929 * @ts: timespec64 structure that holds the new time value
1930 *
1931 * Set the device clock to the user input value. The conversion from timespec
1932 * to ns happens in the write function.
1933 */
1934static int
1935ice_ptp_settime64(struct ptp_clock_info *info, const struct timespec64 *ts)
1936{
1937 struct ice_pf *pf = ptp_info_to_pf(info);
1938 struct timespec64 ts64 = *ts;
1939 struct ice_hw *hw = &pf->hw;
1940 int err;
1941
1942 /* For Vernier mode, we need to recalibrate after new settime
1943 * Start with disabling timestamp block
1944 */
1945 if (pf->ptp.port.link_up)
1946 ice_ptp_port_phy_stop(&pf->ptp.port);
1947
1948 if (!ice_ptp_lock(hw)) {
1949 err = -EBUSY;
1950 goto exit;
1951 }
1952
1953 /* Disable periodic outputs */
1954 ice_ptp_disable_all_clkout(pf);
1955
1956 err = ice_ptp_write_init(pf, &ts64);
1957 ice_ptp_unlock(hw);
1958
1959 if (!err)
1960 ice_ptp_reset_cached_phctime(pf);
1961
1962 /* Reenable periodic outputs */
1963 ice_ptp_enable_all_clkout(pf);
1964
1965 /* Recalibrate and re-enable timestamp blocks for E822/E823 */
1966 if (hw->phy_model == ICE_PHY_E82X)
1967 ice_ptp_restart_all_phy(pf);
1968exit:
1969 if (err) {
1970 dev_err(ice_pf_to_dev(pf), "PTP failed to set time %d\n", err);
1971 return err;
1972 }
1973
1974 return 0;
1975}
1976
1977/**
1978 * ice_ptp_adjtime_nonatomic - Do a non-atomic clock adjustment
1979 * @info: the driver's PTP info structure
1980 * @delta: Offset in nanoseconds to adjust the time by
1981 */
1982static int ice_ptp_adjtime_nonatomic(struct ptp_clock_info *info, s64 delta)
1983{
1984 struct timespec64 now, then;
1985 int ret;
1986
1987 then = ns_to_timespec64(delta);
1988 ret = ice_ptp_gettimex64(info, &now, NULL);
1989 if (ret)
1990 return ret;
1991 now = timespec64_add(now, then);
1992
1993 return ice_ptp_settime64(info, (const struct timespec64 *)&now);
1994}
1995
1996/**
1997 * ice_ptp_adjtime - Adjust the time of the clock by the indicated delta
1998 * @info: the driver's PTP info structure
1999 * @delta: Offset in nanoseconds to adjust the time by
2000 */
2001static int ice_ptp_adjtime(struct ptp_clock_info *info, s64 delta)
2002{
2003 struct ice_pf *pf = ptp_info_to_pf(info);
2004 struct ice_hw *hw = &pf->hw;
2005 struct device *dev;
2006 int err;
2007
2008 dev = ice_pf_to_dev(pf);
2009
2010 /* Hardware only supports atomic adjustments using signed 32-bit
2011 * integers. For any adjustment outside this range, perform
2012 * a non-atomic get->adjust->set flow.
2013 */
2014 if (delta > S32_MAX || delta < S32_MIN) {
2015 dev_dbg(dev, "delta = %lld, adjtime non-atomic\n", delta);
2016 return ice_ptp_adjtime_nonatomic(info, delta);
2017 }
2018
2019 if (!ice_ptp_lock(hw)) {
2020 dev_err(dev, "PTP failed to acquire semaphore in adjtime\n");
2021 return -EBUSY;
2022 }
2023
2024 /* Disable periodic outputs */
2025 ice_ptp_disable_all_clkout(pf);
2026
2027 err = ice_ptp_write_adj(pf, delta);
2028
2029 /* Reenable periodic outputs */
2030 ice_ptp_enable_all_clkout(pf);
2031
2032 ice_ptp_unlock(hw);
2033
2034 if (err) {
2035 dev_err(dev, "PTP failed to adjust time, err %d\n", err);
2036 return err;
2037 }
2038
2039 ice_ptp_reset_cached_phctime(pf);
2040
2041 return 0;
2042}
2043
2044#ifdef CONFIG_ICE_HWTS
2045/**
2046 * ice_ptp_get_syncdevicetime - Get the cross time stamp info
2047 * @device: Current device time
2048 * @system: System counter value read synchronously with device time
2049 * @ctx: Context provided by timekeeping code
2050 *
2051 * Read device and system (ART) clock simultaneously and return the corrected
2052 * clock values in ns.
2053 */
2054static int
2055ice_ptp_get_syncdevicetime(ktime_t *device,
2056 struct system_counterval_t *system,
2057 void *ctx)
2058{
2059 struct ice_pf *pf = (struct ice_pf *)ctx;
2060 struct ice_hw *hw = &pf->hw;
2061 u32 hh_lock, hh_art_ctl;
2062 int i;
2063
2064#define MAX_HH_HW_LOCK_TRIES 5
2065#define MAX_HH_CTL_LOCK_TRIES 100
2066
2067 for (i = 0; i < MAX_HH_HW_LOCK_TRIES; i++) {
2068 /* Get the HW lock */
2069 hh_lock = rd32(hw, PFHH_SEM + (PFTSYN_SEM_BYTES * hw->pf_id));
2070 if (hh_lock & PFHH_SEM_BUSY_M) {
2071 usleep_range(10000, 15000);
2072 continue;
2073 }
2074 break;
2075 }
2076 if (hh_lock & PFHH_SEM_BUSY_M) {
2077 dev_err(ice_pf_to_dev(pf), "PTP failed to get hh lock\n");
2078 return -EBUSY;
2079 }
2080
2081 /* Program cmd to master timer */
2082 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME);
2083
2084 /* Start the ART and device clock sync sequence */
2085 hh_art_ctl = rd32(hw, GLHH_ART_CTL);
2086 hh_art_ctl = hh_art_ctl | GLHH_ART_CTL_ACTIVE_M;
2087 wr32(hw, GLHH_ART_CTL, hh_art_ctl);
2088
2089 for (i = 0; i < MAX_HH_CTL_LOCK_TRIES; i++) {
2090 /* Wait for sync to complete */
2091 hh_art_ctl = rd32(hw, GLHH_ART_CTL);
2092 if (hh_art_ctl & GLHH_ART_CTL_ACTIVE_M) {
2093 udelay(1);
2094 continue;
2095 } else {
2096 u32 hh_ts_lo, hh_ts_hi, tmr_idx;
2097 u64 hh_ts;
2098
2099 tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc;
2100 /* Read ART time */
2101 hh_ts_lo = rd32(hw, GLHH_ART_TIME_L);
2102 hh_ts_hi = rd32(hw, GLHH_ART_TIME_H);
2103 hh_ts = ((u64)hh_ts_hi << 32) | hh_ts_lo;
2104 *system = convert_art_ns_to_tsc(hh_ts);
2105 /* Read Device source clock time */
2106 hh_ts_lo = rd32(hw, GLTSYN_HHTIME_L(tmr_idx));
2107 hh_ts_hi = rd32(hw, GLTSYN_HHTIME_H(tmr_idx));
2108 hh_ts = ((u64)hh_ts_hi << 32) | hh_ts_lo;
2109 *device = ns_to_ktime(hh_ts);
2110 break;
2111 }
2112 }
2113
2114 /* Clear the master timer */
2115 ice_ptp_src_cmd(hw, ICE_PTP_NOP);
2116
2117 /* Release HW lock */
2118 hh_lock = rd32(hw, PFHH_SEM + (PFTSYN_SEM_BYTES * hw->pf_id));
2119 hh_lock = hh_lock & ~PFHH_SEM_BUSY_M;
2120 wr32(hw, PFHH_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), hh_lock);
2121
2122 if (i == MAX_HH_CTL_LOCK_TRIES)
2123 return -ETIMEDOUT;
2124
2125 return 0;
2126}
2127
2128/**
2129 * ice_ptp_getcrosststamp_e82x - Capture a device cross timestamp
2130 * @info: the driver's PTP info structure
2131 * @cts: The memory to fill the cross timestamp info
2132 *
2133 * Capture a cross timestamp between the ART and the device PTP hardware
2134 * clock. Fill the cross timestamp information and report it back to the
2135 * caller.
2136 *
2137 * This is only valid for E822 and E823 devices which have support for
2138 * generating the cross timestamp via PCIe PTM.
2139 *
2140 * In order to correctly correlate the ART timestamp back to the TSC time, the
2141 * CPU must have X86_FEATURE_TSC_KNOWN_FREQ.
2142 */
2143static int
2144ice_ptp_getcrosststamp_e82x(struct ptp_clock_info *info,
2145 struct system_device_crosststamp *cts)
2146{
2147 struct ice_pf *pf = ptp_info_to_pf(info);
2148
2149 return get_device_system_crosststamp(ice_ptp_get_syncdevicetime,
2150 pf, NULL, cts);
2151}
2152#endif /* CONFIG_ICE_HWTS */
2153
2154/**
2155 * ice_ptp_get_ts_config - ioctl interface to read the timestamping config
2156 * @pf: Board private structure
2157 * @ifr: ioctl data
2158 *
2159 * Copy the timestamping config to user buffer
2160 */
2161int ice_ptp_get_ts_config(struct ice_pf *pf, struct ifreq *ifr)
2162{
2163 struct hwtstamp_config *config;
2164
2165 if (!test_bit(ICE_FLAG_PTP, pf->flags))
2166 return -EIO;
2167
2168 config = &pf->ptp.tstamp_config;
2169
2170 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
2171 -EFAULT : 0;
2172}
2173
2174/**
2175 * ice_ptp_set_timestamp_mode - Setup driver for requested timestamp mode
2176 * @pf: Board private structure
2177 * @config: hwtstamp settings requested or saved
2178 */
2179static int
2180ice_ptp_set_timestamp_mode(struct ice_pf *pf, struct hwtstamp_config *config)
2181{
2182 switch (config->tx_type) {
2183 case HWTSTAMP_TX_OFF:
2184 pf->ptp.tstamp_config.tx_type = HWTSTAMP_TX_OFF;
2185 break;
2186 case HWTSTAMP_TX_ON:
2187 pf->ptp.tstamp_config.tx_type = HWTSTAMP_TX_ON;
2188 break;
2189 default:
2190 return -ERANGE;
2191 }
2192
2193 switch (config->rx_filter) {
2194 case HWTSTAMP_FILTER_NONE:
2195 pf->ptp.tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
2196 break;
2197 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2198 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2199 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2200 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2201 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2202 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2203 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2204 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2205 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2206 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2207 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2208 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2209 case HWTSTAMP_FILTER_NTP_ALL:
2210 case HWTSTAMP_FILTER_ALL:
2211 pf->ptp.tstamp_config.rx_filter = HWTSTAMP_FILTER_ALL;
2212 break;
2213 default:
2214 return -ERANGE;
2215 }
2216
2217 /* Immediately update the device timestamping mode */
2218 ice_ptp_restore_timestamp_mode(pf);
2219
2220 return 0;
2221}
2222
2223/**
2224 * ice_ptp_set_ts_config - ioctl interface to control the timestamping
2225 * @pf: Board private structure
2226 * @ifr: ioctl data
2227 *
2228 * Get the user config and store it
2229 */
2230int ice_ptp_set_ts_config(struct ice_pf *pf, struct ifreq *ifr)
2231{
2232 struct hwtstamp_config config;
2233 int err;
2234
2235 if (!test_bit(ICE_FLAG_PTP, pf->flags))
2236 return -EAGAIN;
2237
2238 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2239 return -EFAULT;
2240
2241 err = ice_ptp_set_timestamp_mode(pf, &config);
2242 if (err)
2243 return err;
2244
2245 /* Return the actual configuration set */
2246 config = pf->ptp.tstamp_config;
2247
2248 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
2249 -EFAULT : 0;
2250}
2251
2252/**
2253 * ice_ptp_get_rx_hwts - Get packet Rx timestamp in ns
2254 * @rx_desc: Receive descriptor
2255 * @pkt_ctx: Packet context to get the cached time
2256 *
2257 * The driver receives a notification in the receive descriptor with timestamp.
2258 */
2259u64 ice_ptp_get_rx_hwts(const union ice_32b_rx_flex_desc *rx_desc,
2260 const struct ice_pkt_ctx *pkt_ctx)
2261{
2262 u64 ts_ns, cached_time;
2263 u32 ts_high;
2264
2265 if (!(rx_desc->wb.time_stamp_low & ICE_PTP_TS_VALID))
2266 return 0;
2267
2268 cached_time = READ_ONCE(pkt_ctx->cached_phctime);
2269
2270 /* Do not report a timestamp if we don't have a cached PHC time */
2271 if (!cached_time)
2272 return 0;
2273
2274 /* Use ice_ptp_extend_32b_ts directly, using the ring-specific cached
2275 * PHC value, rather than accessing the PF. This also allows us to
2276 * simply pass the upper 32bits of nanoseconds directly. Calling
2277 * ice_ptp_extend_40b_ts is unnecessary as it would just discard these
2278 * bits itself.
2279 */
2280 ts_high = le32_to_cpu(rx_desc->wb.flex_ts.ts_high);
2281 ts_ns = ice_ptp_extend_32b_ts(cached_time, ts_high);
2282
2283 return ts_ns;
2284}
2285
2286/**
2287 * ice_ptp_disable_sma_pins_e810t - Disable E810-T SMA pins
2288 * @pf: pointer to the PF structure
2289 * @info: PTP clock info structure
2290 *
2291 * Disable the OS access to the SMA pins. Called to clear out the OS
2292 * indications of pin support when we fail to setup the E810-T SMA control
2293 * register.
2294 */
2295static void
2296ice_ptp_disable_sma_pins_e810t(struct ice_pf *pf, struct ptp_clock_info *info)
2297{
2298 struct device *dev = ice_pf_to_dev(pf);
2299
2300 dev_warn(dev, "Failed to configure E810-T SMA pin control\n");
2301
2302 info->enable = NULL;
2303 info->verify = NULL;
2304 info->n_pins = 0;
2305 info->n_ext_ts = 0;
2306 info->n_per_out = 0;
2307}
2308
2309/**
2310 * ice_ptp_setup_sma_pins_e810t - Setup the SMA pins
2311 * @pf: pointer to the PF structure
2312 * @info: PTP clock info structure
2313 *
2314 * Finish setting up the SMA pins by allocating pin_config, and setting it up
2315 * according to the current status of the SMA. On failure, disable all of the
2316 * extended SMA pin support.
2317 */
2318static void
2319ice_ptp_setup_sma_pins_e810t(struct ice_pf *pf, struct ptp_clock_info *info)
2320{
2321 struct device *dev = ice_pf_to_dev(pf);
2322 int err;
2323
2324 /* Allocate memory for kernel pins interface */
2325 info->pin_config = devm_kcalloc(dev, info->n_pins,
2326 sizeof(*info->pin_config), GFP_KERNEL);
2327 if (!info->pin_config) {
2328 ice_ptp_disable_sma_pins_e810t(pf, info);
2329 return;
2330 }
2331
2332 /* Read current SMA status */
2333 err = ice_get_sma_config_e810t(&pf->hw, info->pin_config);
2334 if (err)
2335 ice_ptp_disable_sma_pins_e810t(pf, info);
2336}
2337
2338/**
2339 * ice_ptp_setup_pins_e810 - Setup PTP pins in sysfs
2340 * @pf: pointer to the PF instance
2341 * @info: PTP clock capabilities
2342 */
2343static void
2344ice_ptp_setup_pins_e810(struct ice_pf *pf, struct ptp_clock_info *info)
2345{
2346 if (ice_is_feature_supported(pf, ICE_F_SMA_CTRL)) {
2347 info->n_ext_ts = N_EXT_TS_E810;
2348 info->n_per_out = N_PER_OUT_E810T;
2349 info->n_pins = NUM_PTP_PINS_E810T;
2350 info->verify = ice_verify_pin_e810t;
2351
2352 /* Complete setup of the SMA pins */
2353 ice_ptp_setup_sma_pins_e810t(pf, info);
2354 } else if (ice_is_e810t(&pf->hw)) {
2355 info->n_ext_ts = N_EXT_TS_NO_SMA_E810T;
2356 info->n_per_out = N_PER_OUT_NO_SMA_E810T;
2357 } else {
2358 info->n_per_out = N_PER_OUT_E810;
2359 info->n_ext_ts = N_EXT_TS_E810;
2360 }
2361}
2362
2363/**
2364 * ice_ptp_setup_pins_e823 - Setup PTP pins in sysfs
2365 * @pf: pointer to the PF instance
2366 * @info: PTP clock capabilities
2367 */
2368static void
2369ice_ptp_setup_pins_e823(struct ice_pf *pf, struct ptp_clock_info *info)
2370{
2371 info->pps = 1;
2372 info->n_per_out = 0;
2373 info->n_ext_ts = 1;
2374}
2375
2376/**
2377 * ice_ptp_set_funcs_e82x - Set specialized functions for E82x support
2378 * @pf: Board private structure
2379 * @info: PTP info to fill
2380 *
2381 * Assign functions to the PTP capabiltiies structure for E82x devices.
2382 * Functions which operate across all device families should be set directly
2383 * in ice_ptp_set_caps. Only add functions here which are distinct for E82x
2384 * devices.
2385 */
2386static void
2387ice_ptp_set_funcs_e82x(struct ice_pf *pf, struct ptp_clock_info *info)
2388{
2389#ifdef CONFIG_ICE_HWTS
2390 if (boot_cpu_has(X86_FEATURE_ART) &&
2391 boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ))
2392 info->getcrosststamp = ice_ptp_getcrosststamp_e82x;
2393#endif /* CONFIG_ICE_HWTS */
2394}
2395
2396/**
2397 * ice_ptp_set_funcs_e810 - Set specialized functions for E810 support
2398 * @pf: Board private structure
2399 * @info: PTP info to fill
2400 *
2401 * Assign functions to the PTP capabiltiies structure for E810 devices.
2402 * Functions which operate across all device families should be set directly
2403 * in ice_ptp_set_caps. Only add functions here which are distinct for e810
2404 * devices.
2405 */
2406static void
2407ice_ptp_set_funcs_e810(struct ice_pf *pf, struct ptp_clock_info *info)
2408{
2409 info->enable = ice_ptp_gpio_enable_e810;
2410 ice_ptp_setup_pins_e810(pf, info);
2411}
2412
2413/**
2414 * ice_ptp_set_funcs_e823 - Set specialized functions for E823 support
2415 * @pf: Board private structure
2416 * @info: PTP info to fill
2417 *
2418 * Assign functions to the PTP capabiltiies structure for E823 devices.
2419 * Functions which operate across all device families should be set directly
2420 * in ice_ptp_set_caps. Only add functions here which are distinct for e823
2421 * devices.
2422 */
2423static void
2424ice_ptp_set_funcs_e823(struct ice_pf *pf, struct ptp_clock_info *info)
2425{
2426 ice_ptp_set_funcs_e82x(pf, info);
2427
2428 info->enable = ice_ptp_gpio_enable_e823;
2429 ice_ptp_setup_pins_e823(pf, info);
2430}
2431
2432/**
2433 * ice_ptp_set_caps - Set PTP capabilities
2434 * @pf: Board private structure
2435 */
2436static void ice_ptp_set_caps(struct ice_pf *pf)
2437{
2438 struct ptp_clock_info *info = &pf->ptp.info;
2439 struct device *dev = ice_pf_to_dev(pf);
2440
2441 snprintf(info->name, sizeof(info->name) - 1, "%s-%s-clk",
2442 dev_driver_string(dev), dev_name(dev));
2443 info->owner = THIS_MODULE;
2444 info->max_adj = 100000000;
2445 info->adjtime = ice_ptp_adjtime;
2446 info->adjfine = ice_ptp_adjfine;
2447 info->gettimex64 = ice_ptp_gettimex64;
2448 info->settime64 = ice_ptp_settime64;
2449
2450 if (ice_is_e810(&pf->hw))
2451 ice_ptp_set_funcs_e810(pf, info);
2452 else if (ice_is_e823(&pf->hw))
2453 ice_ptp_set_funcs_e823(pf, info);
2454 else
2455 ice_ptp_set_funcs_e82x(pf, info);
2456}
2457
2458/**
2459 * ice_ptp_create_clock - Create PTP clock device for userspace
2460 * @pf: Board private structure
2461 *
2462 * This function creates a new PTP clock device. It only creates one if we
2463 * don't already have one. Will return error if it can't create one, but success
2464 * if we already have a device. Should be used by ice_ptp_init to create clock
2465 * initially, and prevent global resets from creating new clock devices.
2466 */
2467static long ice_ptp_create_clock(struct ice_pf *pf)
2468{
2469 struct ptp_clock_info *info;
2470 struct device *dev;
2471
2472 /* No need to create a clock device if we already have one */
2473 if (pf->ptp.clock)
2474 return 0;
2475
2476 ice_ptp_set_caps(pf);
2477
2478 info = &pf->ptp.info;
2479 dev = ice_pf_to_dev(pf);
2480
2481 /* Attempt to register the clock before enabling the hardware. */
2482 pf->ptp.clock = ptp_clock_register(info, dev);
2483 if (IS_ERR(pf->ptp.clock)) {
2484 dev_err(ice_pf_to_dev(pf), "Failed to register PTP clock device");
2485 return PTR_ERR(pf->ptp.clock);
2486 }
2487
2488 return 0;
2489}
2490
2491/**
2492 * ice_ptp_request_ts - Request an available Tx timestamp index
2493 * @tx: the PTP Tx timestamp tracker to request from
2494 * @skb: the SKB to associate with this timestamp request
2495 */
2496s8 ice_ptp_request_ts(struct ice_ptp_tx *tx, struct sk_buff *skb)
2497{
2498 unsigned long flags;
2499 u8 idx;
2500
2501 spin_lock_irqsave(&tx->lock, flags);
2502
2503 /* Check that this tracker is accepting new timestamp requests */
2504 if (!ice_ptp_is_tx_tracker_up(tx)) {
2505 spin_unlock_irqrestore(&tx->lock, flags);
2506 return -1;
2507 }
2508
2509 /* Find and set the first available index */
2510 idx = find_next_zero_bit(tx->in_use, tx->len,
2511 tx->last_ll_ts_idx_read + 1);
2512 if (idx == tx->len)
2513 idx = find_first_zero_bit(tx->in_use, tx->len);
2514
2515 if (idx < tx->len) {
2516 /* We got a valid index that no other thread could have set. Store
2517 * a reference to the skb and the start time to allow discarding old
2518 * requests.
2519 */
2520 set_bit(idx, tx->in_use);
2521 clear_bit(idx, tx->stale);
2522 tx->tstamps[idx].start = jiffies;
2523 tx->tstamps[idx].skb = skb_get(skb);
2524 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2525 ice_trace(tx_tstamp_request, skb, idx);
2526 }
2527
2528 spin_unlock_irqrestore(&tx->lock, flags);
2529
2530 /* return the appropriate PHY timestamp register index, -1 if no
2531 * indexes were available.
2532 */
2533 if (idx >= tx->len)
2534 return -1;
2535 else
2536 return idx + tx->offset;
2537}
2538
2539/**
2540 * ice_ptp_process_ts - Process the PTP Tx timestamps
2541 * @pf: Board private structure
2542 *
2543 * Returns: ICE_TX_TSTAMP_WORK_PENDING if there are any outstanding Tx
2544 * timestamps that need processing, and ICE_TX_TSTAMP_WORK_DONE otherwise.
2545 */
2546enum ice_tx_tstamp_work ice_ptp_process_ts(struct ice_pf *pf)
2547{
2548 switch (pf->ptp.tx_interrupt_mode) {
2549 case ICE_PTP_TX_INTERRUPT_NONE:
2550 /* This device has the clock owner handle timestamps for it */
2551 return ICE_TX_TSTAMP_WORK_DONE;
2552 case ICE_PTP_TX_INTERRUPT_SELF:
2553 /* This device handles its own timestamps */
2554 return ice_ptp_tx_tstamp(&pf->ptp.port.tx);
2555 case ICE_PTP_TX_INTERRUPT_ALL:
2556 /* This device handles timestamps for all ports */
2557 return ice_ptp_tx_tstamp_owner(pf);
2558 default:
2559 WARN_ONCE(1, "Unexpected Tx timestamp interrupt mode %u\n",
2560 pf->ptp.tx_interrupt_mode);
2561 return ICE_TX_TSTAMP_WORK_DONE;
2562 }
2563}
2564
2565/**
2566 * ice_ptp_maybe_trigger_tx_interrupt - Trigger Tx timstamp interrupt
2567 * @pf: Board private structure
2568 *
2569 * The device PHY issues Tx timestamp interrupts to the driver for processing
2570 * timestamp data from the PHY. It will not interrupt again until all
2571 * current timestamp data is read. In rare circumstances, it is possible that
2572 * the driver fails to read all outstanding data.
2573 *
2574 * To avoid getting permanently stuck, periodically check if the PHY has
2575 * outstanding timestamp data. If so, trigger an interrupt from software to
2576 * process this data.
2577 */
2578static void ice_ptp_maybe_trigger_tx_interrupt(struct ice_pf *pf)
2579{
2580 struct device *dev = ice_pf_to_dev(pf);
2581 struct ice_hw *hw = &pf->hw;
2582 bool trigger_oicr = false;
2583 unsigned int i;
2584
2585 if (ice_is_e810(hw))
2586 return;
2587
2588 if (!ice_pf_src_tmr_owned(pf))
2589 return;
2590
2591 for (i = 0; i < ICE_MAX_QUAD; i++) {
2592 u64 tstamp_ready;
2593 int err;
2594
2595 err = ice_get_phy_tx_tstamp_ready(&pf->hw, i, &tstamp_ready);
2596 if (!err && tstamp_ready) {
2597 trigger_oicr = true;
2598 break;
2599 }
2600 }
2601
2602 if (trigger_oicr) {
2603 /* Trigger a software interrupt, to ensure this data
2604 * gets processed.
2605 */
2606 dev_dbg(dev, "PTP periodic task detected waiting timestamps. Triggering Tx timestamp interrupt now.\n");
2607
2608 wr32(hw, PFINT_OICR, PFINT_OICR_TSYN_TX_M);
2609 ice_flush(hw);
2610 }
2611}
2612
2613static void ice_ptp_periodic_work(struct kthread_work *work)
2614{
2615 struct ice_ptp *ptp = container_of(work, struct ice_ptp, work.work);
2616 struct ice_pf *pf = container_of(ptp, struct ice_pf, ptp);
2617 int err;
2618
2619 if (!test_bit(ICE_FLAG_PTP, pf->flags))
2620 return;
2621
2622 err = ice_ptp_update_cached_phctime(pf);
2623
2624 ice_ptp_maybe_trigger_tx_interrupt(pf);
2625
2626 /* Run twice a second or reschedule if phc update failed */
2627 kthread_queue_delayed_work(ptp->kworker, &ptp->work,
2628 msecs_to_jiffies(err ? 10 : 500));
2629}
2630
2631/**
2632 * ice_ptp_reset - Initialize PTP hardware clock support after reset
2633 * @pf: Board private structure
2634 */
2635void ice_ptp_reset(struct ice_pf *pf)
2636{
2637 struct ice_ptp *ptp = &pf->ptp;
2638 struct ice_hw *hw = &pf->hw;
2639 struct timespec64 ts;
2640 int err, itr = 1;
2641 u64 time_diff;
2642
2643 if (test_bit(ICE_PFR_REQ, pf->state) ||
2644 !ice_pf_src_tmr_owned(pf))
2645 goto pfr;
2646
2647 err = ice_ptp_init_phc(hw);
2648 if (err)
2649 goto err;
2650
2651 /* Acquire the global hardware lock */
2652 if (!ice_ptp_lock(hw)) {
2653 err = -EBUSY;
2654 goto err;
2655 }
2656
2657 /* Write the increment time value to PHY and LAN */
2658 err = ice_ptp_write_incval(hw, ice_base_incval(pf));
2659 if (err) {
2660 ice_ptp_unlock(hw);
2661 goto err;
2662 }
2663
2664 /* Write the initial Time value to PHY and LAN using the cached PHC
2665 * time before the reset and time difference between stopping and
2666 * starting the clock.
2667 */
2668 if (ptp->cached_phc_time) {
2669 time_diff = ktime_get_real_ns() - ptp->reset_time;
2670 ts = ns_to_timespec64(ptp->cached_phc_time + time_diff);
2671 } else {
2672 ts = ktime_to_timespec64(ktime_get_real());
2673 }
2674 err = ice_ptp_write_init(pf, &ts);
2675 if (err) {
2676 ice_ptp_unlock(hw);
2677 goto err;
2678 }
2679
2680 /* Release the global hardware lock */
2681 ice_ptp_unlock(hw);
2682
2683 if (!ice_is_e810(hw)) {
2684 /* Enable quad interrupts */
2685 err = ice_ptp_tx_ena_intr(pf, true, itr);
2686 if (err)
2687 goto err;
2688 }
2689
2690pfr:
2691 /* Init Tx structures */
2692 if (ice_is_e810(&pf->hw)) {
2693 err = ice_ptp_init_tx_e810(pf, &ptp->port.tx);
2694 } else {
2695 kthread_init_delayed_work(&ptp->port.ov_work,
2696 ice_ptp_wait_for_offsets);
2697 err = ice_ptp_init_tx_e82x(pf, &ptp->port.tx,
2698 ptp->port.port_num);
2699 }
2700 if (err)
2701 goto err;
2702
2703 set_bit(ICE_FLAG_PTP, pf->flags);
2704
2705 /* Restart the PHY timestamping block */
2706 if (!test_bit(ICE_PFR_REQ, pf->state) &&
2707 ice_pf_src_tmr_owned(pf))
2708 ice_ptp_restart_all_phy(pf);
2709
2710 /* Start periodic work going */
2711 kthread_queue_delayed_work(ptp->kworker, &ptp->work, 0);
2712
2713 dev_info(ice_pf_to_dev(pf), "PTP reset successful\n");
2714 return;
2715
2716err:
2717 dev_err(ice_pf_to_dev(pf), "PTP reset failed %d\n", err);
2718}
2719
2720/**
2721 * ice_ptp_aux_dev_to_aux_pf - Get auxiliary PF handle for the auxiliary device
2722 * @aux_dev: auxiliary device to get the auxiliary PF for
2723 */
2724static struct ice_pf *
2725ice_ptp_aux_dev_to_aux_pf(struct auxiliary_device *aux_dev)
2726{
2727 struct ice_ptp_port *aux_port;
2728 struct ice_ptp *aux_ptp;
2729
2730 aux_port = container_of(aux_dev, struct ice_ptp_port, aux_dev);
2731 aux_ptp = container_of(aux_port, struct ice_ptp, port);
2732
2733 return container_of(aux_ptp, struct ice_pf, ptp);
2734}
2735
2736/**
2737 * ice_ptp_aux_dev_to_owner_pf - Get PF handle for the auxiliary device
2738 * @aux_dev: auxiliary device to get the PF for
2739 */
2740static struct ice_pf *
2741ice_ptp_aux_dev_to_owner_pf(struct auxiliary_device *aux_dev)
2742{
2743 struct ice_ptp_port_owner *ports_owner;
2744 struct auxiliary_driver *aux_drv;
2745 struct ice_ptp *owner_ptp;
2746
2747 if (!aux_dev->dev.driver)
2748 return NULL;
2749
2750 aux_drv = to_auxiliary_drv(aux_dev->dev.driver);
2751 ports_owner = container_of(aux_drv, struct ice_ptp_port_owner,
2752 aux_driver);
2753 owner_ptp = container_of(ports_owner, struct ice_ptp, ports_owner);
2754 return container_of(owner_ptp, struct ice_pf, ptp);
2755}
2756
2757/**
2758 * ice_ptp_auxbus_probe - Probe auxiliary devices
2759 * @aux_dev: PF's auxiliary device
2760 * @id: Auxiliary device ID
2761 */
2762static int ice_ptp_auxbus_probe(struct auxiliary_device *aux_dev,
2763 const struct auxiliary_device_id *id)
2764{
2765 struct ice_pf *owner_pf = ice_ptp_aux_dev_to_owner_pf(aux_dev);
2766 struct ice_pf *aux_pf = ice_ptp_aux_dev_to_aux_pf(aux_dev);
2767
2768 if (WARN_ON(!owner_pf))
2769 return -ENODEV;
2770
2771 INIT_LIST_HEAD(&aux_pf->ptp.port.list_member);
2772 mutex_lock(&owner_pf->ptp.ports_owner.lock);
2773 list_add(&aux_pf->ptp.port.list_member,
2774 &owner_pf->ptp.ports_owner.ports);
2775 mutex_unlock(&owner_pf->ptp.ports_owner.lock);
2776
2777 return 0;
2778}
2779
2780/**
2781 * ice_ptp_auxbus_remove - Remove auxiliary devices from the bus
2782 * @aux_dev: PF's auxiliary device
2783 */
2784static void ice_ptp_auxbus_remove(struct auxiliary_device *aux_dev)
2785{
2786 struct ice_pf *owner_pf = ice_ptp_aux_dev_to_owner_pf(aux_dev);
2787 struct ice_pf *aux_pf = ice_ptp_aux_dev_to_aux_pf(aux_dev);
2788
2789 mutex_lock(&owner_pf->ptp.ports_owner.lock);
2790 list_del(&aux_pf->ptp.port.list_member);
2791 mutex_unlock(&owner_pf->ptp.ports_owner.lock);
2792}
2793
2794/**
2795 * ice_ptp_auxbus_shutdown
2796 * @aux_dev: PF's auxiliary device
2797 */
2798static void ice_ptp_auxbus_shutdown(struct auxiliary_device *aux_dev)
2799{
2800 /* Doing nothing here, but handle to auxbus driver must be satisfied */
2801}
2802
2803/**
2804 * ice_ptp_auxbus_suspend
2805 * @aux_dev: PF's auxiliary device
2806 * @state: power management state indicator
2807 */
2808static int
2809ice_ptp_auxbus_suspend(struct auxiliary_device *aux_dev, pm_message_t state)
2810{
2811 /* Doing nothing here, but handle to auxbus driver must be satisfied */
2812 return 0;
2813}
2814
2815/**
2816 * ice_ptp_auxbus_resume
2817 * @aux_dev: PF's auxiliary device
2818 */
2819static int ice_ptp_auxbus_resume(struct auxiliary_device *aux_dev)
2820{
2821 /* Doing nothing here, but handle to auxbus driver must be satisfied */
2822 return 0;
2823}
2824
2825/**
2826 * ice_ptp_auxbus_create_id_table - Create auxiliary device ID table
2827 * @pf: Board private structure
2828 * @name: auxiliary bus driver name
2829 */
2830static struct auxiliary_device_id *
2831ice_ptp_auxbus_create_id_table(struct ice_pf *pf, const char *name)
2832{
2833 struct auxiliary_device_id *ids;
2834
2835 /* Second id left empty to terminate the array */
2836 ids = devm_kcalloc(ice_pf_to_dev(pf), 2,
2837 sizeof(struct auxiliary_device_id), GFP_KERNEL);
2838 if (!ids)
2839 return NULL;
2840
2841 snprintf(ids[0].name, sizeof(ids[0].name), "ice.%s", name);
2842
2843 return ids;
2844}
2845
2846/**
2847 * ice_ptp_register_auxbus_driver - Register PTP auxiliary bus driver
2848 * @pf: Board private structure
2849 */
2850static int ice_ptp_register_auxbus_driver(struct ice_pf *pf)
2851{
2852 struct auxiliary_driver *aux_driver;
2853 struct ice_ptp *ptp;
2854 struct device *dev;
2855 char *name;
2856 int err;
2857
2858 ptp = &pf->ptp;
2859 dev = ice_pf_to_dev(pf);
2860 aux_driver = &ptp->ports_owner.aux_driver;
2861 INIT_LIST_HEAD(&ptp->ports_owner.ports);
2862 mutex_init(&ptp->ports_owner.lock);
2863 name = devm_kasprintf(dev, GFP_KERNEL, "ptp_aux_dev_%u_%u_clk%u",
2864 pf->pdev->bus->number, PCI_SLOT(pf->pdev->devfn),
2865 ice_get_ptp_src_clock_index(&pf->hw));
2866 if (!name)
2867 return -ENOMEM;
2868
2869 aux_driver->name = name;
2870 aux_driver->shutdown = ice_ptp_auxbus_shutdown;
2871 aux_driver->suspend = ice_ptp_auxbus_suspend;
2872 aux_driver->remove = ice_ptp_auxbus_remove;
2873 aux_driver->resume = ice_ptp_auxbus_resume;
2874 aux_driver->probe = ice_ptp_auxbus_probe;
2875 aux_driver->id_table = ice_ptp_auxbus_create_id_table(pf, name);
2876 if (!aux_driver->id_table)
2877 return -ENOMEM;
2878
2879 err = auxiliary_driver_register(aux_driver);
2880 if (err) {
2881 devm_kfree(dev, aux_driver->id_table);
2882 dev_err(dev, "Failed registering aux_driver, name <%s>\n",
2883 name);
2884 }
2885
2886 return err;
2887}
2888
2889/**
2890 * ice_ptp_unregister_auxbus_driver - Unregister PTP auxiliary bus driver
2891 * @pf: Board private structure
2892 */
2893static void ice_ptp_unregister_auxbus_driver(struct ice_pf *pf)
2894{
2895 struct auxiliary_driver *aux_driver = &pf->ptp.ports_owner.aux_driver;
2896
2897 auxiliary_driver_unregister(aux_driver);
2898 devm_kfree(ice_pf_to_dev(pf), aux_driver->id_table);
2899
2900 mutex_destroy(&pf->ptp.ports_owner.lock);
2901}
2902
2903/**
2904 * ice_ptp_clock_index - Get the PTP clock index for this device
2905 * @pf: Board private structure
2906 *
2907 * Returns: the PTP clock index associated with this PF, or -1 if no PTP clock
2908 * is associated.
2909 */
2910int ice_ptp_clock_index(struct ice_pf *pf)
2911{
2912 struct auxiliary_device *aux_dev;
2913 struct ice_pf *owner_pf;
2914 struct ptp_clock *clock;
2915
2916 aux_dev = &pf->ptp.port.aux_dev;
2917 owner_pf = ice_ptp_aux_dev_to_owner_pf(aux_dev);
2918 if (!owner_pf)
2919 return -1;
2920 clock = owner_pf->ptp.clock;
2921
2922 return clock ? ptp_clock_index(clock) : -1;
2923}
2924
2925/**
2926 * ice_ptp_prepare_for_reset - Prepare PTP for reset
2927 * @pf: Board private structure
2928 */
2929void ice_ptp_prepare_for_reset(struct ice_pf *pf)
2930{
2931 struct ice_ptp *ptp = &pf->ptp;
2932 u8 src_tmr;
2933
2934 clear_bit(ICE_FLAG_PTP, pf->flags);
2935
2936 /* Disable timestamping for both Tx and Rx */
2937 ice_ptp_disable_timestamp_mode(pf);
2938
2939 kthread_cancel_delayed_work_sync(&ptp->work);
2940
2941 if (test_bit(ICE_PFR_REQ, pf->state))
2942 return;
2943
2944 ice_ptp_release_tx_tracker(pf, &pf->ptp.port.tx);
2945
2946 /* Disable periodic outputs */
2947 ice_ptp_disable_all_clkout(pf);
2948
2949 src_tmr = ice_get_ptp_src_clock_index(&pf->hw);
2950
2951 /* Disable source clock */
2952 wr32(&pf->hw, GLTSYN_ENA(src_tmr), (u32)~GLTSYN_ENA_TSYN_ENA_M);
2953
2954 /* Acquire PHC and system timer to restore after reset */
2955 ptp->reset_time = ktime_get_real_ns();
2956}
2957
2958/**
2959 * ice_ptp_init_owner - Initialize PTP_1588_CLOCK device
2960 * @pf: Board private structure
2961 *
2962 * Setup and initialize a PTP clock device that represents the device hardware
2963 * clock. Save the clock index for other functions connected to the same
2964 * hardware resource.
2965 */
2966static int ice_ptp_init_owner(struct ice_pf *pf)
2967{
2968 struct ice_hw *hw = &pf->hw;
2969 struct timespec64 ts;
2970 int err, itr = 1;
2971
2972 err = ice_ptp_init_phc(hw);
2973 if (err) {
2974 dev_err(ice_pf_to_dev(pf), "Failed to initialize PHC, err %d\n",
2975 err);
2976 return err;
2977 }
2978
2979 /* Acquire the global hardware lock */
2980 if (!ice_ptp_lock(hw)) {
2981 err = -EBUSY;
2982 goto err_exit;
2983 }
2984
2985 /* Write the increment time value to PHY and LAN */
2986 err = ice_ptp_write_incval(hw, ice_base_incval(pf));
2987 if (err) {
2988 ice_ptp_unlock(hw);
2989 goto err_exit;
2990 }
2991
2992 ts = ktime_to_timespec64(ktime_get_real());
2993 /* Write the initial Time value to PHY and LAN */
2994 err = ice_ptp_write_init(pf, &ts);
2995 if (err) {
2996 ice_ptp_unlock(hw);
2997 goto err_exit;
2998 }
2999
3000 /* Release the global hardware lock */
3001 ice_ptp_unlock(hw);
3002
3003 if (!ice_is_e810(hw)) {
3004 /* Enable quad interrupts */
3005 err = ice_ptp_tx_ena_intr(pf, true, itr);
3006 if (err)
3007 goto err_exit;
3008 }
3009
3010 /* Ensure we have a clock device */
3011 err = ice_ptp_create_clock(pf);
3012 if (err)
3013 goto err_clk;
3014
3015 err = ice_ptp_register_auxbus_driver(pf);
3016 if (err) {
3017 dev_err(ice_pf_to_dev(pf), "Failed to register PTP auxbus driver");
3018 goto err_aux;
3019 }
3020
3021 return 0;
3022err_aux:
3023 ptp_clock_unregister(pf->ptp.clock);
3024err_clk:
3025 pf->ptp.clock = NULL;
3026err_exit:
3027 return err;
3028}
3029
3030/**
3031 * ice_ptp_init_work - Initialize PTP work threads
3032 * @pf: Board private structure
3033 * @ptp: PF PTP structure
3034 */
3035static int ice_ptp_init_work(struct ice_pf *pf, struct ice_ptp *ptp)
3036{
3037 struct kthread_worker *kworker;
3038
3039 /* Initialize work functions */
3040 kthread_init_delayed_work(&ptp->work, ice_ptp_periodic_work);
3041
3042 /* Allocate a kworker for handling work required for the ports
3043 * connected to the PTP hardware clock.
3044 */
3045 kworker = kthread_create_worker(0, "ice-ptp-%s",
3046 dev_name(ice_pf_to_dev(pf)));
3047 if (IS_ERR(kworker))
3048 return PTR_ERR(kworker);
3049
3050 ptp->kworker = kworker;
3051
3052 /* Start periodic work going */
3053 kthread_queue_delayed_work(ptp->kworker, &ptp->work, 0);
3054
3055 return 0;
3056}
3057
3058/**
3059 * ice_ptp_init_port - Initialize PTP port structure
3060 * @pf: Board private structure
3061 * @ptp_port: PTP port structure
3062 */
3063static int ice_ptp_init_port(struct ice_pf *pf, struct ice_ptp_port *ptp_port)
3064{
3065 struct ice_hw *hw = &pf->hw;
3066
3067 mutex_init(&ptp_port->ps_lock);
3068
3069 switch (hw->phy_model) {
3070 case ICE_PHY_E810:
3071 return ice_ptp_init_tx_e810(pf, &ptp_port->tx);
3072 case ICE_PHY_E82X:
3073 kthread_init_delayed_work(&ptp_port->ov_work,
3074 ice_ptp_wait_for_offsets);
3075
3076 return ice_ptp_init_tx_e82x(pf, &ptp_port->tx,
3077 ptp_port->port_num);
3078 default:
3079 return -ENODEV;
3080 }
3081}
3082
3083/**
3084 * ice_ptp_release_auxbus_device
3085 * @dev: device that utilizes the auxbus
3086 */
3087static void ice_ptp_release_auxbus_device(struct device *dev)
3088{
3089 /* Doing nothing here, but handle to auxbux device must be satisfied */
3090}
3091
3092/**
3093 * ice_ptp_create_auxbus_device - Create PTP auxiliary bus device
3094 * @pf: Board private structure
3095 */
3096static int ice_ptp_create_auxbus_device(struct ice_pf *pf)
3097{
3098 struct auxiliary_device *aux_dev;
3099 struct ice_ptp *ptp;
3100 struct device *dev;
3101 char *name;
3102 int err;
3103 u32 id;
3104
3105 ptp = &pf->ptp;
3106 id = ptp->port.port_num;
3107 dev = ice_pf_to_dev(pf);
3108
3109 aux_dev = &ptp->port.aux_dev;
3110
3111 name = devm_kasprintf(dev, GFP_KERNEL, "ptp_aux_dev_%u_%u_clk%u",
3112 pf->pdev->bus->number, PCI_SLOT(pf->pdev->devfn),
3113 ice_get_ptp_src_clock_index(&pf->hw));
3114 if (!name)
3115 return -ENOMEM;
3116
3117 aux_dev->name = name;
3118 aux_dev->id = id;
3119 aux_dev->dev.release = ice_ptp_release_auxbus_device;
3120 aux_dev->dev.parent = dev;
3121
3122 err = auxiliary_device_init(aux_dev);
3123 if (err)
3124 goto aux_err;
3125
3126 err = auxiliary_device_add(aux_dev);
3127 if (err) {
3128 auxiliary_device_uninit(aux_dev);
3129 goto aux_err;
3130 }
3131
3132 return 0;
3133aux_err:
3134 dev_err(dev, "Failed to create PTP auxiliary bus device <%s>\n", name);
3135 devm_kfree(dev, name);
3136 return err;
3137}
3138
3139/**
3140 * ice_ptp_remove_auxbus_device - Remove PTP auxiliary bus device
3141 * @pf: Board private structure
3142 */
3143static void ice_ptp_remove_auxbus_device(struct ice_pf *pf)
3144{
3145 struct auxiliary_device *aux_dev = &pf->ptp.port.aux_dev;
3146
3147 auxiliary_device_delete(aux_dev);
3148 auxiliary_device_uninit(aux_dev);
3149
3150 memset(aux_dev, 0, sizeof(*aux_dev));
3151}
3152
3153/**
3154 * ice_ptp_init_tx_interrupt_mode - Initialize device Tx interrupt mode
3155 * @pf: Board private structure
3156 *
3157 * Initialize the Tx timestamp interrupt mode for this device. For most device
3158 * types, each PF processes the interrupt and manages its own timestamps. For
3159 * E822-based devices, only the clock owner processes the timestamps. Other
3160 * PFs disable the interrupt and do not process their own timestamps.
3161 */
3162static void ice_ptp_init_tx_interrupt_mode(struct ice_pf *pf)
3163{
3164 switch (pf->hw.phy_model) {
3165 case ICE_PHY_E82X:
3166 /* E822 based PHY has the clock owner process the interrupt
3167 * for all ports.
3168 */
3169 if (ice_pf_src_tmr_owned(pf))
3170 pf->ptp.tx_interrupt_mode = ICE_PTP_TX_INTERRUPT_ALL;
3171 else
3172 pf->ptp.tx_interrupt_mode = ICE_PTP_TX_INTERRUPT_NONE;
3173 break;
3174 default:
3175 /* other PHY types handle their own Tx interrupt */
3176 pf->ptp.tx_interrupt_mode = ICE_PTP_TX_INTERRUPT_SELF;
3177 }
3178}
3179
3180/**
3181 * ice_ptp_init - Initialize PTP hardware clock support
3182 * @pf: Board private structure
3183 *
3184 * Set up the device for interacting with the PTP hardware clock for all
3185 * functions, both the function that owns the clock hardware, and the
3186 * functions connected to the clock hardware.
3187 *
3188 * The clock owner will allocate and register a ptp_clock with the
3189 * PTP_1588_CLOCK infrastructure. All functions allocate a kthread and work
3190 * items used for asynchronous work such as Tx timestamps and periodic work.
3191 */
3192void ice_ptp_init(struct ice_pf *pf)
3193{
3194 struct ice_ptp *ptp = &pf->ptp;
3195 struct ice_hw *hw = &pf->hw;
3196 int err;
3197
3198 ice_ptp_init_phy_model(hw);
3199
3200 ice_ptp_init_tx_interrupt_mode(pf);
3201
3202 /* If this function owns the clock hardware, it must allocate and
3203 * configure the PTP clock device to represent it.
3204 */
3205 if (ice_pf_src_tmr_owned(pf)) {
3206 err = ice_ptp_init_owner(pf);
3207 if (err)
3208 goto err;
3209 }
3210
3211 ptp->port.port_num = hw->pf_id;
3212 err = ice_ptp_init_port(pf, &ptp->port);
3213 if (err)
3214 goto err;
3215
3216 /* Start the PHY timestamping block */
3217 ice_ptp_reset_phy_timestamping(pf);
3218
3219 /* Configure initial Tx interrupt settings */
3220 ice_ptp_cfg_tx_interrupt(pf);
3221
3222 set_bit(ICE_FLAG_PTP, pf->flags);
3223 err = ice_ptp_init_work(pf, ptp);
3224 if (err)
3225 goto err;
3226
3227 err = ice_ptp_create_auxbus_device(pf);
3228 if (err)
3229 goto err;
3230
3231 dev_info(ice_pf_to_dev(pf), "PTP init successful\n");
3232 return;
3233
3234err:
3235 /* If we registered a PTP clock, release it */
3236 if (pf->ptp.clock) {
3237 ptp_clock_unregister(ptp->clock);
3238 pf->ptp.clock = NULL;
3239 }
3240 clear_bit(ICE_FLAG_PTP, pf->flags);
3241 dev_err(ice_pf_to_dev(pf), "PTP failed %d\n", err);
3242}
3243
3244/**
3245 * ice_ptp_release - Disable the driver/HW support and unregister the clock
3246 * @pf: Board private structure
3247 *
3248 * This function handles the cleanup work required from the initialization by
3249 * clearing out the important information and unregistering the clock
3250 */
3251void ice_ptp_release(struct ice_pf *pf)
3252{
3253 if (!test_bit(ICE_FLAG_PTP, pf->flags))
3254 return;
3255
3256 /* Disable timestamping for both Tx and Rx */
3257 ice_ptp_disable_timestamp_mode(pf);
3258
3259 ice_ptp_remove_auxbus_device(pf);
3260
3261 ice_ptp_release_tx_tracker(pf, &pf->ptp.port.tx);
3262
3263 clear_bit(ICE_FLAG_PTP, pf->flags);
3264
3265 kthread_cancel_delayed_work_sync(&pf->ptp.work);
3266
3267 ice_ptp_port_phy_stop(&pf->ptp.port);
3268 mutex_destroy(&pf->ptp.port.ps_lock);
3269 if (pf->ptp.kworker) {
3270 kthread_destroy_worker(pf->ptp.kworker);
3271 pf->ptp.kworker = NULL;
3272 }
3273
3274 if (!pf->ptp.clock)
3275 return;
3276
3277 /* Disable periodic outputs */
3278 ice_ptp_disable_all_clkout(pf);
3279
3280 ptp_clock_unregister(pf->ptp.clock);
3281 pf->ptp.clock = NULL;
3282
3283 ice_ptp_unregister_auxbus_driver(pf);
3284
3285 dev_info(ice_pf_to_dev(pf), "Removed PTP clock\n");
3286}
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (C) 2021, Intel Corporation. */
3
4#include "ice.h"
5#include "ice_lib.h"
6#include "ice_trace.h"
7
8#define E810_OUT_PROP_DELAY_NS 1
9
10#define UNKNOWN_INCVAL_E822 0x100000000ULL
11
12static const struct ptp_pin_desc ice_pin_desc_e810t[] = {
13 /* name idx func chan */
14 { "GNSS", GNSS, PTP_PF_EXTTS, 0, { 0, } },
15 { "SMA1", SMA1, PTP_PF_NONE, 1, { 0, } },
16 { "U.FL1", UFL1, PTP_PF_NONE, 1, { 0, } },
17 { "SMA2", SMA2, PTP_PF_NONE, 2, { 0, } },
18 { "U.FL2", UFL2, PTP_PF_NONE, 2, { 0, } },
19};
20
21/**
22 * ice_get_sma_config_e810t
23 * @hw: pointer to the hw struct
24 * @ptp_pins: pointer to the ptp_pin_desc struture
25 *
26 * Read the configuration of the SMA control logic and put it into the
27 * ptp_pin_desc structure
28 */
29static int
30ice_get_sma_config_e810t(struct ice_hw *hw, struct ptp_pin_desc *ptp_pins)
31{
32 u8 data, i;
33 int status;
34
35 /* Read initial pin state */
36 status = ice_read_sma_ctrl_e810t(hw, &data);
37 if (status)
38 return status;
39
40 /* initialize with defaults */
41 for (i = 0; i < NUM_PTP_PINS_E810T; i++) {
42 snprintf(ptp_pins[i].name, sizeof(ptp_pins[i].name),
43 "%s", ice_pin_desc_e810t[i].name);
44 ptp_pins[i].index = ice_pin_desc_e810t[i].index;
45 ptp_pins[i].func = ice_pin_desc_e810t[i].func;
46 ptp_pins[i].chan = ice_pin_desc_e810t[i].chan;
47 }
48
49 /* Parse SMA1/UFL1 */
50 switch (data & ICE_SMA1_MASK_E810T) {
51 case ICE_SMA1_MASK_E810T:
52 default:
53 ptp_pins[SMA1].func = PTP_PF_NONE;
54 ptp_pins[UFL1].func = PTP_PF_NONE;
55 break;
56 case ICE_SMA1_DIR_EN_E810T:
57 ptp_pins[SMA1].func = PTP_PF_PEROUT;
58 ptp_pins[UFL1].func = PTP_PF_NONE;
59 break;
60 case ICE_SMA1_TX_EN_E810T:
61 ptp_pins[SMA1].func = PTP_PF_EXTTS;
62 ptp_pins[UFL1].func = PTP_PF_NONE;
63 break;
64 case 0:
65 ptp_pins[SMA1].func = PTP_PF_EXTTS;
66 ptp_pins[UFL1].func = PTP_PF_PEROUT;
67 break;
68 }
69
70 /* Parse SMA2/UFL2 */
71 switch (data & ICE_SMA2_MASK_E810T) {
72 case ICE_SMA2_MASK_E810T:
73 default:
74 ptp_pins[SMA2].func = PTP_PF_NONE;
75 ptp_pins[UFL2].func = PTP_PF_NONE;
76 break;
77 case (ICE_SMA2_TX_EN_E810T | ICE_SMA2_UFL2_RX_DIS_E810T):
78 ptp_pins[SMA2].func = PTP_PF_EXTTS;
79 ptp_pins[UFL2].func = PTP_PF_NONE;
80 break;
81 case (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_UFL2_RX_DIS_E810T):
82 ptp_pins[SMA2].func = PTP_PF_PEROUT;
83 ptp_pins[UFL2].func = PTP_PF_NONE;
84 break;
85 case (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_TX_EN_E810T):
86 ptp_pins[SMA2].func = PTP_PF_NONE;
87 ptp_pins[UFL2].func = PTP_PF_EXTTS;
88 break;
89 case ICE_SMA2_DIR_EN_E810T:
90 ptp_pins[SMA2].func = PTP_PF_PEROUT;
91 ptp_pins[UFL2].func = PTP_PF_EXTTS;
92 break;
93 }
94
95 return 0;
96}
97
98/**
99 * ice_ptp_set_sma_config_e810t
100 * @hw: pointer to the hw struct
101 * @ptp_pins: pointer to the ptp_pin_desc struture
102 *
103 * Set the configuration of the SMA control logic based on the configuration in
104 * num_pins parameter
105 */
106static int
107ice_ptp_set_sma_config_e810t(struct ice_hw *hw,
108 const struct ptp_pin_desc *ptp_pins)
109{
110 int status;
111 u8 data;
112
113 /* SMA1 and UFL1 cannot be set to TX at the same time */
114 if (ptp_pins[SMA1].func == PTP_PF_PEROUT &&
115 ptp_pins[UFL1].func == PTP_PF_PEROUT)
116 return -EINVAL;
117
118 /* SMA2 and UFL2 cannot be set to RX at the same time */
119 if (ptp_pins[SMA2].func == PTP_PF_EXTTS &&
120 ptp_pins[UFL2].func == PTP_PF_EXTTS)
121 return -EINVAL;
122
123 /* Read initial pin state value */
124 status = ice_read_sma_ctrl_e810t(hw, &data);
125 if (status)
126 return status;
127
128 /* Set the right sate based on the desired configuration */
129 data &= ~ICE_SMA1_MASK_E810T;
130 if (ptp_pins[SMA1].func == PTP_PF_NONE &&
131 ptp_pins[UFL1].func == PTP_PF_NONE) {
132 dev_info(ice_hw_to_dev(hw), "SMA1 + U.FL1 disabled");
133 data |= ICE_SMA1_MASK_E810T;
134 } else if (ptp_pins[SMA1].func == PTP_PF_EXTTS &&
135 ptp_pins[UFL1].func == PTP_PF_NONE) {
136 dev_info(ice_hw_to_dev(hw), "SMA1 RX");
137 data |= ICE_SMA1_TX_EN_E810T;
138 } else if (ptp_pins[SMA1].func == PTP_PF_NONE &&
139 ptp_pins[UFL1].func == PTP_PF_PEROUT) {
140 /* U.FL 1 TX will always enable SMA 1 RX */
141 dev_info(ice_hw_to_dev(hw), "SMA1 RX + U.FL1 TX");
142 } else if (ptp_pins[SMA1].func == PTP_PF_EXTTS &&
143 ptp_pins[UFL1].func == PTP_PF_PEROUT) {
144 dev_info(ice_hw_to_dev(hw), "SMA1 RX + U.FL1 TX");
145 } else if (ptp_pins[SMA1].func == PTP_PF_PEROUT &&
146 ptp_pins[UFL1].func == PTP_PF_NONE) {
147 dev_info(ice_hw_to_dev(hw), "SMA1 TX");
148 data |= ICE_SMA1_DIR_EN_E810T;
149 }
150
151 data &= ~ICE_SMA2_MASK_E810T;
152 if (ptp_pins[SMA2].func == PTP_PF_NONE &&
153 ptp_pins[UFL2].func == PTP_PF_NONE) {
154 dev_info(ice_hw_to_dev(hw), "SMA2 + U.FL2 disabled");
155 data |= ICE_SMA2_MASK_E810T;
156 } else if (ptp_pins[SMA2].func == PTP_PF_EXTTS &&
157 ptp_pins[UFL2].func == PTP_PF_NONE) {
158 dev_info(ice_hw_to_dev(hw), "SMA2 RX");
159 data |= (ICE_SMA2_TX_EN_E810T |
160 ICE_SMA2_UFL2_RX_DIS_E810T);
161 } else if (ptp_pins[SMA2].func == PTP_PF_NONE &&
162 ptp_pins[UFL2].func == PTP_PF_EXTTS) {
163 dev_info(ice_hw_to_dev(hw), "UFL2 RX");
164 data |= (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_TX_EN_E810T);
165 } else if (ptp_pins[SMA2].func == PTP_PF_PEROUT &&
166 ptp_pins[UFL2].func == PTP_PF_NONE) {
167 dev_info(ice_hw_to_dev(hw), "SMA2 TX");
168 data |= (ICE_SMA2_DIR_EN_E810T |
169 ICE_SMA2_UFL2_RX_DIS_E810T);
170 } else if (ptp_pins[SMA2].func == PTP_PF_PEROUT &&
171 ptp_pins[UFL2].func == PTP_PF_EXTTS) {
172 dev_info(ice_hw_to_dev(hw), "SMA2 TX + U.FL2 RX");
173 data |= ICE_SMA2_DIR_EN_E810T;
174 }
175
176 return ice_write_sma_ctrl_e810t(hw, data);
177}
178
179/**
180 * ice_ptp_set_sma_e810t
181 * @info: the driver's PTP info structure
182 * @pin: pin index in kernel structure
183 * @func: Pin function to be set (PTP_PF_NONE, PTP_PF_EXTTS or PTP_PF_PEROUT)
184 *
185 * Set the configuration of a single SMA pin
186 */
187static int
188ice_ptp_set_sma_e810t(struct ptp_clock_info *info, unsigned int pin,
189 enum ptp_pin_function func)
190{
191 struct ptp_pin_desc ptp_pins[NUM_PTP_PINS_E810T];
192 struct ice_pf *pf = ptp_info_to_pf(info);
193 struct ice_hw *hw = &pf->hw;
194 int err;
195
196 if (pin < SMA1 || func > PTP_PF_PEROUT)
197 return -EOPNOTSUPP;
198
199 err = ice_get_sma_config_e810t(hw, ptp_pins);
200 if (err)
201 return err;
202
203 /* Disable the same function on the other pin sharing the channel */
204 if (pin == SMA1 && ptp_pins[UFL1].func == func)
205 ptp_pins[UFL1].func = PTP_PF_NONE;
206 if (pin == UFL1 && ptp_pins[SMA1].func == func)
207 ptp_pins[SMA1].func = PTP_PF_NONE;
208
209 if (pin == SMA2 && ptp_pins[UFL2].func == func)
210 ptp_pins[UFL2].func = PTP_PF_NONE;
211 if (pin == UFL2 && ptp_pins[SMA2].func == func)
212 ptp_pins[SMA2].func = PTP_PF_NONE;
213
214 /* Set up new pin function in the temp table */
215 ptp_pins[pin].func = func;
216
217 return ice_ptp_set_sma_config_e810t(hw, ptp_pins);
218}
219
220/**
221 * ice_verify_pin_e810t
222 * @info: the driver's PTP info structure
223 * @pin: Pin index
224 * @func: Assigned function
225 * @chan: Assigned channel
226 *
227 * Verify if pin supports requested pin function. If the Check pins consistency.
228 * Reconfigure the SMA logic attached to the given pin to enable its
229 * desired functionality
230 */
231static int
232ice_verify_pin_e810t(struct ptp_clock_info *info, unsigned int pin,
233 enum ptp_pin_function func, unsigned int chan)
234{
235 /* Don't allow channel reassignment */
236 if (chan != ice_pin_desc_e810t[pin].chan)
237 return -EOPNOTSUPP;
238
239 /* Check if functions are properly assigned */
240 switch (func) {
241 case PTP_PF_NONE:
242 break;
243 case PTP_PF_EXTTS:
244 if (pin == UFL1)
245 return -EOPNOTSUPP;
246 break;
247 case PTP_PF_PEROUT:
248 if (pin == UFL2 || pin == GNSS)
249 return -EOPNOTSUPP;
250 break;
251 case PTP_PF_PHYSYNC:
252 return -EOPNOTSUPP;
253 }
254
255 return ice_ptp_set_sma_e810t(info, pin, func);
256}
257
258/**
259 * ice_set_tx_tstamp - Enable or disable Tx timestamping
260 * @pf: The PF pointer to search in
261 * @on: bool value for whether timestamps are enabled or disabled
262 */
263static void ice_set_tx_tstamp(struct ice_pf *pf, bool on)
264{
265 struct ice_vsi *vsi;
266 u32 val;
267 u16 i;
268
269 vsi = ice_get_main_vsi(pf);
270 if (!vsi)
271 return;
272
273 /* Set the timestamp enable flag for all the Tx rings */
274 ice_for_each_txq(vsi, i) {
275 if (!vsi->tx_rings[i])
276 continue;
277 vsi->tx_rings[i]->ptp_tx = on;
278 }
279
280 /* Configure the Tx timestamp interrupt */
281 val = rd32(&pf->hw, PFINT_OICR_ENA);
282 if (on)
283 val |= PFINT_OICR_TSYN_TX_M;
284 else
285 val &= ~PFINT_OICR_TSYN_TX_M;
286 wr32(&pf->hw, PFINT_OICR_ENA, val);
287
288 pf->ptp.tstamp_config.tx_type = on ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
289}
290
291/**
292 * ice_set_rx_tstamp - Enable or disable Rx timestamping
293 * @pf: The PF pointer to search in
294 * @on: bool value for whether timestamps are enabled or disabled
295 */
296static void ice_set_rx_tstamp(struct ice_pf *pf, bool on)
297{
298 struct ice_vsi *vsi;
299 u16 i;
300
301 vsi = ice_get_main_vsi(pf);
302 if (!vsi)
303 return;
304
305 /* Set the timestamp flag for all the Rx rings */
306 ice_for_each_rxq(vsi, i) {
307 if (!vsi->rx_rings[i])
308 continue;
309 vsi->rx_rings[i]->ptp_rx = on;
310 }
311
312 pf->ptp.tstamp_config.rx_filter = on ? HWTSTAMP_FILTER_ALL :
313 HWTSTAMP_FILTER_NONE;
314}
315
316/**
317 * ice_ptp_cfg_timestamp - Configure timestamp for init/deinit
318 * @pf: Board private structure
319 * @ena: bool value to enable or disable time stamp
320 *
321 * This function will configure timestamping during PTP initialization
322 * and deinitialization
323 */
324void ice_ptp_cfg_timestamp(struct ice_pf *pf, bool ena)
325{
326 ice_set_tx_tstamp(pf, ena);
327 ice_set_rx_tstamp(pf, ena);
328}
329
330/**
331 * ice_get_ptp_clock_index - Get the PTP clock index
332 * @pf: the PF pointer
333 *
334 * Determine the clock index of the PTP clock associated with this device. If
335 * this is the PF controlling the clock, just use the local access to the
336 * clock device pointer.
337 *
338 * Otherwise, read from the driver shared parameters to determine the clock
339 * index value.
340 *
341 * Returns: the index of the PTP clock associated with this device, or -1 if
342 * there is no associated clock.
343 */
344int ice_get_ptp_clock_index(struct ice_pf *pf)
345{
346 struct device *dev = ice_pf_to_dev(pf);
347 enum ice_aqc_driver_params param_idx;
348 struct ice_hw *hw = &pf->hw;
349 u8 tmr_idx;
350 u32 value;
351 int err;
352
353 /* Use the ptp_clock structure if we're the main PF */
354 if (pf->ptp.clock)
355 return ptp_clock_index(pf->ptp.clock);
356
357 tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc;
358 if (!tmr_idx)
359 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0;
360 else
361 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1;
362
363 err = ice_aq_get_driver_param(hw, param_idx, &value, NULL);
364 if (err) {
365 dev_err(dev, "Failed to read PTP clock index parameter, err %d aq_err %s\n",
366 err, ice_aq_str(hw->adminq.sq_last_status));
367 return -1;
368 }
369
370 /* The PTP clock index is an integer, and will be between 0 and
371 * INT_MAX. The highest bit of the driver shared parameter is used to
372 * indicate whether or not the currently stored clock index is valid.
373 */
374 if (!(value & PTP_SHARED_CLK_IDX_VALID))
375 return -1;
376
377 return value & ~PTP_SHARED_CLK_IDX_VALID;
378}
379
380/**
381 * ice_set_ptp_clock_index - Set the PTP clock index
382 * @pf: the PF pointer
383 *
384 * Set the PTP clock index for this device into the shared driver parameters,
385 * so that other PFs associated with this device can read it.
386 *
387 * If the PF is unable to store the clock index, it will log an error, but
388 * will continue operating PTP.
389 */
390static void ice_set_ptp_clock_index(struct ice_pf *pf)
391{
392 struct device *dev = ice_pf_to_dev(pf);
393 enum ice_aqc_driver_params param_idx;
394 struct ice_hw *hw = &pf->hw;
395 u8 tmr_idx;
396 u32 value;
397 int err;
398
399 if (!pf->ptp.clock)
400 return;
401
402 tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc;
403 if (!tmr_idx)
404 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0;
405 else
406 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1;
407
408 value = (u32)ptp_clock_index(pf->ptp.clock);
409 if (value > INT_MAX) {
410 dev_err(dev, "PTP Clock index is too large to store\n");
411 return;
412 }
413 value |= PTP_SHARED_CLK_IDX_VALID;
414
415 err = ice_aq_set_driver_param(hw, param_idx, value, NULL);
416 if (err) {
417 dev_err(dev, "Failed to set PTP clock index parameter, err %d aq_err %s\n",
418 err, ice_aq_str(hw->adminq.sq_last_status));
419 }
420}
421
422/**
423 * ice_clear_ptp_clock_index - Clear the PTP clock index
424 * @pf: the PF pointer
425 *
426 * Clear the PTP clock index for this device. Must be called when
427 * unregistering the PTP clock, in order to ensure other PFs stop reporting
428 * a clock object that no longer exists.
429 */
430static void ice_clear_ptp_clock_index(struct ice_pf *pf)
431{
432 struct device *dev = ice_pf_to_dev(pf);
433 enum ice_aqc_driver_params param_idx;
434 struct ice_hw *hw = &pf->hw;
435 u8 tmr_idx;
436 int err;
437
438 /* Do not clear the index if we don't own the timer */
439 if (!hw->func_caps.ts_func_info.src_tmr_owned)
440 return;
441
442 tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc;
443 if (!tmr_idx)
444 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0;
445 else
446 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1;
447
448 err = ice_aq_set_driver_param(hw, param_idx, 0, NULL);
449 if (err) {
450 dev_dbg(dev, "Failed to clear PTP clock index parameter, err %d aq_err %s\n",
451 err, ice_aq_str(hw->adminq.sq_last_status));
452 }
453}
454
455/**
456 * ice_ptp_read_src_clk_reg - Read the source clock register
457 * @pf: Board private structure
458 * @sts: Optional parameter for holding a pair of system timestamps from
459 * the system clock. Will be ignored if NULL is given.
460 */
461static u64
462ice_ptp_read_src_clk_reg(struct ice_pf *pf, struct ptp_system_timestamp *sts)
463{
464 struct ice_hw *hw = &pf->hw;
465 u32 hi, lo, lo2;
466 u8 tmr_idx;
467
468 tmr_idx = ice_get_ptp_src_clock_index(hw);
469 /* Read the system timestamp pre PHC read */
470 ptp_read_system_prets(sts);
471
472 lo = rd32(hw, GLTSYN_TIME_L(tmr_idx));
473
474 /* Read the system timestamp post PHC read */
475 ptp_read_system_postts(sts);
476
477 hi = rd32(hw, GLTSYN_TIME_H(tmr_idx));
478 lo2 = rd32(hw, GLTSYN_TIME_L(tmr_idx));
479
480 if (lo2 < lo) {
481 /* if TIME_L rolled over read TIME_L again and update
482 * system timestamps
483 */
484 ptp_read_system_prets(sts);
485 lo = rd32(hw, GLTSYN_TIME_L(tmr_idx));
486 ptp_read_system_postts(sts);
487 hi = rd32(hw, GLTSYN_TIME_H(tmr_idx));
488 }
489
490 return ((u64)hi << 32) | lo;
491}
492
493/**
494 * ice_ptp_extend_32b_ts - Convert a 32b nanoseconds timestamp to 64b
495 * @cached_phc_time: recently cached copy of PHC time
496 * @in_tstamp: Ingress/egress 32b nanoseconds timestamp value
497 *
498 * Hardware captures timestamps which contain only 32 bits of nominal
499 * nanoseconds, as opposed to the 64bit timestamps that the stack expects.
500 * Note that the captured timestamp values may be 40 bits, but the lower
501 * 8 bits are sub-nanoseconds and generally discarded.
502 *
503 * Extend the 32bit nanosecond timestamp using the following algorithm and
504 * assumptions:
505 *
506 * 1) have a recently cached copy of the PHC time
507 * 2) assume that the in_tstamp was captured 2^31 nanoseconds (~2.1
508 * seconds) before or after the PHC time was captured.
509 * 3) calculate the delta between the cached time and the timestamp
510 * 4) if the delta is smaller than 2^31 nanoseconds, then the timestamp was
511 * captured after the PHC time. In this case, the full timestamp is just
512 * the cached PHC time plus the delta.
513 * 5) otherwise, if the delta is larger than 2^31 nanoseconds, then the
514 * timestamp was captured *before* the PHC time, i.e. because the PHC
515 * cache was updated after the timestamp was captured by hardware. In this
516 * case, the full timestamp is the cached time minus the inverse delta.
517 *
518 * This algorithm works even if the PHC time was updated after a Tx timestamp
519 * was requested, but before the Tx timestamp event was reported from
520 * hardware.
521 *
522 * This calculation primarily relies on keeping the cached PHC time up to
523 * date. If the timestamp was captured more than 2^31 nanoseconds after the
524 * PHC time, it is possible that the lower 32bits of PHC time have
525 * overflowed more than once, and we might generate an incorrect timestamp.
526 *
527 * This is prevented by (a) periodically updating the cached PHC time once
528 * a second, and (b) discarding any Tx timestamp packet if it has waited for
529 * a timestamp for more than one second.
530 */
531static u64 ice_ptp_extend_32b_ts(u64 cached_phc_time, u32 in_tstamp)
532{
533 u32 delta, phc_time_lo;
534 u64 ns;
535
536 /* Extract the lower 32 bits of the PHC time */
537 phc_time_lo = (u32)cached_phc_time;
538
539 /* Calculate the delta between the lower 32bits of the cached PHC
540 * time and the in_tstamp value
541 */
542 delta = (in_tstamp - phc_time_lo);
543
544 /* Do not assume that the in_tstamp is always more recent than the
545 * cached PHC time. If the delta is large, it indicates that the
546 * in_tstamp was taken in the past, and should be converted
547 * forward.
548 */
549 if (delta > (U32_MAX / 2)) {
550 /* reverse the delta calculation here */
551 delta = (phc_time_lo - in_tstamp);
552 ns = cached_phc_time - delta;
553 } else {
554 ns = cached_phc_time + delta;
555 }
556
557 return ns;
558}
559
560/**
561 * ice_ptp_extend_40b_ts - Convert a 40b timestamp to 64b nanoseconds
562 * @pf: Board private structure
563 * @in_tstamp: Ingress/egress 40b timestamp value
564 *
565 * The Tx and Rx timestamps are 40 bits wide, including 32 bits of nominal
566 * nanoseconds, 7 bits of sub-nanoseconds, and a valid bit.
567 *
568 * *--------------------------------------------------------------*
569 * | 32 bits of nanoseconds | 7 high bits of sub ns underflow | v |
570 * *--------------------------------------------------------------*
571 *
572 * The low bit is an indicator of whether the timestamp is valid. The next
573 * 7 bits are a capture of the upper 7 bits of the sub-nanosecond underflow,
574 * and the remaining 32 bits are the lower 32 bits of the PHC timer.
575 *
576 * It is assumed that the caller verifies the timestamp is valid prior to
577 * calling this function.
578 *
579 * Extract the 32bit nominal nanoseconds and extend them. Use the cached PHC
580 * time stored in the device private PTP structure as the basis for timestamp
581 * extension.
582 *
583 * See ice_ptp_extend_32b_ts for a detailed explanation of the extension
584 * algorithm.
585 */
586static u64 ice_ptp_extend_40b_ts(struct ice_pf *pf, u64 in_tstamp)
587{
588 const u64 mask = GENMASK_ULL(31, 0);
589 unsigned long discard_time;
590
591 /* Discard the hardware timestamp if the cached PHC time is too old */
592 discard_time = pf->ptp.cached_phc_jiffies + msecs_to_jiffies(2000);
593 if (time_is_before_jiffies(discard_time)) {
594 pf->ptp.tx_hwtstamp_discarded++;
595 return 0;
596 }
597
598 return ice_ptp_extend_32b_ts(pf->ptp.cached_phc_time,
599 (in_tstamp >> 8) & mask);
600}
601
602/**
603 * ice_ptp_is_tx_tracker_up - Check if Tx tracker is ready for new timestamps
604 * @tx: the PTP Tx timestamp tracker to check
605 *
606 * Check that a given PTP Tx timestamp tracker is up, i.e. that it is ready
607 * to accept new timestamp requests.
608 *
609 * Assumes the tx->lock spinlock is already held.
610 */
611static bool
612ice_ptp_is_tx_tracker_up(struct ice_ptp_tx *tx)
613{
614 lockdep_assert_held(&tx->lock);
615
616 return tx->init && !tx->calibrating;
617}
618
619/**
620 * ice_ptp_tx_tstamp - Process Tx timestamps for a port
621 * @tx: the PTP Tx timestamp tracker
622 *
623 * Process timestamps captured by the PHY associated with this port. To do
624 * this, loop over each index with a waiting skb.
625 *
626 * If a given index has a valid timestamp, perform the following steps:
627 *
628 * 1) check that the timestamp request is not stale
629 * 2) check that a timestamp is ready and available in the PHY memory bank
630 * 3) read and copy the timestamp out of the PHY register
631 * 4) unlock the index by clearing the associated in_use bit
632 * 5) check if the timestamp is stale, and discard if so
633 * 6) extend the 40 bit timestamp value to get a 64 bit timestamp value
634 * 7) send this 64 bit timestamp to the stack
635 *
636 * Returns true if all timestamps were handled, and false if any slots remain
637 * without a timestamp.
638 *
639 * After looping, if we still have waiting SKBs, return false. This may cause
640 * us effectively poll even when not strictly necessary. We do this because
641 * it's possible a new timestamp was requested around the same time as the
642 * interrupt. In some cases hardware might not interrupt us again when the
643 * timestamp is captured.
644 *
645 * Note that we do not hold the tracking lock while reading the Tx timestamp.
646 * This is because reading the timestamp requires taking a mutex that might
647 * sleep.
648 *
649 * The only place where we set in_use is when a new timestamp is initiated
650 * with a slot index. This is only called in the hard xmit routine where an
651 * SKB has a request flag set. The only places where we clear this bit is this
652 * function, or during teardown when the Tx timestamp tracker is being
653 * removed. A timestamp index will never be re-used until the in_use bit for
654 * that index is cleared.
655 *
656 * If a Tx thread starts a new timestamp, we might not begin processing it
657 * right away but we will notice it at the end when we re-queue the task.
658 *
659 * If a Tx thread starts a new timestamp just after this function exits, the
660 * interrupt for that timestamp should re-trigger this function once
661 * a timestamp is ready.
662 *
663 * In cases where the PTP hardware clock was directly adjusted, some
664 * timestamps may not be able to safely use the timestamp extension math. In
665 * this case, software will set the stale bit for any outstanding Tx
666 * timestamps when the clock is adjusted. Then this function will discard
667 * those captured timestamps instead of sending them to the stack.
668 *
669 * If a Tx packet has been waiting for more than 2 seconds, it is not possible
670 * to correctly extend the timestamp using the cached PHC time. It is
671 * extremely unlikely that a packet will ever take this long to timestamp. If
672 * we detect a Tx timestamp request that has waited for this long we assume
673 * the packet will never be sent by hardware and discard it without reading
674 * the timestamp register.
675 */
676static bool ice_ptp_tx_tstamp(struct ice_ptp_tx *tx)
677{
678 struct ice_ptp_port *ptp_port;
679 bool more_timestamps;
680 struct ice_pf *pf;
681 struct ice_hw *hw;
682 u64 tstamp_ready;
683 int err;
684 u8 idx;
685
686 if (!tx->init)
687 return true;
688
689 ptp_port = container_of(tx, struct ice_ptp_port, tx);
690 pf = ptp_port_to_pf(ptp_port);
691 hw = &pf->hw;
692
693 /* Read the Tx ready status first */
694 err = ice_get_phy_tx_tstamp_ready(hw, tx->block, &tstamp_ready);
695 if (err)
696 return false;
697
698 for_each_set_bit(idx, tx->in_use, tx->len) {
699 struct skb_shared_hwtstamps shhwtstamps = {};
700 u8 phy_idx = idx + tx->offset;
701 u64 raw_tstamp = 0, tstamp;
702 bool drop_ts = false;
703 struct sk_buff *skb;
704
705 /* Drop packets which have waited for more than 2 seconds */
706 if (time_is_before_jiffies(tx->tstamps[idx].start + 2 * HZ)) {
707 drop_ts = true;
708
709 /* Count the number of Tx timestamps that timed out */
710 pf->ptp.tx_hwtstamp_timeouts++;
711 }
712
713 /* Only read a timestamp from the PHY if its marked as ready
714 * by the tstamp_ready register. This avoids unnecessary
715 * reading of timestamps which are not yet valid. This is
716 * important as we must read all timestamps which are valid
717 * and only timestamps which are valid during each interrupt.
718 * If we do not, the hardware logic for generating a new
719 * interrupt can get stuck on some devices.
720 */
721 if (!(tstamp_ready & BIT_ULL(phy_idx))) {
722 if (drop_ts)
723 goto skip_ts_read;
724
725 continue;
726 }
727
728 ice_trace(tx_tstamp_fw_req, tx->tstamps[idx].skb, idx);
729
730 err = ice_read_phy_tstamp(hw, tx->block, phy_idx, &raw_tstamp);
731 if (err)
732 continue;
733
734 ice_trace(tx_tstamp_fw_done, tx->tstamps[idx].skb, idx);
735
736 /* For PHYs which don't implement a proper timestamp ready
737 * bitmap, verify that the timestamp value is different
738 * from the last cached timestamp. If it is not, skip this for
739 * now assuming it hasn't yet been captured by hardware.
740 */
741 if (!drop_ts && tx->verify_cached &&
742 raw_tstamp == tx->tstamps[idx].cached_tstamp)
743 continue;
744
745 /* Discard any timestamp value without the valid bit set */
746 if (!(raw_tstamp & ICE_PTP_TS_VALID))
747 drop_ts = true;
748
749skip_ts_read:
750 spin_lock(&tx->lock);
751 if (tx->verify_cached && raw_tstamp)
752 tx->tstamps[idx].cached_tstamp = raw_tstamp;
753 clear_bit(idx, tx->in_use);
754 skb = tx->tstamps[idx].skb;
755 tx->tstamps[idx].skb = NULL;
756 if (test_and_clear_bit(idx, tx->stale))
757 drop_ts = true;
758 spin_unlock(&tx->lock);
759
760 /* It is unlikely but possible that the SKB will have been
761 * flushed at this point due to link change or teardown.
762 */
763 if (!skb)
764 continue;
765
766 if (drop_ts) {
767 dev_kfree_skb_any(skb);
768 continue;
769 }
770
771 /* Extend the timestamp using cached PHC time */
772 tstamp = ice_ptp_extend_40b_ts(pf, raw_tstamp);
773 if (tstamp) {
774 shhwtstamps.hwtstamp = ns_to_ktime(tstamp);
775 ice_trace(tx_tstamp_complete, skb, idx);
776 }
777
778 skb_tstamp_tx(skb, &shhwtstamps);
779 dev_kfree_skb_any(skb);
780 }
781
782 /* Check if we still have work to do. If so, re-queue this task to
783 * poll for remaining timestamps.
784 */
785 spin_lock(&tx->lock);
786 more_timestamps = tx->init && !bitmap_empty(tx->in_use, tx->len);
787 spin_unlock(&tx->lock);
788
789 return !more_timestamps;
790}
791
792/**
793 * ice_ptp_alloc_tx_tracker - Initialize tracking for Tx timestamps
794 * @tx: Tx tracking structure to initialize
795 *
796 * Assumes that the length has already been initialized. Do not call directly,
797 * use the ice_ptp_init_tx_* instead.
798 */
799static int
800ice_ptp_alloc_tx_tracker(struct ice_ptp_tx *tx)
801{
802 unsigned long *in_use, *stale;
803 struct ice_tx_tstamp *tstamps;
804
805 tstamps = kcalloc(tx->len, sizeof(*tstamps), GFP_KERNEL);
806 in_use = bitmap_zalloc(tx->len, GFP_KERNEL);
807 stale = bitmap_zalloc(tx->len, GFP_KERNEL);
808
809 if (!tstamps || !in_use || !stale) {
810 kfree(tstamps);
811 bitmap_free(in_use);
812 bitmap_free(stale);
813
814 return -ENOMEM;
815 }
816
817 tx->tstamps = tstamps;
818 tx->in_use = in_use;
819 tx->stale = stale;
820 tx->init = 1;
821
822 spin_lock_init(&tx->lock);
823
824 return 0;
825}
826
827/**
828 * ice_ptp_flush_tx_tracker - Flush any remaining timestamps from the tracker
829 * @pf: Board private structure
830 * @tx: the tracker to flush
831 *
832 * Called during teardown when a Tx tracker is being removed.
833 */
834static void
835ice_ptp_flush_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx)
836{
837 struct ice_hw *hw = &pf->hw;
838 u64 tstamp_ready;
839 int err;
840 u8 idx;
841
842 err = ice_get_phy_tx_tstamp_ready(hw, tx->block, &tstamp_ready);
843 if (err) {
844 dev_dbg(ice_pf_to_dev(pf), "Failed to get the Tx tstamp ready bitmap for block %u, err %d\n",
845 tx->block, err);
846
847 /* If we fail to read the Tx timestamp ready bitmap just
848 * skip clearing the PHY timestamps.
849 */
850 tstamp_ready = 0;
851 }
852
853 for_each_set_bit(idx, tx->in_use, tx->len) {
854 u8 phy_idx = idx + tx->offset;
855 struct sk_buff *skb;
856
857 /* In case this timestamp is ready, we need to clear it. */
858 if (!hw->reset_ongoing && (tstamp_ready & BIT_ULL(phy_idx)))
859 ice_clear_phy_tstamp(hw, tx->block, phy_idx);
860
861 spin_lock(&tx->lock);
862 skb = tx->tstamps[idx].skb;
863 tx->tstamps[idx].skb = NULL;
864 clear_bit(idx, tx->in_use);
865 clear_bit(idx, tx->stale);
866 spin_unlock(&tx->lock);
867
868 /* Count the number of Tx timestamps flushed */
869 pf->ptp.tx_hwtstamp_flushed++;
870
871 /* Free the SKB after we've cleared the bit */
872 dev_kfree_skb_any(skb);
873 }
874}
875
876/**
877 * ice_ptp_mark_tx_tracker_stale - Mark unfinished timestamps as stale
878 * @tx: the tracker to mark
879 *
880 * Mark currently outstanding Tx timestamps as stale. This prevents sending
881 * their timestamp value to the stack. This is required to prevent extending
882 * the 40bit hardware timestamp incorrectly.
883 *
884 * This should be called when the PTP clock is modified such as after a set
885 * time request.
886 */
887static void
888ice_ptp_mark_tx_tracker_stale(struct ice_ptp_tx *tx)
889{
890 spin_lock(&tx->lock);
891 bitmap_or(tx->stale, tx->stale, tx->in_use, tx->len);
892 spin_unlock(&tx->lock);
893}
894
895/**
896 * ice_ptp_release_tx_tracker - Release allocated memory for Tx tracker
897 * @pf: Board private structure
898 * @tx: Tx tracking structure to release
899 *
900 * Free memory associated with the Tx timestamp tracker.
901 */
902static void
903ice_ptp_release_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx)
904{
905 spin_lock(&tx->lock);
906 tx->init = 0;
907 spin_unlock(&tx->lock);
908
909 /* wait for potentially outstanding interrupt to complete */
910 synchronize_irq(pf->msix_entries[pf->oicr_idx].vector);
911
912 ice_ptp_flush_tx_tracker(pf, tx);
913
914 kfree(tx->tstamps);
915 tx->tstamps = NULL;
916
917 bitmap_free(tx->in_use);
918 tx->in_use = NULL;
919
920 bitmap_free(tx->stale);
921 tx->stale = NULL;
922
923 tx->len = 0;
924}
925
926/**
927 * ice_ptp_init_tx_e822 - Initialize tracking for Tx timestamps
928 * @pf: Board private structure
929 * @tx: the Tx tracking structure to initialize
930 * @port: the port this structure tracks
931 *
932 * Initialize the Tx timestamp tracker for this port. For generic MAC devices,
933 * the timestamp block is shared for all ports in the same quad. To avoid
934 * ports using the same timestamp index, logically break the block of
935 * registers into chunks based on the port number.
936 */
937static int
938ice_ptp_init_tx_e822(struct ice_pf *pf, struct ice_ptp_tx *tx, u8 port)
939{
940 tx->block = port / ICE_PORTS_PER_QUAD;
941 tx->offset = (port % ICE_PORTS_PER_QUAD) * INDEX_PER_PORT_E822;
942 tx->len = INDEX_PER_PORT_E822;
943 tx->verify_cached = 0;
944
945 return ice_ptp_alloc_tx_tracker(tx);
946}
947
948/**
949 * ice_ptp_init_tx_e810 - Initialize tracking for Tx timestamps
950 * @pf: Board private structure
951 * @tx: the Tx tracking structure to initialize
952 *
953 * Initialize the Tx timestamp tracker for this PF. For E810 devices, each
954 * port has its own block of timestamps, independent of the other ports.
955 */
956static int
957ice_ptp_init_tx_e810(struct ice_pf *pf, struct ice_ptp_tx *tx)
958{
959 tx->block = pf->hw.port_info->lport;
960 tx->offset = 0;
961 tx->len = INDEX_PER_PORT_E810;
962 /* The E810 PHY does not provide a timestamp ready bitmap. Instead,
963 * verify new timestamps against cached copy of the last read
964 * timestamp.
965 */
966 tx->verify_cached = 1;
967
968 return ice_ptp_alloc_tx_tracker(tx);
969}
970
971/**
972 * ice_ptp_update_cached_phctime - Update the cached PHC time values
973 * @pf: Board specific private structure
974 *
975 * This function updates the system time values which are cached in the PF
976 * structure and the Rx rings.
977 *
978 * This function must be called periodically to ensure that the cached value
979 * is never more than 2 seconds old.
980 *
981 * Note that the cached copy in the PF PTP structure is always updated, even
982 * if we can't update the copy in the Rx rings.
983 *
984 * Return:
985 * * 0 - OK, successfully updated
986 * * -EAGAIN - PF was busy, need to reschedule the update
987 */
988static int ice_ptp_update_cached_phctime(struct ice_pf *pf)
989{
990 struct device *dev = ice_pf_to_dev(pf);
991 unsigned long update_before;
992 u64 systime;
993 int i;
994
995 update_before = pf->ptp.cached_phc_jiffies + msecs_to_jiffies(2000);
996 if (pf->ptp.cached_phc_time &&
997 time_is_before_jiffies(update_before)) {
998 unsigned long time_taken = jiffies - pf->ptp.cached_phc_jiffies;
999
1000 dev_warn(dev, "%u msecs passed between update to cached PHC time\n",
1001 jiffies_to_msecs(time_taken));
1002 pf->ptp.late_cached_phc_updates++;
1003 }
1004
1005 /* Read the current PHC time */
1006 systime = ice_ptp_read_src_clk_reg(pf, NULL);
1007
1008 /* Update the cached PHC time stored in the PF structure */
1009 WRITE_ONCE(pf->ptp.cached_phc_time, systime);
1010 WRITE_ONCE(pf->ptp.cached_phc_jiffies, jiffies);
1011
1012 if (test_and_set_bit(ICE_CFG_BUSY, pf->state))
1013 return -EAGAIN;
1014
1015 ice_for_each_vsi(pf, i) {
1016 struct ice_vsi *vsi = pf->vsi[i];
1017 int j;
1018
1019 if (!vsi)
1020 continue;
1021
1022 if (vsi->type != ICE_VSI_PF)
1023 continue;
1024
1025 ice_for_each_rxq(vsi, j) {
1026 if (!vsi->rx_rings[j])
1027 continue;
1028 WRITE_ONCE(vsi->rx_rings[j]->cached_phctime, systime);
1029 }
1030 }
1031 clear_bit(ICE_CFG_BUSY, pf->state);
1032
1033 return 0;
1034}
1035
1036/**
1037 * ice_ptp_reset_cached_phctime - Reset cached PHC time after an update
1038 * @pf: Board specific private structure
1039 *
1040 * This function must be called when the cached PHC time is no longer valid,
1041 * such as after a time adjustment. It marks any currently outstanding Tx
1042 * timestamps as stale and updates the cached PHC time for both the PF and Rx
1043 * rings.
1044 *
1045 * If updating the PHC time cannot be done immediately, a warning message is
1046 * logged and the work item is scheduled immediately to minimize the window
1047 * with a wrong cached timestamp.
1048 */
1049static void ice_ptp_reset_cached_phctime(struct ice_pf *pf)
1050{
1051 struct device *dev = ice_pf_to_dev(pf);
1052 int err;
1053
1054 /* Update the cached PHC time immediately if possible, otherwise
1055 * schedule the work item to execute soon.
1056 */
1057 err = ice_ptp_update_cached_phctime(pf);
1058 if (err) {
1059 /* If another thread is updating the Rx rings, we won't
1060 * properly reset them here. This could lead to reporting of
1061 * invalid timestamps, but there isn't much we can do.
1062 */
1063 dev_warn(dev, "%s: ICE_CFG_BUSY, unable to immediately update cached PHC time\n",
1064 __func__);
1065
1066 /* Queue the work item to update the Rx rings when possible */
1067 kthread_queue_delayed_work(pf->ptp.kworker, &pf->ptp.work,
1068 msecs_to_jiffies(10));
1069 }
1070
1071 /* Mark any outstanding timestamps as stale, since they might have
1072 * been captured in hardware before the time update. This could lead
1073 * to us extending them with the wrong cached value resulting in
1074 * incorrect timestamp values.
1075 */
1076 ice_ptp_mark_tx_tracker_stale(&pf->ptp.port.tx);
1077}
1078
1079/**
1080 * ice_ptp_read_time - Read the time from the device
1081 * @pf: Board private structure
1082 * @ts: timespec structure to hold the current time value
1083 * @sts: Optional parameter for holding a pair of system timestamps from
1084 * the system clock. Will be ignored if NULL is given.
1085 *
1086 * This function reads the source clock registers and stores them in a timespec.
1087 * However, since the registers are 64 bits of nanoseconds, we must convert the
1088 * result to a timespec before we can return.
1089 */
1090static void
1091ice_ptp_read_time(struct ice_pf *pf, struct timespec64 *ts,
1092 struct ptp_system_timestamp *sts)
1093{
1094 u64 time_ns = ice_ptp_read_src_clk_reg(pf, sts);
1095
1096 *ts = ns_to_timespec64(time_ns);
1097}
1098
1099/**
1100 * ice_ptp_write_init - Set PHC time to provided value
1101 * @pf: Board private structure
1102 * @ts: timespec structure that holds the new time value
1103 *
1104 * Set the PHC time to the specified time provided in the timespec.
1105 */
1106static int ice_ptp_write_init(struct ice_pf *pf, struct timespec64 *ts)
1107{
1108 u64 ns = timespec64_to_ns(ts);
1109 struct ice_hw *hw = &pf->hw;
1110
1111 return ice_ptp_init_time(hw, ns);
1112}
1113
1114/**
1115 * ice_ptp_write_adj - Adjust PHC clock time atomically
1116 * @pf: Board private structure
1117 * @adj: Adjustment in nanoseconds
1118 *
1119 * Perform an atomic adjustment of the PHC time by the specified number of
1120 * nanoseconds.
1121 */
1122static int ice_ptp_write_adj(struct ice_pf *pf, s32 adj)
1123{
1124 struct ice_hw *hw = &pf->hw;
1125
1126 return ice_ptp_adj_clock(hw, adj);
1127}
1128
1129/**
1130 * ice_base_incval - Get base timer increment value
1131 * @pf: Board private structure
1132 *
1133 * Look up the base timer increment value for this device. The base increment
1134 * value is used to define the nominal clock tick rate. This increment value
1135 * is programmed during device initialization. It is also used as the basis
1136 * for calculating adjustments using scaled_ppm.
1137 */
1138static u64 ice_base_incval(struct ice_pf *pf)
1139{
1140 struct ice_hw *hw = &pf->hw;
1141 u64 incval;
1142
1143 if (ice_is_e810(hw))
1144 incval = ICE_PTP_NOMINAL_INCVAL_E810;
1145 else if (ice_e822_time_ref(hw) < NUM_ICE_TIME_REF_FREQ)
1146 incval = ice_e822_nominal_incval(ice_e822_time_ref(hw));
1147 else
1148 incval = UNKNOWN_INCVAL_E822;
1149
1150 dev_dbg(ice_pf_to_dev(pf), "PTP: using base increment value of 0x%016llx\n",
1151 incval);
1152
1153 return incval;
1154}
1155
1156/**
1157 * ice_ptp_check_tx_fifo - Check whether Tx FIFO is in an OK state
1158 * @port: PTP port for which Tx FIFO is checked
1159 */
1160static int ice_ptp_check_tx_fifo(struct ice_ptp_port *port)
1161{
1162 int quad = port->port_num / ICE_PORTS_PER_QUAD;
1163 int offs = port->port_num % ICE_PORTS_PER_QUAD;
1164 struct ice_pf *pf;
1165 struct ice_hw *hw;
1166 u32 val, phy_sts;
1167 int err;
1168
1169 pf = ptp_port_to_pf(port);
1170 hw = &pf->hw;
1171
1172 if (port->tx_fifo_busy_cnt == FIFO_OK)
1173 return 0;
1174
1175 /* need to read FIFO state */
1176 if (offs == 0 || offs == 1)
1177 err = ice_read_quad_reg_e822(hw, quad, Q_REG_FIFO01_STATUS,
1178 &val);
1179 else
1180 err = ice_read_quad_reg_e822(hw, quad, Q_REG_FIFO23_STATUS,
1181 &val);
1182
1183 if (err) {
1184 dev_err(ice_pf_to_dev(pf), "PTP failed to check port %d Tx FIFO, err %d\n",
1185 port->port_num, err);
1186 return err;
1187 }
1188
1189 if (offs & 0x1)
1190 phy_sts = (val & Q_REG_FIFO13_M) >> Q_REG_FIFO13_S;
1191 else
1192 phy_sts = (val & Q_REG_FIFO02_M) >> Q_REG_FIFO02_S;
1193
1194 if (phy_sts & FIFO_EMPTY) {
1195 port->tx_fifo_busy_cnt = FIFO_OK;
1196 return 0;
1197 }
1198
1199 port->tx_fifo_busy_cnt++;
1200
1201 dev_dbg(ice_pf_to_dev(pf), "Try %d, port %d FIFO not empty\n",
1202 port->tx_fifo_busy_cnt, port->port_num);
1203
1204 if (port->tx_fifo_busy_cnt == ICE_PTP_FIFO_NUM_CHECKS) {
1205 dev_dbg(ice_pf_to_dev(pf),
1206 "Port %d Tx FIFO still not empty; resetting quad %d\n",
1207 port->port_num, quad);
1208 ice_ptp_reset_ts_memory_quad_e822(hw, quad);
1209 port->tx_fifo_busy_cnt = FIFO_OK;
1210 return 0;
1211 }
1212
1213 return -EAGAIN;
1214}
1215
1216/**
1217 * ice_ptp_wait_for_offsets - Check for valid Tx and Rx offsets
1218 * @work: Pointer to the kthread_work structure for this task
1219 *
1220 * Check whether hardware has completed measuring the Tx and Rx offset values
1221 * used to configure and enable vernier timestamp calibration.
1222 *
1223 * Once the offset in either direction is measured, configure the associated
1224 * registers with the calibrated offset values and enable timestamping. The Tx
1225 * and Rx directions are configured independently as soon as their associated
1226 * offsets are known.
1227 *
1228 * This function reschedules itself until both Tx and Rx calibration have
1229 * completed.
1230 */
1231static void ice_ptp_wait_for_offsets(struct kthread_work *work)
1232{
1233 struct ice_ptp_port *port;
1234 struct ice_pf *pf;
1235 struct ice_hw *hw;
1236 int tx_err;
1237 int rx_err;
1238
1239 port = container_of(work, struct ice_ptp_port, ov_work.work);
1240 pf = ptp_port_to_pf(port);
1241 hw = &pf->hw;
1242
1243 if (ice_is_reset_in_progress(pf->state)) {
1244 /* wait for device driver to complete reset */
1245 kthread_queue_delayed_work(pf->ptp.kworker,
1246 &port->ov_work,
1247 msecs_to_jiffies(100));
1248 return;
1249 }
1250
1251 tx_err = ice_ptp_check_tx_fifo(port);
1252 if (!tx_err)
1253 tx_err = ice_phy_cfg_tx_offset_e822(hw, port->port_num);
1254 rx_err = ice_phy_cfg_rx_offset_e822(hw, port->port_num);
1255 if (tx_err || rx_err) {
1256 /* Tx and/or Rx offset not yet configured, try again later */
1257 kthread_queue_delayed_work(pf->ptp.kworker,
1258 &port->ov_work,
1259 msecs_to_jiffies(100));
1260 return;
1261 }
1262}
1263
1264/**
1265 * ice_ptp_port_phy_stop - Stop timestamping for a PHY port
1266 * @ptp_port: PTP port to stop
1267 */
1268static int
1269ice_ptp_port_phy_stop(struct ice_ptp_port *ptp_port)
1270{
1271 struct ice_pf *pf = ptp_port_to_pf(ptp_port);
1272 u8 port = ptp_port->port_num;
1273 struct ice_hw *hw = &pf->hw;
1274 int err;
1275
1276 if (ice_is_e810(hw))
1277 return 0;
1278
1279 mutex_lock(&ptp_port->ps_lock);
1280
1281 kthread_cancel_delayed_work_sync(&ptp_port->ov_work);
1282
1283 err = ice_stop_phy_timer_e822(hw, port, true);
1284 if (err)
1285 dev_err(ice_pf_to_dev(pf), "PTP failed to set PHY port %d down, err %d\n",
1286 port, err);
1287
1288 mutex_unlock(&ptp_port->ps_lock);
1289
1290 return err;
1291}
1292
1293/**
1294 * ice_ptp_port_phy_restart - (Re)start and calibrate PHY timestamping
1295 * @ptp_port: PTP port for which the PHY start is set
1296 *
1297 * Start the PHY timestamping block, and initiate Vernier timestamping
1298 * calibration. If timestamping cannot be calibrated (such as if link is down)
1299 * then disable the timestamping block instead.
1300 */
1301static int
1302ice_ptp_port_phy_restart(struct ice_ptp_port *ptp_port)
1303{
1304 struct ice_pf *pf = ptp_port_to_pf(ptp_port);
1305 u8 port = ptp_port->port_num;
1306 struct ice_hw *hw = &pf->hw;
1307 int err;
1308
1309 if (ice_is_e810(hw))
1310 return 0;
1311
1312 if (!ptp_port->link_up)
1313 return ice_ptp_port_phy_stop(ptp_port);
1314
1315 mutex_lock(&ptp_port->ps_lock);
1316
1317 kthread_cancel_delayed_work_sync(&ptp_port->ov_work);
1318
1319 /* temporarily disable Tx timestamps while calibrating PHY offset */
1320 spin_lock(&ptp_port->tx.lock);
1321 ptp_port->tx.calibrating = true;
1322 spin_unlock(&ptp_port->tx.lock);
1323 ptp_port->tx_fifo_busy_cnt = 0;
1324
1325 /* Start the PHY timer in Vernier mode */
1326 err = ice_start_phy_timer_e822(hw, port);
1327 if (err)
1328 goto out_unlock;
1329
1330 /* Enable Tx timestamps right away */
1331 spin_lock(&ptp_port->tx.lock);
1332 ptp_port->tx.calibrating = false;
1333 spin_unlock(&ptp_port->tx.lock);
1334
1335 kthread_queue_delayed_work(pf->ptp.kworker, &ptp_port->ov_work, 0);
1336
1337out_unlock:
1338 if (err)
1339 dev_err(ice_pf_to_dev(pf), "PTP failed to set PHY port %d up, err %d\n",
1340 port, err);
1341
1342 mutex_unlock(&ptp_port->ps_lock);
1343
1344 return err;
1345}
1346
1347/**
1348 * ice_ptp_link_change - Reconfigure PTP after link status change
1349 * @pf: Board private structure
1350 * @port: Port for which the PHY start is set
1351 * @linkup: Link is up or down
1352 */
1353void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup)
1354{
1355 struct ice_ptp_port *ptp_port;
1356
1357 if (!test_bit(ICE_FLAG_PTP, pf->flags))
1358 return;
1359
1360 if (WARN_ON_ONCE(port >= ICE_NUM_EXTERNAL_PORTS))
1361 return;
1362
1363 ptp_port = &pf->ptp.port;
1364 if (WARN_ON_ONCE(ptp_port->port_num != port))
1365 return;
1366
1367 /* Update cached link status for this port immediately */
1368 ptp_port->link_up = linkup;
1369
1370 /* E810 devices do not need to reconfigure the PHY */
1371 if (ice_is_e810(&pf->hw))
1372 return;
1373
1374 ice_ptp_port_phy_restart(ptp_port);
1375}
1376
1377/**
1378 * ice_ptp_tx_ena_intr - Enable or disable the Tx timestamp interrupt
1379 * @pf: PF private structure
1380 * @ena: bool value to enable or disable interrupt
1381 * @threshold: Minimum number of packets at which intr is triggered
1382 *
1383 * Utility function to enable or disable Tx timestamp interrupt and threshold
1384 */
1385static int ice_ptp_tx_ena_intr(struct ice_pf *pf, bool ena, u32 threshold)
1386{
1387 struct ice_hw *hw = &pf->hw;
1388 int err = 0;
1389 int quad;
1390 u32 val;
1391
1392 ice_ptp_reset_ts_memory(hw);
1393
1394 for (quad = 0; quad < ICE_MAX_QUAD; quad++) {
1395 err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG,
1396 &val);
1397 if (err)
1398 break;
1399
1400 if (ena) {
1401 val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
1402 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M;
1403 val |= ((threshold << Q_REG_TX_MEM_GBL_CFG_INTR_THR_S) &
1404 Q_REG_TX_MEM_GBL_CFG_INTR_THR_M);
1405 } else {
1406 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
1407 }
1408
1409 err = ice_write_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG,
1410 val);
1411 if (err)
1412 break;
1413 }
1414
1415 if (err)
1416 dev_err(ice_pf_to_dev(pf), "PTP failed in intr ena, err %d\n",
1417 err);
1418 return err;
1419}
1420
1421/**
1422 * ice_ptp_reset_phy_timestamping - Reset PHY timestamping block
1423 * @pf: Board private structure
1424 */
1425static void ice_ptp_reset_phy_timestamping(struct ice_pf *pf)
1426{
1427 ice_ptp_port_phy_restart(&pf->ptp.port);
1428}
1429
1430/**
1431 * ice_ptp_adjfine - Adjust clock increment rate
1432 * @info: the driver's PTP info structure
1433 * @scaled_ppm: Parts per million with 16-bit fractional field
1434 *
1435 * Adjust the frequency of the clock by the indicated scaled ppm from the
1436 * base frequency.
1437 */
1438static int ice_ptp_adjfine(struct ptp_clock_info *info, long scaled_ppm)
1439{
1440 struct ice_pf *pf = ptp_info_to_pf(info);
1441 struct ice_hw *hw = &pf->hw;
1442 u64 incval;
1443 int err;
1444
1445 incval = adjust_by_scaled_ppm(ice_base_incval(pf), scaled_ppm);
1446 err = ice_ptp_write_incval_locked(hw, incval);
1447 if (err) {
1448 dev_err(ice_pf_to_dev(pf), "PTP failed to set incval, err %d\n",
1449 err);
1450 return -EIO;
1451 }
1452
1453 return 0;
1454}
1455
1456/**
1457 * ice_ptp_extts_work - Workqueue task function
1458 * @work: external timestamp work structure
1459 *
1460 * Service for PTP external clock event
1461 */
1462static void ice_ptp_extts_work(struct kthread_work *work)
1463{
1464 struct ice_ptp *ptp = container_of(work, struct ice_ptp, extts_work);
1465 struct ice_pf *pf = container_of(ptp, struct ice_pf, ptp);
1466 struct ptp_clock_event event;
1467 struct ice_hw *hw = &pf->hw;
1468 u8 chan, tmr_idx;
1469 u32 hi, lo;
1470
1471 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
1472 /* Event time is captured by one of the two matched registers
1473 * GLTSYN_EVNT_L: 32 LSB of sampled time event
1474 * GLTSYN_EVNT_H: 32 MSB of sampled time event
1475 * Event is defined in GLTSYN_EVNT_0 register
1476 */
1477 for (chan = 0; chan < GLTSYN_EVNT_H_IDX_MAX; chan++) {
1478 /* Check if channel is enabled */
1479 if (pf->ptp.ext_ts_irq & (1 << chan)) {
1480 lo = rd32(hw, GLTSYN_EVNT_L(chan, tmr_idx));
1481 hi = rd32(hw, GLTSYN_EVNT_H(chan, tmr_idx));
1482 event.timestamp = (((u64)hi) << 32) | lo;
1483 event.type = PTP_CLOCK_EXTTS;
1484 event.index = chan;
1485
1486 /* Fire event */
1487 ptp_clock_event(pf->ptp.clock, &event);
1488 pf->ptp.ext_ts_irq &= ~(1 << chan);
1489 }
1490 }
1491}
1492
1493/**
1494 * ice_ptp_cfg_extts - Configure EXTTS pin and channel
1495 * @pf: Board private structure
1496 * @ena: true to enable; false to disable
1497 * @chan: GPIO channel (0-3)
1498 * @gpio_pin: GPIO pin
1499 * @extts_flags: request flags from the ptp_extts_request.flags
1500 */
1501static int
1502ice_ptp_cfg_extts(struct ice_pf *pf, bool ena, unsigned int chan, u32 gpio_pin,
1503 unsigned int extts_flags)
1504{
1505 u32 func, aux_reg, gpio_reg, irq_reg;
1506 struct ice_hw *hw = &pf->hw;
1507 u8 tmr_idx;
1508
1509 if (chan > (unsigned int)pf->ptp.info.n_ext_ts)
1510 return -EINVAL;
1511
1512 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
1513
1514 irq_reg = rd32(hw, PFINT_OICR_ENA);
1515
1516 if (ena) {
1517 /* Enable the interrupt */
1518 irq_reg |= PFINT_OICR_TSYN_EVNT_M;
1519 aux_reg = GLTSYN_AUX_IN_0_INT_ENA_M;
1520
1521#define GLTSYN_AUX_IN_0_EVNTLVL_RISING_EDGE BIT(0)
1522#define GLTSYN_AUX_IN_0_EVNTLVL_FALLING_EDGE BIT(1)
1523
1524 /* set event level to requested edge */
1525 if (extts_flags & PTP_FALLING_EDGE)
1526 aux_reg |= GLTSYN_AUX_IN_0_EVNTLVL_FALLING_EDGE;
1527 if (extts_flags & PTP_RISING_EDGE)
1528 aux_reg |= GLTSYN_AUX_IN_0_EVNTLVL_RISING_EDGE;
1529
1530 /* Write GPIO CTL reg.
1531 * 0x1 is input sampled by EVENT register(channel)
1532 * + num_in_channels * tmr_idx
1533 */
1534 func = 1 + chan + (tmr_idx * 3);
1535 gpio_reg = ((func << GLGEN_GPIO_CTL_PIN_FUNC_S) &
1536 GLGEN_GPIO_CTL_PIN_FUNC_M);
1537 pf->ptp.ext_ts_chan |= (1 << chan);
1538 } else {
1539 /* clear the values we set to reset defaults */
1540 aux_reg = 0;
1541 gpio_reg = 0;
1542 pf->ptp.ext_ts_chan &= ~(1 << chan);
1543 if (!pf->ptp.ext_ts_chan)
1544 irq_reg &= ~PFINT_OICR_TSYN_EVNT_M;
1545 }
1546
1547 wr32(hw, PFINT_OICR_ENA, irq_reg);
1548 wr32(hw, GLTSYN_AUX_IN(chan, tmr_idx), aux_reg);
1549 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), gpio_reg);
1550
1551 return 0;
1552}
1553
1554/**
1555 * ice_ptp_cfg_clkout - Configure clock to generate periodic wave
1556 * @pf: Board private structure
1557 * @chan: GPIO channel (0-3)
1558 * @config: desired periodic clk configuration. NULL will disable channel
1559 * @store: If set to true the values will be stored
1560 *
1561 * Configure the internal clock generator modules to generate the clock wave of
1562 * specified period.
1563 */
1564static int ice_ptp_cfg_clkout(struct ice_pf *pf, unsigned int chan,
1565 struct ice_perout_channel *config, bool store)
1566{
1567 u64 current_time, period, start_time, phase;
1568 struct ice_hw *hw = &pf->hw;
1569 u32 func, val, gpio_pin;
1570 u8 tmr_idx;
1571
1572 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
1573
1574 /* 0. Reset mode & out_en in AUX_OUT */
1575 wr32(hw, GLTSYN_AUX_OUT(chan, tmr_idx), 0);
1576
1577 /* If we're disabling the output, clear out CLKO and TGT and keep
1578 * output level low
1579 */
1580 if (!config || !config->ena) {
1581 wr32(hw, GLTSYN_CLKO(chan, tmr_idx), 0);
1582 wr32(hw, GLTSYN_TGT_L(chan, tmr_idx), 0);
1583 wr32(hw, GLTSYN_TGT_H(chan, tmr_idx), 0);
1584
1585 val = GLGEN_GPIO_CTL_PIN_DIR_M;
1586 gpio_pin = pf->ptp.perout_channels[chan].gpio_pin;
1587 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), val);
1588
1589 /* Store the value if requested */
1590 if (store)
1591 memset(&pf->ptp.perout_channels[chan], 0,
1592 sizeof(struct ice_perout_channel));
1593
1594 return 0;
1595 }
1596 period = config->period;
1597 start_time = config->start_time;
1598 div64_u64_rem(start_time, period, &phase);
1599 gpio_pin = config->gpio_pin;
1600
1601 /* 1. Write clkout with half of required period value */
1602 if (period & 0x1) {
1603 dev_err(ice_pf_to_dev(pf), "CLK Period must be an even value\n");
1604 goto err;
1605 }
1606
1607 period >>= 1;
1608
1609 /* For proper operation, the GLTSYN_CLKO must be larger than clock tick
1610 */
1611#define MIN_PULSE 3
1612 if (period <= MIN_PULSE || period > U32_MAX) {
1613 dev_err(ice_pf_to_dev(pf), "CLK Period must be > %d && < 2^33",
1614 MIN_PULSE * 2);
1615 goto err;
1616 }
1617
1618 wr32(hw, GLTSYN_CLKO(chan, tmr_idx), lower_32_bits(period));
1619
1620 /* Allow time for programming before start_time is hit */
1621 current_time = ice_ptp_read_src_clk_reg(pf, NULL);
1622
1623 /* if start time is in the past start the timer at the nearest second
1624 * maintaining phase
1625 */
1626 if (start_time < current_time)
1627 start_time = div64_u64(current_time + NSEC_PER_SEC - 1,
1628 NSEC_PER_SEC) * NSEC_PER_SEC + phase;
1629
1630 if (ice_is_e810(hw))
1631 start_time -= E810_OUT_PROP_DELAY_NS;
1632 else
1633 start_time -= ice_e822_pps_delay(ice_e822_time_ref(hw));
1634
1635 /* 2. Write TARGET time */
1636 wr32(hw, GLTSYN_TGT_L(chan, tmr_idx), lower_32_bits(start_time));
1637 wr32(hw, GLTSYN_TGT_H(chan, tmr_idx), upper_32_bits(start_time));
1638
1639 /* 3. Write AUX_OUT register */
1640 val = GLTSYN_AUX_OUT_0_OUT_ENA_M | GLTSYN_AUX_OUT_0_OUTMOD_M;
1641 wr32(hw, GLTSYN_AUX_OUT(chan, tmr_idx), val);
1642
1643 /* 4. write GPIO CTL reg */
1644 func = 8 + chan + (tmr_idx * 4);
1645 val = GLGEN_GPIO_CTL_PIN_DIR_M |
1646 ((func << GLGEN_GPIO_CTL_PIN_FUNC_S) & GLGEN_GPIO_CTL_PIN_FUNC_M);
1647 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), val);
1648
1649 /* Store the value if requested */
1650 if (store) {
1651 memcpy(&pf->ptp.perout_channels[chan], config,
1652 sizeof(struct ice_perout_channel));
1653 pf->ptp.perout_channels[chan].start_time = phase;
1654 }
1655
1656 return 0;
1657err:
1658 dev_err(ice_pf_to_dev(pf), "PTP failed to cfg per_clk\n");
1659 return -EFAULT;
1660}
1661
1662/**
1663 * ice_ptp_disable_all_clkout - Disable all currently configured outputs
1664 * @pf: pointer to the PF structure
1665 *
1666 * Disable all currently configured clock outputs. This is necessary before
1667 * certain changes to the PTP hardware clock. Use ice_ptp_enable_all_clkout to
1668 * re-enable the clocks again.
1669 */
1670static void ice_ptp_disable_all_clkout(struct ice_pf *pf)
1671{
1672 uint i;
1673
1674 for (i = 0; i < pf->ptp.info.n_per_out; i++)
1675 if (pf->ptp.perout_channels[i].ena)
1676 ice_ptp_cfg_clkout(pf, i, NULL, false);
1677}
1678
1679/**
1680 * ice_ptp_enable_all_clkout - Enable all configured periodic clock outputs
1681 * @pf: pointer to the PF structure
1682 *
1683 * Enable all currently configured clock outputs. Use this after
1684 * ice_ptp_disable_all_clkout to reconfigure the output signals according to
1685 * their configuration.
1686 */
1687static void ice_ptp_enable_all_clkout(struct ice_pf *pf)
1688{
1689 uint i;
1690
1691 for (i = 0; i < pf->ptp.info.n_per_out; i++)
1692 if (pf->ptp.perout_channels[i].ena)
1693 ice_ptp_cfg_clkout(pf, i, &pf->ptp.perout_channels[i],
1694 false);
1695}
1696
1697/**
1698 * ice_ptp_gpio_enable_e810 - Enable/disable ancillary features of PHC
1699 * @info: the driver's PTP info structure
1700 * @rq: The requested feature to change
1701 * @on: Enable/disable flag
1702 */
1703static int
1704ice_ptp_gpio_enable_e810(struct ptp_clock_info *info,
1705 struct ptp_clock_request *rq, int on)
1706{
1707 struct ice_pf *pf = ptp_info_to_pf(info);
1708 struct ice_perout_channel clk_cfg = {0};
1709 bool sma_pres = false;
1710 unsigned int chan;
1711 u32 gpio_pin;
1712 int err;
1713
1714 if (ice_is_feature_supported(pf, ICE_F_SMA_CTRL))
1715 sma_pres = true;
1716
1717 switch (rq->type) {
1718 case PTP_CLK_REQ_PEROUT:
1719 chan = rq->perout.index;
1720 if (sma_pres) {
1721 if (chan == ice_pin_desc_e810t[SMA1].chan)
1722 clk_cfg.gpio_pin = GPIO_20;
1723 else if (chan == ice_pin_desc_e810t[SMA2].chan)
1724 clk_cfg.gpio_pin = GPIO_22;
1725 else
1726 return -1;
1727 } else if (ice_is_e810t(&pf->hw)) {
1728 if (chan == 0)
1729 clk_cfg.gpio_pin = GPIO_20;
1730 else
1731 clk_cfg.gpio_pin = GPIO_22;
1732 } else if (chan == PPS_CLK_GEN_CHAN) {
1733 clk_cfg.gpio_pin = PPS_PIN_INDEX;
1734 } else {
1735 clk_cfg.gpio_pin = chan;
1736 }
1737
1738 clk_cfg.period = ((rq->perout.period.sec * NSEC_PER_SEC) +
1739 rq->perout.period.nsec);
1740 clk_cfg.start_time = ((rq->perout.start.sec * NSEC_PER_SEC) +
1741 rq->perout.start.nsec);
1742 clk_cfg.ena = !!on;
1743
1744 err = ice_ptp_cfg_clkout(pf, chan, &clk_cfg, true);
1745 break;
1746 case PTP_CLK_REQ_EXTTS:
1747 chan = rq->extts.index;
1748 if (sma_pres) {
1749 if (chan < ice_pin_desc_e810t[SMA2].chan)
1750 gpio_pin = GPIO_21;
1751 else
1752 gpio_pin = GPIO_23;
1753 } else if (ice_is_e810t(&pf->hw)) {
1754 if (chan == 0)
1755 gpio_pin = GPIO_21;
1756 else
1757 gpio_pin = GPIO_23;
1758 } else {
1759 gpio_pin = chan;
1760 }
1761
1762 err = ice_ptp_cfg_extts(pf, !!on, chan, gpio_pin,
1763 rq->extts.flags);
1764 break;
1765 default:
1766 return -EOPNOTSUPP;
1767 }
1768
1769 return err;
1770}
1771
1772/**
1773 * ice_ptp_gettimex64 - Get the time of the clock
1774 * @info: the driver's PTP info structure
1775 * @ts: timespec64 structure to hold the current time value
1776 * @sts: Optional parameter for holding a pair of system timestamps from
1777 * the system clock. Will be ignored if NULL is given.
1778 *
1779 * Read the device clock and return the correct value on ns, after converting it
1780 * into a timespec struct.
1781 */
1782static int
1783ice_ptp_gettimex64(struct ptp_clock_info *info, struct timespec64 *ts,
1784 struct ptp_system_timestamp *sts)
1785{
1786 struct ice_pf *pf = ptp_info_to_pf(info);
1787 struct ice_hw *hw = &pf->hw;
1788
1789 if (!ice_ptp_lock(hw)) {
1790 dev_err(ice_pf_to_dev(pf), "PTP failed to get time\n");
1791 return -EBUSY;
1792 }
1793
1794 ice_ptp_read_time(pf, ts, sts);
1795 ice_ptp_unlock(hw);
1796
1797 return 0;
1798}
1799
1800/**
1801 * ice_ptp_settime64 - Set the time of the clock
1802 * @info: the driver's PTP info structure
1803 * @ts: timespec64 structure that holds the new time value
1804 *
1805 * Set the device clock to the user input value. The conversion from timespec
1806 * to ns happens in the write function.
1807 */
1808static int
1809ice_ptp_settime64(struct ptp_clock_info *info, const struct timespec64 *ts)
1810{
1811 struct ice_pf *pf = ptp_info_to_pf(info);
1812 struct timespec64 ts64 = *ts;
1813 struct ice_hw *hw = &pf->hw;
1814 int err;
1815
1816 /* For Vernier mode, we need to recalibrate after new settime
1817 * Start with disabling timestamp block
1818 */
1819 if (pf->ptp.port.link_up)
1820 ice_ptp_port_phy_stop(&pf->ptp.port);
1821
1822 if (!ice_ptp_lock(hw)) {
1823 err = -EBUSY;
1824 goto exit;
1825 }
1826
1827 /* Disable periodic outputs */
1828 ice_ptp_disable_all_clkout(pf);
1829
1830 err = ice_ptp_write_init(pf, &ts64);
1831 ice_ptp_unlock(hw);
1832
1833 if (!err)
1834 ice_ptp_reset_cached_phctime(pf);
1835
1836 /* Reenable periodic outputs */
1837 ice_ptp_enable_all_clkout(pf);
1838
1839 /* Recalibrate and re-enable timestamp block */
1840 if (pf->ptp.port.link_up)
1841 ice_ptp_port_phy_restart(&pf->ptp.port);
1842exit:
1843 if (err) {
1844 dev_err(ice_pf_to_dev(pf), "PTP failed to set time %d\n", err);
1845 return err;
1846 }
1847
1848 return 0;
1849}
1850
1851/**
1852 * ice_ptp_adjtime_nonatomic - Do a non-atomic clock adjustment
1853 * @info: the driver's PTP info structure
1854 * @delta: Offset in nanoseconds to adjust the time by
1855 */
1856static int ice_ptp_adjtime_nonatomic(struct ptp_clock_info *info, s64 delta)
1857{
1858 struct timespec64 now, then;
1859 int ret;
1860
1861 then = ns_to_timespec64(delta);
1862 ret = ice_ptp_gettimex64(info, &now, NULL);
1863 if (ret)
1864 return ret;
1865 now = timespec64_add(now, then);
1866
1867 return ice_ptp_settime64(info, (const struct timespec64 *)&now);
1868}
1869
1870/**
1871 * ice_ptp_adjtime - Adjust the time of the clock by the indicated delta
1872 * @info: the driver's PTP info structure
1873 * @delta: Offset in nanoseconds to adjust the time by
1874 */
1875static int ice_ptp_adjtime(struct ptp_clock_info *info, s64 delta)
1876{
1877 struct ice_pf *pf = ptp_info_to_pf(info);
1878 struct ice_hw *hw = &pf->hw;
1879 struct device *dev;
1880 int err;
1881
1882 dev = ice_pf_to_dev(pf);
1883
1884 /* Hardware only supports atomic adjustments using signed 32-bit
1885 * integers. For any adjustment outside this range, perform
1886 * a non-atomic get->adjust->set flow.
1887 */
1888 if (delta > S32_MAX || delta < S32_MIN) {
1889 dev_dbg(dev, "delta = %lld, adjtime non-atomic\n", delta);
1890 return ice_ptp_adjtime_nonatomic(info, delta);
1891 }
1892
1893 if (!ice_ptp_lock(hw)) {
1894 dev_err(dev, "PTP failed to acquire semaphore in adjtime\n");
1895 return -EBUSY;
1896 }
1897
1898 /* Disable periodic outputs */
1899 ice_ptp_disable_all_clkout(pf);
1900
1901 err = ice_ptp_write_adj(pf, delta);
1902
1903 /* Reenable periodic outputs */
1904 ice_ptp_enable_all_clkout(pf);
1905
1906 ice_ptp_unlock(hw);
1907
1908 if (err) {
1909 dev_err(dev, "PTP failed to adjust time, err %d\n", err);
1910 return err;
1911 }
1912
1913 ice_ptp_reset_cached_phctime(pf);
1914
1915 return 0;
1916}
1917
1918#ifdef CONFIG_ICE_HWTS
1919/**
1920 * ice_ptp_get_syncdevicetime - Get the cross time stamp info
1921 * @device: Current device time
1922 * @system: System counter value read synchronously with device time
1923 * @ctx: Context provided by timekeeping code
1924 *
1925 * Read device and system (ART) clock simultaneously and return the corrected
1926 * clock values in ns.
1927 */
1928static int
1929ice_ptp_get_syncdevicetime(ktime_t *device,
1930 struct system_counterval_t *system,
1931 void *ctx)
1932{
1933 struct ice_pf *pf = (struct ice_pf *)ctx;
1934 struct ice_hw *hw = &pf->hw;
1935 u32 hh_lock, hh_art_ctl;
1936 int i;
1937
1938 /* Get the HW lock */
1939 hh_lock = rd32(hw, PFHH_SEM + (PFTSYN_SEM_BYTES * hw->pf_id));
1940 if (hh_lock & PFHH_SEM_BUSY_M) {
1941 dev_err(ice_pf_to_dev(pf), "PTP failed to get hh lock\n");
1942 return -EFAULT;
1943 }
1944
1945 /* Start the ART and device clock sync sequence */
1946 hh_art_ctl = rd32(hw, GLHH_ART_CTL);
1947 hh_art_ctl = hh_art_ctl | GLHH_ART_CTL_ACTIVE_M;
1948 wr32(hw, GLHH_ART_CTL, hh_art_ctl);
1949
1950#define MAX_HH_LOCK_TRIES 100
1951
1952 for (i = 0; i < MAX_HH_LOCK_TRIES; i++) {
1953 /* Wait for sync to complete */
1954 hh_art_ctl = rd32(hw, GLHH_ART_CTL);
1955 if (hh_art_ctl & GLHH_ART_CTL_ACTIVE_M) {
1956 udelay(1);
1957 continue;
1958 } else {
1959 u32 hh_ts_lo, hh_ts_hi, tmr_idx;
1960 u64 hh_ts;
1961
1962 tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc;
1963 /* Read ART time */
1964 hh_ts_lo = rd32(hw, GLHH_ART_TIME_L);
1965 hh_ts_hi = rd32(hw, GLHH_ART_TIME_H);
1966 hh_ts = ((u64)hh_ts_hi << 32) | hh_ts_lo;
1967 *system = convert_art_ns_to_tsc(hh_ts);
1968 /* Read Device source clock time */
1969 hh_ts_lo = rd32(hw, GLTSYN_HHTIME_L(tmr_idx));
1970 hh_ts_hi = rd32(hw, GLTSYN_HHTIME_H(tmr_idx));
1971 hh_ts = ((u64)hh_ts_hi << 32) | hh_ts_lo;
1972 *device = ns_to_ktime(hh_ts);
1973 break;
1974 }
1975 }
1976 /* Release HW lock */
1977 hh_lock = rd32(hw, PFHH_SEM + (PFTSYN_SEM_BYTES * hw->pf_id));
1978 hh_lock = hh_lock & ~PFHH_SEM_BUSY_M;
1979 wr32(hw, PFHH_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), hh_lock);
1980
1981 if (i == MAX_HH_LOCK_TRIES)
1982 return -ETIMEDOUT;
1983
1984 return 0;
1985}
1986
1987/**
1988 * ice_ptp_getcrosststamp_e822 - Capture a device cross timestamp
1989 * @info: the driver's PTP info structure
1990 * @cts: The memory to fill the cross timestamp info
1991 *
1992 * Capture a cross timestamp between the ART and the device PTP hardware
1993 * clock. Fill the cross timestamp information and report it back to the
1994 * caller.
1995 *
1996 * This is only valid for E822 devices which have support for generating the
1997 * cross timestamp via PCIe PTM.
1998 *
1999 * In order to correctly correlate the ART timestamp back to the TSC time, the
2000 * CPU must have X86_FEATURE_TSC_KNOWN_FREQ.
2001 */
2002static int
2003ice_ptp_getcrosststamp_e822(struct ptp_clock_info *info,
2004 struct system_device_crosststamp *cts)
2005{
2006 struct ice_pf *pf = ptp_info_to_pf(info);
2007
2008 return get_device_system_crosststamp(ice_ptp_get_syncdevicetime,
2009 pf, NULL, cts);
2010}
2011#endif /* CONFIG_ICE_HWTS */
2012
2013/**
2014 * ice_ptp_get_ts_config - ioctl interface to read the timestamping config
2015 * @pf: Board private structure
2016 * @ifr: ioctl data
2017 *
2018 * Copy the timestamping config to user buffer
2019 */
2020int ice_ptp_get_ts_config(struct ice_pf *pf, struct ifreq *ifr)
2021{
2022 struct hwtstamp_config *config;
2023
2024 if (!test_bit(ICE_FLAG_PTP, pf->flags))
2025 return -EIO;
2026
2027 config = &pf->ptp.tstamp_config;
2028
2029 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
2030 -EFAULT : 0;
2031}
2032
2033/**
2034 * ice_ptp_set_timestamp_mode - Setup driver for requested timestamp mode
2035 * @pf: Board private structure
2036 * @config: hwtstamp settings requested or saved
2037 */
2038static int
2039ice_ptp_set_timestamp_mode(struct ice_pf *pf, struct hwtstamp_config *config)
2040{
2041 switch (config->tx_type) {
2042 case HWTSTAMP_TX_OFF:
2043 ice_set_tx_tstamp(pf, false);
2044 break;
2045 case HWTSTAMP_TX_ON:
2046 ice_set_tx_tstamp(pf, true);
2047 break;
2048 default:
2049 return -ERANGE;
2050 }
2051
2052 switch (config->rx_filter) {
2053 case HWTSTAMP_FILTER_NONE:
2054 ice_set_rx_tstamp(pf, false);
2055 break;
2056 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2057 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2058 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2059 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2060 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2061 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2062 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2063 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2064 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2065 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2066 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2067 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2068 case HWTSTAMP_FILTER_NTP_ALL:
2069 case HWTSTAMP_FILTER_ALL:
2070 ice_set_rx_tstamp(pf, true);
2071 break;
2072 default:
2073 return -ERANGE;
2074 }
2075
2076 return 0;
2077}
2078
2079/**
2080 * ice_ptp_set_ts_config - ioctl interface to control the timestamping
2081 * @pf: Board private structure
2082 * @ifr: ioctl data
2083 *
2084 * Get the user config and store it
2085 */
2086int ice_ptp_set_ts_config(struct ice_pf *pf, struct ifreq *ifr)
2087{
2088 struct hwtstamp_config config;
2089 int err;
2090
2091 if (!test_bit(ICE_FLAG_PTP, pf->flags))
2092 return -EAGAIN;
2093
2094 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2095 return -EFAULT;
2096
2097 err = ice_ptp_set_timestamp_mode(pf, &config);
2098 if (err)
2099 return err;
2100
2101 /* Return the actual configuration set */
2102 config = pf->ptp.tstamp_config;
2103
2104 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
2105 -EFAULT : 0;
2106}
2107
2108/**
2109 * ice_ptp_rx_hwtstamp - Check for an Rx timestamp
2110 * @rx_ring: Ring to get the VSI info
2111 * @rx_desc: Receive descriptor
2112 * @skb: Particular skb to send timestamp with
2113 *
2114 * The driver receives a notification in the receive descriptor with timestamp.
2115 * The timestamp is in ns, so we must convert the result first.
2116 */
2117void
2118ice_ptp_rx_hwtstamp(struct ice_rx_ring *rx_ring,
2119 union ice_32b_rx_flex_desc *rx_desc, struct sk_buff *skb)
2120{
2121 struct skb_shared_hwtstamps *hwtstamps;
2122 u64 ts_ns, cached_time;
2123 u32 ts_high;
2124
2125 if (!(rx_desc->wb.time_stamp_low & ICE_PTP_TS_VALID))
2126 return;
2127
2128 cached_time = READ_ONCE(rx_ring->cached_phctime);
2129
2130 /* Do not report a timestamp if we don't have a cached PHC time */
2131 if (!cached_time)
2132 return;
2133
2134 /* Use ice_ptp_extend_32b_ts directly, using the ring-specific cached
2135 * PHC value, rather than accessing the PF. This also allows us to
2136 * simply pass the upper 32bits of nanoseconds directly. Calling
2137 * ice_ptp_extend_40b_ts is unnecessary as it would just discard these
2138 * bits itself.
2139 */
2140 ts_high = le32_to_cpu(rx_desc->wb.flex_ts.ts_high);
2141 ts_ns = ice_ptp_extend_32b_ts(cached_time, ts_high);
2142
2143 hwtstamps = skb_hwtstamps(skb);
2144 memset(hwtstamps, 0, sizeof(*hwtstamps));
2145 hwtstamps->hwtstamp = ns_to_ktime(ts_ns);
2146}
2147
2148/**
2149 * ice_ptp_disable_sma_pins_e810t - Disable E810-T SMA pins
2150 * @pf: pointer to the PF structure
2151 * @info: PTP clock info structure
2152 *
2153 * Disable the OS access to the SMA pins. Called to clear out the OS
2154 * indications of pin support when we fail to setup the E810-T SMA control
2155 * register.
2156 */
2157static void
2158ice_ptp_disable_sma_pins_e810t(struct ice_pf *pf, struct ptp_clock_info *info)
2159{
2160 struct device *dev = ice_pf_to_dev(pf);
2161
2162 dev_warn(dev, "Failed to configure E810-T SMA pin control\n");
2163
2164 info->enable = NULL;
2165 info->verify = NULL;
2166 info->n_pins = 0;
2167 info->n_ext_ts = 0;
2168 info->n_per_out = 0;
2169}
2170
2171/**
2172 * ice_ptp_setup_sma_pins_e810t - Setup the SMA pins
2173 * @pf: pointer to the PF structure
2174 * @info: PTP clock info structure
2175 *
2176 * Finish setting up the SMA pins by allocating pin_config, and setting it up
2177 * according to the current status of the SMA. On failure, disable all of the
2178 * extended SMA pin support.
2179 */
2180static void
2181ice_ptp_setup_sma_pins_e810t(struct ice_pf *pf, struct ptp_clock_info *info)
2182{
2183 struct device *dev = ice_pf_to_dev(pf);
2184 int err;
2185
2186 /* Allocate memory for kernel pins interface */
2187 info->pin_config = devm_kcalloc(dev, info->n_pins,
2188 sizeof(*info->pin_config), GFP_KERNEL);
2189 if (!info->pin_config) {
2190 ice_ptp_disable_sma_pins_e810t(pf, info);
2191 return;
2192 }
2193
2194 /* Read current SMA status */
2195 err = ice_get_sma_config_e810t(&pf->hw, info->pin_config);
2196 if (err)
2197 ice_ptp_disable_sma_pins_e810t(pf, info);
2198}
2199
2200/**
2201 * ice_ptp_setup_pins_e810 - Setup PTP pins in sysfs
2202 * @pf: pointer to the PF instance
2203 * @info: PTP clock capabilities
2204 */
2205static void
2206ice_ptp_setup_pins_e810(struct ice_pf *pf, struct ptp_clock_info *info)
2207{
2208 info->n_per_out = N_PER_OUT_E810;
2209
2210 if (ice_is_feature_supported(pf, ICE_F_PTP_EXTTS))
2211 info->n_ext_ts = N_EXT_TS_E810;
2212
2213 if (ice_is_feature_supported(pf, ICE_F_SMA_CTRL)) {
2214 info->n_ext_ts = N_EXT_TS_E810;
2215 info->n_pins = NUM_PTP_PINS_E810T;
2216 info->verify = ice_verify_pin_e810t;
2217
2218 /* Complete setup of the SMA pins */
2219 ice_ptp_setup_sma_pins_e810t(pf, info);
2220 }
2221}
2222
2223/**
2224 * ice_ptp_set_funcs_e822 - Set specialized functions for E822 support
2225 * @pf: Board private structure
2226 * @info: PTP info to fill
2227 *
2228 * Assign functions to the PTP capabiltiies structure for E822 devices.
2229 * Functions which operate across all device families should be set directly
2230 * in ice_ptp_set_caps. Only add functions here which are distinct for E822
2231 * devices.
2232 */
2233static void
2234ice_ptp_set_funcs_e822(struct ice_pf *pf, struct ptp_clock_info *info)
2235{
2236#ifdef CONFIG_ICE_HWTS
2237 if (boot_cpu_has(X86_FEATURE_ART) &&
2238 boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ))
2239 info->getcrosststamp = ice_ptp_getcrosststamp_e822;
2240#endif /* CONFIG_ICE_HWTS */
2241}
2242
2243/**
2244 * ice_ptp_set_funcs_e810 - Set specialized functions for E810 support
2245 * @pf: Board private structure
2246 * @info: PTP info to fill
2247 *
2248 * Assign functions to the PTP capabiltiies structure for E810 devices.
2249 * Functions which operate across all device families should be set directly
2250 * in ice_ptp_set_caps. Only add functions here which are distinct for e810
2251 * devices.
2252 */
2253static void
2254ice_ptp_set_funcs_e810(struct ice_pf *pf, struct ptp_clock_info *info)
2255{
2256 info->enable = ice_ptp_gpio_enable_e810;
2257 ice_ptp_setup_pins_e810(pf, info);
2258}
2259
2260/**
2261 * ice_ptp_set_caps - Set PTP capabilities
2262 * @pf: Board private structure
2263 */
2264static void ice_ptp_set_caps(struct ice_pf *pf)
2265{
2266 struct ptp_clock_info *info = &pf->ptp.info;
2267 struct device *dev = ice_pf_to_dev(pf);
2268
2269 snprintf(info->name, sizeof(info->name) - 1, "%s-%s-clk",
2270 dev_driver_string(dev), dev_name(dev));
2271 info->owner = THIS_MODULE;
2272 info->max_adj = 999999999;
2273 info->adjtime = ice_ptp_adjtime;
2274 info->adjfine = ice_ptp_adjfine;
2275 info->gettimex64 = ice_ptp_gettimex64;
2276 info->settime64 = ice_ptp_settime64;
2277
2278 if (ice_is_e810(&pf->hw))
2279 ice_ptp_set_funcs_e810(pf, info);
2280 else
2281 ice_ptp_set_funcs_e822(pf, info);
2282}
2283
2284/**
2285 * ice_ptp_create_clock - Create PTP clock device for userspace
2286 * @pf: Board private structure
2287 *
2288 * This function creates a new PTP clock device. It only creates one if we
2289 * don't already have one. Will return error if it can't create one, but success
2290 * if we already have a device. Should be used by ice_ptp_init to create clock
2291 * initially, and prevent global resets from creating new clock devices.
2292 */
2293static long ice_ptp_create_clock(struct ice_pf *pf)
2294{
2295 struct ptp_clock_info *info;
2296 struct ptp_clock *clock;
2297 struct device *dev;
2298
2299 /* No need to create a clock device if we already have one */
2300 if (pf->ptp.clock)
2301 return 0;
2302
2303 ice_ptp_set_caps(pf);
2304
2305 info = &pf->ptp.info;
2306 dev = ice_pf_to_dev(pf);
2307
2308 /* Attempt to register the clock before enabling the hardware. */
2309 clock = ptp_clock_register(info, dev);
2310 if (IS_ERR(clock))
2311 return PTR_ERR(clock);
2312
2313 pf->ptp.clock = clock;
2314
2315 return 0;
2316}
2317
2318/**
2319 * ice_ptp_request_ts - Request an available Tx timestamp index
2320 * @tx: the PTP Tx timestamp tracker to request from
2321 * @skb: the SKB to associate with this timestamp request
2322 */
2323s8 ice_ptp_request_ts(struct ice_ptp_tx *tx, struct sk_buff *skb)
2324{
2325 u8 idx;
2326
2327 spin_lock(&tx->lock);
2328
2329 /* Check that this tracker is accepting new timestamp requests */
2330 if (!ice_ptp_is_tx_tracker_up(tx)) {
2331 spin_unlock(&tx->lock);
2332 return -1;
2333 }
2334
2335 /* Find and set the first available index */
2336 idx = find_first_zero_bit(tx->in_use, tx->len);
2337 if (idx < tx->len) {
2338 /* We got a valid index that no other thread could have set. Store
2339 * a reference to the skb and the start time to allow discarding old
2340 * requests.
2341 */
2342 set_bit(idx, tx->in_use);
2343 clear_bit(idx, tx->stale);
2344 tx->tstamps[idx].start = jiffies;
2345 tx->tstamps[idx].skb = skb_get(skb);
2346 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2347 ice_trace(tx_tstamp_request, skb, idx);
2348 }
2349
2350 spin_unlock(&tx->lock);
2351
2352 /* return the appropriate PHY timestamp register index, -1 if no
2353 * indexes were available.
2354 */
2355 if (idx >= tx->len)
2356 return -1;
2357 else
2358 return idx + tx->offset;
2359}
2360
2361/**
2362 * ice_ptp_process_ts - Process the PTP Tx timestamps
2363 * @pf: Board private structure
2364 *
2365 * Returns true if timestamps are processed.
2366 */
2367bool ice_ptp_process_ts(struct ice_pf *pf)
2368{
2369 return ice_ptp_tx_tstamp(&pf->ptp.port.tx);
2370}
2371
2372static void ice_ptp_periodic_work(struct kthread_work *work)
2373{
2374 struct ice_ptp *ptp = container_of(work, struct ice_ptp, work.work);
2375 struct ice_pf *pf = container_of(ptp, struct ice_pf, ptp);
2376 int err;
2377
2378 if (!test_bit(ICE_FLAG_PTP, pf->flags))
2379 return;
2380
2381 err = ice_ptp_update_cached_phctime(pf);
2382
2383 /* Run twice a second or reschedule if phc update failed */
2384 kthread_queue_delayed_work(ptp->kworker, &ptp->work,
2385 msecs_to_jiffies(err ? 10 : 500));
2386}
2387
2388/**
2389 * ice_ptp_reset - Initialize PTP hardware clock support after reset
2390 * @pf: Board private structure
2391 */
2392void ice_ptp_reset(struct ice_pf *pf)
2393{
2394 struct ice_ptp *ptp = &pf->ptp;
2395 struct ice_hw *hw = &pf->hw;
2396 struct timespec64 ts;
2397 int err, itr = 1;
2398 u64 time_diff;
2399
2400 if (test_bit(ICE_PFR_REQ, pf->state))
2401 goto pfr;
2402
2403 if (!hw->func_caps.ts_func_info.src_tmr_owned)
2404 goto reset_ts;
2405
2406 err = ice_ptp_init_phc(hw);
2407 if (err)
2408 goto err;
2409
2410 /* Acquire the global hardware lock */
2411 if (!ice_ptp_lock(hw)) {
2412 err = -EBUSY;
2413 goto err;
2414 }
2415
2416 /* Write the increment time value to PHY and LAN */
2417 err = ice_ptp_write_incval(hw, ice_base_incval(pf));
2418 if (err) {
2419 ice_ptp_unlock(hw);
2420 goto err;
2421 }
2422
2423 /* Write the initial Time value to PHY and LAN using the cached PHC
2424 * time before the reset and time difference between stopping and
2425 * starting the clock.
2426 */
2427 if (ptp->cached_phc_time) {
2428 time_diff = ktime_get_real_ns() - ptp->reset_time;
2429 ts = ns_to_timespec64(ptp->cached_phc_time + time_diff);
2430 } else {
2431 ts = ktime_to_timespec64(ktime_get_real());
2432 }
2433 err = ice_ptp_write_init(pf, &ts);
2434 if (err) {
2435 ice_ptp_unlock(hw);
2436 goto err;
2437 }
2438
2439 /* Release the global hardware lock */
2440 ice_ptp_unlock(hw);
2441
2442 if (!ice_is_e810(hw)) {
2443 /* Enable quad interrupts */
2444 err = ice_ptp_tx_ena_intr(pf, true, itr);
2445 if (err)
2446 goto err;
2447 }
2448
2449reset_ts:
2450 /* Restart the PHY timestamping block */
2451 ice_ptp_reset_phy_timestamping(pf);
2452
2453pfr:
2454 /* Init Tx structures */
2455 if (ice_is_e810(&pf->hw)) {
2456 err = ice_ptp_init_tx_e810(pf, &ptp->port.tx);
2457 } else {
2458 kthread_init_delayed_work(&ptp->port.ov_work,
2459 ice_ptp_wait_for_offsets);
2460 err = ice_ptp_init_tx_e822(pf, &ptp->port.tx,
2461 ptp->port.port_num);
2462 }
2463 if (err)
2464 goto err;
2465
2466 set_bit(ICE_FLAG_PTP, pf->flags);
2467
2468 /* Start periodic work going */
2469 kthread_queue_delayed_work(ptp->kworker, &ptp->work, 0);
2470
2471 dev_info(ice_pf_to_dev(pf), "PTP reset successful\n");
2472 return;
2473
2474err:
2475 dev_err(ice_pf_to_dev(pf), "PTP reset failed %d\n", err);
2476}
2477
2478/**
2479 * ice_ptp_prepare_for_reset - Prepare PTP for reset
2480 * @pf: Board private structure
2481 */
2482void ice_ptp_prepare_for_reset(struct ice_pf *pf)
2483{
2484 struct ice_ptp *ptp = &pf->ptp;
2485 u8 src_tmr;
2486
2487 clear_bit(ICE_FLAG_PTP, pf->flags);
2488
2489 /* Disable timestamping for both Tx and Rx */
2490 ice_ptp_cfg_timestamp(pf, false);
2491
2492 kthread_cancel_delayed_work_sync(&ptp->work);
2493 kthread_cancel_work_sync(&ptp->extts_work);
2494
2495 if (test_bit(ICE_PFR_REQ, pf->state))
2496 return;
2497
2498 ice_ptp_release_tx_tracker(pf, &pf->ptp.port.tx);
2499
2500 /* Disable periodic outputs */
2501 ice_ptp_disable_all_clkout(pf);
2502
2503 src_tmr = ice_get_ptp_src_clock_index(&pf->hw);
2504
2505 /* Disable source clock */
2506 wr32(&pf->hw, GLTSYN_ENA(src_tmr), (u32)~GLTSYN_ENA_TSYN_ENA_M);
2507
2508 /* Acquire PHC and system timer to restore after reset */
2509 ptp->reset_time = ktime_get_real_ns();
2510}
2511
2512/**
2513 * ice_ptp_init_owner - Initialize PTP_1588_CLOCK device
2514 * @pf: Board private structure
2515 *
2516 * Setup and initialize a PTP clock device that represents the device hardware
2517 * clock. Save the clock index for other functions connected to the same
2518 * hardware resource.
2519 */
2520static int ice_ptp_init_owner(struct ice_pf *pf)
2521{
2522 struct ice_hw *hw = &pf->hw;
2523 struct timespec64 ts;
2524 int err, itr = 1;
2525
2526 err = ice_ptp_init_phc(hw);
2527 if (err) {
2528 dev_err(ice_pf_to_dev(pf), "Failed to initialize PHC, err %d\n",
2529 err);
2530 return err;
2531 }
2532
2533 /* Acquire the global hardware lock */
2534 if (!ice_ptp_lock(hw)) {
2535 err = -EBUSY;
2536 goto err_exit;
2537 }
2538
2539 /* Write the increment time value to PHY and LAN */
2540 err = ice_ptp_write_incval(hw, ice_base_incval(pf));
2541 if (err) {
2542 ice_ptp_unlock(hw);
2543 goto err_exit;
2544 }
2545
2546 ts = ktime_to_timespec64(ktime_get_real());
2547 /* Write the initial Time value to PHY and LAN */
2548 err = ice_ptp_write_init(pf, &ts);
2549 if (err) {
2550 ice_ptp_unlock(hw);
2551 goto err_exit;
2552 }
2553
2554 /* Release the global hardware lock */
2555 ice_ptp_unlock(hw);
2556
2557 if (!ice_is_e810(hw)) {
2558 /* Enable quad interrupts */
2559 err = ice_ptp_tx_ena_intr(pf, true, itr);
2560 if (err)
2561 goto err_exit;
2562 }
2563
2564 /* Ensure we have a clock device */
2565 err = ice_ptp_create_clock(pf);
2566 if (err)
2567 goto err_clk;
2568
2569 /* Store the PTP clock index for other PFs */
2570 ice_set_ptp_clock_index(pf);
2571
2572 return 0;
2573
2574err_clk:
2575 pf->ptp.clock = NULL;
2576err_exit:
2577 return err;
2578}
2579
2580/**
2581 * ice_ptp_init_work - Initialize PTP work threads
2582 * @pf: Board private structure
2583 * @ptp: PF PTP structure
2584 */
2585static int ice_ptp_init_work(struct ice_pf *pf, struct ice_ptp *ptp)
2586{
2587 struct kthread_worker *kworker;
2588
2589 /* Initialize work functions */
2590 kthread_init_delayed_work(&ptp->work, ice_ptp_periodic_work);
2591 kthread_init_work(&ptp->extts_work, ice_ptp_extts_work);
2592
2593 /* Allocate a kworker for handling work required for the ports
2594 * connected to the PTP hardware clock.
2595 */
2596 kworker = kthread_create_worker(0, "ice-ptp-%s",
2597 dev_name(ice_pf_to_dev(pf)));
2598 if (IS_ERR(kworker))
2599 return PTR_ERR(kworker);
2600
2601 ptp->kworker = kworker;
2602
2603 /* Start periodic work going */
2604 kthread_queue_delayed_work(ptp->kworker, &ptp->work, 0);
2605
2606 return 0;
2607}
2608
2609/**
2610 * ice_ptp_init_port - Initialize PTP port structure
2611 * @pf: Board private structure
2612 * @ptp_port: PTP port structure
2613 */
2614static int ice_ptp_init_port(struct ice_pf *pf, struct ice_ptp_port *ptp_port)
2615{
2616 mutex_init(&ptp_port->ps_lock);
2617
2618 if (ice_is_e810(&pf->hw))
2619 return ice_ptp_init_tx_e810(pf, &ptp_port->tx);
2620
2621 kthread_init_delayed_work(&ptp_port->ov_work,
2622 ice_ptp_wait_for_offsets);
2623 return ice_ptp_init_tx_e822(pf, &ptp_port->tx, ptp_port->port_num);
2624}
2625
2626/**
2627 * ice_ptp_init - Initialize PTP hardware clock support
2628 * @pf: Board private structure
2629 *
2630 * Set up the device for interacting with the PTP hardware clock for all
2631 * functions, both the function that owns the clock hardware, and the
2632 * functions connected to the clock hardware.
2633 *
2634 * The clock owner will allocate and register a ptp_clock with the
2635 * PTP_1588_CLOCK infrastructure. All functions allocate a kthread and work
2636 * items used for asynchronous work such as Tx timestamps and periodic work.
2637 */
2638void ice_ptp_init(struct ice_pf *pf)
2639{
2640 struct ice_ptp *ptp = &pf->ptp;
2641 struct ice_hw *hw = &pf->hw;
2642 int err;
2643
2644 /* If this function owns the clock hardware, it must allocate and
2645 * configure the PTP clock device to represent it.
2646 */
2647 if (hw->func_caps.ts_func_info.src_tmr_owned) {
2648 err = ice_ptp_init_owner(pf);
2649 if (err)
2650 goto err;
2651 }
2652
2653 ptp->port.port_num = hw->pf_id;
2654 err = ice_ptp_init_port(pf, &ptp->port);
2655 if (err)
2656 goto err;
2657
2658 /* Start the PHY timestamping block */
2659 ice_ptp_reset_phy_timestamping(pf);
2660
2661 set_bit(ICE_FLAG_PTP, pf->flags);
2662 err = ice_ptp_init_work(pf, ptp);
2663 if (err)
2664 goto err;
2665
2666 dev_info(ice_pf_to_dev(pf), "PTP init successful\n");
2667 return;
2668
2669err:
2670 /* If we registered a PTP clock, release it */
2671 if (pf->ptp.clock) {
2672 ptp_clock_unregister(ptp->clock);
2673 pf->ptp.clock = NULL;
2674 }
2675 clear_bit(ICE_FLAG_PTP, pf->flags);
2676 dev_err(ice_pf_to_dev(pf), "PTP failed %d\n", err);
2677}
2678
2679/**
2680 * ice_ptp_release - Disable the driver/HW support and unregister the clock
2681 * @pf: Board private structure
2682 *
2683 * This function handles the cleanup work required from the initialization by
2684 * clearing out the important information and unregistering the clock
2685 */
2686void ice_ptp_release(struct ice_pf *pf)
2687{
2688 if (!test_bit(ICE_FLAG_PTP, pf->flags))
2689 return;
2690
2691 /* Disable timestamping for both Tx and Rx */
2692 ice_ptp_cfg_timestamp(pf, false);
2693
2694 ice_ptp_release_tx_tracker(pf, &pf->ptp.port.tx);
2695
2696 clear_bit(ICE_FLAG_PTP, pf->flags);
2697
2698 kthread_cancel_delayed_work_sync(&pf->ptp.work);
2699
2700 ice_ptp_port_phy_stop(&pf->ptp.port);
2701 mutex_destroy(&pf->ptp.port.ps_lock);
2702 if (pf->ptp.kworker) {
2703 kthread_destroy_worker(pf->ptp.kworker);
2704 pf->ptp.kworker = NULL;
2705 }
2706
2707 if (!pf->ptp.clock)
2708 return;
2709
2710 /* Disable periodic outputs */
2711 ice_ptp_disable_all_clkout(pf);
2712
2713 ice_clear_ptp_clock_index(pf);
2714 ptp_clock_unregister(pf->ptp.clock);
2715 pf->ptp.clock = NULL;
2716
2717 dev_info(ice_pf_to_dev(pf), "Removed PTP clock\n");
2718}