1// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
   2/* ADIN1110 Low Power 10BASE-T1L Ethernet MAC-PHY
   3 * ADIN2111 2-Port Ethernet Switch with Integrated 10BASE-T1L PHY
   4 *
   5 * Copyright 2021 Analog Devices Inc.
   6 */
   7
   8#include <linux/bitfield.h>
   9#include <linux/bits.h>
  10#include <linux/cache.h>
  11#include <linux/crc8.h>
  12#include <linux/etherdevice.h>
  13#include <linux/ethtool.h>
  14#include <linux/if_bridge.h>
  15#include <linux/interrupt.h>
  16#include <linux/iopoll.h>
  17#include <linux/gpio.h>
  18#include <linux/kernel.h>
  19#include <linux/mii.h>
  20#include <linux/module.h>
  21#include <linux/netdevice.h>
  22#include <linux/regulator/consumer.h>
  23#include <linux/phy.h>
  24#include <linux/property.h>
  25#include <linux/spi/spi.h>
  26
  27#include <net/switchdev.h>
  28
  29#include <asm/unaligned.h>
  30
  31#define ADIN1110_PHY_ID				0x1
  32
  33#define ADIN1110_RESET				0x03
  34#define   ADIN1110_SWRESET			BIT(0)
  35
  36#define ADIN1110_CONFIG1			0x04
  37#define   ADIN1110_CONFIG1_SYNC			BIT(15)
  38
  39#define ADIN1110_CONFIG2			0x06
  40#define   ADIN2111_P2_FWD_UNK2HOST		BIT(12)
  41#define   ADIN2111_PORT_CUT_THRU_EN		BIT(11)
  42#define   ADIN1110_CRC_APPEND			BIT(5)
  43#define   ADIN1110_FWD_UNK2HOST			BIT(2)
  44
  45#define ADIN1110_STATUS0			0x08
  46
  47#define ADIN1110_STATUS1			0x09
  48#define   ADIN2111_P2_RX_RDY			BIT(17)
  49#define   ADIN1110_SPI_ERR			BIT(10)
  50#define   ADIN1110_RX_RDY			BIT(4)
  51
  52#define ADIN1110_IMASK1				0x0D
  53#define   ADIN2111_RX_RDY_IRQ			BIT(17)
  54#define   ADIN1110_SPI_ERR_IRQ			BIT(10)
  55#define   ADIN1110_RX_RDY_IRQ			BIT(4)
  56#define   ADIN1110_TX_RDY_IRQ			BIT(3)
  57
  58#define ADIN1110_MDIOACC			0x20
  59#define   ADIN1110_MDIO_TRDONE			BIT(31)
  60#define   ADIN1110_MDIO_ST			GENMASK(29, 28)
  61#define   ADIN1110_MDIO_OP			GENMASK(27, 26)
  62#define   ADIN1110_MDIO_PRTAD			GENMASK(25, 21)
  63#define   ADIN1110_MDIO_DEVAD			GENMASK(20, 16)
  64#define   ADIN1110_MDIO_DATA			GENMASK(15, 0)
  65
  66#define ADIN1110_TX_FSIZE			0x30
  67#define ADIN1110_TX				0x31
  68#define ADIN1110_TX_SPACE			0x32
  69
  70#define ADIN1110_MAC_ADDR_FILTER_UPR		0x50
  71#define   ADIN2111_MAC_ADDR_APPLY2PORT2		BIT(31)
  72#define   ADIN1110_MAC_ADDR_APPLY2PORT		BIT(30)
  73#define   ADIN2111_MAC_ADDR_TO_OTHER_PORT	BIT(17)
  74#define   ADIN1110_MAC_ADDR_TO_HOST		BIT(16)
  75
  76#define ADIN1110_MAC_ADDR_FILTER_LWR		0x51
  77
  78#define ADIN1110_MAC_ADDR_MASK_UPR		0x70
  79#define ADIN1110_MAC_ADDR_MASK_LWR		0x71
  80
  81#define ADIN1110_RX_FSIZE			0x90
  82#define ADIN1110_RX				0x91
  83
  84#define ADIN2111_RX_P2_FSIZE			0xC0
  85#define ADIN2111_RX_P2				0xC1
  86
  87#define ADIN1110_CLEAR_STATUS0			0xFFF
  88
  89/* MDIO_OP codes */
  90#define ADIN1110_MDIO_OP_WR			0x1
  91#define ADIN1110_MDIO_OP_RD			0x3
  92
  93#define ADIN1110_CD				BIT(7)
  94#define ADIN1110_WRITE				BIT(5)
  95
  96#define ADIN1110_MAX_BUFF			2048
  97#define ADIN1110_MAX_FRAMES_READ		64
  98#define ADIN1110_WR_HEADER_LEN			2
  99#define ADIN1110_FRAME_HEADER_LEN		2
 100#define ADIN1110_INTERNAL_SIZE_HEADER_LEN	2
 101#define ADIN1110_RD_HEADER_LEN			3
 102#define ADIN1110_REG_LEN			4
 103#define ADIN1110_FEC_LEN			4
 104
 105#define ADIN1110_PHY_ID_VAL			0x0283BC91
 106#define ADIN2111_PHY_ID_VAL			0x0283BCA1
 107
 108#define ADIN_MAC_MAX_PORTS			2
 109#define ADIN_MAC_MAX_ADDR_SLOTS			16
 110
 111#define ADIN_MAC_MULTICAST_ADDR_SLOT		0
 112#define ADIN_MAC_BROADCAST_ADDR_SLOT		1
 113#define ADIN_MAC_P1_ADDR_SLOT			2
 114#define ADIN_MAC_P2_ADDR_SLOT			3
 115#define ADIN_MAC_FDB_ADDR_SLOT			4
 116
 117DECLARE_CRC8_TABLE(adin1110_crc_table);
 118
 119enum adin1110_chips_id {
 120	ADIN1110_MAC = 0,
 121	ADIN2111_MAC,
 122};
 123
 124struct adin1110_cfg {
 125	enum adin1110_chips_id	id;
 126	char			name[MDIO_NAME_SIZE];
 127	u32			phy_ids[PHY_MAX_ADDR];
 128	u32			ports_nr;
 129	u32			phy_id_val;
 130};
 131
 132struct adin1110_port_priv {
 133	struct adin1110_priv		*priv;
 134	struct net_device		*netdev;
 135	struct net_device		*bridge;
 136	struct phy_device		*phydev;
 137	struct work_struct		tx_work;
 138	u64				rx_packets;
 139	u64				tx_packets;
 140	u64				rx_bytes;
 141	u64				tx_bytes;
 142	struct work_struct		rx_mode_work;
 143	u32				flags;
 144	struct sk_buff_head		txq;
 145	u32				nr;
 146	u32				state;
 147	struct adin1110_cfg		*cfg;
 148};
 149
 150struct adin1110_priv {
 151	struct mutex			lock; /* protect spi */
 152	spinlock_t			state_lock; /* protect RX mode */
 153	struct mii_bus			*mii_bus;
 154	struct spi_device		*spidev;
 155	bool				append_crc;
 156	struct adin1110_cfg		*cfg;
 157	u32				tx_space;
 158	u32				irq_mask;
 159	bool				forwarding;
 160	int				irq;
 161	struct adin1110_port_priv	*ports[ADIN_MAC_MAX_PORTS];
 162	char				mii_bus_name[MII_BUS_ID_SIZE];
 163	u8				data[ADIN1110_MAX_BUFF] ____cacheline_aligned;
 164};
 165
 166struct adin1110_switchdev_event_work {
 167	struct work_struct work;
 168	struct switchdev_notifier_fdb_info fdb_info;
 169	struct adin1110_port_priv *port_priv;
 170	unsigned long event;
 171};
 172
 173static struct adin1110_cfg adin1110_cfgs[] = {
 174	{
 175		.id = ADIN1110_MAC,
 176		.name = "adin1110",
 177		.phy_ids = {1},
 178		.ports_nr = 1,
 179		.phy_id_val = ADIN1110_PHY_ID_VAL,
 180	},
 181	{
 182		.id = ADIN2111_MAC,
 183		.name = "adin2111",
 184		.phy_ids = {1, 2},
 185		.ports_nr = 2,
 186		.phy_id_val = ADIN2111_PHY_ID_VAL,
 187	},
 188};
 189
 190static u8 adin1110_crc_data(u8 *data, u32 len)
 191{
 192	return crc8(adin1110_crc_table, data, len, 0);
 193}
 194
 195static int adin1110_read_reg(struct adin1110_priv *priv, u16 reg, u32 *val)
 196{
 197	u32 header_len = ADIN1110_RD_HEADER_LEN;
 198	u32 read_len = ADIN1110_REG_LEN;
 199	struct spi_transfer t = {0};
 200	int ret;
 201
 202	priv->data[0] = ADIN1110_CD | FIELD_GET(GENMASK(12, 8), reg);
 203	priv->data[1] = FIELD_GET(GENMASK(7, 0), reg);
 204	priv->data[2] = 0x00;
 205
 206	if (priv->append_crc) {
 207		priv->data[2] = adin1110_crc_data(&priv->data[0], 2);
 208		priv->data[3] = 0x00;
 209		header_len++;
 210	}
 211
 212	if (priv->append_crc)
 213		read_len++;
 214
 215	memset(&priv->data[header_len], 0, read_len);
 216	t.tx_buf = &priv->data[0];
 217	t.rx_buf = &priv->data[0];
 218	t.len = read_len + header_len;
 219
 220	ret = spi_sync_transfer(priv->spidev, &t, 1);
 221	if (ret)
 222		return ret;
 223
 224	if (priv->append_crc) {
 225		u8 recv_crc;
 226		u8 crc;
 227
 228		crc = adin1110_crc_data(&priv->data[header_len],
 229					ADIN1110_REG_LEN);
 230		recv_crc = priv->data[header_len + ADIN1110_REG_LEN];
 231
 232		if (crc != recv_crc) {
 233			dev_err_ratelimited(&priv->spidev->dev, "CRC error.");
 234			return -EBADMSG;
 235		}
 236	}
 237
 238	*val = get_unaligned_be32(&priv->data[header_len]);
 239
 240	return ret;
 241}
 242
 243static int adin1110_write_reg(struct adin1110_priv *priv, u16 reg, u32 val)
 244{
 245	u32 header_len = ADIN1110_WR_HEADER_LEN;
 246	u32 write_len = ADIN1110_REG_LEN;
 247
 248	priv->data[0] = ADIN1110_CD | ADIN1110_WRITE | FIELD_GET(GENMASK(12, 8), reg);
 249	priv->data[1] = FIELD_GET(GENMASK(7, 0), reg);
 250
 251	if (priv->append_crc) {
 252		priv->data[2] = adin1110_crc_data(&priv->data[0], header_len);
 253		header_len++;
 254	}
 255
 256	put_unaligned_be32(val, &priv->data[header_len]);
 257	if (priv->append_crc) {
 258		priv->data[header_len + write_len] = adin1110_crc_data(&priv->data[header_len],
 259								       write_len);
 260		write_len++;
 261	}
 262
 263	return spi_write(priv->spidev, &priv->data[0], header_len + write_len);
 264}
 265
 266static int adin1110_set_bits(struct adin1110_priv *priv, u16 reg,
 267			     unsigned long mask, unsigned long val)
 268{
 269	u32 write_val;
 270	int ret;
 271
 272	ret = adin1110_read_reg(priv, reg, &write_val);
 273	if (ret < 0)
 274		return ret;
 275
 276	set_mask_bits(&write_val, mask, val);
 277
 278	return adin1110_write_reg(priv, reg, write_val);
 279}
 280
 281static int adin1110_round_len(int len)
 282{
 283	/* can read/write only mutiples of 4 bytes of payload */
 284	len = ALIGN(len, 4);
 285
 286	/* NOTE: ADIN1110_WR_HEADER_LEN should be used for write ops. */
 287	if (len + ADIN1110_RD_HEADER_LEN > ADIN1110_MAX_BUFF)
 288		return -EINVAL;
 289
 290	return len;
 291}
 292
 293static int adin1110_read_fifo(struct adin1110_port_priv *port_priv)
 294{
 295	struct adin1110_priv *priv = port_priv->priv;
 296	u32 header_len = ADIN1110_RD_HEADER_LEN;
 297	struct spi_transfer t = {0};
 298	u32 frame_size_no_fcs;
 299	struct sk_buff *rxb;
 300	u32 frame_size;
 301	int round_len;
 302	u16 reg;
 303	int ret;
 304
 305	if (!port_priv->nr) {
 306		reg = ADIN1110_RX;
 307		ret = adin1110_read_reg(priv, ADIN1110_RX_FSIZE, &frame_size);
 308	} else {
 309		reg = ADIN2111_RX_P2;
 310		ret = adin1110_read_reg(priv, ADIN2111_RX_P2_FSIZE,
 311					&frame_size);
 312	}
 313
 314	if (ret < 0)
 315		return ret;
 316
 317	/* The read frame size includes the extra 2 bytes
 318	 * from the  ADIN1110 frame header.
 319	 */
 320	if (frame_size < ADIN1110_FRAME_HEADER_LEN + ADIN1110_FEC_LEN)
 321		return ret;
 322
 323	round_len = adin1110_round_len(frame_size);
 324	if (round_len < 0)
 325		return ret;
 326
 327	frame_size_no_fcs = frame_size - ADIN1110_FRAME_HEADER_LEN - ADIN1110_FEC_LEN;
 328	memset(priv->data, 0, ADIN1110_RD_HEADER_LEN);
 329
 330	priv->data[0] = ADIN1110_CD | FIELD_GET(GENMASK(12, 8), reg);
 331	priv->data[1] = FIELD_GET(GENMASK(7, 0), reg);
 332
 333	if (priv->append_crc) {
 334		priv->data[2] = adin1110_crc_data(&priv->data[0], 2);
 335		header_len++;
 336	}
 337
 338	rxb = netdev_alloc_skb(port_priv->netdev, round_len + header_len);
 339	if (!rxb)
 340		return -ENOMEM;
 341
 342	skb_put(rxb, frame_size_no_fcs + header_len + ADIN1110_FRAME_HEADER_LEN);
 343
 344	t.tx_buf = &priv->data[0];
 345	t.rx_buf = &rxb->data[0];
 346	t.len = header_len + round_len;
 347
 348	ret = spi_sync_transfer(priv->spidev, &t, 1);
 349	if (ret) {
 350		kfree_skb(rxb);
 351		return ret;
 352	}
 353
 354	skb_pull(rxb, header_len + ADIN1110_FRAME_HEADER_LEN);
 355	rxb->protocol = eth_type_trans(rxb, port_priv->netdev);
 356
 357	if ((port_priv->flags & IFF_ALLMULTI && rxb->pkt_type == PACKET_MULTICAST) ||
 358	    (port_priv->flags & IFF_BROADCAST && rxb->pkt_type == PACKET_BROADCAST))
 359		rxb->offload_fwd_mark = port_priv->priv->forwarding;
 360
 361	netif_rx(rxb);
 362
 363	port_priv->rx_bytes += frame_size - ADIN1110_FRAME_HEADER_LEN;
 364	port_priv->rx_packets++;
 365
 366	return 0;
 367}
 368
 369static int adin1110_write_fifo(struct adin1110_port_priv *port_priv,
 370			       struct sk_buff *txb)
 371{
 372	struct adin1110_priv *priv = port_priv->priv;
 373	u32 header_len = ADIN1110_WR_HEADER_LEN;
 374	__be16 frame_header;
 375	int padding = 0;
 376	int padded_len;
 377	int round_len;
 378	int ret;
 379
 380	/* Pad frame to 64 byte length,
 381	 * MAC nor PHY will otherwise add the
 382	 * required padding.
 383	 * The FEC will be added by the MAC internally.
 384	 */
 385	if (txb->len + ADIN1110_FEC_LEN < 64)
 386		padding = 64 - (txb->len + ADIN1110_FEC_LEN);
 387
 388	padded_len = txb->len + padding + ADIN1110_FRAME_HEADER_LEN;
 389
 390	round_len = adin1110_round_len(padded_len);
 391	if (round_len < 0)
 392		return round_len;
 393
 394	ret = adin1110_write_reg(priv, ADIN1110_TX_FSIZE, padded_len);
 395	if (ret < 0)
 396		return ret;
 397
 398	memset(priv->data, 0, round_len + ADIN1110_WR_HEADER_LEN);
 399
 400	priv->data[0] = ADIN1110_CD | ADIN1110_WRITE;
 401	priv->data[0] |= FIELD_GET(GENMASK(12, 8), ADIN1110_TX);
 402	priv->data[1] = FIELD_GET(GENMASK(7, 0), ADIN1110_TX);
 403	if (priv->append_crc) {
 404		priv->data[2] = adin1110_crc_data(&priv->data[0], 2);
 405		header_len++;
 406	}
 407
 408	/* mention the port on which to send the frame in the frame header */
 409	frame_header = cpu_to_be16(port_priv->nr);
 410	memcpy(&priv->data[header_len], &frame_header,
 411	       ADIN1110_FRAME_HEADER_LEN);
 412
 413	memcpy(&priv->data[header_len + ADIN1110_FRAME_HEADER_LEN],
 414	       txb->data, txb->len);
 415
 416	ret = spi_write(priv->spidev, &priv->data[0], round_len + header_len);
 417	if (ret < 0)
 418		return ret;
 419
 420	port_priv->tx_bytes += txb->len;
 421	port_priv->tx_packets++;
 422
 423	return 0;
 424}
 425
 426static int adin1110_read_mdio_acc(struct adin1110_priv *priv)
 427{
 428	u32 val;
 429	int ret;
 430
 431	mutex_lock(&priv->lock);
 432	ret = adin1110_read_reg(priv, ADIN1110_MDIOACC, &val);
 433	mutex_unlock(&priv->lock);
 434	if (ret < 0)
 435		return 0;
 436
 437	return val;
 438}
 439
 440static int adin1110_mdio_read(struct mii_bus *bus, int phy_id, int reg)
 441{
 442	struct adin1110_priv *priv = bus->priv;
 443	u32 val = 0;
 444	int ret;
 445
 446	if (mdio_phy_id_is_c45(phy_id))
 447		return -EOPNOTSUPP;
 448
 449	val |= FIELD_PREP(ADIN1110_MDIO_OP, ADIN1110_MDIO_OP_RD);
 450	val |= FIELD_PREP(ADIN1110_MDIO_ST, 0x1);
 451	val |= FIELD_PREP(ADIN1110_MDIO_PRTAD, phy_id);
 452	val |= FIELD_PREP(ADIN1110_MDIO_DEVAD, reg);
 453
 454	/* write the clause 22 read command to the chip */
 455	mutex_lock(&priv->lock);
 456	ret = adin1110_write_reg(priv, ADIN1110_MDIOACC, val);
 457	mutex_unlock(&priv->lock);
 458	if (ret < 0)
 459		return ret;
 460
 461	/* ADIN1110_MDIO_TRDONE BIT of the ADIN1110_MDIOACC
 462	 * register is set when the read is done.
 463	 * After the transaction is done, ADIN1110_MDIO_DATA
 464	 * bitfield of ADIN1110_MDIOACC register will contain
 465	 * the requested register value.
 466	 */
 467	ret = readx_poll_timeout(adin1110_read_mdio_acc, priv, val,
 468				 (val & ADIN1110_MDIO_TRDONE), 10000, 30000);
 469	if (ret < 0)
 470		return ret;
 471
 472	return (val & ADIN1110_MDIO_DATA);
 473}
 474
 475static int adin1110_mdio_write(struct mii_bus *bus, int phy_id,
 476			       int reg, u16 reg_val)
 477{
 478	struct adin1110_priv *priv = bus->priv;
 479	u32 val = 0;
 480	int ret;
 481
 482	if (mdio_phy_id_is_c45(phy_id))
 483		return -EOPNOTSUPP;
 484
 485	val |= FIELD_PREP(ADIN1110_MDIO_OP, ADIN1110_MDIO_OP_WR);
 486	val |= FIELD_PREP(ADIN1110_MDIO_ST, 0x1);
 487	val |= FIELD_PREP(ADIN1110_MDIO_PRTAD, phy_id);
 488	val |= FIELD_PREP(ADIN1110_MDIO_DEVAD, reg);
 489	val |= FIELD_PREP(ADIN1110_MDIO_DATA, reg_val);
 490
 491	/* write the clause 22 write command to the chip */
 492	mutex_lock(&priv->lock);
 493	ret = adin1110_write_reg(priv, ADIN1110_MDIOACC, val);
 494	mutex_unlock(&priv->lock);
 495	if (ret < 0)
 496		return ret;
 497
 498	return readx_poll_timeout(adin1110_read_mdio_acc, priv, val,
 499				  (val & ADIN1110_MDIO_TRDONE), 10000, 30000);
 500}
 501
 502/* ADIN1110 MAC-PHY contains an ADIN1100 PHY.
 503 * ADIN2111 MAC-PHY contains two ADIN1100 PHYs.
 504 * By registering a new MDIO bus we allow the PAL to discover
 505 * the encapsulated PHY and probe the ADIN1100 driver.
 506 */
 507static int adin1110_register_mdiobus(struct adin1110_priv *priv,
 508				     struct device *dev)
 509{
 510	struct mii_bus *mii_bus;
 511	int ret;
 512
 513	mii_bus = devm_mdiobus_alloc(dev);
 514	if (!mii_bus)
 515		return -ENOMEM;
 516
 517	snprintf(priv->mii_bus_name, MII_BUS_ID_SIZE, "%s-%u",
 518		 priv->cfg->name, spi_get_chipselect(priv->spidev, 0));
 519
 520	mii_bus->name = priv->mii_bus_name;
 521	mii_bus->read = adin1110_mdio_read;
 522	mii_bus->write = adin1110_mdio_write;
 523	mii_bus->priv = priv;
 524	mii_bus->parent = dev;
 525	mii_bus->phy_mask = ~((u32)GENMASK(2, 0));
 
 526	snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev));
 527
 528	ret = devm_mdiobus_register(dev, mii_bus);
 529	if (ret)
 530		return ret;
 531
 532	priv->mii_bus = mii_bus;
 533
 534	return 0;
 535}
 536
 537static bool adin1110_port_rx_ready(struct adin1110_port_priv *port_priv,
 538				   u32 status)
 539{
 540	if (!netif_oper_up(port_priv->netdev))
 541		return false;
 542
 543	if (!port_priv->nr)
 544		return !!(status & ADIN1110_RX_RDY);
 545	else
 546		return !!(status & ADIN2111_P2_RX_RDY);
 547}
 548
 549static void adin1110_read_frames(struct adin1110_port_priv *port_priv,
 550				 unsigned int budget)
 551{
 552	struct adin1110_priv *priv = port_priv->priv;
 553	u32 status1;
 554	int ret;
 555
 556	while (budget) {
 557		ret = adin1110_read_reg(priv, ADIN1110_STATUS1, &status1);
 558		if (ret < 0)
 559			return;
 560
 561		if (!adin1110_port_rx_ready(port_priv, status1))
 562			break;
 563
 564		ret = adin1110_read_fifo(port_priv);
 565		if (ret < 0)
 566			return;
 567
 568		budget--;
 569	}
 570}
 571
 572static void adin1110_wake_queues(struct adin1110_priv *priv)
 573{
 574	int i;
 575
 576	for (i = 0; i < priv->cfg->ports_nr; i++)
 577		netif_wake_queue(priv->ports[i]->netdev);
 578}
 579
 580static irqreturn_t adin1110_irq(int irq, void *p)
 581{
 582	struct adin1110_priv *priv = p;
 583	u32 status1;
 584	u32 val;
 585	int ret;
 586	int i;
 587
 588	mutex_lock(&priv->lock);
 589
 590	ret = adin1110_read_reg(priv, ADIN1110_STATUS1, &status1);
 591	if (ret < 0)
 592		goto out;
 593
 594	if (priv->append_crc && (status1 & ADIN1110_SPI_ERR))
 595		dev_warn_ratelimited(&priv->spidev->dev,
 596				     "SPI CRC error on write.\n");
 597
 598	ret = adin1110_read_reg(priv, ADIN1110_TX_SPACE, &val);
 599	if (ret < 0)
 600		goto out;
 601
 602	/* TX FIFO space is expressed in half-words */
 603	priv->tx_space = 2 * val;
 604
 605	for (i = 0; i < priv->cfg->ports_nr; i++) {
 606		if (adin1110_port_rx_ready(priv->ports[i], status1))
 607			adin1110_read_frames(priv->ports[i],
 608					     ADIN1110_MAX_FRAMES_READ);
 609	}
 610
 611	/* clear IRQ sources */
 612	adin1110_write_reg(priv, ADIN1110_STATUS0, ADIN1110_CLEAR_STATUS0);
 613	adin1110_write_reg(priv, ADIN1110_STATUS1, priv->irq_mask);
 614
 615out:
 616	mutex_unlock(&priv->lock);
 617
 618	if (priv->tx_space > 0 && ret >= 0)
 619		adin1110_wake_queues(priv);
 620
 621	return IRQ_HANDLED;
 622}
 623
 624/* ADIN1110 can filter up to 16 MAC addresses, mac_nr here is the slot used */
 625static int adin1110_write_mac_address(struct adin1110_port_priv *port_priv,
 626				      int mac_nr, const u8 *addr,
 627				      u8 *mask, u32 port_rules)
 628{
 629	struct adin1110_priv *priv = port_priv->priv;
 630	u32 offset = mac_nr * 2;
 631	u32 port_rules_mask;
 632	int ret;
 633	u32 val;
 634
 635	if (!port_priv->nr)
 636		port_rules_mask = ADIN1110_MAC_ADDR_APPLY2PORT;
 637	else
 638		port_rules_mask = ADIN2111_MAC_ADDR_APPLY2PORT2;
 639
 640	if (port_rules & port_rules_mask)
 641		port_rules_mask |= ADIN1110_MAC_ADDR_TO_HOST | ADIN2111_MAC_ADDR_TO_OTHER_PORT;
 642
 643	port_rules_mask |= GENMASK(15, 0);
 644	val = port_rules | get_unaligned_be16(&addr[0]);
 645	ret = adin1110_set_bits(priv, ADIN1110_MAC_ADDR_FILTER_UPR + offset,
 646				port_rules_mask, val);
 647	if (ret < 0)
 648		return ret;
 649
 650	val = get_unaligned_be32(&addr[2]);
 651	ret =  adin1110_write_reg(priv,
 652				  ADIN1110_MAC_ADDR_FILTER_LWR + offset, val);
 653	if (ret < 0)
 654		return ret;
 655
 656	/* Only the first two MAC address slots support masking. */
 657	if (mac_nr < ADIN_MAC_P1_ADDR_SLOT) {
 658		val = get_unaligned_be16(&mask[0]);
 659		ret = adin1110_write_reg(priv,
 660					 ADIN1110_MAC_ADDR_MASK_UPR + offset,
 661					 val);
 662		if (ret < 0)
 663			return ret;
 664
 665		val = get_unaligned_be32(&mask[2]);
 666		return adin1110_write_reg(priv,
 667					  ADIN1110_MAC_ADDR_MASK_LWR + offset,
 668					  val);
 669	}
 670
 671	return 0;
 672}
 673
 674static int adin1110_clear_mac_address(struct adin1110_priv *priv, int mac_nr)
 675{
 676	u32 offset = mac_nr * 2;
 677	int ret;
 678
 679	ret = adin1110_write_reg(priv, ADIN1110_MAC_ADDR_FILTER_UPR + offset, 0);
 680	if (ret < 0)
 681		return ret;
 682
 683	ret =  adin1110_write_reg(priv, ADIN1110_MAC_ADDR_FILTER_LWR + offset, 0);
 684	if (ret < 0)
 685		return ret;
 686
 687	/* only the first two MAC address slots are maskable */
 688	if (mac_nr <= 1) {
 689		ret = adin1110_write_reg(priv, ADIN1110_MAC_ADDR_MASK_UPR + offset, 0);
 690		if (ret < 0)
 691			return ret;
 692
 693		ret = adin1110_write_reg(priv, ADIN1110_MAC_ADDR_MASK_LWR + offset, 0);
 694	}
 695
 696	return ret;
 697}
 698
 699static u32 adin1110_port_rules(struct adin1110_port_priv *port_priv,
 700			       bool fw_to_host,
 701			       bool fw_to_other_port)
 702{
 703	u32 port_rules = 0;
 704
 705	if (!port_priv->nr)
 706		port_rules |= ADIN1110_MAC_ADDR_APPLY2PORT;
 707	else
 708		port_rules |= ADIN2111_MAC_ADDR_APPLY2PORT2;
 709
 710	if (fw_to_host)
 711		port_rules |= ADIN1110_MAC_ADDR_TO_HOST;
 712
 713	if (fw_to_other_port && port_priv->priv->forwarding)
 714		port_rules |= ADIN2111_MAC_ADDR_TO_OTHER_PORT;
 715
 716	return port_rules;
 717}
 718
 719static int adin1110_multicast_filter(struct adin1110_port_priv *port_priv,
 720				     int mac_nr, bool accept_multicast)
 721{
 722	u8 mask[ETH_ALEN] = {0};
 723	u8 mac[ETH_ALEN] = {0};
 724	u32 port_rules = 0;
 725
 726	mask[0] = BIT(0);
 727	mac[0] = BIT(0);
 728
 729	if (accept_multicast && port_priv->state == BR_STATE_FORWARDING)
 730		port_rules = adin1110_port_rules(port_priv, true, true);
 731
 732	return adin1110_write_mac_address(port_priv, mac_nr, mac,
 733					  mask, port_rules);
 734}
 735
 736static int adin1110_broadcasts_filter(struct adin1110_port_priv *port_priv,
 737				      int mac_nr, bool accept_broadcast)
 738{
 739	u32 port_rules = 0;
 740	u8 mask[ETH_ALEN];
 741
 742	eth_broadcast_addr(mask);
 743
 744	if (accept_broadcast && port_priv->state == BR_STATE_FORWARDING)
 745		port_rules = adin1110_port_rules(port_priv, true, true);
 746
 747	return adin1110_write_mac_address(port_priv, mac_nr, mask,
 748					  mask, port_rules);
 749}
 750
 751static int adin1110_set_mac_address(struct net_device *netdev,
 752				    const unsigned char *dev_addr)
 753{
 754	struct adin1110_port_priv *port_priv = netdev_priv(netdev);
 755	u8 mask[ETH_ALEN];
 756	u32 port_rules;
 757	u32 mac_slot;
 758
 759	if (!is_valid_ether_addr(dev_addr))
 760		return -EADDRNOTAVAIL;
 761
 762	eth_hw_addr_set(netdev, dev_addr);
 763	eth_broadcast_addr(mask);
 764
 765	mac_slot = (!port_priv->nr) ?  ADIN_MAC_P1_ADDR_SLOT : ADIN_MAC_P2_ADDR_SLOT;
 766	port_rules = adin1110_port_rules(port_priv, true, false);
 767
 768	return adin1110_write_mac_address(port_priv, mac_slot, netdev->dev_addr,
 769					  mask, port_rules);
 770}
 771
 772static int adin1110_ndo_set_mac_address(struct net_device *netdev, void *addr)
 773{
 774	struct sockaddr *sa = addr;
 775	int ret;
 776
 777	ret = eth_prepare_mac_addr_change(netdev, addr);
 778	if (ret < 0)
 779		return ret;
 780
 781	return adin1110_set_mac_address(netdev, sa->sa_data);
 782}
 783
 784static int adin1110_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
 785{
 786	if (!netif_running(netdev))
 787		return -EINVAL;
 788
 789	return phy_do_ioctl(netdev, rq, cmd);
 790}
 791
 792static int adin1110_set_promisc_mode(struct adin1110_port_priv *port_priv,
 793				     bool promisc)
 794{
 795	struct adin1110_priv *priv = port_priv->priv;
 796	u32 mask;
 797
 798	if (port_priv->state != BR_STATE_FORWARDING)
 799		promisc = false;
 800
 801	if (!port_priv->nr)
 802		mask = ADIN1110_FWD_UNK2HOST;
 803	else
 804		mask = ADIN2111_P2_FWD_UNK2HOST;
 805
 806	return adin1110_set_bits(priv, ADIN1110_CONFIG2,
 807				 mask, promisc ? mask : 0);
 808}
 809
 810static int adin1110_setup_rx_mode(struct adin1110_port_priv *port_priv)
 811{
 812	int ret;
 813
 814	ret = adin1110_set_promisc_mode(port_priv,
 815					!!(port_priv->flags & IFF_PROMISC));
 816	if (ret < 0)
 817		return ret;
 818
 819	ret = adin1110_multicast_filter(port_priv, ADIN_MAC_MULTICAST_ADDR_SLOT,
 820					!!(port_priv->flags & IFF_ALLMULTI));
 821	if (ret < 0)
 822		return ret;
 823
 824	ret = adin1110_broadcasts_filter(port_priv,
 825					 ADIN_MAC_BROADCAST_ADDR_SLOT,
 826					 !!(port_priv->flags & IFF_BROADCAST));
 827	if (ret < 0)
 828		return ret;
 829
 830	return adin1110_set_bits(port_priv->priv, ADIN1110_CONFIG1,
 831				 ADIN1110_CONFIG1_SYNC, ADIN1110_CONFIG1_SYNC);
 832}
 833
 834static bool adin1110_can_offload_forwarding(struct adin1110_priv *priv)
 835{
 836	int i;
 837
 838	if (priv->cfg->id != ADIN2111_MAC)
 839		return false;
 840
 841	/* Can't enable forwarding if ports do not belong to the same bridge */
 842	if (priv->ports[0]->bridge != priv->ports[1]->bridge || !priv->ports[0]->bridge)
 843		return false;
 844
 845	/* Can't enable forwarding if there is a port
 846	 * that has been blocked by STP.
 847	 */
 848	for (i = 0; i < priv->cfg->ports_nr; i++) {
 849		if (priv->ports[i]->state != BR_STATE_FORWARDING)
 850			return false;
 851	}
 852
 853	return true;
 854}
 855
 856static void adin1110_rx_mode_work(struct work_struct *work)
 857{
 858	struct adin1110_port_priv *port_priv;
 859	struct adin1110_priv *priv;
 860
 861	port_priv = container_of(work, struct adin1110_port_priv, rx_mode_work);
 862	priv = port_priv->priv;
 863
 864	mutex_lock(&priv->lock);
 865	adin1110_setup_rx_mode(port_priv);
 866	mutex_unlock(&priv->lock);
 867}
 868
 869static void adin1110_set_rx_mode(struct net_device *dev)
 870{
 871	struct adin1110_port_priv *port_priv = netdev_priv(dev);
 872	struct adin1110_priv *priv = port_priv->priv;
 873
 874	spin_lock(&priv->state_lock);
 875
 876	port_priv->flags = dev->flags;
 877	schedule_work(&port_priv->rx_mode_work);
 878
 879	spin_unlock(&priv->state_lock);
 880}
 881
 882static int adin1110_net_open(struct net_device *net_dev)
 883{
 884	struct adin1110_port_priv *port_priv = netdev_priv(net_dev);
 885	struct adin1110_priv *priv = port_priv->priv;
 886	u32 val;
 887	int ret;
 888
 889	mutex_lock(&priv->lock);
 890
 891	/* Configure MAC to compute and append the FCS itself. */
 892	ret = adin1110_write_reg(priv, ADIN1110_CONFIG2, ADIN1110_CRC_APPEND);
 893	if (ret < 0)
 894		goto out;
 895
 896	val = ADIN1110_TX_RDY_IRQ | ADIN1110_RX_RDY_IRQ | ADIN1110_SPI_ERR_IRQ;
 897	if (priv->cfg->id == ADIN2111_MAC)
 898		val |= ADIN2111_RX_RDY_IRQ;
 899
 900	priv->irq_mask = val;
 901	ret = adin1110_write_reg(priv, ADIN1110_IMASK1, ~val);
 902	if (ret < 0) {
 903		netdev_err(net_dev, "Failed to enable chip IRQs: %d\n", ret);
 904		goto out;
 905	}
 906
 907	ret = adin1110_read_reg(priv, ADIN1110_TX_SPACE, &val);
 908	if (ret < 0) {
 909		netdev_err(net_dev, "Failed to read TX FIFO space: %d\n", ret);
 910		goto out;
 911	}
 912
 913	priv->tx_space = 2 * val;
 914
 915	port_priv->state = BR_STATE_FORWARDING;
 916	ret = adin1110_set_mac_address(net_dev, net_dev->dev_addr);
 917	if (ret < 0) {
 918		netdev_err(net_dev, "Could not set MAC address: %pM, %d\n",
 919			   net_dev->dev_addr, ret);
 920		goto out;
 921	}
 922
 923	ret = adin1110_set_bits(priv, ADIN1110_CONFIG1, ADIN1110_CONFIG1_SYNC,
 924				ADIN1110_CONFIG1_SYNC);
 925
 926out:
 927	mutex_unlock(&priv->lock);
 928
 929	if (ret < 0)
 930		return ret;
 931
 932	phy_start(port_priv->phydev);
 933
 934	netif_start_queue(net_dev);
 935
 936	return 0;
 937}
 938
 939static int adin1110_net_stop(struct net_device *net_dev)
 940{
 941	struct adin1110_port_priv *port_priv = netdev_priv(net_dev);
 942	struct adin1110_priv *priv = port_priv->priv;
 943	u32 mask;
 944	int ret;
 945
 946	mask = !port_priv->nr ? ADIN2111_RX_RDY_IRQ : ADIN1110_RX_RDY_IRQ;
 947
 948	/* Disable RX RDY IRQs */
 949	mutex_lock(&priv->lock);
 950	ret = adin1110_set_bits(priv, ADIN1110_IMASK1, mask, mask);
 951	mutex_unlock(&priv->lock);
 952	if (ret < 0)
 953		return ret;
 954
 955	netif_stop_queue(port_priv->netdev);
 956	flush_work(&port_priv->tx_work);
 957	phy_stop(port_priv->phydev);
 958
 959	return 0;
 960}
 961
 962static void adin1110_tx_work(struct work_struct *work)
 963{
 964	struct adin1110_port_priv *port_priv;
 965	struct adin1110_priv *priv;
 966	struct sk_buff *txb;
 967	int ret;
 968
 969	port_priv = container_of(work, struct adin1110_port_priv, tx_work);
 970	priv = port_priv->priv;
 971
 972	mutex_lock(&priv->lock);
 973
 974	while ((txb = skb_dequeue(&port_priv->txq))) {
 975		ret = adin1110_write_fifo(port_priv, txb);
 976		if (ret < 0)
 977			dev_err_ratelimited(&priv->spidev->dev,
 978					    "Frame write error: %d\n", ret);
 979
 980		dev_kfree_skb(txb);
 981	}
 982
 983	mutex_unlock(&priv->lock);
 984}
 985
 986static netdev_tx_t adin1110_start_xmit(struct sk_buff *skb, struct net_device *dev)
 987{
 988	struct adin1110_port_priv *port_priv = netdev_priv(dev);
 989	struct adin1110_priv *priv = port_priv->priv;
 990	netdev_tx_t netdev_ret = NETDEV_TX_OK;
 991	u32 tx_space_needed;
 992
 993	tx_space_needed = skb->len + ADIN1110_FRAME_HEADER_LEN + ADIN1110_INTERNAL_SIZE_HEADER_LEN;
 994	if (tx_space_needed > priv->tx_space) {
 995		netif_stop_queue(dev);
 996		netdev_ret = NETDEV_TX_BUSY;
 997	} else {
 998		priv->tx_space -= tx_space_needed;
 999		skb_queue_tail(&port_priv->txq, skb);
1000	}
1001
1002	schedule_work(&port_priv->tx_work);
1003
1004	return netdev_ret;
1005}
1006
1007static void adin1110_ndo_get_stats64(struct net_device *dev,
1008				     struct rtnl_link_stats64 *storage)
1009{
1010	struct adin1110_port_priv *port_priv = netdev_priv(dev);
1011
1012	storage->rx_packets = port_priv->rx_packets;
1013	storage->tx_packets = port_priv->tx_packets;
1014
1015	storage->rx_bytes = port_priv->rx_bytes;
1016	storage->tx_bytes = port_priv->tx_bytes;
1017}
1018
1019static int adin1110_port_get_port_parent_id(struct net_device *dev,
1020					    struct netdev_phys_item_id *ppid)
1021{
1022	struct adin1110_port_priv *port_priv = netdev_priv(dev);
1023	struct adin1110_priv *priv = port_priv->priv;
1024
1025	ppid->id_len = strnlen(priv->mii_bus_name, MAX_PHYS_ITEM_ID_LEN);
1026	memcpy(ppid->id, priv->mii_bus_name, ppid->id_len);
1027
1028	return 0;
1029}
1030
1031static int adin1110_ndo_get_phys_port_name(struct net_device *dev,
1032					   char *name, size_t len)
1033{
1034	struct adin1110_port_priv *port_priv = netdev_priv(dev);
1035	int err;
1036
1037	err = snprintf(name, len, "p%d", port_priv->nr);
1038	if (err >= len)
1039		return -EINVAL;
1040
1041	return 0;
1042}
1043
1044static const struct net_device_ops adin1110_netdev_ops = {
1045	.ndo_open		= adin1110_net_open,
1046	.ndo_stop		= adin1110_net_stop,
1047	.ndo_eth_ioctl		= adin1110_ioctl,
1048	.ndo_start_xmit		= adin1110_start_xmit,
1049	.ndo_set_mac_address	= adin1110_ndo_set_mac_address,
1050	.ndo_set_rx_mode	= adin1110_set_rx_mode,
1051	.ndo_validate_addr	= eth_validate_addr,
1052	.ndo_get_stats64	= adin1110_ndo_get_stats64,
1053	.ndo_get_port_parent_id	= adin1110_port_get_port_parent_id,
1054	.ndo_get_phys_port_name	= adin1110_ndo_get_phys_port_name,
1055};
1056
1057static void adin1110_get_drvinfo(struct net_device *dev,
1058				 struct ethtool_drvinfo *di)
1059{
1060	strscpy(di->driver, "ADIN1110", sizeof(di->driver));
1061	strscpy(di->bus_info, dev_name(dev->dev.parent), sizeof(di->bus_info));
1062}
1063
1064static const struct ethtool_ops adin1110_ethtool_ops = {
1065	.get_drvinfo		= adin1110_get_drvinfo,
1066	.get_link		= ethtool_op_get_link,
1067	.get_link_ksettings	= phy_ethtool_get_link_ksettings,
1068	.set_link_ksettings	= phy_ethtool_set_link_ksettings,
1069};
1070
1071static void adin1110_adjust_link(struct net_device *dev)
1072{
1073	struct phy_device *phydev = dev->phydev;
1074
1075	if (!phydev->link)
1076		phy_print_status(phydev);
1077}
1078
1079/* PHY ID is stored in the MAC registers too,
1080 * check spi connection by reading it.
1081 */
1082static int adin1110_check_spi(struct adin1110_priv *priv)
1083{
1084	struct gpio_desc *reset_gpio;
1085	int ret;
1086	u32 val;
1087
1088	reset_gpio = devm_gpiod_get_optional(&priv->spidev->dev, "reset",
1089					     GPIOD_OUT_LOW);
1090	if (reset_gpio) {
1091		/* MISO pin is used for internal configuration, can't have
1092		 * anyone else disturbing the SDO line.
1093		 */
1094		spi_bus_lock(priv->spidev->controller);
1095
1096		gpiod_set_value(reset_gpio, 1);
1097		fsleep(10000);
1098		gpiod_set_value(reset_gpio, 0);
1099
1100		/* Need to wait 90 ms before interacting with
1101		 * the MAC after a HW reset.
1102		 */
1103		fsleep(90000);
1104
1105		spi_bus_unlock(priv->spidev->controller);
1106	}
1107
1108	ret = adin1110_read_reg(priv, ADIN1110_PHY_ID, &val);
1109	if (ret < 0)
1110		return ret;
1111
1112	if (val != priv->cfg->phy_id_val) {
1113		dev_err(&priv->spidev->dev, "PHY ID expected: %x, read: %x\n",
1114			priv->cfg->phy_id_val, val);
1115		return -EIO;
1116	}
1117
1118	return 0;
1119}
1120
1121static int adin1110_hw_forwarding(struct adin1110_priv *priv, bool enable)
1122{
1123	int ret;
1124	int i;
1125
1126	priv->forwarding = enable;
1127
1128	if (!priv->forwarding) {
1129		for (i = ADIN_MAC_FDB_ADDR_SLOT; i < ADIN_MAC_MAX_ADDR_SLOTS; i++) {
1130			ret = adin1110_clear_mac_address(priv, i);
1131			if (ret < 0)
1132				return ret;
1133		}
1134	}
1135
1136	/* Forwarding is optimised when MAC runs in Cut Through mode. */
1137	ret = adin1110_set_bits(priv, ADIN1110_CONFIG2,
1138				ADIN2111_PORT_CUT_THRU_EN,
1139				priv->forwarding ? ADIN2111_PORT_CUT_THRU_EN : 0);
1140	if (ret < 0)
1141		return ret;
1142
1143	for (i = 0; i < priv->cfg->ports_nr; i++) {
1144		ret = adin1110_setup_rx_mode(priv->ports[i]);
1145		if (ret < 0)
1146			return ret;
1147	}
1148
1149	return ret;
1150}
1151
1152static int adin1110_port_bridge_join(struct adin1110_port_priv *port_priv,
1153				     struct net_device *bridge)
1154{
1155	struct adin1110_priv *priv = port_priv->priv;
1156	int ret;
1157
1158	port_priv->bridge = bridge;
1159
1160	if (adin1110_can_offload_forwarding(priv)) {
1161		mutex_lock(&priv->lock);
1162		ret = adin1110_hw_forwarding(priv, true);
1163		mutex_unlock(&priv->lock);
1164
1165		if (ret < 0)
1166			return ret;
1167	}
1168
1169	return adin1110_set_mac_address(port_priv->netdev, bridge->dev_addr);
1170}
1171
1172static int adin1110_port_bridge_leave(struct adin1110_port_priv *port_priv,
1173				      struct net_device *bridge)
1174{
1175	struct adin1110_priv *priv = port_priv->priv;
1176	int ret;
1177
1178	port_priv->bridge = NULL;
1179
1180	mutex_lock(&priv->lock);
1181	ret = adin1110_hw_forwarding(priv, false);
1182	mutex_unlock(&priv->lock);
1183
1184	return ret;
1185}
1186
1187static bool adin1110_port_dev_check(const struct net_device *dev)
1188{
1189	return dev->netdev_ops == &adin1110_netdev_ops;
1190}
1191
1192static int adin1110_netdevice_event(struct notifier_block *unused,
1193				    unsigned long event, void *ptr)
1194{
1195	struct net_device *dev = netdev_notifier_info_to_dev(ptr);
1196	struct adin1110_port_priv *port_priv = netdev_priv(dev);
1197	struct netdev_notifier_changeupper_info *info = ptr;
1198	int ret = 0;
1199
1200	if (!adin1110_port_dev_check(dev))
1201		return NOTIFY_DONE;
1202
1203	switch (event) {
1204	case NETDEV_CHANGEUPPER:
1205		if (netif_is_bridge_master(info->upper_dev)) {
1206			if (info->linking)
1207				ret = adin1110_port_bridge_join(port_priv, info->upper_dev);
1208			else
1209				ret = adin1110_port_bridge_leave(port_priv, info->upper_dev);
1210		}
1211		break;
1212	default:
1213		break;
1214	}
1215
1216	return notifier_from_errno(ret);
1217}
1218
1219static struct notifier_block adin1110_netdevice_nb = {
1220	.notifier_call = adin1110_netdevice_event,
1221};
1222
1223static void adin1110_disconnect_phy(void *data)
1224{
1225	phy_disconnect(data);
1226}
1227
1228static int adin1110_port_set_forwarding_state(struct adin1110_port_priv *port_priv)
1229{
1230	struct adin1110_priv *priv = port_priv->priv;
1231	int ret;
1232
1233	port_priv->state = BR_STATE_FORWARDING;
1234
1235	mutex_lock(&priv->lock);
1236	ret = adin1110_set_mac_address(port_priv->netdev,
1237				       port_priv->netdev->dev_addr);
1238	if (ret < 0)
1239		goto out;
1240
1241	if (adin1110_can_offload_forwarding(priv))
1242		ret = adin1110_hw_forwarding(priv, true);
1243	else
1244		ret = adin1110_setup_rx_mode(port_priv);
1245out:
1246	mutex_unlock(&priv->lock);
1247
1248	return ret;
1249}
1250
1251static int adin1110_port_set_blocking_state(struct adin1110_port_priv *port_priv)
1252{
1253	u8 mac[ETH_ALEN] = {0x01, 0x80, 0xC2, 0x00, 0x00, 0x00};
1254	struct adin1110_priv *priv = port_priv->priv;
1255	u8 mask[ETH_ALEN];
1256	u32 port_rules;
1257	int mac_slot;
1258	int ret;
1259
1260	port_priv->state = BR_STATE_BLOCKING;
1261
1262	mutex_lock(&priv->lock);
1263
1264	mac_slot = (!port_priv->nr) ?  ADIN_MAC_P1_ADDR_SLOT : ADIN_MAC_P2_ADDR_SLOT;
1265	ret = adin1110_clear_mac_address(priv, mac_slot);
1266	if (ret < 0)
1267		goto out;
1268
1269	ret = adin1110_hw_forwarding(priv, false);
1270	if (ret < 0)
1271		goto out;
1272
1273	/* Allow only BPDUs to be passed to the CPU */
1274	eth_broadcast_addr(mask);
1275	port_rules = adin1110_port_rules(port_priv, true, false);
1276	ret = adin1110_write_mac_address(port_priv, mac_slot, mac,
1277					 mask, port_rules);
1278out:
1279	mutex_unlock(&priv->lock);
1280
1281	return ret;
1282}
1283
1284/* ADIN1110/2111 does not have any native STP support.
1285 * Listen for bridge core state changes and
1286 * allow all frames to pass or only the BPDUs.
1287 */
1288static int adin1110_port_attr_stp_state_set(struct adin1110_port_priv *port_priv,
1289					    u8 state)
1290{
1291	switch (state) {
1292	case BR_STATE_FORWARDING:
1293		return adin1110_port_set_forwarding_state(port_priv);
1294	case BR_STATE_LEARNING:
1295	case BR_STATE_LISTENING:
1296	case BR_STATE_DISABLED:
1297	case BR_STATE_BLOCKING:
1298		return adin1110_port_set_blocking_state(port_priv);
1299	default:
1300		return -EINVAL;
1301	}
1302}
1303
1304static int adin1110_port_attr_set(struct net_device *dev, const void *ctx,
1305				  const struct switchdev_attr *attr,
1306				  struct netlink_ext_ack *extack)
1307{
1308	struct adin1110_port_priv *port_priv = netdev_priv(dev);
1309
1310	switch (attr->id) {
1311	case SWITCHDEV_ATTR_ID_PORT_STP_STATE:
1312		return adin1110_port_attr_stp_state_set(port_priv,
1313							attr->u.stp_state);
1314	default:
1315		return -EOPNOTSUPP;
1316	}
1317}
1318
1319static int adin1110_switchdev_blocking_event(struct notifier_block *unused,
1320					     unsigned long event,
1321					     void *ptr)
1322{
1323	struct net_device *netdev = switchdev_notifier_info_to_dev(ptr);
1324	int ret;
1325
1326	if (event == SWITCHDEV_PORT_ATTR_SET) {
1327		ret = switchdev_handle_port_attr_set(netdev, ptr,
1328						     adin1110_port_dev_check,
1329						     adin1110_port_attr_set);
1330
1331		return notifier_from_errno(ret);
1332	}
1333
1334	return NOTIFY_DONE;
1335}
1336
1337static struct notifier_block adin1110_switchdev_blocking_notifier = {
1338	.notifier_call = adin1110_switchdev_blocking_event,
1339};
1340
1341static void adin1110_fdb_offload_notify(struct net_device *netdev,
1342					struct switchdev_notifier_fdb_info *rcv)
1343{
1344	struct switchdev_notifier_fdb_info info = {};
1345
1346	info.addr = rcv->addr;
1347	info.vid = rcv->vid;
1348	info.offloaded = true;
1349	call_switchdev_notifiers(SWITCHDEV_FDB_OFFLOADED,
1350				 netdev, &info.info, NULL);
1351}
1352
1353static int adin1110_fdb_add(struct adin1110_port_priv *port_priv,
1354			    struct switchdev_notifier_fdb_info *fdb)
1355{
1356	struct adin1110_priv *priv = port_priv->priv;
1357	struct adin1110_port_priv *other_port;
1358	u8 mask[ETH_ALEN];
1359	u32 port_rules;
1360	int mac_nr;
1361	u32 val;
1362	int ret;
1363
1364	netdev_dbg(port_priv->netdev,
1365		   "DEBUG: %s: MACID = %pM vid = %u flags = %u %u -- port %d\n",
1366		    __func__, fdb->addr, fdb->vid, fdb->added_by_user,
1367		    fdb->offloaded, port_priv->nr);
1368
1369	if (!priv->forwarding)
1370		return 0;
1371
1372	if (fdb->is_local)
1373		return -EINVAL;
1374
1375	/* Find free FDB slot on device. */
1376	for (mac_nr = ADIN_MAC_FDB_ADDR_SLOT; mac_nr < ADIN_MAC_MAX_ADDR_SLOTS; mac_nr++) {
1377		ret = adin1110_read_reg(priv, ADIN1110_MAC_ADDR_FILTER_UPR + (mac_nr * 2), &val);
1378		if (ret < 0)
1379			return ret;
1380		if (!val)
1381			break;
1382	}
1383
1384	if (mac_nr == ADIN_MAC_MAX_ADDR_SLOTS)
1385		return -ENOMEM;
1386
1387	other_port = priv->ports[!port_priv->nr];
1388	port_rules = adin1110_port_rules(other_port, false, true);
1389	eth_broadcast_addr(mask);
1390
1391	return adin1110_write_mac_address(other_port, mac_nr, (u8 *)fdb->addr,
1392					  mask, port_rules);
1393}
1394
1395static int adin1110_read_mac(struct adin1110_priv *priv, int mac_nr, u8 *addr)
1396{
1397	u32 val;
1398	int ret;
1399
1400	ret = adin1110_read_reg(priv, ADIN1110_MAC_ADDR_FILTER_UPR + (mac_nr * 2), &val);
1401	if (ret < 0)
1402		return ret;
1403
1404	put_unaligned_be16(val, addr);
1405
1406	ret = adin1110_read_reg(priv, ADIN1110_MAC_ADDR_FILTER_LWR + (mac_nr * 2), &val);
1407	if (ret < 0)
1408		return ret;
1409
1410	put_unaligned_be32(val, addr + 2);
1411
1412	return 0;
1413}
1414
1415static int adin1110_fdb_del(struct adin1110_port_priv *port_priv,
1416			    struct switchdev_notifier_fdb_info *fdb)
1417{
1418	struct adin1110_priv *priv = port_priv->priv;
1419	u8 addr[ETH_ALEN];
1420	int mac_nr;
1421	int ret;
1422
1423	netdev_dbg(port_priv->netdev,
1424		   "DEBUG: %s: MACID = %pM vid = %u flags = %u %u -- port %d\n",
1425		   __func__, fdb->addr, fdb->vid, fdb->added_by_user,
1426		   fdb->offloaded, port_priv->nr);
1427
1428	if (fdb->is_local)
1429		return -EINVAL;
1430
1431	for (mac_nr = ADIN_MAC_FDB_ADDR_SLOT; mac_nr < ADIN_MAC_MAX_ADDR_SLOTS; mac_nr++) {
1432		ret = adin1110_read_mac(priv, mac_nr, addr);
1433		if (ret < 0)
1434			return ret;
1435
1436		if (ether_addr_equal(addr, fdb->addr)) {
1437			ret = adin1110_clear_mac_address(priv, mac_nr);
1438			if (ret < 0)
1439				return ret;
1440		}
1441	}
1442
1443	return 0;
1444}
1445
1446static void adin1110_switchdev_event_work(struct work_struct *work)
1447{
1448	struct adin1110_switchdev_event_work *switchdev_work;
1449	struct adin1110_port_priv *port_priv;
1450	int ret;
1451
1452	switchdev_work = container_of(work, struct adin1110_switchdev_event_work, work);
1453	port_priv = switchdev_work->port_priv;
1454
1455	mutex_lock(&port_priv->priv->lock);
1456
1457	switch (switchdev_work->event) {
1458	case SWITCHDEV_FDB_ADD_TO_DEVICE:
1459		ret = adin1110_fdb_add(port_priv, &switchdev_work->fdb_info);
1460		if (!ret)
1461			adin1110_fdb_offload_notify(port_priv->netdev,
1462						    &switchdev_work->fdb_info);
1463		break;
1464	case SWITCHDEV_FDB_DEL_TO_DEVICE:
1465		adin1110_fdb_del(port_priv, &switchdev_work->fdb_info);
1466		break;
1467	default:
1468		break;
1469	}
1470
1471	mutex_unlock(&port_priv->priv->lock);
1472
1473	kfree(switchdev_work->fdb_info.addr);
1474	kfree(switchdev_work);
1475	dev_put(port_priv->netdev);
1476}
1477
1478/* called under rcu_read_lock() */
1479static int adin1110_switchdev_event(struct notifier_block *unused,
1480				    unsigned long event, void *ptr)
1481{
1482	struct net_device *netdev = switchdev_notifier_info_to_dev(ptr);
1483	struct adin1110_port_priv *port_priv = netdev_priv(netdev);
1484	struct adin1110_switchdev_event_work *switchdev_work;
1485	struct switchdev_notifier_fdb_info *fdb_info = ptr;
1486
1487	if (!adin1110_port_dev_check(netdev))
1488		return NOTIFY_DONE;
1489
1490	switchdev_work = kzalloc(sizeof(*switchdev_work), GFP_ATOMIC);
1491	if (WARN_ON(!switchdev_work))
1492		return NOTIFY_BAD;
1493
1494	INIT_WORK(&switchdev_work->work, adin1110_switchdev_event_work);
1495	switchdev_work->port_priv = port_priv;
1496	switchdev_work->event = event;
1497
1498	switch (event) {
1499	case SWITCHDEV_FDB_ADD_TO_DEVICE:
1500	case SWITCHDEV_FDB_DEL_TO_DEVICE:
1501		memcpy(&switchdev_work->fdb_info, ptr,
1502		       sizeof(switchdev_work->fdb_info));
1503		switchdev_work->fdb_info.addr = kzalloc(ETH_ALEN, GFP_ATOMIC);
1504
1505		if (!switchdev_work->fdb_info.addr)
1506			goto err_addr_alloc;
1507
1508		ether_addr_copy((u8 *)switchdev_work->fdb_info.addr,
1509				fdb_info->addr);
1510		dev_hold(netdev);
1511		break;
1512	default:
1513		kfree(switchdev_work);
1514		return NOTIFY_DONE;
1515	}
1516
1517	queue_work(system_long_wq, &switchdev_work->work);
1518
1519	return NOTIFY_DONE;
1520
1521err_addr_alloc:
1522	kfree(switchdev_work);
1523	return NOTIFY_BAD;
1524}
1525
1526static struct notifier_block adin1110_switchdev_notifier = {
1527	.notifier_call = adin1110_switchdev_event,
1528};
1529
1530static void adin1110_unregister_notifiers(void)
1531{
1532	unregister_switchdev_blocking_notifier(&adin1110_switchdev_blocking_notifier);
1533	unregister_switchdev_notifier(&adin1110_switchdev_notifier);
1534	unregister_netdevice_notifier(&adin1110_netdevice_nb);
1535}
1536
1537static int adin1110_setup_notifiers(void)
1538{
1539	int ret;
1540
1541	ret = register_netdevice_notifier(&adin1110_netdevice_nb);
1542	if (ret < 0)
1543		return ret;
1544
1545	ret = register_switchdev_notifier(&adin1110_switchdev_notifier);
1546	if (ret < 0)
1547		goto err_netdev;
1548
1549	ret = register_switchdev_blocking_notifier(&adin1110_switchdev_blocking_notifier);
1550	if (ret < 0)
1551		goto err_sdev;
1552
1553	return 0;
1554
1555err_sdev:
1556	unregister_switchdev_notifier(&adin1110_switchdev_notifier);
1557
1558err_netdev:
1559	unregister_netdevice_notifier(&adin1110_netdevice_nb);
1560
1561	return ret;
1562}
1563
1564static int adin1110_probe_netdevs(struct adin1110_priv *priv)
1565{
1566	struct device *dev = &priv->spidev->dev;
1567	struct adin1110_port_priv *port_priv;
1568	struct net_device *netdev;
1569	int ret;
1570	int i;
1571
1572	for (i = 0; i < priv->cfg->ports_nr; i++) {
1573		netdev = devm_alloc_etherdev(dev, sizeof(*port_priv));
1574		if (!netdev)
1575			return -ENOMEM;
1576
1577		port_priv = netdev_priv(netdev);
1578		port_priv->netdev = netdev;
1579		port_priv->priv = priv;
1580		port_priv->cfg = priv->cfg;
1581		port_priv->nr = i;
1582		priv->ports[i] = port_priv;
1583		SET_NETDEV_DEV(netdev, dev);
1584
1585		ret = device_get_ethdev_address(dev, netdev);
1586		if (ret < 0)
1587			return ret;
1588
1589		netdev->irq = priv->spidev->irq;
1590		INIT_WORK(&port_priv->tx_work, adin1110_tx_work);
1591		INIT_WORK(&port_priv->rx_mode_work, adin1110_rx_mode_work);
1592		skb_queue_head_init(&port_priv->txq);
1593
1594		netif_carrier_off(netdev);
1595
1596		netdev->if_port = IF_PORT_10BASET;
1597		netdev->netdev_ops = &adin1110_netdev_ops;
1598		netdev->ethtool_ops = &adin1110_ethtool_ops;
1599		netdev->priv_flags |= IFF_UNICAST_FLT;
1600		netdev->features |= NETIF_F_NETNS_LOCAL;
1601
1602		port_priv->phydev = get_phy_device(priv->mii_bus, i + 1, false);
1603		if (IS_ERR(port_priv->phydev)) {
1604			netdev_err(netdev, "Could not find PHY with device address: %d.\n", i);
1605			return PTR_ERR(port_priv->phydev);
1606		}
1607
1608		port_priv->phydev = phy_connect(netdev,
1609						phydev_name(port_priv->phydev),
1610						adin1110_adjust_link,
1611						PHY_INTERFACE_MODE_INTERNAL);
1612		if (IS_ERR(port_priv->phydev)) {
1613			netdev_err(netdev, "Could not connect PHY with device address: %d.\n", i);
1614			return PTR_ERR(port_priv->phydev);
1615		}
1616
1617		ret = devm_add_action_or_reset(dev, adin1110_disconnect_phy,
1618					       port_priv->phydev);
1619		if (ret < 0)
1620			return ret;
1621	}
1622
1623	/* ADIN1110 INT_N pin will be used to signal the host */
1624	ret = devm_request_threaded_irq(dev, priv->spidev->irq, NULL,
1625					adin1110_irq,
1626					IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1627					dev_name(dev), priv);
1628	if (ret < 0)
1629		return ret;
1630
1631	for (i = 0; i < priv->cfg->ports_nr; i++) {
1632		ret = devm_register_netdev(dev, priv->ports[i]->netdev);
1633		if (ret < 0) {
1634			dev_err(dev, "Failed to register network device.\n");
1635			return ret;
1636		}
1637	}
1638
1639	return 0;
1640}
1641
1642static int adin1110_probe(struct spi_device *spi)
1643{
1644	const struct spi_device_id *dev_id = spi_get_device_id(spi);
1645	struct device *dev = &spi->dev;
1646	struct adin1110_priv *priv;
1647	int ret;
1648
1649	priv = devm_kzalloc(dev, sizeof(struct adin1110_priv), GFP_KERNEL);
1650	if (!priv)
1651		return -ENOMEM;
1652
1653	priv->spidev = spi;
1654	priv->cfg = &adin1110_cfgs[dev_id->driver_data];
1655	spi->bits_per_word = 8;
1656	spi->mode = SPI_MODE_0;
1657
1658	mutex_init(&priv->lock);
1659	spin_lock_init(&priv->state_lock);
1660
1661	/* use of CRC on control and data transactions is pin dependent */
1662	priv->append_crc = device_property_read_bool(dev, "adi,spi-crc");
1663	if (priv->append_crc)
1664		crc8_populate_msb(adin1110_crc_table, 0x7);
1665
1666	ret = adin1110_check_spi(priv);
1667	if (ret < 0) {
1668		dev_err(dev, "Probe SPI Read check failed: %d\n", ret);
1669		return ret;
1670	}
1671
1672	ret = adin1110_write_reg(priv, ADIN1110_RESET, ADIN1110_SWRESET);
1673	if (ret < 0)
1674		return ret;
1675
1676	ret = adin1110_register_mdiobus(priv, dev);
1677	if (ret < 0) {
1678		dev_err(dev, "Could not register MDIO bus %d\n", ret);
1679		return ret;
1680	}
1681
1682	return adin1110_probe_netdevs(priv);
1683}
1684
1685static const struct of_device_id adin1110_match_table[] = {
1686	{ .compatible = "adi,adin1110" },
1687	{ .compatible = "adi,adin2111" },
1688	{ }
1689};
1690MODULE_DEVICE_TABLE(of, adin1110_match_table);
1691
1692static const struct spi_device_id adin1110_spi_id[] = {
1693	{ .name = "adin1110", .driver_data = ADIN1110_MAC },
1694	{ .name = "adin2111", .driver_data = ADIN2111_MAC },
1695	{ }
1696};
1697MODULE_DEVICE_TABLE(spi, adin1110_spi_id);
1698
1699static struct spi_driver adin1110_driver = {
1700	.driver = {
1701		.name = "adin1110",
1702		.of_match_table = adin1110_match_table,
1703	},
1704	.probe = adin1110_probe,
1705	.id_table = adin1110_spi_id,
1706};
1707
1708static int __init adin1110_driver_init(void)
1709{
1710	int ret;
1711
1712	ret = adin1110_setup_notifiers();
1713	if (ret < 0)
1714		return ret;
1715
1716	ret = spi_register_driver(&adin1110_driver);
1717	if (ret < 0) {
1718		adin1110_unregister_notifiers();
1719		return ret;
1720	}
1721
1722	return 0;
1723}
1724
1725static void __exit adin1110_exit(void)
1726{
1727	adin1110_unregister_notifiers();
1728	spi_unregister_driver(&adin1110_driver);
1729}
1730module_init(adin1110_driver_init);
1731module_exit(adin1110_exit);
1732
1733MODULE_DESCRIPTION("ADIN1110 Network driver");
1734MODULE_AUTHOR("Alexandru Tachici <alexandru.tachici@analog.com>");
1735MODULE_LICENSE("Dual BSD/GPL");