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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Marvell 88E6xxx Ethernet switch single-chip definition
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 */
7
8#ifndef _MV88E6XXX_CHIP_H
9#define _MV88E6XXX_CHIP_H
10
11#include <linux/idr.h>
12#include <linux/if_vlan.h>
13#include <linux/irq.h>
14#include <linux/gpio/consumer.h>
15#include <linux/kthread.h>
16#include <linux/phy.h>
17#include <linux/ptp_clock_kernel.h>
18#include <linux/timecounter.h>
19#include <net/dsa.h>
20
21#define EDSA_HLEN 8
22#define MV88E6XXX_N_FID 4096
23#define MV88E6XXX_N_SID 64
24
25#define MV88E6XXX_FID_STANDALONE 0
26#define MV88E6XXX_FID_BRIDGED 1
27
28/* PVT limits for 4-bit port and 5-bit switch */
29#define MV88E6XXX_MAX_PVT_SWITCHES 32
30#define MV88E6XXX_MAX_PVT_PORTS 16
31#define MV88E6XXX_MAX_PVT_ENTRIES \
32 (MV88E6XXX_MAX_PVT_SWITCHES * MV88E6XXX_MAX_PVT_PORTS)
33
34#define MV88E6XXX_MAX_GPIO 16
35
36enum mv88e6xxx_egress_mode {
37 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
38 MV88E6XXX_EGRESS_MODE_UNTAGGED,
39 MV88E6XXX_EGRESS_MODE_TAGGED,
40 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
41};
42
43enum mv88e6xxx_egress_direction {
44 MV88E6XXX_EGRESS_DIR_INGRESS,
45 MV88E6XXX_EGRESS_DIR_EGRESS,
46};
47
48enum mv88e6xxx_frame_mode {
49 MV88E6XXX_FRAME_MODE_NORMAL,
50 MV88E6XXX_FRAME_MODE_DSA,
51 MV88E6XXX_FRAME_MODE_PROVIDER,
52 MV88E6XXX_FRAME_MODE_ETHERTYPE,
53};
54
55/* List of supported models */
56enum mv88e6xxx_model {
57 MV88E6020,
58 MV88E6071,
59 MV88E6085,
60 MV88E6095,
61 MV88E6097,
62 MV88E6123,
63 MV88E6131,
64 MV88E6141,
65 MV88E6161,
66 MV88E6165,
67 MV88E6171,
68 MV88E6172,
69 MV88E6175,
70 MV88E6176,
71 MV88E6185,
72 MV88E6190,
73 MV88E6190X,
74 MV88E6191,
75 MV88E6191X,
76 MV88E6193X,
77 MV88E6220,
78 MV88E6240,
79 MV88E6250,
80 MV88E6290,
81 MV88E6320,
82 MV88E6321,
83 MV88E6341,
84 MV88E6350,
85 MV88E6351,
86 MV88E6352,
87 MV88E6361,
88 MV88E6390,
89 MV88E6390X,
90 MV88E6393X,
91};
92
93enum mv88e6xxx_family {
94 MV88E6XXX_FAMILY_NONE,
95 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */
96 MV88E6XXX_FAMILY_6095, /* 6092 6095 */
97 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */
98 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */
99 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
100 MV88E6XXX_FAMILY_6250, /* 6220 6250 6020 6071 */
101 MV88E6XXX_FAMILY_6320, /* 6320 6321 */
102 MV88E6XXX_FAMILY_6341, /* 6141 6341 */
103 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
104 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
105 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
106 MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6361 6393X */
107};
108
109/**
110 * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level
111 * @MV88E6XXX_EDSA_UNSUPPORTED: Device has no support for EDSA tags
112 * @MV88E6XXX_EDSA_UNDOCUMENTED: Documentation indicates that
113 * egressing FORWARD frames with an EDSA
114 * tag is reserved for future use, but
115 * empirical data shows that this mode
116 * is supported.
117 * @MV88E6XXX_EDSA_SUPPORTED: EDSA tags are fully supported.
118 */
119enum mv88e6xxx_edsa_support {
120 MV88E6XXX_EDSA_UNSUPPORTED = 0,
121 MV88E6XXX_EDSA_UNDOCUMENTED,
122 MV88E6XXX_EDSA_SUPPORTED,
123};
124
125struct mv88e6xxx_ops;
126
127struct mv88e6xxx_info {
128 enum mv88e6xxx_family family;
129 u16 prod_num;
130 const char *name;
131 unsigned int num_databases;
132 unsigned int num_macs;
133 unsigned int num_ports;
134 unsigned int num_internal_phys;
135 unsigned int num_gpio;
136 unsigned int max_vid;
137 unsigned int max_sid;
138 unsigned int port_base_addr;
139 unsigned int phy_base_addr;
140 unsigned int global1_addr;
141 unsigned int global2_addr;
142 unsigned int age_time_coeff;
143 unsigned int g1_irqs;
144 unsigned int g2_irqs;
145 bool pvt;
146
147 /* Mark certain ports as invalid. This is required for example for the
148 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the
149 * ports 2-4 are not routet to pins.
150 */
151 unsigned int invalid_port_mask;
152 /* Multi-chip Addressing Mode.
153 * Some chips respond to only 2 registers of its own SMI device address
154 * when it is non-zero, and use indirect access to internal registers.
155 */
156 bool multi_chip;
157 /* Dual-chip Addressing Mode
158 * Some chips respond to only half of the 32 SMI addresses,
159 * allowing two to coexist on the same SMI interface.
160 */
161 bool dual_chip;
162
163 enum mv88e6xxx_edsa_support edsa_support;
164
165 /* Mask for FromPort and ToPort value of PortVec used in ATU Move
166 * operation. 0 means that the ATU Move operation is not supported.
167 */
168 u8 atu_move_port_mask;
169 const struct mv88e6xxx_ops *ops;
170
171 /* Supports PTP */
172 bool ptp_support;
173
174 /* Internal PHY start index. 0 means that internal PHYs range starts at
175 * port 0, 1 means internal PHYs range starts at port 1, etc
176 */
177 unsigned int internal_phys_offset;
178};
179
180struct mv88e6xxx_atu_entry {
181 u8 state;
182 bool trunk;
183 u16 portvec;
184 u8 mac[ETH_ALEN];
185};
186
187struct mv88e6xxx_vtu_entry {
188 u16 vid;
189 u16 fid;
190 u8 sid;
191 bool valid;
192 bool policy;
193 u8 member[DSA_MAX_PORTS];
194 u8 state[DSA_MAX_PORTS]; /* Older silicon has no STU */
195};
196
197struct mv88e6xxx_stu_entry {
198 u8 sid;
199 bool valid;
200 u8 state[DSA_MAX_PORTS];
201};
202
203struct mv88e6xxx_bus_ops;
204struct mv88e6xxx_irq_ops;
205struct mv88e6xxx_gpio_ops;
206struct mv88e6xxx_avb_ops;
207struct mv88e6xxx_ptp_ops;
208struct mv88e6xxx_pcs_ops;
209
210struct mv88e6xxx_irq {
211 u16 masked;
212 struct irq_chip chip;
213 struct irq_domain *domain;
214 int nirqs;
215};
216
217/* state flags for mv88e6xxx_port_hwtstamp::state */
218enum {
219 MV88E6XXX_HWTSTAMP_ENABLED,
220 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
221};
222
223struct mv88e6xxx_port_hwtstamp {
224 /* Port index */
225 int port_id;
226
227 /* Timestamping state */
228 unsigned long state;
229
230 /* Resources for receive timestamping */
231 struct sk_buff_head rx_queue;
232 struct sk_buff_head rx_queue2;
233
234 /* Resources for transmit timestamping */
235 unsigned long tx_tstamp_start;
236 struct sk_buff *tx_skb;
237 u16 tx_seq_id;
238
239 /* Current timestamp configuration */
240 struct hwtstamp_config tstamp_config;
241};
242
243enum mv88e6xxx_policy_mapping {
244 MV88E6XXX_POLICY_MAPPING_DA,
245 MV88E6XXX_POLICY_MAPPING_SA,
246 MV88E6XXX_POLICY_MAPPING_VTU,
247 MV88E6XXX_POLICY_MAPPING_ETYPE,
248 MV88E6XXX_POLICY_MAPPING_PPPOE,
249 MV88E6XXX_POLICY_MAPPING_VBAS,
250 MV88E6XXX_POLICY_MAPPING_OPT82,
251 MV88E6XXX_POLICY_MAPPING_UDP,
252};
253
254enum mv88e6xxx_policy_action {
255 MV88E6XXX_POLICY_ACTION_NORMAL,
256 MV88E6XXX_POLICY_ACTION_MIRROR,
257 MV88E6XXX_POLICY_ACTION_TRAP,
258 MV88E6XXX_POLICY_ACTION_DISCARD,
259};
260
261struct mv88e6xxx_policy {
262 enum mv88e6xxx_policy_mapping mapping;
263 enum mv88e6xxx_policy_action action;
264 struct ethtool_rx_flow_spec fs;
265 u8 addr[ETH_ALEN];
266 int port;
267 u16 vid;
268};
269
270struct mv88e6xxx_vlan {
271 u16 vid;
272 bool valid;
273};
274
275struct mv88e6xxx_port {
276 struct mv88e6xxx_chip *chip;
277 int port;
278 struct mv88e6xxx_vlan bridge_pvid;
279 u64 serdes_stats[2];
280 u64 atu_member_violation;
281 u64 atu_miss_violation;
282 u64 atu_full_violation;
283 u64 vtu_member_violation;
284 u64 vtu_miss_violation;
285 phy_interface_t interface;
286 u8 cmode;
287 bool mirror_ingress;
288 bool mirror_egress;
289 struct devlink_region *region;
290 void *pcs_private;
291
292 /* MacAuth Bypass control flag */
293 bool mab;
294};
295
296enum mv88e6xxx_region_id {
297 MV88E6XXX_REGION_GLOBAL1 = 0,
298 MV88E6XXX_REGION_GLOBAL2,
299 MV88E6XXX_REGION_ATU,
300 MV88E6XXX_REGION_VTU,
301 MV88E6XXX_REGION_STU,
302 MV88E6XXX_REGION_PVT,
303
304 _MV88E6XXX_REGION_MAX,
305};
306
307struct mv88e6xxx_region_priv {
308 enum mv88e6xxx_region_id id;
309};
310
311struct mv88e6xxx_mst {
312 struct list_head node;
313
314 refcount_t refcnt;
315 struct net_device *br;
316 u16 msti;
317
318 struct mv88e6xxx_stu_entry stu;
319};
320
321#define STATS_TYPE_PORT BIT(0)
322#define STATS_TYPE_BANK0 BIT(1)
323#define STATS_TYPE_BANK1 BIT(2)
324
325struct mv88e6xxx_hw_stat {
326 char string[ETH_GSTRING_LEN];
327 size_t size;
328 int reg;
329 int type;
330};
331
332struct mv88e6xxx_chip {
333 const struct mv88e6xxx_info *info;
334
335 /* Currently configured tagging protocol */
336 enum dsa_tag_protocol tag_protocol;
337
338 /* The dsa_switch this private structure is related to */
339 struct dsa_switch *ds;
340
341 /* The device this structure is associated to */
342 struct device *dev;
343
344 /* This mutex protects the access to the switch registers */
345 struct mutex reg_lock;
346
347 /* The MII bus and the address on the bus that is used to
348 * communication with the switch
349 */
350 const struct mv88e6xxx_bus_ops *smi_ops;
351 struct mii_bus *bus;
352 int sw_addr;
353
354 /* Handles automatic disabling and re-enabling of the PHY
355 * polling unit.
356 */
357 const struct mv88e6xxx_bus_ops *phy_ops;
358 struct mutex ppu_mutex;
359 int ppu_disabled;
360 struct work_struct ppu_work;
361 struct timer_list ppu_timer;
362
363 /* This mutex serialises access to the statistics unit.
364 * Hold this mutex over snapshot + dump sequences.
365 */
366 struct mutex stats_mutex;
367
368 /* A switch may have a GPIO line tied to its reset pin. Parse
369 * this from the device tree, and use it before performing
370 * switch soft reset.
371 */
372 struct gpio_desc *reset;
373
374 /* set to size of eeprom if supported by the switch */
375 u32 eeprom_len;
376
377 /* List of mdio busses */
378 struct list_head mdios;
379
380 /* Policy Control List IDs and rules */
381 struct idr policies;
382
383 /* There can be two interrupt controllers, which are chained
384 * off a GPIO as interrupt source
385 */
386 struct mv88e6xxx_irq g1_irq;
387 struct mv88e6xxx_irq g2_irq;
388 int irq;
389 char irq_name[64];
390 int device_irq;
391 char device_irq_name[64];
392 int watchdog_irq;
393 char watchdog_irq_name[64];
394
395 int atu_prob_irq;
396 char atu_prob_irq_name[64];
397 int vtu_prob_irq;
398 char vtu_prob_irq_name[64];
399 struct kthread_worker *kworker;
400 struct kthread_delayed_work irq_poll_work;
401
402 /* GPIO resources */
403 u8 gpio_data[2];
404
405 /* This cyclecounter abstracts the switch PTP time.
406 * reg_lock must be held for any operation that read()s.
407 */
408 struct cyclecounter tstamp_cc;
409 struct timecounter tstamp_tc;
410 struct delayed_work overflow_work;
411
412 struct ptp_clock *ptp_clock;
413 struct ptp_clock_info ptp_clock_info;
414 struct delayed_work tai_event_work;
415 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO];
416 u16 trig_config;
417 u16 evcap_config;
418 u16 enable_count;
419
420 /* Current ingress and egress monitor ports */
421 int egress_dest_port;
422 int ingress_dest_port;
423
424 /* Per-port timestamping resources. */
425 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
426
427 /* Array of port structures. */
428 struct mv88e6xxx_port ports[DSA_MAX_PORTS];
429
430 /* devlink regions */
431 struct devlink_region *regions[_MV88E6XXX_REGION_MAX];
432
433 /* Bridge MST to SID mappings */
434 struct list_head msts;
435};
436
437struct mv88e6xxx_bus_ops {
438 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
439 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
440 int (*init)(struct mv88e6xxx_chip *chip);
441};
442
443struct mv88e6xxx_mdio_bus {
444 struct mii_bus *bus;
445 struct mv88e6xxx_chip *chip;
446 struct list_head list;
447 bool external;
448};
449
450struct mv88e6xxx_ops {
451 /* Switch Setup Errata, called early in the switch setup to
452 * allow any errata actions to be performed
453 */
454 int (*setup_errata)(struct mv88e6xxx_chip *chip);
455
456 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip);
457 int (*ip_pri_map)(struct mv88e6xxx_chip *chip);
458
459 /* Ingress Rate Limit unit (IRL) operations */
460 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
461
462 int (*get_eeprom)(struct mv88e6xxx_chip *chip,
463 struct ethtool_eeprom *eeprom, u8 *data);
464 int (*set_eeprom)(struct mv88e6xxx_chip *chip,
465 struct ethtool_eeprom *eeprom, u8 *data);
466
467 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
468
469 int (*phy_read)(struct mv88e6xxx_chip *chip,
470 struct mii_bus *bus,
471 int addr, int reg, u16 *val);
472 int (*phy_write)(struct mv88e6xxx_chip *chip,
473 struct mii_bus *bus,
474 int addr, int reg, u16 val);
475
476 int (*phy_read_c45)(struct mv88e6xxx_chip *chip,
477 struct mii_bus *bus,
478 int addr, int devad, int reg, u16 *val);
479 int (*phy_write_c45)(struct mv88e6xxx_chip *chip,
480 struct mii_bus *bus,
481 int addr, int devad, int reg, u16 val);
482
483 /* Priority Override Table operations */
484 int (*pot_clear)(struct mv88e6xxx_chip *chip);
485
486 /* PHY Polling Unit (PPU) operations */
487 int (*ppu_enable)(struct mv88e6xxx_chip *chip);
488 int (*ppu_disable)(struct mv88e6xxx_chip *chip);
489
490 /* Switch Software Reset */
491 int (*reset)(struct mv88e6xxx_chip *chip);
492
493 /* RGMII Receive/Transmit Timing Control
494 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
495 */
496 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
497 phy_interface_t mode);
498
499#define LINK_FORCED_DOWN 0
500#define LINK_FORCED_UP 1
501#define LINK_UNFORCED -2
502
503 /* Port's MAC link state
504 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
505 * or LINK_UNFORCED for normal link detection.
506 */
507 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
508
509 /* Synchronise the port link state with that of the SERDES
510 */
511 int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);
512
513#define PAUSE_ON 1
514#define PAUSE_OFF 0
515
516 /* Enable/disable sending Pause */
517 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
518 int pause);
519
520#define SPEED_UNFORCED -2
521#define DUPLEX_UNFORCED -2
522
523 /* Port's MAC speed (in Mbps) and MAC duplex mode
524 *
525 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
526 * Use SPEED_UNFORCED for normal detection.
527 *
528 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
529 * or DUPLEX_UNFORCED for normal duplex detection.
530 */
531 int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port,
532 int speed, int duplex);
533
534 /* What interface mode should be used for maximum speed? */
535 phy_interface_t (*port_max_speed_mode)(struct mv88e6xxx_chip *chip,
536 int port);
537
538 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
539
540 int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port,
541 enum mv88e6xxx_policy_mapping mapping,
542 enum mv88e6xxx_policy_action action);
543
544 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
545 enum mv88e6xxx_frame_mode mode);
546 int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port,
547 bool unicast);
548 int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port,
549 bool multicast);
550 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
551 u16 etype);
552 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
553 size_t size);
554
555 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
556 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
557 u8 out);
558 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
559 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
560 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port);
561
562 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
563 * Some chips allow this to be configured on specific ports.
564 */
565 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
566 phy_interface_t mode);
567 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
568
569 /* Some devices have a per port register indicating what is
570 * the upstream port this port should forward to.
571 */
572 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
573 int upstream_port);
574
575 /* Snapshot the statistics for a port. The statistics can then
576 * be read back a leisure but still with a consistent view.
577 */
578 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
579
580 /* Set the histogram mode for statistics, when the control registers
581 * are separated out of the STATS_OP register.
582 */
583 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
584
585 /* Return the number of strings describing statistics */
586 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
587 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data);
588 size_t (*stats_get_stat)(struct mv88e6xxx_chip *chip, int port,
589 const struct mv88e6xxx_hw_stat *stat,
590 uint64_t *data);
591 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
592 int (*set_egress_port)(struct mv88e6xxx_chip *chip,
593 enum mv88e6xxx_egress_direction direction,
594 int port);
595
596#define MV88E6XXX_CASCADE_PORT_NONE 0xe
597#define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf
598
599 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
600
601 const struct mv88e6xxx_irq_ops *watchdog_ops;
602
603 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
604
605 /* SERDES lane mapping */
606 int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port);
607
608 /* SERDES interrupt handling */
609 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip,
610 int port);
611
612 /* Statistics from the SERDES interface */
613 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
614 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port,
615 uint8_t *data);
616 size_t (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port,
617 uint64_t *data);
618
619 /* SERDES registers for ethtool */
620 int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port);
621 void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port,
622 void *_p);
623
624 /* SERDES SGMII/Fiber Output Amplitude */
625 int (*serdes_set_tx_amplitude)(struct mv88e6xxx_chip *chip, int port,
626 int val);
627
628 /* Address Translation Unit operations */
629 int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash);
630 int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash);
631
632 /* VLAN Translation Unit operations */
633 int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
634 struct mv88e6xxx_vtu_entry *entry);
635 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
636 struct mv88e6xxx_vtu_entry *entry);
637
638 /* Spanning Tree Unit operations */
639 int (*stu_getnext)(struct mv88e6xxx_chip *chip,
640 struct mv88e6xxx_stu_entry *entry);
641 int (*stu_loadpurge)(struct mv88e6xxx_chip *chip,
642 struct mv88e6xxx_stu_entry *entry);
643
644 /* GPIO operations */
645 const struct mv88e6xxx_gpio_ops *gpio_ops;
646
647 /* Interface to the AVB/PTP registers */
648 const struct mv88e6xxx_avb_ops *avb_ops;
649
650 /* Remote Management Unit operations */
651 int (*rmu_disable)(struct mv88e6xxx_chip *chip);
652
653 /* Precision Time Protocol operations */
654 const struct mv88e6xxx_ptp_ops *ptp_ops;
655
656 /* Phylink */
657 void (*phylink_get_caps)(struct mv88e6xxx_chip *chip, int port,
658 struct phylink_config *config);
659
660 const struct mv88e6xxx_pcs_ops *pcs_ops;
661
662 /* Max Frame Size */
663 int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu);
664};
665
666struct mv88e6xxx_irq_ops {
667 /* Action to be performed when the interrupt happens */
668 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
669 /* Setup the hardware to generate the interrupt */
670 int (*irq_setup)(struct mv88e6xxx_chip *chip);
671 /* Reset the hardware to stop generating the interrupt */
672 void (*irq_free)(struct mv88e6xxx_chip *chip);
673};
674
675struct mv88e6xxx_gpio_ops {
676 /* Get/set data on GPIO pin */
677 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
678 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
679 int value);
680
681 /* get/set GPIO direction */
682 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
683 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
684 bool input);
685
686 /* get/set GPIO pin control */
687 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
688 int *func);
689 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
690 int func);
691};
692
693struct mv88e6xxx_avb_ops {
694 /* Access port-scoped Precision Time Protocol registers */
695 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
696 u16 *data, int len);
697 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
698 u16 data);
699
700 /* Access global Precision Time Protocol registers */
701 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
702 int len);
703 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
704
705 /* Access global Time Application Interface registers */
706 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
707 int len);
708 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
709};
710
711struct mv88e6xxx_ptp_ops {
712 u64 (*clock_read)(const struct cyclecounter *cc);
713 int (*ptp_enable)(struct ptp_clock_info *ptp,
714 struct ptp_clock_request *rq, int on);
715 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin,
716 enum ptp_pin_function func, unsigned int chan);
717 void (*event_work)(struct work_struct *ugly);
718 int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
719 int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
720 int (*global_enable)(struct mv88e6xxx_chip *chip);
721 int (*global_disable)(struct mv88e6xxx_chip *chip);
722 int (*set_ptp_cpu_port)(struct mv88e6xxx_chip *chip, int port);
723 int n_ext_ts;
724 int arr0_sts_reg;
725 int arr1_sts_reg;
726 int dep_sts_reg;
727 u32 rx_filters;
728 u32 cc_shift;
729 u32 cc_mult;
730 u32 cc_mult_num;
731 u32 cc_mult_dem;
732};
733
734struct mv88e6xxx_pcs_ops {
735 int (*pcs_init)(struct mv88e6xxx_chip *chip, int port);
736 void (*pcs_teardown)(struct mv88e6xxx_chip *chip, int port);
737 struct phylink_pcs *(*pcs_select)(struct mv88e6xxx_chip *chip, int port,
738 phy_interface_t mode);
739
740};
741
742static inline bool mv88e6xxx_has_stu(struct mv88e6xxx_chip *chip)
743{
744 return chip->info->max_sid > 0 &&
745 chip->info->ops->stu_loadpurge &&
746 chip->info->ops->stu_getnext;
747}
748
749static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
750{
751 return chip->info->pvt;
752}
753
754static inline bool mv88e6xxx_has_lag(struct mv88e6xxx_chip *chip)
755{
756 return !!chip->info->global2_addr;
757}
758
759static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
760{
761 return chip->info->num_databases;
762}
763
764static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip)
765{
766 return chip->info->num_macs;
767}
768
769static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
770{
771 return chip->info->num_ports;
772}
773
774static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip)
775{
776 return chip->info->max_vid;
777}
778
779static inline unsigned int mv88e6xxx_max_sid(struct mv88e6xxx_chip *chip)
780{
781 return chip->info->max_sid;
782}
783
784static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
785{
786 return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0);
787}
788
789static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
790{
791 return chip->info->num_gpio;
792}
793
794static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port)
795{
796 return (chip->info->invalid_port_mask & BIT(port)) != 0;
797}
798
799static inline void mv88e6xxx_port_set_mab(struct mv88e6xxx_chip *chip,
800 int port, bool mab)
801{
802 chip->ports[port].mab = mab;
803}
804
805int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
806int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
807int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
808 u16 mask, u16 val);
809int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
810 int bit, int val);
811struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
812
813static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip)
814{
815 mutex_lock(&chip->reg_lock);
816}
817
818static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip)
819{
820 mutex_unlock(&chip->reg_lock);
821}
822
823int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
824 int (*cb)(struct mv88e6xxx_chip *chip,
825 const struct mv88e6xxx_vtu_entry *entry,
826 void *priv),
827 void *priv);
828
829int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap);
830
831#endif /* _MV88E6XXX_CHIP_H */
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Marvell 88E6xxx Ethernet switch single-chip definition
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 */
7
8#ifndef _MV88E6XXX_CHIP_H
9#define _MV88E6XXX_CHIP_H
10
11#include <linux/idr.h>
12#include <linux/if_vlan.h>
13#include <linux/irq.h>
14#include <linux/gpio/consumer.h>
15#include <linux/kthread.h>
16#include <linux/phy.h>
17#include <linux/ptp_clock_kernel.h>
18#include <linux/timecounter.h>
19#include <net/dsa.h>
20
21#define EDSA_HLEN 8
22#define MV88E6XXX_N_FID 4096
23#define MV88E6XXX_N_SID 64
24
25#define MV88E6XXX_FID_STANDALONE 0
26#define MV88E6XXX_FID_BRIDGED 1
27
28/* PVT limits for 4-bit port and 5-bit switch */
29#define MV88E6XXX_MAX_PVT_SWITCHES 32
30#define MV88E6XXX_MAX_PVT_PORTS 16
31#define MV88E6XXX_MAX_PVT_ENTRIES \
32 (MV88E6XXX_MAX_PVT_SWITCHES * MV88E6XXX_MAX_PVT_PORTS)
33
34#define MV88E6XXX_MAX_GPIO 16
35
36enum mv88e6xxx_egress_mode {
37 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
38 MV88E6XXX_EGRESS_MODE_UNTAGGED,
39 MV88E6XXX_EGRESS_MODE_TAGGED,
40 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
41};
42
43enum mv88e6xxx_egress_direction {
44 MV88E6XXX_EGRESS_DIR_INGRESS,
45 MV88E6XXX_EGRESS_DIR_EGRESS,
46};
47
48enum mv88e6xxx_frame_mode {
49 MV88E6XXX_FRAME_MODE_NORMAL,
50 MV88E6XXX_FRAME_MODE_DSA,
51 MV88E6XXX_FRAME_MODE_PROVIDER,
52 MV88E6XXX_FRAME_MODE_ETHERTYPE,
53};
54
55/* List of supported models */
56enum mv88e6xxx_model {
57 MV88E6085,
58 MV88E6095,
59 MV88E6097,
60 MV88E6123,
61 MV88E6131,
62 MV88E6141,
63 MV88E6161,
64 MV88E6165,
65 MV88E6171,
66 MV88E6172,
67 MV88E6175,
68 MV88E6176,
69 MV88E6185,
70 MV88E6190,
71 MV88E6190X,
72 MV88E6191,
73 MV88E6191X,
74 MV88E6193X,
75 MV88E6220,
76 MV88E6240,
77 MV88E6250,
78 MV88E6290,
79 MV88E6320,
80 MV88E6321,
81 MV88E6341,
82 MV88E6350,
83 MV88E6351,
84 MV88E6352,
85 MV88E6390,
86 MV88E6390X,
87 MV88E6393X,
88};
89
90enum mv88e6xxx_family {
91 MV88E6XXX_FAMILY_NONE,
92 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */
93 MV88E6XXX_FAMILY_6095, /* 6092 6095 */
94 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */
95 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */
96 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
97 MV88E6XXX_FAMILY_6250, /* 6220 6250 */
98 MV88E6XXX_FAMILY_6320, /* 6320 6321 */
99 MV88E6XXX_FAMILY_6341, /* 6141 6341 */
100 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
101 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
102 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
103 MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6393X */
104};
105
106/**
107 * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level
108 * @MV88E6XXX_EDSA_UNSUPPORTED: Device has no support for EDSA tags
109 * @MV88E6XXX_EDSA_UNDOCUMENTED: Documentation indicates that
110 * egressing FORWARD frames with an EDSA
111 * tag is reserved for future use, but
112 * empirical data shows that this mode
113 * is supported.
114 * @MV88E6XXX_EDSA_SUPPORTED: EDSA tags are fully supported.
115 */
116enum mv88e6xxx_edsa_support {
117 MV88E6XXX_EDSA_UNSUPPORTED = 0,
118 MV88E6XXX_EDSA_UNDOCUMENTED,
119 MV88E6XXX_EDSA_SUPPORTED,
120};
121
122struct mv88e6xxx_ops;
123
124struct mv88e6xxx_info {
125 enum mv88e6xxx_family family;
126 u16 prod_num;
127 const char *name;
128 unsigned int num_databases;
129 unsigned int num_macs;
130 unsigned int num_ports;
131 unsigned int num_internal_phys;
132 unsigned int num_gpio;
133 unsigned int max_vid;
134 unsigned int max_sid;
135 unsigned int port_base_addr;
136 unsigned int phy_base_addr;
137 unsigned int global1_addr;
138 unsigned int global2_addr;
139 unsigned int age_time_coeff;
140 unsigned int g1_irqs;
141 unsigned int g2_irqs;
142 bool pvt;
143
144 /* Mark certain ports as invalid. This is required for example for the
145 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the
146 * ports 2-4 are not routet to pins.
147 */
148 unsigned int invalid_port_mask;
149 /* Multi-chip Addressing Mode.
150 * Some chips respond to only 2 registers of its own SMI device address
151 * when it is non-zero, and use indirect access to internal registers.
152 */
153 bool multi_chip;
154 /* Dual-chip Addressing Mode
155 * Some chips respond to only half of the 32 SMI addresses,
156 * allowing two to coexist on the same SMI interface.
157 */
158 bool dual_chip;
159
160 enum mv88e6xxx_edsa_support edsa_support;
161
162 /* Mask for FromPort and ToPort value of PortVec used in ATU Move
163 * operation. 0 means that the ATU Move operation is not supported.
164 */
165 u8 atu_move_port_mask;
166 const struct mv88e6xxx_ops *ops;
167
168 /* Supports PTP */
169 bool ptp_support;
170};
171
172struct mv88e6xxx_atu_entry {
173 u8 state;
174 bool trunk;
175 u16 portvec;
176 u8 mac[ETH_ALEN];
177};
178
179struct mv88e6xxx_vtu_entry {
180 u16 vid;
181 u16 fid;
182 u8 sid;
183 bool valid;
184 bool policy;
185 u8 member[DSA_MAX_PORTS];
186 u8 state[DSA_MAX_PORTS]; /* Older silicon has no STU */
187};
188
189struct mv88e6xxx_stu_entry {
190 u8 sid;
191 bool valid;
192 u8 state[DSA_MAX_PORTS];
193};
194
195struct mv88e6xxx_bus_ops;
196struct mv88e6xxx_irq_ops;
197struct mv88e6xxx_gpio_ops;
198struct mv88e6xxx_avb_ops;
199struct mv88e6xxx_ptp_ops;
200
201struct mv88e6xxx_irq {
202 u16 masked;
203 struct irq_chip chip;
204 struct irq_domain *domain;
205 int nirqs;
206};
207
208/* state flags for mv88e6xxx_port_hwtstamp::state */
209enum {
210 MV88E6XXX_HWTSTAMP_ENABLED,
211 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
212};
213
214struct mv88e6xxx_port_hwtstamp {
215 /* Port index */
216 int port_id;
217
218 /* Timestamping state */
219 unsigned long state;
220
221 /* Resources for receive timestamping */
222 struct sk_buff_head rx_queue;
223 struct sk_buff_head rx_queue2;
224
225 /* Resources for transmit timestamping */
226 unsigned long tx_tstamp_start;
227 struct sk_buff *tx_skb;
228 u16 tx_seq_id;
229
230 /* Current timestamp configuration */
231 struct hwtstamp_config tstamp_config;
232};
233
234enum mv88e6xxx_policy_mapping {
235 MV88E6XXX_POLICY_MAPPING_DA,
236 MV88E6XXX_POLICY_MAPPING_SA,
237 MV88E6XXX_POLICY_MAPPING_VTU,
238 MV88E6XXX_POLICY_MAPPING_ETYPE,
239 MV88E6XXX_POLICY_MAPPING_PPPOE,
240 MV88E6XXX_POLICY_MAPPING_VBAS,
241 MV88E6XXX_POLICY_MAPPING_OPT82,
242 MV88E6XXX_POLICY_MAPPING_UDP,
243};
244
245enum mv88e6xxx_policy_action {
246 MV88E6XXX_POLICY_ACTION_NORMAL,
247 MV88E6XXX_POLICY_ACTION_MIRROR,
248 MV88E6XXX_POLICY_ACTION_TRAP,
249 MV88E6XXX_POLICY_ACTION_DISCARD,
250};
251
252struct mv88e6xxx_policy {
253 enum mv88e6xxx_policy_mapping mapping;
254 enum mv88e6xxx_policy_action action;
255 struct ethtool_rx_flow_spec fs;
256 u8 addr[ETH_ALEN];
257 int port;
258 u16 vid;
259};
260
261struct mv88e6xxx_vlan {
262 u16 vid;
263 bool valid;
264};
265
266struct mv88e6xxx_port {
267 struct mv88e6xxx_chip *chip;
268 int port;
269 struct mv88e6xxx_vlan bridge_pvid;
270 u64 serdes_stats[2];
271 u64 atu_member_violation;
272 u64 atu_miss_violation;
273 u64 atu_full_violation;
274 u64 vtu_member_violation;
275 u64 vtu_miss_violation;
276 phy_interface_t interface;
277 u8 cmode;
278 bool mirror_ingress;
279 bool mirror_egress;
280 unsigned int serdes_irq;
281 char serdes_irq_name[64];
282 struct devlink_region *region;
283};
284
285enum mv88e6xxx_region_id {
286 MV88E6XXX_REGION_GLOBAL1 = 0,
287 MV88E6XXX_REGION_GLOBAL2,
288 MV88E6XXX_REGION_ATU,
289 MV88E6XXX_REGION_VTU,
290 MV88E6XXX_REGION_STU,
291 MV88E6XXX_REGION_PVT,
292
293 _MV88E6XXX_REGION_MAX,
294};
295
296struct mv88e6xxx_region_priv {
297 enum mv88e6xxx_region_id id;
298};
299
300struct mv88e6xxx_mst {
301 struct list_head node;
302
303 refcount_t refcnt;
304 struct net_device *br;
305 u16 msti;
306
307 struct mv88e6xxx_stu_entry stu;
308};
309
310struct mv88e6xxx_chip {
311 const struct mv88e6xxx_info *info;
312
313 /* Currently configured tagging protocol */
314 enum dsa_tag_protocol tag_protocol;
315
316 /* The dsa_switch this private structure is related to */
317 struct dsa_switch *ds;
318
319 /* The device this structure is associated to */
320 struct device *dev;
321
322 /* This mutex protects the access to the switch registers */
323 struct mutex reg_lock;
324
325 /* The MII bus and the address on the bus that is used to
326 * communication with the switch
327 */
328 const struct mv88e6xxx_bus_ops *smi_ops;
329 struct mii_bus *bus;
330 int sw_addr;
331
332 /* Handles automatic disabling and re-enabling of the PHY
333 * polling unit.
334 */
335 const struct mv88e6xxx_bus_ops *phy_ops;
336 struct mutex ppu_mutex;
337 int ppu_disabled;
338 struct work_struct ppu_work;
339 struct timer_list ppu_timer;
340
341 /* This mutex serialises access to the statistics unit.
342 * Hold this mutex over snapshot + dump sequences.
343 */
344 struct mutex stats_mutex;
345
346 /* A switch may have a GPIO line tied to its reset pin. Parse
347 * this from the device tree, and use it before performing
348 * switch soft reset.
349 */
350 struct gpio_desc *reset;
351
352 /* set to size of eeprom if supported by the switch */
353 u32 eeprom_len;
354
355 /* List of mdio busses */
356 struct list_head mdios;
357
358 /* Policy Control List IDs and rules */
359 struct idr policies;
360
361 /* There can be two interrupt controllers, which are chained
362 * off a GPIO as interrupt source
363 */
364 struct mv88e6xxx_irq g1_irq;
365 struct mv88e6xxx_irq g2_irq;
366 int irq;
367 char irq_name[64];
368 int device_irq;
369 char device_irq_name[64];
370 int watchdog_irq;
371 char watchdog_irq_name[64];
372
373 int atu_prob_irq;
374 char atu_prob_irq_name[64];
375 int vtu_prob_irq;
376 char vtu_prob_irq_name[64];
377 struct kthread_worker *kworker;
378 struct kthread_delayed_work irq_poll_work;
379
380 /* GPIO resources */
381 u8 gpio_data[2];
382
383 /* This cyclecounter abstracts the switch PTP time.
384 * reg_lock must be held for any operation that read()s.
385 */
386 struct cyclecounter tstamp_cc;
387 struct timecounter tstamp_tc;
388 struct delayed_work overflow_work;
389
390 struct ptp_clock *ptp_clock;
391 struct ptp_clock_info ptp_clock_info;
392 struct delayed_work tai_event_work;
393 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO];
394 u16 trig_config;
395 u16 evcap_config;
396 u16 enable_count;
397
398 /* Current ingress and egress monitor ports */
399 int egress_dest_port;
400 int ingress_dest_port;
401
402 /* Per-port timestamping resources. */
403 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
404
405 /* Array of port structures. */
406 struct mv88e6xxx_port ports[DSA_MAX_PORTS];
407
408 /* devlink regions */
409 struct devlink_region *regions[_MV88E6XXX_REGION_MAX];
410
411 /* Bridge MST to SID mappings */
412 struct list_head msts;
413};
414
415struct mv88e6xxx_bus_ops {
416 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
417 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
418 int (*init)(struct mv88e6xxx_chip *chip);
419};
420
421struct mv88e6xxx_mdio_bus {
422 struct mii_bus *bus;
423 struct mv88e6xxx_chip *chip;
424 struct list_head list;
425 bool external;
426};
427
428struct mv88e6xxx_ops {
429 /* Switch Setup Errata, called early in the switch setup to
430 * allow any errata actions to be performed
431 */
432 int (*setup_errata)(struct mv88e6xxx_chip *chip);
433
434 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip);
435 int (*ip_pri_map)(struct mv88e6xxx_chip *chip);
436
437 /* Ingress Rate Limit unit (IRL) operations */
438 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
439
440 int (*get_eeprom)(struct mv88e6xxx_chip *chip,
441 struct ethtool_eeprom *eeprom, u8 *data);
442 int (*set_eeprom)(struct mv88e6xxx_chip *chip,
443 struct ethtool_eeprom *eeprom, u8 *data);
444
445 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
446
447 int (*phy_read)(struct mv88e6xxx_chip *chip,
448 struct mii_bus *bus,
449 int addr, int reg, u16 *val);
450 int (*phy_write)(struct mv88e6xxx_chip *chip,
451 struct mii_bus *bus,
452 int addr, int reg, u16 val);
453
454 /* Priority Override Table operations */
455 int (*pot_clear)(struct mv88e6xxx_chip *chip);
456
457 /* PHY Polling Unit (PPU) operations */
458 int (*ppu_enable)(struct mv88e6xxx_chip *chip);
459 int (*ppu_disable)(struct mv88e6xxx_chip *chip);
460
461 /* Switch Software Reset */
462 int (*reset)(struct mv88e6xxx_chip *chip);
463
464 /* RGMII Receive/Transmit Timing Control
465 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
466 */
467 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
468 phy_interface_t mode);
469
470#define LINK_FORCED_DOWN 0
471#define LINK_FORCED_UP 1
472#define LINK_UNFORCED -2
473
474 /* Port's MAC link state
475 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
476 * or LINK_UNFORCED for normal link detection.
477 */
478 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
479
480 /* Synchronise the port link state with that of the SERDES
481 */
482 int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);
483
484#define PAUSE_ON 1
485#define PAUSE_OFF 0
486
487 /* Enable/disable sending Pause */
488 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
489 int pause);
490
491#define SPEED_UNFORCED -2
492#define DUPLEX_UNFORCED -2
493
494 /* Port's MAC speed (in Mbps) and MAC duplex mode
495 *
496 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
497 * Use SPEED_UNFORCED for normal detection.
498 *
499 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
500 * or DUPLEX_UNFORCED for normal duplex detection.
501 */
502 int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port,
503 int speed, int duplex);
504
505 /* What interface mode should be used for maximum speed? */
506 phy_interface_t (*port_max_speed_mode)(int port);
507
508 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
509
510 int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port,
511 enum mv88e6xxx_policy_mapping mapping,
512 enum mv88e6xxx_policy_action action);
513
514 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
515 enum mv88e6xxx_frame_mode mode);
516 int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port,
517 bool unicast);
518 int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port,
519 bool multicast);
520 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
521 u16 etype);
522 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
523 size_t size);
524
525 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
526 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
527 u8 out);
528 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
529 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
530 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port);
531
532 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
533 * Some chips allow this to be configured on specific ports.
534 */
535 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
536 phy_interface_t mode);
537 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
538
539 /* Some devices have a per port register indicating what is
540 * the upstream port this port should forward to.
541 */
542 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
543 int upstream_port);
544
545 /* Snapshot the statistics for a port. The statistics can then
546 * be read back a leisure but still with a consistent view.
547 */
548 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
549
550 /* Set the histogram mode for statistics, when the control registers
551 * are separated out of the STATS_OP register.
552 */
553 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
554
555 /* Return the number of strings describing statistics */
556 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
557 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data);
558 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port,
559 uint64_t *data);
560 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
561 int (*set_egress_port)(struct mv88e6xxx_chip *chip,
562 enum mv88e6xxx_egress_direction direction,
563 int port);
564
565#define MV88E6XXX_CASCADE_PORT_NONE 0xe
566#define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf
567
568 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
569
570 const struct mv88e6xxx_irq_ops *watchdog_ops;
571
572 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
573
574 /* Power on/off a SERDES interface */
575 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, int lane,
576 bool up);
577
578 /* SERDES lane mapping */
579 int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port);
580
581 int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port,
582 int lane, struct phylink_link_state *state);
583 int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port,
584 int lane, unsigned int mode,
585 phy_interface_t interface,
586 const unsigned long *advertise);
587 int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port,
588 int lane);
589 int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port,
590 int lane, int speed, int duplex);
591
592 /* SERDES interrupt handling */
593 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip,
594 int port);
595 int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, int lane,
596 bool enable);
597 irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port,
598 int lane);
599
600 /* Statistics from the SERDES interface */
601 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
602 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port,
603 uint8_t *data);
604 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port,
605 uint64_t *data);
606
607 /* SERDES registers for ethtool */
608 int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port);
609 void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port,
610 void *_p);
611
612 /* SERDES SGMII/Fiber Output Amplitude */
613 int (*serdes_set_tx_amplitude)(struct mv88e6xxx_chip *chip, int port,
614 int val);
615
616 /* Address Translation Unit operations */
617 int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash);
618 int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash);
619
620 /* VLAN Translation Unit operations */
621 int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
622 struct mv88e6xxx_vtu_entry *entry);
623 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
624 struct mv88e6xxx_vtu_entry *entry);
625
626 /* Spanning Tree Unit operations */
627 int (*stu_getnext)(struct mv88e6xxx_chip *chip,
628 struct mv88e6xxx_stu_entry *entry);
629 int (*stu_loadpurge)(struct mv88e6xxx_chip *chip,
630 struct mv88e6xxx_stu_entry *entry);
631
632 /* GPIO operations */
633 const struct mv88e6xxx_gpio_ops *gpio_ops;
634
635 /* Interface to the AVB/PTP registers */
636 const struct mv88e6xxx_avb_ops *avb_ops;
637
638 /* Remote Management Unit operations */
639 int (*rmu_disable)(struct mv88e6xxx_chip *chip);
640
641 /* Precision Time Protocol operations */
642 const struct mv88e6xxx_ptp_ops *ptp_ops;
643
644 /* Phylink */
645 void (*phylink_get_caps)(struct mv88e6xxx_chip *chip, int port,
646 struct phylink_config *config);
647
648 /* Max Frame Size */
649 int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu);
650};
651
652struct mv88e6xxx_irq_ops {
653 /* Action to be performed when the interrupt happens */
654 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
655 /* Setup the hardware to generate the interrupt */
656 int (*irq_setup)(struct mv88e6xxx_chip *chip);
657 /* Reset the hardware to stop generating the interrupt */
658 void (*irq_free)(struct mv88e6xxx_chip *chip);
659};
660
661struct mv88e6xxx_gpio_ops {
662 /* Get/set data on GPIO pin */
663 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
664 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
665 int value);
666
667 /* get/set GPIO direction */
668 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
669 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
670 bool input);
671
672 /* get/set GPIO pin control */
673 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
674 int *func);
675 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
676 int func);
677};
678
679struct mv88e6xxx_avb_ops {
680 /* Access port-scoped Precision Time Protocol registers */
681 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
682 u16 *data, int len);
683 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
684 u16 data);
685
686 /* Access global Precision Time Protocol registers */
687 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
688 int len);
689 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
690
691 /* Access global Time Application Interface registers */
692 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
693 int len);
694 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
695};
696
697struct mv88e6xxx_ptp_ops {
698 u64 (*clock_read)(const struct cyclecounter *cc);
699 int (*ptp_enable)(struct ptp_clock_info *ptp,
700 struct ptp_clock_request *rq, int on);
701 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin,
702 enum ptp_pin_function func, unsigned int chan);
703 void (*event_work)(struct work_struct *ugly);
704 int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
705 int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
706 int (*global_enable)(struct mv88e6xxx_chip *chip);
707 int (*global_disable)(struct mv88e6xxx_chip *chip);
708 int n_ext_ts;
709 int arr0_sts_reg;
710 int arr1_sts_reg;
711 int dep_sts_reg;
712 u32 rx_filters;
713 u32 cc_shift;
714 u32 cc_mult;
715 u32 cc_mult_num;
716 u32 cc_mult_dem;
717};
718
719#define STATS_TYPE_PORT BIT(0)
720#define STATS_TYPE_BANK0 BIT(1)
721#define STATS_TYPE_BANK1 BIT(2)
722
723struct mv88e6xxx_hw_stat {
724 char string[ETH_GSTRING_LEN];
725 size_t size;
726 int reg;
727 int type;
728};
729
730static inline bool mv88e6xxx_has_stu(struct mv88e6xxx_chip *chip)
731{
732 return chip->info->max_sid > 0 &&
733 chip->info->ops->stu_loadpurge &&
734 chip->info->ops->stu_getnext;
735}
736
737static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
738{
739 return chip->info->pvt;
740}
741
742static inline bool mv88e6xxx_has_lag(struct mv88e6xxx_chip *chip)
743{
744 return !!chip->info->global2_addr;
745}
746
747static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
748{
749 return chip->info->num_databases;
750}
751
752static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip)
753{
754 return chip->info->num_macs;
755}
756
757static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
758{
759 return chip->info->num_ports;
760}
761
762static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip)
763{
764 return chip->info->max_vid;
765}
766
767static inline unsigned int mv88e6xxx_max_sid(struct mv88e6xxx_chip *chip)
768{
769 return chip->info->max_sid;
770}
771
772static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
773{
774 return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0);
775}
776
777static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
778{
779 return chip->info->num_gpio;
780}
781
782static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port)
783{
784 return (chip->info->invalid_port_mask & BIT(port)) != 0;
785}
786
787int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
788int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
789int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
790 u16 mask, u16 val);
791int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
792 int bit, int val);
793struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
794
795static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip)
796{
797 mutex_lock(&chip->reg_lock);
798}
799
800static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip)
801{
802 mutex_unlock(&chip->reg_lock);
803}
804
805int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap);
806
807#endif /* _MV88E6XXX_CHIP_H */