1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (C) 2009 ST-Ericsson SA
   4 * Copyright (C) 2009 STMicroelectronics
   5 *
   6 * I2C master mode controller driver, used in Nomadik 8815
   7 * and Ux500 platforms.
   8 *
   9 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
  10 * Author: Sachin Verma <sachin.verma@st.com>
  11 */
  12#include <linux/init.h>
  13#include <linux/module.h>
  14#include <linux/amba/bus.h>
  15#include <linux/slab.h>
  16#include <linux/interrupt.h>
  17#include <linux/i2c.h>
  18#include <linux/err.h>
  19#include <linux/clk.h>
  20#include <linux/io.h>
  21#include <linux/pm_runtime.h>
  22#include <linux/of.h>
  23#include <linux/pinctrl/consumer.h>
  24
  25#define DRIVER_NAME "nmk-i2c"
  26
  27/* I2C Controller register offsets */
  28#define I2C_CR		(0x000)
  29#define I2C_SCR		(0x004)
  30#define I2C_HSMCR	(0x008)
  31#define I2C_MCR		(0x00C)
  32#define I2C_TFR		(0x010)
  33#define I2C_SR		(0x014)
  34#define I2C_RFR		(0x018)
  35#define I2C_TFTR	(0x01C)
  36#define I2C_RFTR	(0x020)
  37#define I2C_DMAR	(0x024)
  38#define I2C_BRCR	(0x028)
  39#define I2C_IMSCR	(0x02C)
  40#define I2C_RISR	(0x030)
  41#define I2C_MISR	(0x034)
  42#define I2C_ICR		(0x038)
  43
  44/* Control registers */
  45#define I2C_CR_PE		(0x1 << 0)	/* Peripheral Enable */
  46#define I2C_CR_OM		(0x3 << 1)	/* Operating mode */
  47#define I2C_CR_SAM		(0x1 << 3)	/* Slave addressing mode */
  48#define I2C_CR_SM		(0x3 << 4)	/* Speed mode */
  49#define I2C_CR_SGCM		(0x1 << 6)	/* Slave general call mode */
  50#define I2C_CR_FTX		(0x1 << 7)	/* Flush Transmit */
  51#define I2C_CR_FRX		(0x1 << 8)	/* Flush Receive */
  52#define I2C_CR_DMA_TX_EN	(0x1 << 9)	/* DMA Tx enable */
  53#define I2C_CR_DMA_RX_EN	(0x1 << 10)	/* DMA Rx Enable */
  54#define I2C_CR_DMA_SLE		(0x1 << 11)	/* DMA sync. logic enable */
  55#define I2C_CR_LM		(0x1 << 12)	/* Loopback mode */
  56#define I2C_CR_FON		(0x3 << 13)	/* Filtering on */
  57#define I2C_CR_FS		(0x3 << 15)	/* Force stop enable */
  58
  59/* Master controller (MCR) register */
  60#define I2C_MCR_OP		(0x1 << 0)	/* Operation */
  61#define I2C_MCR_A7		(0x7f << 1)	/* 7-bit address */
  62#define I2C_MCR_EA10		(0x7 << 8)	/* 10-bit Extended address */
  63#define I2C_MCR_SB		(0x1 << 11)	/* Extended address */
  64#define I2C_MCR_AM		(0x3 << 12)	/* Address type */
  65#define I2C_MCR_STOP		(0x1 << 14)	/* Stop condition */
  66#define I2C_MCR_LENGTH		(0x7ff << 15)	/* Transaction length */
  67
  68/* Status register (SR) */
  69#define I2C_SR_OP		(0x3 << 0)	/* Operation */
  70#define I2C_SR_STATUS		(0x3 << 2)	/* controller status */
  71#define I2C_SR_CAUSE		(0x7 << 4)	/* Abort cause */
  72#define I2C_SR_TYPE		(0x3 << 7)	/* Receive type */
  73#define I2C_SR_LENGTH		(0x7ff << 9)	/* Transfer length */
  74
  75/* Interrupt mask set/clear (IMSCR) bits */
  76#define I2C_IT_TXFE		(0x1 << 0)
  77#define I2C_IT_TXFNE		(0x1 << 1)
  78#define I2C_IT_TXFF		(0x1 << 2)
  79#define I2C_IT_TXFOVR		(0x1 << 3)
  80#define I2C_IT_RXFE		(0x1 << 4)
  81#define I2C_IT_RXFNF		(0x1 << 5)
  82#define I2C_IT_RXFF		(0x1 << 6)
  83#define I2C_IT_RFSR		(0x1 << 16)
  84#define I2C_IT_RFSE		(0x1 << 17)
  85#define I2C_IT_WTSR		(0x1 << 18)
  86#define I2C_IT_MTD		(0x1 << 19)
  87#define I2C_IT_STD		(0x1 << 20)
  88#define I2C_IT_MAL		(0x1 << 24)
  89#define I2C_IT_BERR		(0x1 << 25)
  90#define I2C_IT_MTDWS		(0x1 << 28)
  91
  92#define GEN_MASK(val, mask, sb)  (((val) << (sb)) & (mask))
  93
  94/* some bits in ICR are reserved */
  95#define I2C_CLEAR_ALL_INTS	0x131f007f
  96
  97/* first three msb bits are reserved */
  98#define IRQ_MASK(mask)		(mask & 0x1fffffff)
  99
 100/* maximum threshold value */
 101#define MAX_I2C_FIFO_THRESHOLD	15
 102
 103enum i2c_freq_mode {
 104	I2C_FREQ_MODE_STANDARD,		/* up to 100 Kb/s */
 105	I2C_FREQ_MODE_FAST,		/* up to 400 Kb/s */
 106	I2C_FREQ_MODE_HIGH_SPEED,	/* up to 3.4 Mb/s */
 107	I2C_FREQ_MODE_FAST_PLUS,	/* up to 1 Mb/s */
 108};
 109
 110/**
 111 * struct i2c_vendor_data - per-vendor variations
 112 * @has_mtdws: variant has the MTDWS bit
 113 * @fifodepth: variant FIFO depth
 114 */
 115struct i2c_vendor_data {
 116	bool has_mtdws;
 117	u32 fifodepth;
 118};
 119
 120enum i2c_status {
 121	I2C_NOP,
 122	I2C_ON_GOING,
 123	I2C_OK,
 124	I2C_ABORT
 125};
 126
 127/* operation */
 128enum i2c_operation {
 129	I2C_NO_OPERATION = 0xff,
 130	I2C_WRITE = 0x00,
 131	I2C_READ = 0x01
 132};
 133
 134/**
 135 * struct i2c_nmk_client - client specific data
 136 * @slave_adr: 7-bit slave address
 137 * @count: no. bytes to be transferred
 138 * @buffer: client data buffer
 139 * @xfer_bytes: bytes transferred till now
 140 * @operation: current I2C operation
 141 */
 142struct i2c_nmk_client {
 143	unsigned short		slave_adr;
 144	unsigned long		count;
 145	unsigned char		*buffer;
 146	unsigned long		xfer_bytes;
 147	enum i2c_operation	operation;
 148};
 149
 150/**
 151 * struct nmk_i2c_dev - private data structure of the controller.
 152 * @vendor: vendor data for this variant.
 153 * @adev: parent amba device.
 154 * @adap: corresponding I2C adapter.
 155 * @irq: interrupt line for the controller.
 156 * @virtbase: virtual io memory area.
 157 * @clk: hardware i2c block clock.
 158 * @cli: holder of client specific data.
 159 * @clk_freq: clock frequency for the operation mode
 160 * @tft: Tx FIFO Threshold in bytes
 161 * @rft: Rx FIFO Threshold in bytes
 162 * @timeout: Slave response timeout (ms)
 163 * @sm: speed mode
 164 * @stop: stop condition.
 165 * @xfer_complete: acknowledge completion for a I2C message.
 166 * @result: controller propogated result.
 167 */
 168struct nmk_i2c_dev {
 169	struct i2c_vendor_data		*vendor;
 170	struct amba_device		*adev;
 171	struct i2c_adapter		adap;
 172	int				irq;
 173	void __iomem			*virtbase;
 174	struct clk			*clk;
 175	struct i2c_nmk_client		cli;
 176	u32				clk_freq;
 177	unsigned char			tft;
 178	unsigned char			rft;
 179	int				timeout;
 180	enum i2c_freq_mode		sm;
 181	int				stop;
 182	struct completion		xfer_complete;
 183	int				result;
 184};
 185
 186/* controller's abort causes */
 187static const char *abort_causes[] = {
 188	"no ack received after address transmission",
 189	"no ack received during data phase",
 190	"ack received after xmission of master code",
 191	"master lost arbitration",
 192	"slave restarts",
 193	"slave reset",
 194	"overflow, maxsize is 2047 bytes",
 195};
 196
 197static inline void i2c_set_bit(void __iomem *reg, u32 mask)
 198{
 199	writel(readl(reg) | mask, reg);
 200}
 201
 202static inline void i2c_clr_bit(void __iomem *reg, u32 mask)
 203{
 204	writel(readl(reg) & ~mask, reg);
 205}
 206
 207/**
 208 * flush_i2c_fifo() - This function flushes the I2C FIFO
 209 * @dev: private data of I2C Driver
 210 *
 211 * This function flushes the I2C Tx and Rx FIFOs. It returns
 212 * 0 on successful flushing of FIFO
 213 */
 214static int flush_i2c_fifo(struct nmk_i2c_dev *dev)
 215{
 216#define LOOP_ATTEMPTS 10
 217	int i;
 218	unsigned long timeout;
 219
 220	/*
 221	 * flush the transmit and receive FIFO. The flushing
 222	 * operation takes several cycles before to be completed.
 223	 * On the completion, the I2C internal logic clears these
 224	 * bits, until then no one must access Tx, Rx FIFO and
 225	 * should poll on these bits waiting for the completion.
 226	 */
 227	writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR);
 228
 229	for (i = 0; i < LOOP_ATTEMPTS; i++) {
 230		timeout = jiffies + dev->adap.timeout;
 231
 232		while (!time_after(jiffies, timeout)) {
 233			if ((readl(dev->virtbase + I2C_CR) &
 234				(I2C_CR_FTX | I2C_CR_FRX)) == 0)
 235					return 0;
 236		}
 237	}
 238
 239	dev_err(&dev->adev->dev,
 240		"flushing operation timed out giving up after %d attempts",
 241		LOOP_ATTEMPTS);
 242
 243	return -ETIMEDOUT;
 244}
 245
 246/**
 247 * disable_all_interrupts() - Disable all interrupts of this I2c Bus
 248 * @dev: private data of I2C Driver
 249 */
 250static void disable_all_interrupts(struct nmk_i2c_dev *dev)
 251{
 252	u32 mask = IRQ_MASK(0);
 253	writel(mask, dev->virtbase + I2C_IMSCR);
 254}
 255
 256/**
 257 * clear_all_interrupts() - Clear all interrupts of I2C Controller
 258 * @dev: private data of I2C Driver
 259 */
 260static void clear_all_interrupts(struct nmk_i2c_dev *dev)
 261{
 262	u32 mask;
 263	mask = IRQ_MASK(I2C_CLEAR_ALL_INTS);
 264	writel(mask, dev->virtbase + I2C_ICR);
 265}
 266
 267/**
 268 * init_hw() - initialize the I2C hardware
 269 * @dev: private data of I2C Driver
 270 */
 271static int init_hw(struct nmk_i2c_dev *dev)
 272{
 273	int stat;
 274
 275	stat = flush_i2c_fifo(dev);
 276	if (stat)
 277		goto exit;
 278
 279	/* disable the controller */
 280	i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
 281
 282	disable_all_interrupts(dev);
 283
 284	clear_all_interrupts(dev);
 285
 286	dev->cli.operation = I2C_NO_OPERATION;
 287
 288exit:
 289	return stat;
 290}
 291
 292/* enable peripheral, master mode operation */
 293#define DEFAULT_I2C_REG_CR	((1 << 1) | I2C_CR_PE)
 294
 295/**
 296 * load_i2c_mcr_reg() - load the MCR register
 297 * @dev: private data of controller
 298 * @flags: message flags
 299 */
 300static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags)
 301{
 302	u32 mcr = 0;
 303	unsigned short slave_adr_3msb_bits;
 304
 305	mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1);
 306
 307	if (unlikely(flags & I2C_M_TEN)) {
 308		/* 10-bit address transaction */
 309		mcr |= GEN_MASK(2, I2C_MCR_AM, 12);
 310		/*
 311		 * Get the top 3 bits.
 312		 * EA10 represents extended address in MCR. This includes
 313		 * the extension (MSB bits) of the 7 bit address loaded
 314		 * in A7
 315		 */
 316		slave_adr_3msb_bits = (dev->cli.slave_adr >> 7) & 0x7;
 317
 318		mcr |= GEN_MASK(slave_adr_3msb_bits, I2C_MCR_EA10, 8);
 319	} else {
 320		/* 7-bit address transaction */
 321		mcr |= GEN_MASK(1, I2C_MCR_AM, 12);
 322	}
 323
 324	/* start byte procedure not applied */
 325	mcr |= GEN_MASK(0, I2C_MCR_SB, 11);
 326
 327	/* check the operation, master read/write? */
 328	if (dev->cli.operation == I2C_WRITE)
 329		mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0);
 330	else
 331		mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0);
 332
 333	/* stop or repeated start? */
 334	if (dev->stop)
 335		mcr |= GEN_MASK(1, I2C_MCR_STOP, 14);
 336	else
 337		mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14));
 338
 339	mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15);
 340
 341	return mcr;
 342}
 343
 344/**
 345 * setup_i2c_controller() - setup the controller
 346 * @dev: private data of controller
 347 */
 348static void setup_i2c_controller(struct nmk_i2c_dev *dev)
 349{
 350	u32 brcr1, brcr2;
 351	u32 i2c_clk, div;
 352	u32 ns;
 353	u16 slsu;
 354
 355	writel(0x0, dev->virtbase + I2C_CR);
 356	writel(0x0, dev->virtbase + I2C_HSMCR);
 357	writel(0x0, dev->virtbase + I2C_TFTR);
 358	writel(0x0, dev->virtbase + I2C_RFTR);
 359	writel(0x0, dev->virtbase + I2C_DMAR);
 360
 361	i2c_clk = clk_get_rate(dev->clk);
 362
 363	/*
 364	 * set the slsu:
 365	 *
 366	 * slsu defines the data setup time after SCL clock
 367	 * stretching in terms of i2c clk cycles + 1 (zero means
 368	 * "wait one cycle"), the needed setup time for the three
 369	 * modes are 250ns, 100ns, 10ns respectively.
 370	 *
 371	 * As the time for one cycle T in nanoseconds is
 372	 * T = (1/f) * 1000000000 =>
 373	 * slsu = cycles / (1000000000 / f) + 1
 374	 */
 375	ns = DIV_ROUND_UP_ULL(1000000000ULL, i2c_clk);
 376	switch (dev->sm) {
 377	case I2C_FREQ_MODE_FAST:
 378	case I2C_FREQ_MODE_FAST_PLUS:
 379		slsu = DIV_ROUND_UP(100, ns); /* Fast */
 380		break;
 381	case I2C_FREQ_MODE_HIGH_SPEED:
 382		slsu = DIV_ROUND_UP(10, ns); /* High */
 383		break;
 384	case I2C_FREQ_MODE_STANDARD:
 385	default:
 386		slsu = DIV_ROUND_UP(250, ns); /* Standard */
 387		break;
 388	}
 389	slsu += 1;
 390
 391	dev_dbg(&dev->adev->dev, "calculated SLSU = %04x\n", slsu);
 392	writel(slsu << 16, dev->virtbase + I2C_SCR);
 393
 394	/*
 395	 * The spec says, in case of std. mode the divider is
 396	 * 2 whereas it is 3 for fast and fastplus mode of
 397	 * operation. TODO - high speed support.
 398	 */
 399	div = (dev->clk_freq > I2C_MAX_STANDARD_MODE_FREQ) ? 3 : 2;
 400
 401	/*
 402	 * generate the mask for baud rate counters. The controller
 403	 * has two baud rate counters. One is used for High speed
 404	 * operation, and the other is for std, fast mode, fast mode
 405	 * plus operation. Currently we do not supprt high speed mode
 406	 * so set brcr1 to 0.
 407	 */
 408	brcr1 = 0 << 16;
 409	brcr2 = (i2c_clk/(dev->clk_freq * div)) & 0xffff;
 410
 411	/* set the baud rate counter register */
 412	writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
 413
 414	/*
 415	 * set the speed mode. Currently we support
 416	 * only standard and fast mode of operation
 417	 * TODO - support for fast mode plus (up to 1Mb/s)
 418	 * and high speed (up to 3.4 Mb/s)
 419	 */
 420	if (dev->sm > I2C_FREQ_MODE_FAST) {
 421		dev_err(&dev->adev->dev,
 422			"do not support this mode defaulting to std. mode\n");
 423		brcr2 = i2c_clk / (I2C_MAX_STANDARD_MODE_FREQ * 2) & 0xffff;
 424		writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
 425		writel(I2C_FREQ_MODE_STANDARD << 4,
 426				dev->virtbase + I2C_CR);
 427	}
 428	writel(dev->sm << 4, dev->virtbase + I2C_CR);
 429
 430	/* set the Tx and Rx FIFO threshold */
 431	writel(dev->tft, dev->virtbase + I2C_TFTR);
 432	writel(dev->rft, dev->virtbase + I2C_RFTR);
 433}
 434
 435/**
 436 * read_i2c() - Read from I2C client device
 437 * @dev: private data of I2C Driver
 438 * @flags: message flags
 439 *
 440 * This function reads from i2c client device when controller is in
 441 * master mode. There is a completion timeout. If there is no transfer
 442 * before timeout error is returned.
 443 */
 444static int read_i2c(struct nmk_i2c_dev *dev, u16 flags)
 445{
 446	int status = 0;
 447	u32 mcr, irq_mask;
 448	unsigned long timeout;
 449
 450	mcr = load_i2c_mcr_reg(dev, flags);
 451	writel(mcr, dev->virtbase + I2C_MCR);
 452
 453	/* load the current CR value */
 454	writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
 455			dev->virtbase + I2C_CR);
 456
 457	/* enable the controller */
 458	i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
 459
 460	init_completion(&dev->xfer_complete);
 461
 462	/* enable interrupts by setting the mask */
 463	irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |
 464			I2C_IT_MAL | I2C_IT_BERR);
 465
 466	if (dev->stop || !dev->vendor->has_mtdws)
 467		irq_mask |= I2C_IT_MTD;
 468	else
 469		irq_mask |= I2C_IT_MTDWS;
 470
 471	irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
 472
 473	writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
 474			dev->virtbase + I2C_IMSCR);
 475
 476	timeout = wait_for_completion_timeout(
 477		&dev->xfer_complete, dev->adap.timeout);
 478
 479	if (timeout == 0) {
 480		/* Controller timed out */
 481		dev_err(&dev->adev->dev, "read from slave 0x%x timed out\n",
 482				dev->cli.slave_adr);
 483		status = -ETIMEDOUT;
 484	}
 485	return status;
 486}
 487
 488static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes)
 489{
 490	int count;
 491
 492	for (count = (no_bytes - 2);
 493			(count > 0) &&
 494			(dev->cli.count != 0);
 495			count--) {
 496		/* write to the Tx FIFO */
 497		writeb(*dev->cli.buffer,
 498			dev->virtbase + I2C_TFR);
 499		dev->cli.buffer++;
 500		dev->cli.count--;
 501		dev->cli.xfer_bytes++;
 502	}
 503
 504}
 505
 506/**
 507 * write_i2c() - Write data to I2C client.
 508 * @dev: private data of I2C Driver
 509 * @flags: message flags
 510 *
 511 * This function writes data to I2C client
 512 */
 513static int write_i2c(struct nmk_i2c_dev *dev, u16 flags)
 514{
 515	u32 status = 0;
 516	u32 mcr, irq_mask;
 517	unsigned long timeout;
 518
 519	mcr = load_i2c_mcr_reg(dev, flags);
 520
 521	writel(mcr, dev->virtbase + I2C_MCR);
 522
 523	/* load the current CR value */
 524	writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
 525			dev->virtbase + I2C_CR);
 526
 527	/* enable the controller */
 528	i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
 529
 530	init_completion(&dev->xfer_complete);
 531
 532	/* enable interrupts by settings the masks */
 533	irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR);
 534
 535	/* Fill the TX FIFO with transmit data */
 536	fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD);
 537
 538	if (dev->cli.count != 0)
 539		irq_mask |= I2C_IT_TXFNE;
 540
 541	/*
 542	 * check if we want to transfer a single or multiple bytes, if so
 543	 * set the MTDWS bit (Master Transaction Done Without Stop)
 544	 * to start repeated start operation
 545	 */
 546	if (dev->stop || !dev->vendor->has_mtdws)
 547		irq_mask |= I2C_IT_MTD;
 548	else
 549		irq_mask |= I2C_IT_MTDWS;
 550
 551	irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
 552
 553	writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
 554			dev->virtbase + I2C_IMSCR);
 555
 556	timeout = wait_for_completion_timeout(
 557		&dev->xfer_complete, dev->adap.timeout);
 558
 559	if (timeout == 0) {
 560		/* Controller timed out */
 561		dev_err(&dev->adev->dev, "write to slave 0x%x timed out\n",
 562				dev->cli.slave_adr);
 563		status = -ETIMEDOUT;
 564	}
 565
 566	return status;
 567}
 568
 569/**
 570 * nmk_i2c_xfer_one() - transmit a single I2C message
 571 * @dev: device with a message encoded into it
 572 * @flags: message flags
 573 */
 574static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags)
 575{
 576	int status;
 577
 578	if (flags & I2C_M_RD) {
 579		/* read operation */
 580		dev->cli.operation = I2C_READ;
 581		status = read_i2c(dev, flags);
 582	} else {
 583		/* write operation */
 584		dev->cli.operation = I2C_WRITE;
 585		status = write_i2c(dev, flags);
 586	}
 587
 588	if (status || (dev->result)) {
 589		u32 i2c_sr;
 590		u32 cause;
 591
 592		i2c_sr = readl(dev->virtbase + I2C_SR);
 593		/*
 594		 * Check if the controller I2C operation status
 595		 * is set to ABORT(11b).
 596		 */
 597		if (((i2c_sr >> 2) & 0x3) == 0x3) {
 598			/* get the abort cause */
 599			cause =	(i2c_sr >> 4) & 0x7;
 600			dev_err(&dev->adev->dev, "%s\n",
 601				cause >= ARRAY_SIZE(abort_causes) ?
 602				"unknown reason" :
 603				abort_causes[cause]);
 604		}
 605
 606		(void) init_hw(dev);
 607
 608		status = status ? status : dev->result;
 609	}
 610
 611	return status;
 612}
 613
 614/**
 615 * nmk_i2c_xfer() - I2C transfer function used by kernel framework
 616 * @i2c_adap: Adapter pointer to the controller
 617 * @msgs: Pointer to data to be written.
 618 * @num_msgs: Number of messages to be executed
 619 *
 620 * This is the function called by the generic kernel i2c_transfer()
 621 * or i2c_smbus...() API calls. Note that this code is protected by the
 622 * semaphore set in the kernel i2c_transfer() function.
 623 *
 624 * NOTE:
 625 * READ TRANSFER : We impose a restriction of the first message to be the
 626 *		index message for any read transaction.
 627 *		- a no index is coded as '0',
 628 *		- 2byte big endian index is coded as '3'
 629 *		!!! msg[0].buf holds the actual index.
 630 *		This is compatible with generic messages of smbus emulator
 631 *		that send a one byte index.
 632 *		eg. a I2C transation to read 2 bytes from index 0
 633 *			idx = 0;
 634 *			msg[0].addr = client->addr;
 635 *			msg[0].flags = 0x0;
 636 *			msg[0].len = 1;
 637 *			msg[0].buf = &idx;
 638 *
 639 *			msg[1].addr = client->addr;
 640 *			msg[1].flags = I2C_M_RD;
 641 *			msg[1].len = 2;
 642 *			msg[1].buf = rd_buff
 643 *			i2c_transfer(adap, msg, 2);
 644 *
 645 * WRITE TRANSFER : The I2C standard interface interprets all data as payload.
 646 *		If you want to emulate an SMBUS write transaction put the
 647 *		index as first byte(or first and second) in the payload.
 648 *		eg. a I2C transation to write 2 bytes from index 1
 649 *			wr_buff[0] = 0x1;
 650 *			wr_buff[1] = 0x23;
 651 *			wr_buff[2] = 0x46;
 652 *			msg[0].flags = 0x0;
 653 *			msg[0].len = 3;
 654 *			msg[0].buf = wr_buff;
 655 *			i2c_transfer(adap, msg, 1);
 656 *
 657 * To read or write a block of data (multiple bytes) using SMBUS emulation
 658 * please use the i2c_smbus_read_i2c_block_data()
 659 * or i2c_smbus_write_i2c_block_data() API
 660 */
 661static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
 662		struct i2c_msg msgs[], int num_msgs)
 663{
 664	int status = 0;
 665	int i;
 666	struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap);
 667	int j;
 668
 669	pm_runtime_get_sync(&dev->adev->dev);
 670
 671	/* Attempt three times to send the message queue */
 672	for (j = 0; j < 3; j++) {
 673		/* setup the i2c controller */
 674		setup_i2c_controller(dev);
 675
 676		for (i = 0; i < num_msgs; i++) {
 677			dev->cli.slave_adr	= msgs[i].addr;
 678			dev->cli.buffer		= msgs[i].buf;
 679			dev->cli.count		= msgs[i].len;
 680			dev->stop = (i < (num_msgs - 1)) ? 0 : 1;
 681			dev->result = 0;
 682
 683			status = nmk_i2c_xfer_one(dev, msgs[i].flags);
 684			if (status != 0)
 685				break;
 686		}
 687		if (status == 0)
 688			break;
 689	}
 690
 691	pm_runtime_put_sync(&dev->adev->dev);
 692
 693	/* return the no. messages processed */
 694	if (status)
 695		return status;
 696	else
 697		return num_msgs;
 698}
 699
 700/**
 701 * disable_interrupts() - disable the interrupts
 702 * @dev: private data of controller
 703 * @irq: interrupt number
 704 */
 705static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq)
 706{
 707	irq = IRQ_MASK(irq);
 708	writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq),
 709			dev->virtbase + I2C_IMSCR);
 710	return 0;
 711}
 712
 713/**
 714 * i2c_irq_handler() - interrupt routine
 715 * @irq: interrupt number
 716 * @arg: data passed to the handler
 717 *
 718 * This is the interrupt handler for the i2c driver. Currently
 719 * it handles the major interrupts like Rx & Tx FIFO management
 720 * interrupts, master transaction interrupts, arbitration and
 721 * bus error interrupts. The rest of the interrupts are treated as
 722 * unhandled.
 723 */
 724static irqreturn_t i2c_irq_handler(int irq, void *arg)
 725{
 726	struct nmk_i2c_dev *dev = arg;
 727	u32 tft, rft;
 728	u32 count;
 729	u32 misr, src;
 730
 731	/* load Tx FIFO and Rx FIFO threshold values */
 732	tft = readl(dev->virtbase + I2C_TFTR);
 733	rft = readl(dev->virtbase + I2C_RFTR);
 734
 735	/* read interrupt status register */
 736	misr = readl(dev->virtbase + I2C_MISR);
 737
 738	src = __ffs(misr);
 739	switch ((1 << src)) {
 740
 741	/* Transmit FIFO nearly empty interrupt */
 742	case I2C_IT_TXFNE:
 743	{
 744		if (dev->cli.operation == I2C_READ) {
 745			/*
 746			 * in read operation why do we care for writing?
 747			 * so disable the Transmit FIFO interrupt
 748			 */
 749			disable_interrupts(dev, I2C_IT_TXFNE);
 750		} else {
 751			fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft));
 752			/*
 753			 * if done, close the transfer by disabling the
 754			 * corresponding TXFNE interrupt
 755			 */
 756			if (dev->cli.count == 0)
 757				disable_interrupts(dev,	I2C_IT_TXFNE);
 758		}
 759	}
 760	break;
 761
 762	/*
 763	 * Rx FIFO nearly full interrupt.
 764	 * This is set when the numer of entries in Rx FIFO is
 765	 * greater or equal than the threshold value programmed
 766	 * in RFT
 767	 */
 768	case I2C_IT_RXFNF:
 769		for (count = rft; count > 0; count--) {
 770			/* Read the Rx FIFO */
 771			*dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
 772			dev->cli.buffer++;
 773		}
 774		dev->cli.count -= rft;
 775		dev->cli.xfer_bytes += rft;
 776		break;
 777
 778	/* Rx FIFO full */
 779	case I2C_IT_RXFF:
 780		for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) {
 781			*dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
 782			dev->cli.buffer++;
 783		}
 784		dev->cli.count -= MAX_I2C_FIFO_THRESHOLD;
 785		dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;
 786		break;
 787
 788	/* Master Transaction Done with/without stop */
 789	case I2C_IT_MTD:
 790	case I2C_IT_MTDWS:
 791		if (dev->cli.operation == I2C_READ) {
 792			while (!(readl(dev->virtbase + I2C_RISR)
 793				 & I2C_IT_RXFE)) {
 794				if (dev->cli.count == 0)
 795					break;
 796				*dev->cli.buffer =
 797					readb(dev->virtbase + I2C_RFR);
 798				dev->cli.buffer++;
 799				dev->cli.count--;
 800				dev->cli.xfer_bytes++;
 801			}
 802		}
 803
 804		disable_all_interrupts(dev);
 805		clear_all_interrupts(dev);
 806
 807		if (dev->cli.count) {
 808			dev->result = -EIO;
 809			dev_err(&dev->adev->dev,
 810				"%lu bytes still remain to be xfered\n",
 811				dev->cli.count);
 812			(void) init_hw(dev);
 813		}
 814		complete(&dev->xfer_complete);
 815
 816		break;
 817
 818	/* Master Arbitration lost interrupt */
 819	case I2C_IT_MAL:
 820		dev->result = -EIO;
 821		(void) init_hw(dev);
 822
 823		i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL);
 824		complete(&dev->xfer_complete);
 825
 826		break;
 827
 828	/*
 829	 * Bus Error interrupt.
 830	 * This happens when an unexpected start/stop condition occurs
 831	 * during the transaction.
 832	 */
 833	case I2C_IT_BERR:
 834		dev->result = -EIO;
 835		/* get the status */
 836		if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT)
 837			(void) init_hw(dev);
 838
 839		i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR);
 840		complete(&dev->xfer_complete);
 841
 842		break;
 843
 844	/*
 845	 * Tx FIFO overrun interrupt.
 846	 * This is set when a write operation in Tx FIFO is performed and
 847	 * the Tx FIFO is full.
 848	 */
 849	case I2C_IT_TXFOVR:
 850		dev->result = -EIO;
 851		(void) init_hw(dev);
 852
 853		dev_err(&dev->adev->dev, "Tx Fifo Over run\n");
 854		complete(&dev->xfer_complete);
 855
 856		break;
 857
 858	/* unhandled interrupts by this driver - TODO*/
 859	case I2C_IT_TXFE:
 860	case I2C_IT_TXFF:
 861	case I2C_IT_RXFE:
 862	case I2C_IT_RFSR:
 863	case I2C_IT_RFSE:
 864	case I2C_IT_WTSR:
 865	case I2C_IT_STD:
 866		dev_err(&dev->adev->dev, "unhandled Interrupt\n");
 867		break;
 868	default:
 869		dev_err(&dev->adev->dev, "spurious Interrupt..\n");
 870		break;
 871	}
 872
 873	return IRQ_HANDLED;
 874}
 875
 
 876static int nmk_i2c_suspend_late(struct device *dev)
 877{
 878	int ret;
 879
 880	ret = pm_runtime_force_suspend(dev);
 881	if (ret)
 882		return ret;
 883
 884	pinctrl_pm_select_sleep_state(dev);
 885	return 0;
 886}
 887
 888static int nmk_i2c_resume_early(struct device *dev)
 889{
 890	return pm_runtime_force_resume(dev);
 891}
 
 892
 
 893static int nmk_i2c_runtime_suspend(struct device *dev)
 894{
 895	struct amba_device *adev = to_amba_device(dev);
 896	struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev);
 897
 898	clk_disable_unprepare(nmk_i2c->clk);
 899	pinctrl_pm_select_idle_state(dev);
 900	return 0;
 901}
 902
 903static int nmk_i2c_runtime_resume(struct device *dev)
 904{
 905	struct amba_device *adev = to_amba_device(dev);
 906	struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev);
 907	int ret;
 908
 909	ret = clk_prepare_enable(nmk_i2c->clk);
 910	if (ret) {
 911		dev_err(dev, "can't prepare_enable clock\n");
 912		return ret;
 913	}
 914
 915	pinctrl_pm_select_default_state(dev);
 916
 917	ret = init_hw(nmk_i2c);
 918	if (ret) {
 919		clk_disable_unprepare(nmk_i2c->clk);
 920		pinctrl_pm_select_idle_state(dev);
 921	}
 922
 923	return ret;
 924}
 
 925
 926static const struct dev_pm_ops nmk_i2c_pm = {
 927	LATE_SYSTEM_SLEEP_PM_OPS(nmk_i2c_suspend_late, nmk_i2c_resume_early)
 928	RUNTIME_PM_OPS(nmk_i2c_runtime_suspend, nmk_i2c_runtime_resume, NULL)
 
 
 929};
 930
 931static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap)
 932{
 933	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
 934}
 935
 936static const struct i2c_algorithm nmk_i2c_algo = {
 937	.master_xfer	= nmk_i2c_xfer,
 938	.functionality	= nmk_i2c_functionality
 939};
 940
 941static void nmk_i2c_of_probe(struct device_node *np,
 942			     struct nmk_i2c_dev *nmk)
 943{
 944	/* Default to 100 kHz if no frequency is given in the node */
 945	if (of_property_read_u32(np, "clock-frequency", &nmk->clk_freq))
 946		nmk->clk_freq = I2C_MAX_STANDARD_MODE_FREQ;
 947
 948	/* This driver only supports 'standard' and 'fast' modes of operation. */
 949	if (nmk->clk_freq <= I2C_MAX_STANDARD_MODE_FREQ)
 950		nmk->sm = I2C_FREQ_MODE_STANDARD;
 951	else
 952		nmk->sm = I2C_FREQ_MODE_FAST;
 953	nmk->tft = 1; /* Tx FIFO threshold */
 954	nmk->rft = 8; /* Rx FIFO threshold */
 955	nmk->timeout = 200; /* Slave response timeout(ms) */
 956}
 957
 958static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
 959{
 960	int ret = 0;
 961	struct device_node *np = adev->dev.of_node;
 962	struct nmk_i2c_dev	*dev;
 963	struct i2c_adapter *adap;
 964	struct i2c_vendor_data *vendor = id->data;
 965	u32 max_fifo_threshold = (vendor->fifodepth / 2) - 1;
 966
 967	dev = devm_kzalloc(&adev->dev, sizeof(*dev), GFP_KERNEL);
 968	if (!dev)
 969		return -ENOMEM;
 970
 
 
 971	dev->vendor = vendor;
 972	dev->adev = adev;
 973	nmk_i2c_of_probe(np, dev);
 974
 975	if (dev->tft > max_fifo_threshold) {
 976		dev_warn(&adev->dev, "requested TX FIFO threshold %u, adjusted down to %u\n",
 977			 dev->tft, max_fifo_threshold);
 978		dev->tft = max_fifo_threshold;
 979	}
 980
 981	if (dev->rft > max_fifo_threshold) {
 982		dev_warn(&adev->dev, "requested RX FIFO threshold %u, adjusted down to %u\n",
 983			dev->rft, max_fifo_threshold);
 984		dev->rft = max_fifo_threshold;
 985	}
 986
 987	amba_set_drvdata(adev, dev);
 988
 989	dev->virtbase = devm_ioremap(&adev->dev, adev->res.start,
 990				resource_size(&adev->res));
 991	if (!dev->virtbase)
 992		return -ENOMEM;
 
 
 993
 994	dev->irq = adev->irq[0];
 995	ret = devm_request_irq(&adev->dev, dev->irq, i2c_irq_handler, 0,
 996				DRIVER_NAME, dev);
 997	if (ret)
 998		return dev_err_probe(&adev->dev, ret,
 999				     "cannot claim the irq %d\n", dev->irq);
 
 
 
 
 
 
 
 
1000
1001	dev->clk = devm_clk_get_enabled(&adev->dev, NULL);
1002	if (IS_ERR(dev->clk))
1003		return dev_err_probe(&adev->dev, PTR_ERR(dev->clk),
1004				     "could enable i2c clock\n");
 
1005
1006	init_hw(dev);
1007
1008	adap = &dev->adap;
1009	adap->dev.of_node = np;
1010	adap->dev.parent = &adev->dev;
1011	adap->owner = THIS_MODULE;
1012	adap->class = I2C_CLASS_DEPRECATED;
1013	adap->algo = &nmk_i2c_algo;
1014	adap->timeout = msecs_to_jiffies(dev->timeout);
1015	snprintf(adap->name, sizeof(adap->name),
1016		 "Nomadik I2C at %pR", &adev->res);
1017
1018	i2c_set_adapdata(adap, dev);
1019
1020	dev_info(&adev->dev,
1021		 "initialize %s on virtual base %p\n",
1022		 adap->name, dev->virtbase);
1023
1024	ret = i2c_add_adapter(adap);
1025	if (ret)
1026		return ret;
1027
1028	pm_runtime_put(&adev->dev);
1029
1030	return 0;
 
 
 
 
 
 
1031}
1032
1033static void nmk_i2c_remove(struct amba_device *adev)
1034{
 
1035	struct nmk_i2c_dev *dev = amba_get_drvdata(adev);
1036
1037	i2c_del_adapter(&dev->adap);
1038	flush_i2c_fifo(dev);
1039	disable_all_interrupts(dev);
1040	clear_all_interrupts(dev);
1041	/* disable the controller */
1042	i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
 
 
1043}
1044
1045static struct i2c_vendor_data vendor_stn8815 = {
1046	.has_mtdws = false,
1047	.fifodepth = 16, /* Guessed from TFTR/RFTR = 7 */
1048};
1049
1050static struct i2c_vendor_data vendor_db8500 = {
1051	.has_mtdws = true,
1052	.fifodepth = 32, /* Guessed from TFTR/RFTR = 15 */
1053};
1054
1055static const struct amba_id nmk_i2c_ids[] = {
1056	{
1057		.id	= 0x00180024,
1058		.mask	= 0x00ffffff,
1059		.data	= &vendor_stn8815,
1060	},
1061	{
1062		.id	= 0x00380024,
1063		.mask	= 0x00ffffff,
1064		.data	= &vendor_db8500,
1065	},
1066	{},
1067};
1068
1069MODULE_DEVICE_TABLE(amba, nmk_i2c_ids);
1070
1071static struct amba_driver nmk_i2c_driver = {
1072	.drv = {
1073		.owner = THIS_MODULE,
1074		.name = DRIVER_NAME,
1075		.pm = pm_ptr(&nmk_i2c_pm),
1076	},
1077	.id_table = nmk_i2c_ids,
1078	.probe = nmk_i2c_probe,
1079	.remove = nmk_i2c_remove,
1080};
1081
1082static int __init nmk_i2c_init(void)
1083{
1084	return amba_driver_register(&nmk_i2c_driver);
1085}
1086
1087static void __exit nmk_i2c_exit(void)
1088{
1089	amba_driver_unregister(&nmk_i2c_driver);
1090}
1091
1092subsys_initcall(nmk_i2c_init);
1093module_exit(nmk_i2c_exit);
1094
1095MODULE_AUTHOR("Sachin Verma");
1096MODULE_AUTHOR("Srinidhi KASAGAR");
1097MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver");
1098MODULE_LICENSE("GPL");