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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2022 Marek Vasut <marex@denx.de>
4 */
5
6#include <linux/clk.h>
7#include <linux/media-bus-format.h>
8#include <linux/mfd/syscon.h>
9#include <linux/module.h>
10#include <linux/of.h>
11#include <linux/of_graph.h>
12#include <linux/platform_device.h>
13#include <linux/regmap.h>
14
15#include <drm/drm_atomic_helper.h>
16#include <drm/drm_bridge.h>
17#include <drm/drm_of.h>
18#include <drm/drm_panel.h>
19
20#define LDB_CTRL_CH0_ENABLE BIT(0)
21#define LDB_CTRL_CH0_DI_SELECT BIT(1)
22#define LDB_CTRL_CH1_ENABLE BIT(2)
23#define LDB_CTRL_CH1_DI_SELECT BIT(3)
24#define LDB_CTRL_SPLIT_MODE BIT(4)
25#define LDB_CTRL_CH0_DATA_WIDTH BIT(5)
26#define LDB_CTRL_CH0_BIT_MAPPING BIT(6)
27#define LDB_CTRL_CH1_DATA_WIDTH BIT(7)
28#define LDB_CTRL_CH1_BIT_MAPPING BIT(8)
29#define LDB_CTRL_DI0_VSYNC_POLARITY BIT(9)
30#define LDB_CTRL_DI1_VSYNC_POLARITY BIT(10)
31#define LDB_CTRL_REG_CH0_FIFO_RESET BIT(11)
32#define LDB_CTRL_REG_CH1_FIFO_RESET BIT(12)
33#define LDB_CTRL_ASYNC_FIFO_ENABLE BIT(24)
34#define LDB_CTRL_ASYNC_FIFO_THRESHOLD_MASK GENMASK(27, 25)
35
36#define LVDS_CTRL_CH0_EN BIT(0)
37#define LVDS_CTRL_CH1_EN BIT(1)
38/*
39 * LVDS_CTRL_LVDS_EN bit is poorly named in i.MX93 reference manual.
40 * Clear it to enable LVDS and set it to disable LVDS.
41 */
42#define LVDS_CTRL_LVDS_EN BIT(1)
43#define LVDS_CTRL_VBG_EN BIT(2)
44#define LVDS_CTRL_HS_EN BIT(3)
45#define LVDS_CTRL_PRE_EMPH_EN BIT(4)
46#define LVDS_CTRL_PRE_EMPH_ADJ(n) (((n) & 0x7) << 5)
47#define LVDS_CTRL_PRE_EMPH_ADJ_MASK GENMASK(7, 5)
48#define LVDS_CTRL_CM_ADJ(n) (((n) & 0x7) << 8)
49#define LVDS_CTRL_CM_ADJ_MASK GENMASK(10, 8)
50#define LVDS_CTRL_CC_ADJ(n) (((n) & 0x7) << 11)
51#define LVDS_CTRL_CC_ADJ_MASK GENMASK(13, 11)
52#define LVDS_CTRL_SLEW_ADJ(n) (((n) & 0x7) << 14)
53#define LVDS_CTRL_SLEW_ADJ_MASK GENMASK(16, 14)
54#define LVDS_CTRL_VBG_ADJ(n) (((n) & 0x7) << 17)
55#define LVDS_CTRL_VBG_ADJ_MASK GENMASK(19, 17)
56
57enum fsl_ldb_devtype {
58 IMX6SX_LDB,
59 IMX8MP_LDB,
60 IMX93_LDB,
61};
62
63struct fsl_ldb_devdata {
64 u32 ldb_ctrl;
65 u32 lvds_ctrl;
66 bool lvds_en_bit;
67 bool single_ctrl_reg;
68};
69
70static const struct fsl_ldb_devdata fsl_ldb_devdata[] = {
71 [IMX6SX_LDB] = {
72 .ldb_ctrl = 0x18,
73 .single_ctrl_reg = true,
74 },
75 [IMX8MP_LDB] = {
76 .ldb_ctrl = 0x5c,
77 .lvds_ctrl = 0x128,
78 },
79 [IMX93_LDB] = {
80 .ldb_ctrl = 0x20,
81 .lvds_ctrl = 0x24,
82 .lvds_en_bit = true,
83 },
84};
85
86struct fsl_ldb {
87 struct device *dev;
88 struct drm_bridge bridge;
89 struct drm_bridge *panel_bridge;
90 struct clk *clk;
91 struct regmap *regmap;
92 const struct fsl_ldb_devdata *devdata;
93 bool ch0_enabled;
94 bool ch1_enabled;
95};
96
97static bool fsl_ldb_is_dual(const struct fsl_ldb *fsl_ldb)
98{
99 return (fsl_ldb->ch0_enabled && fsl_ldb->ch1_enabled);
100}
101
102static inline struct fsl_ldb *to_fsl_ldb(struct drm_bridge *bridge)
103{
104 return container_of(bridge, struct fsl_ldb, bridge);
105}
106
107static unsigned long fsl_ldb_link_frequency(struct fsl_ldb *fsl_ldb, int clock)
108{
109 if (fsl_ldb_is_dual(fsl_ldb))
110 return clock * 3500;
111 else
112 return clock * 7000;
113}
114
115static int fsl_ldb_attach(struct drm_bridge *bridge,
116 enum drm_bridge_attach_flags flags)
117{
118 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
119
120 return drm_bridge_attach(bridge->encoder, fsl_ldb->panel_bridge,
121 bridge, flags);
122}
123
124static void fsl_ldb_atomic_enable(struct drm_bridge *bridge,
125 struct drm_bridge_state *old_bridge_state)
126{
127 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
128 struct drm_atomic_state *state = old_bridge_state->base.state;
129 const struct drm_bridge_state *bridge_state;
130 const struct drm_crtc_state *crtc_state;
131 const struct drm_display_mode *mode;
132 struct drm_connector *connector;
133 struct drm_crtc *crtc;
134 unsigned long configured_link_freq;
135 unsigned long requested_link_freq;
136 bool lvds_format_24bpp;
137 bool lvds_format_jeida;
138 u32 reg;
139
140 /* Get the LVDS format from the bridge state. */
141 bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
142
143 switch (bridge_state->output_bus_cfg.format) {
144 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
145 lvds_format_24bpp = false;
146 lvds_format_jeida = true;
147 break;
148 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
149 lvds_format_24bpp = true;
150 lvds_format_jeida = true;
151 break;
152 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
153 lvds_format_24bpp = true;
154 lvds_format_jeida = false;
155 break;
156 default:
157 /*
158 * Some bridges still don't set the correct LVDS bus pixel
159 * format, use SPWG24 default format until those are fixed.
160 */
161 lvds_format_24bpp = true;
162 lvds_format_jeida = false;
163 dev_warn(fsl_ldb->dev,
164 "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n",
165 bridge_state->output_bus_cfg.format);
166 break;
167 }
168
169 /*
170 * Retrieve the CRTC adjusted mode. This requires a little dance to go
171 * from the bridge to the encoder, to the connector and to the CRTC.
172 */
173 connector = drm_atomic_get_new_connector_for_encoder(state,
174 bridge->encoder);
175 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
176 crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
177 mode = &crtc_state->adjusted_mode;
178
179 requested_link_freq = fsl_ldb_link_frequency(fsl_ldb, mode->clock);
180 clk_set_rate(fsl_ldb->clk, requested_link_freq);
181
182 configured_link_freq = clk_get_rate(fsl_ldb->clk);
183 if (configured_link_freq != requested_link_freq)
184 dev_warn(fsl_ldb->dev, "Configured LDB clock (%lu Hz) does not match requested LVDS clock: %lu Hz\n",
185 configured_link_freq,
186 requested_link_freq);
187
188 clk_prepare_enable(fsl_ldb->clk);
189
190 /* Program LDB_CTRL */
191 reg = (fsl_ldb->ch0_enabled ? LDB_CTRL_CH0_ENABLE : 0) |
192 (fsl_ldb->ch1_enabled ? LDB_CTRL_CH1_ENABLE : 0) |
193 (fsl_ldb_is_dual(fsl_ldb) ? LDB_CTRL_SPLIT_MODE : 0);
194
195 if (lvds_format_24bpp)
196 reg |= (fsl_ldb->ch0_enabled ? LDB_CTRL_CH0_DATA_WIDTH : 0) |
197 (fsl_ldb->ch1_enabled ? LDB_CTRL_CH1_DATA_WIDTH : 0);
198
199 if (lvds_format_jeida)
200 reg |= (fsl_ldb->ch0_enabled ? LDB_CTRL_CH0_BIT_MAPPING : 0) |
201 (fsl_ldb->ch1_enabled ? LDB_CTRL_CH1_BIT_MAPPING : 0);
202
203 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
204 reg |= (fsl_ldb->ch0_enabled ? LDB_CTRL_DI0_VSYNC_POLARITY : 0) |
205 (fsl_ldb->ch1_enabled ? LDB_CTRL_DI1_VSYNC_POLARITY : 0);
206
207 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, reg);
208
209 if (fsl_ldb->devdata->single_ctrl_reg)
210 return;
211
212 /* Program LVDS_CTRL */
213 reg = LVDS_CTRL_CC_ADJ(2) | LVDS_CTRL_PRE_EMPH_EN |
214 LVDS_CTRL_PRE_EMPH_ADJ(3) | LVDS_CTRL_VBG_EN;
215 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, reg);
216
217 /* Wait for VBG to stabilize. */
218 usleep_range(15, 20);
219
220 reg |= (fsl_ldb->ch0_enabled ? LVDS_CTRL_CH0_EN : 0) |
221 (fsl_ldb->ch1_enabled ? LVDS_CTRL_CH1_EN : 0);
222
223 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, reg);
224}
225
226static void fsl_ldb_atomic_disable(struct drm_bridge *bridge,
227 struct drm_bridge_state *old_bridge_state)
228{
229 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
230
231 /* Stop channel(s). */
232 if (fsl_ldb->devdata->lvds_en_bit)
233 /* Set LVDS_CTRL_LVDS_EN bit to disable. */
234 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl,
235 LVDS_CTRL_LVDS_EN);
236 else
237 if (!fsl_ldb->devdata->single_ctrl_reg)
238 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 0);
239 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, 0);
240
241 clk_disable_unprepare(fsl_ldb->clk);
242}
243
244#define MAX_INPUT_SEL_FORMATS 1
245static u32 *
246fsl_ldb_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
247 struct drm_bridge_state *bridge_state,
248 struct drm_crtc_state *crtc_state,
249 struct drm_connector_state *conn_state,
250 u32 output_fmt,
251 unsigned int *num_input_fmts)
252{
253 u32 *input_fmts;
254
255 *num_input_fmts = 0;
256
257 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
258 GFP_KERNEL);
259 if (!input_fmts)
260 return NULL;
261
262 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
263 *num_input_fmts = MAX_INPUT_SEL_FORMATS;
264
265 return input_fmts;
266}
267
268static enum drm_mode_status
269fsl_ldb_mode_valid(struct drm_bridge *bridge,
270 const struct drm_display_info *info,
271 const struct drm_display_mode *mode)
272{
273 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
274
275 if (mode->clock > (fsl_ldb_is_dual(fsl_ldb) ? 160000 : 80000))
276 return MODE_CLOCK_HIGH;
277
278 return MODE_OK;
279}
280
281static const struct drm_bridge_funcs funcs = {
282 .attach = fsl_ldb_attach,
283 .atomic_enable = fsl_ldb_atomic_enable,
284 .atomic_disable = fsl_ldb_atomic_disable,
285 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
286 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
287 .atomic_get_input_bus_fmts = fsl_ldb_atomic_get_input_bus_fmts,
288 .atomic_reset = drm_atomic_helper_bridge_reset,
289 .mode_valid = fsl_ldb_mode_valid,
290};
291
292static int fsl_ldb_probe(struct platform_device *pdev)
293{
294 struct device *dev = &pdev->dev;
295 struct device_node *panel_node;
296 struct device_node *remote1, *remote2;
297 struct drm_panel *panel;
298 struct fsl_ldb *fsl_ldb;
299 int dual_link;
300
301 fsl_ldb = devm_kzalloc(dev, sizeof(*fsl_ldb), GFP_KERNEL);
302 if (!fsl_ldb)
303 return -ENOMEM;
304
305 fsl_ldb->devdata = of_device_get_match_data(dev);
306 if (!fsl_ldb->devdata)
307 return -EINVAL;
308
309 fsl_ldb->dev = &pdev->dev;
310 fsl_ldb->bridge.funcs = &funcs;
311 fsl_ldb->bridge.of_node = dev->of_node;
312
313 fsl_ldb->clk = devm_clk_get(dev, "ldb");
314 if (IS_ERR(fsl_ldb->clk))
315 return PTR_ERR(fsl_ldb->clk);
316
317 fsl_ldb->regmap = syscon_node_to_regmap(dev->of_node->parent);
318 if (IS_ERR(fsl_ldb->regmap))
319 return PTR_ERR(fsl_ldb->regmap);
320
321 /* Locate the remote ports and the panel node */
322 remote1 = of_graph_get_remote_node(dev->of_node, 1, 0);
323 remote2 = of_graph_get_remote_node(dev->of_node, 2, 0);
324 fsl_ldb->ch0_enabled = (remote1 != NULL);
325 fsl_ldb->ch1_enabled = (remote2 != NULL);
326 panel_node = of_node_get(remote1 ? remote1 : remote2);
327 of_node_put(remote1);
328 of_node_put(remote2);
329
330 if (!fsl_ldb->ch0_enabled && !fsl_ldb->ch1_enabled) {
331 of_node_put(panel_node);
332 return dev_err_probe(dev, -ENXIO, "No panel node found");
333 }
334
335 dev_dbg(dev, "Using %s\n",
336 fsl_ldb_is_dual(fsl_ldb) ? "dual-link mode" :
337 fsl_ldb->ch0_enabled ? "channel 0" : "channel 1");
338
339 panel = of_drm_find_panel(panel_node);
340 of_node_put(panel_node);
341 if (IS_ERR(panel))
342 return PTR_ERR(panel);
343
344 fsl_ldb->panel_bridge = devm_drm_panel_bridge_add(dev, panel);
345 if (IS_ERR(fsl_ldb->panel_bridge))
346 return PTR_ERR(fsl_ldb->panel_bridge);
347
348
349 if (fsl_ldb_is_dual(fsl_ldb)) {
350 struct device_node *port1, *port2;
351
352 port1 = of_graph_get_port_by_id(dev->of_node, 1);
353 port2 = of_graph_get_port_by_id(dev->of_node, 2);
354 dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2);
355 of_node_put(port1);
356 of_node_put(port2);
357
358 if (dual_link < 0)
359 return dev_err_probe(dev, dual_link,
360 "Error getting dual link configuration\n");
361
362 /* Only DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS is supported */
363 if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) {
364 dev_err(dev, "LVDS channel pixel swap not supported.\n");
365 return -EINVAL;
366 }
367 }
368
369 platform_set_drvdata(pdev, fsl_ldb);
370
371 drm_bridge_add(&fsl_ldb->bridge);
372
373 return 0;
374}
375
376static void fsl_ldb_remove(struct platform_device *pdev)
377{
378 struct fsl_ldb *fsl_ldb = platform_get_drvdata(pdev);
379
380 drm_bridge_remove(&fsl_ldb->bridge);
381}
382
383static const struct of_device_id fsl_ldb_match[] = {
384 { .compatible = "fsl,imx6sx-ldb",
385 .data = &fsl_ldb_devdata[IMX6SX_LDB], },
386 { .compatible = "fsl,imx8mp-ldb",
387 .data = &fsl_ldb_devdata[IMX8MP_LDB], },
388 { .compatible = "fsl,imx93-ldb",
389 .data = &fsl_ldb_devdata[IMX93_LDB], },
390 { /* sentinel */ },
391};
392MODULE_DEVICE_TABLE(of, fsl_ldb_match);
393
394static struct platform_driver fsl_ldb_driver = {
395 .probe = fsl_ldb_probe,
396 .remove_new = fsl_ldb_remove,
397 .driver = {
398 .name = "fsl-ldb",
399 .of_match_table = fsl_ldb_match,
400 },
401};
402module_platform_driver(fsl_ldb_driver);
403
404MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
405MODULE_DESCRIPTION("Freescale i.MX8MP LDB");
406MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2022 Marek Vasut <marex@denx.de>
4 */
5
6#include <linux/clk.h>
7#include <linux/media-bus-format.h>
8#include <linux/mfd/syscon.h>
9#include <linux/module.h>
10#include <linux/of.h>
11#include <linux/of_device.h>
12#include <linux/of_graph.h>
13#include <linux/platform_device.h>
14#include <linux/regmap.h>
15
16#include <drm/drm_atomic_helper.h>
17#include <drm/drm_bridge.h>
18#include <drm/drm_of.h>
19#include <drm/drm_panel.h>
20
21#define LDB_CTRL 0x5c
22#define LDB_CTRL_CH0_ENABLE BIT(0)
23#define LDB_CTRL_CH0_DI_SELECT BIT(1)
24#define LDB_CTRL_CH1_ENABLE BIT(2)
25#define LDB_CTRL_CH1_DI_SELECT BIT(3)
26#define LDB_CTRL_SPLIT_MODE BIT(4)
27#define LDB_CTRL_CH0_DATA_WIDTH BIT(5)
28#define LDB_CTRL_CH0_BIT_MAPPING BIT(6)
29#define LDB_CTRL_CH1_DATA_WIDTH BIT(7)
30#define LDB_CTRL_CH1_BIT_MAPPING BIT(8)
31#define LDB_CTRL_DI0_VSYNC_POLARITY BIT(9)
32#define LDB_CTRL_DI1_VSYNC_POLARITY BIT(10)
33#define LDB_CTRL_REG_CH0_FIFO_RESET BIT(11)
34#define LDB_CTRL_REG_CH1_FIFO_RESET BIT(12)
35#define LDB_CTRL_ASYNC_FIFO_ENABLE BIT(24)
36#define LDB_CTRL_ASYNC_FIFO_THRESHOLD_MASK GENMASK(27, 25)
37
38#define LVDS_CTRL 0x128
39#define LVDS_CTRL_CH0_EN BIT(0)
40#define LVDS_CTRL_CH1_EN BIT(1)
41#define LVDS_CTRL_VBG_EN BIT(2)
42#define LVDS_CTRL_HS_EN BIT(3)
43#define LVDS_CTRL_PRE_EMPH_EN BIT(4)
44#define LVDS_CTRL_PRE_EMPH_ADJ(n) (((n) & 0x7) << 5)
45#define LVDS_CTRL_PRE_EMPH_ADJ_MASK GENMASK(7, 5)
46#define LVDS_CTRL_CM_ADJ(n) (((n) & 0x7) << 8)
47#define LVDS_CTRL_CM_ADJ_MASK GENMASK(10, 8)
48#define LVDS_CTRL_CC_ADJ(n) (((n) & 0x7) << 11)
49#define LVDS_CTRL_CC_ADJ_MASK GENMASK(13, 11)
50#define LVDS_CTRL_SLEW_ADJ(n) (((n) & 0x7) << 14)
51#define LVDS_CTRL_SLEW_ADJ_MASK GENMASK(16, 14)
52#define LVDS_CTRL_VBG_ADJ(n) (((n) & 0x7) << 17)
53#define LVDS_CTRL_VBG_ADJ_MASK GENMASK(19, 17)
54
55struct fsl_ldb {
56 struct device *dev;
57 struct drm_bridge bridge;
58 struct drm_bridge *panel_bridge;
59 struct clk *clk;
60 struct regmap *regmap;
61 bool lvds_dual_link;
62};
63
64static inline struct fsl_ldb *to_fsl_ldb(struct drm_bridge *bridge)
65{
66 return container_of(bridge, struct fsl_ldb, bridge);
67}
68
69static int fsl_ldb_attach(struct drm_bridge *bridge,
70 enum drm_bridge_attach_flags flags)
71{
72 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
73
74 return drm_bridge_attach(bridge->encoder, fsl_ldb->panel_bridge,
75 bridge, flags);
76}
77
78static void fsl_ldb_atomic_enable(struct drm_bridge *bridge,
79 struct drm_bridge_state *old_bridge_state)
80{
81 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
82 struct drm_atomic_state *state = old_bridge_state->base.state;
83 const struct drm_bridge_state *bridge_state;
84 const struct drm_crtc_state *crtc_state;
85 const struct drm_display_mode *mode;
86 struct drm_connector *connector;
87 struct drm_crtc *crtc;
88 bool lvds_format_24bpp;
89 bool lvds_format_jeida;
90 u32 reg;
91
92 /* Get the LVDS format from the bridge state. */
93 bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
94
95 switch (bridge_state->output_bus_cfg.format) {
96 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
97 lvds_format_24bpp = false;
98 lvds_format_jeida = true;
99 break;
100 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
101 lvds_format_24bpp = true;
102 lvds_format_jeida = true;
103 break;
104 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
105 lvds_format_24bpp = true;
106 lvds_format_jeida = false;
107 break;
108 default:
109 /*
110 * Some bridges still don't set the correct LVDS bus pixel
111 * format, use SPWG24 default format until those are fixed.
112 */
113 lvds_format_24bpp = true;
114 lvds_format_jeida = false;
115 dev_warn(fsl_ldb->dev,
116 "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n",
117 bridge_state->output_bus_cfg.format);
118 break;
119 }
120
121 /*
122 * Retrieve the CRTC adjusted mode. This requires a little dance to go
123 * from the bridge to the encoder, to the connector and to the CRTC.
124 */
125 connector = drm_atomic_get_new_connector_for_encoder(state,
126 bridge->encoder);
127 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
128 crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
129 mode = &crtc_state->adjusted_mode;
130
131 if (fsl_ldb->lvds_dual_link)
132 clk_set_rate(fsl_ldb->clk, mode->clock * 3500);
133 else
134 clk_set_rate(fsl_ldb->clk, mode->clock * 7000);
135 clk_prepare_enable(fsl_ldb->clk);
136
137 /* Program LDB_CTRL */
138 reg = LDB_CTRL_CH0_ENABLE;
139
140 if (fsl_ldb->lvds_dual_link)
141 reg |= LDB_CTRL_CH1_ENABLE | LDB_CTRL_SPLIT_MODE;
142
143 if (lvds_format_24bpp) {
144 reg |= LDB_CTRL_CH0_DATA_WIDTH;
145 if (fsl_ldb->lvds_dual_link)
146 reg |= LDB_CTRL_CH1_DATA_WIDTH;
147 }
148
149 if (lvds_format_jeida) {
150 reg |= LDB_CTRL_CH0_BIT_MAPPING;
151 if (fsl_ldb->lvds_dual_link)
152 reg |= LDB_CTRL_CH1_BIT_MAPPING;
153 }
154
155 if (mode->flags & DRM_MODE_FLAG_PVSYNC) {
156 reg |= LDB_CTRL_DI0_VSYNC_POLARITY;
157 if (fsl_ldb->lvds_dual_link)
158 reg |= LDB_CTRL_DI1_VSYNC_POLARITY;
159 }
160
161 regmap_write(fsl_ldb->regmap, LDB_CTRL, reg);
162
163 /* Program LVDS_CTRL */
164 reg = LVDS_CTRL_CC_ADJ(2) | LVDS_CTRL_PRE_EMPH_EN |
165 LVDS_CTRL_PRE_EMPH_ADJ(3) | LVDS_CTRL_VBG_EN;
166 regmap_write(fsl_ldb->regmap, LVDS_CTRL, reg);
167
168 /* Wait for VBG to stabilize. */
169 usleep_range(15, 20);
170
171 reg |= LVDS_CTRL_CH0_EN;
172 if (fsl_ldb->lvds_dual_link)
173 reg |= LVDS_CTRL_CH1_EN;
174
175 regmap_write(fsl_ldb->regmap, LVDS_CTRL, reg);
176}
177
178static void fsl_ldb_atomic_disable(struct drm_bridge *bridge,
179 struct drm_bridge_state *old_bridge_state)
180{
181 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
182
183 /* Stop both channels. */
184 regmap_write(fsl_ldb->regmap, LVDS_CTRL, 0);
185 regmap_write(fsl_ldb->regmap, LDB_CTRL, 0);
186
187 clk_disable_unprepare(fsl_ldb->clk);
188}
189
190#define MAX_INPUT_SEL_FORMATS 1
191static u32 *
192fsl_ldb_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
193 struct drm_bridge_state *bridge_state,
194 struct drm_crtc_state *crtc_state,
195 struct drm_connector_state *conn_state,
196 u32 output_fmt,
197 unsigned int *num_input_fmts)
198{
199 u32 *input_fmts;
200
201 *num_input_fmts = 0;
202
203 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
204 GFP_KERNEL);
205 if (!input_fmts)
206 return NULL;
207
208 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
209 *num_input_fmts = MAX_INPUT_SEL_FORMATS;
210
211 return input_fmts;
212}
213
214static enum drm_mode_status
215fsl_ldb_mode_valid(struct drm_bridge *bridge,
216 const struct drm_display_info *info,
217 const struct drm_display_mode *mode)
218{
219 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
220
221 if (mode->clock > (fsl_ldb->lvds_dual_link ? 160000 : 80000))
222 return MODE_CLOCK_HIGH;
223
224 return MODE_OK;
225}
226
227static const struct drm_bridge_funcs funcs = {
228 .attach = fsl_ldb_attach,
229 .atomic_enable = fsl_ldb_atomic_enable,
230 .atomic_disable = fsl_ldb_atomic_disable,
231 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
232 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
233 .atomic_get_input_bus_fmts = fsl_ldb_atomic_get_input_bus_fmts,
234 .atomic_reset = drm_atomic_helper_bridge_reset,
235 .mode_valid = fsl_ldb_mode_valid,
236};
237
238static int fsl_ldb_probe(struct platform_device *pdev)
239{
240 struct device *dev = &pdev->dev;
241 struct device_node *panel_node;
242 struct device_node *port1, *port2;
243 struct drm_panel *panel;
244 struct fsl_ldb *fsl_ldb;
245 int dual_link;
246
247 fsl_ldb = devm_kzalloc(dev, sizeof(*fsl_ldb), GFP_KERNEL);
248 if (!fsl_ldb)
249 return -ENOMEM;
250
251 fsl_ldb->dev = &pdev->dev;
252 fsl_ldb->bridge.funcs = &funcs;
253 fsl_ldb->bridge.of_node = dev->of_node;
254
255 fsl_ldb->clk = devm_clk_get(dev, "ldb");
256 if (IS_ERR(fsl_ldb->clk))
257 return PTR_ERR(fsl_ldb->clk);
258
259 fsl_ldb->regmap = syscon_node_to_regmap(dev->of_node->parent);
260 if (IS_ERR(fsl_ldb->regmap))
261 return PTR_ERR(fsl_ldb->regmap);
262
263 /* Locate the panel DT node. */
264 panel_node = of_graph_get_remote_node(dev->of_node, 1, 0);
265 if (!panel_node)
266 return -ENXIO;
267
268 panel = of_drm_find_panel(panel_node);
269 of_node_put(panel_node);
270 if (IS_ERR(panel))
271 return PTR_ERR(panel);
272
273 fsl_ldb->panel_bridge = devm_drm_panel_bridge_add(dev, panel);
274 if (IS_ERR(fsl_ldb->panel_bridge))
275 return PTR_ERR(fsl_ldb->panel_bridge);
276
277 /* Determine whether this is dual-link configuration */
278 port1 = of_graph_get_port_by_id(dev->of_node, 1);
279 port2 = of_graph_get_port_by_id(dev->of_node, 2);
280 dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2);
281 of_node_put(port1);
282 of_node_put(port2);
283
284 if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) {
285 dev_err(dev, "LVDS channel pixel swap not supported.\n");
286 return -EINVAL;
287 }
288
289 if (dual_link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS)
290 fsl_ldb->lvds_dual_link = true;
291
292 platform_set_drvdata(pdev, fsl_ldb);
293
294 drm_bridge_add(&fsl_ldb->bridge);
295
296 return 0;
297}
298
299static int fsl_ldb_remove(struct platform_device *pdev)
300{
301 struct fsl_ldb *fsl_ldb = platform_get_drvdata(pdev);
302
303 drm_bridge_remove(&fsl_ldb->bridge);
304
305 return 0;
306}
307
308static const struct of_device_id fsl_ldb_match[] = {
309 { .compatible = "fsl,imx8mp-ldb", },
310 { /* sentinel */ },
311};
312MODULE_DEVICE_TABLE(of, fsl_ldb_match);
313
314static struct platform_driver fsl_ldb_driver = {
315 .probe = fsl_ldb_probe,
316 .remove = fsl_ldb_remove,
317 .driver = {
318 .name = "fsl-ldb",
319 .of_match_table = fsl_ldb_match,
320 },
321};
322module_platform_driver(fsl_ldb_driver);
323
324MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
325MODULE_DESCRIPTION("Freescale i.MX8MP LDB");
326MODULE_LICENSE("GPL");