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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Toshiba Visconti GPIO Support
4 *
5 * (C) Copyright 2020 Toshiba Electronic Devices & Storage Corporation
6 * (C) Copyright 2020 TOSHIBA CORPORATION
7 *
8 * Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
9 */
10
11#include <linux/gpio/driver.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/module.h>
15#include <linux/io.h>
16#include <linux/of_irq.h>
17#include <linux/platform_device.h>
18#include <linux/seq_file.h>
19#include <linux/bitops.h>
20
21/* register offset */
22#define GPIO_DIR 0x00
23#define GPIO_IDATA 0x08
24#define GPIO_ODATA 0x10
25#define GPIO_OSET 0x18
26#define GPIO_OCLR 0x20
27#define GPIO_INTMODE 0x30
28
29#define BASE_HW_IRQ 24
30
31struct visconti_gpio {
32 void __iomem *base;
33 spinlock_t lock; /* protect gpio register */
34 struct gpio_chip gpio_chip;
35 struct device *dev;
36};
37
38static int visconti_gpio_irq_set_type(struct irq_data *d, unsigned int type)
39{
40 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
41 struct visconti_gpio *priv = gpiochip_get_data(gc);
42 u32 offset = irqd_to_hwirq(d);
43 u32 bit = BIT(offset);
44 u32 intc_type = IRQ_TYPE_EDGE_RISING;
45 u32 intmode, odata;
46 int ret = 0;
47 unsigned long flags;
48
49 spin_lock_irqsave(&priv->lock, flags);
50
51 odata = readl(priv->base + GPIO_ODATA);
52 intmode = readl(priv->base + GPIO_INTMODE);
53
54 switch (type) {
55 case IRQ_TYPE_EDGE_RISING:
56 odata &= ~bit;
57 intmode &= ~bit;
58 break;
59 case IRQ_TYPE_EDGE_FALLING:
60 odata |= bit;
61 intmode &= ~bit;
62 break;
63 case IRQ_TYPE_EDGE_BOTH:
64 intmode |= bit;
65 break;
66 case IRQ_TYPE_LEVEL_HIGH:
67 intc_type = IRQ_TYPE_LEVEL_HIGH;
68 odata &= ~bit;
69 intmode &= ~bit;
70 break;
71 case IRQ_TYPE_LEVEL_LOW:
72 intc_type = IRQ_TYPE_LEVEL_HIGH;
73 odata |= bit;
74 intmode &= ~bit;
75 break;
76 default:
77 ret = -EINVAL;
78 goto err;
79 }
80
81 writel(odata, priv->base + GPIO_ODATA);
82 writel(intmode, priv->base + GPIO_INTMODE);
83 irq_set_irq_type(offset, intc_type);
84
85 ret = irq_chip_set_type_parent(d, type);
86err:
87 spin_unlock_irqrestore(&priv->lock, flags);
88 return ret;
89}
90
91static int visconti_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
92 unsigned int child,
93 unsigned int child_type,
94 unsigned int *parent,
95 unsigned int *parent_type)
96{
97 /* Interrupts 0..15 mapped to interrupts 24..39 on the GIC */
98 if (child < 16) {
99 /* All these interrupts are level high in the CPU */
100 *parent_type = IRQ_TYPE_LEVEL_HIGH;
101 *parent = child + BASE_HW_IRQ;
102 return 0;
103 }
104 return -EINVAL;
105}
106
107static int visconti_gpio_populate_parent_fwspec(struct gpio_chip *chip,
108 union gpio_irq_fwspec *gfwspec,
109 unsigned int parent_hwirq,
110 unsigned int parent_type)
111{
112 struct irq_fwspec *fwspec = &gfwspec->fwspec;
113
114 fwspec->fwnode = chip->irq.parent_domain->fwnode;
115 fwspec->param_count = 3;
116 fwspec->param[0] = 0;
117 fwspec->param[1] = parent_hwirq;
118 fwspec->param[2] = parent_type;
119
120 return 0;
121}
122
123static void visconti_gpio_mask_irq(struct irq_data *d)
124{
125 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
126
127 irq_chip_mask_parent(d);
128 gpiochip_disable_irq(gc, irqd_to_hwirq(d));
129}
130
131static void visconti_gpio_unmask_irq(struct irq_data *d)
132{
133 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
134
135 gpiochip_enable_irq(gc, irqd_to_hwirq(d));
136 irq_chip_unmask_parent(d);
137}
138
139static void visconti_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p)
140{
141 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
142 struct visconti_gpio *priv = gpiochip_get_data(gc);
143
144 seq_printf(p, dev_name(priv->dev));
145}
146
147static const struct irq_chip visconti_gpio_irq_chip = {
148 .irq_mask = visconti_gpio_mask_irq,
149 .irq_unmask = visconti_gpio_unmask_irq,
150 .irq_eoi = irq_chip_eoi_parent,
151 .irq_set_type = visconti_gpio_irq_set_type,
152 .irq_print_chip = visconti_gpio_irq_print_chip,
153 .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND |
154 IRQCHIP_IMMUTABLE,
155 GPIOCHIP_IRQ_RESOURCE_HELPERS,
156};
157
158static int visconti_gpio_probe(struct platform_device *pdev)
159{
160 struct device *dev = &pdev->dev;
161 struct visconti_gpio *priv;
162 struct gpio_irq_chip *girq;
163 struct irq_domain *parent;
164 struct device_node *irq_parent;
165 int ret;
166
167 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
168 if (!priv)
169 return -ENOMEM;
170
171 spin_lock_init(&priv->lock);
172 priv->dev = dev;
173
174 priv->base = devm_platform_ioremap_resource(pdev, 0);
175 if (IS_ERR(priv->base))
176 return PTR_ERR(priv->base);
177
178 irq_parent = of_irq_find_parent(dev->of_node);
179 if (!irq_parent) {
180 dev_err(dev, "No IRQ parent node\n");
181 return -ENODEV;
182 }
183
184 parent = irq_find_host(irq_parent);
185 of_node_put(irq_parent);
186 if (!parent) {
187 dev_err(dev, "No IRQ parent domain\n");
188 return -ENODEV;
189 }
190
191 ret = bgpio_init(&priv->gpio_chip, dev, 4,
192 priv->base + GPIO_IDATA,
193 priv->base + GPIO_OSET,
194 priv->base + GPIO_OCLR,
195 priv->base + GPIO_DIR,
196 NULL,
197 0);
198 if (ret) {
199 dev_err(dev, "unable to init generic GPIO\n");
200 return ret;
201 }
202
203 girq = &priv->gpio_chip.irq;
204 gpio_irq_chip_set_chip(girq, &visconti_gpio_irq_chip);
205 girq->fwnode = of_node_to_fwnode(dev->of_node);
206 girq->parent_domain = parent;
207 girq->child_to_parent_hwirq = visconti_gpio_child_to_parent_hwirq;
208 girq->populate_parent_alloc_arg = visconti_gpio_populate_parent_fwspec;
209 girq->default_type = IRQ_TYPE_NONE;
210 girq->handler = handle_level_irq;
211
212 return devm_gpiochip_add_data(dev, &priv->gpio_chip, priv);
213}
214
215static const struct of_device_id visconti_gpio_of_match[] = {
216 { .compatible = "toshiba,gpio-tmpv7708", },
217 { /* end of table */ }
218};
219MODULE_DEVICE_TABLE(of, visconti_gpio_of_match);
220
221static struct platform_driver visconti_gpio_driver = {
222 .probe = visconti_gpio_probe,
223 .driver = {
224 .name = "visconti_gpio",
225 .of_match_table = visconti_gpio_of_match,
226 }
227};
228module_platform_driver(visconti_gpio_driver);
229
230MODULE_AUTHOR("Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>");
231MODULE_DESCRIPTION("Toshiba Visconti GPIO Driver");
232MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Toshiba Visconti GPIO Support
4 *
5 * (C) Copyright 2020 Toshiba Electronic Devices & Storage Corporation
6 * (C) Copyright 2020 TOSHIBA CORPORATION
7 *
8 * Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
9 */
10
11#include <linux/gpio/driver.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/module.h>
15#include <linux/io.h>
16#include <linux/of_irq.h>
17#include <linux/platform_device.h>
18#include <linux/bitops.h>
19
20/* register offset */
21#define GPIO_DIR 0x00
22#define GPIO_IDATA 0x08
23#define GPIO_ODATA 0x10
24#define GPIO_OSET 0x18
25#define GPIO_OCLR 0x20
26#define GPIO_INTMODE 0x30
27
28#define BASE_HW_IRQ 24
29
30struct visconti_gpio {
31 void __iomem *base;
32 spinlock_t lock; /* protect gpio register */
33 struct gpio_chip gpio_chip;
34 struct irq_chip irq_chip;
35};
36
37static int visconti_gpio_irq_set_type(struct irq_data *d, unsigned int type)
38{
39 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
40 struct visconti_gpio *priv = gpiochip_get_data(gc);
41 u32 offset = irqd_to_hwirq(d);
42 u32 bit = BIT(offset);
43 u32 intc_type = IRQ_TYPE_EDGE_RISING;
44 u32 intmode, odata;
45 int ret = 0;
46 unsigned long flags;
47
48 spin_lock_irqsave(&priv->lock, flags);
49
50 odata = readl(priv->base + GPIO_ODATA);
51 intmode = readl(priv->base + GPIO_INTMODE);
52
53 switch (type) {
54 case IRQ_TYPE_EDGE_RISING:
55 odata &= ~bit;
56 intmode &= ~bit;
57 break;
58 case IRQ_TYPE_EDGE_FALLING:
59 odata |= bit;
60 intmode &= ~bit;
61 break;
62 case IRQ_TYPE_EDGE_BOTH:
63 intmode |= bit;
64 break;
65 case IRQ_TYPE_LEVEL_HIGH:
66 intc_type = IRQ_TYPE_LEVEL_HIGH;
67 odata &= ~bit;
68 intmode &= ~bit;
69 break;
70 case IRQ_TYPE_LEVEL_LOW:
71 intc_type = IRQ_TYPE_LEVEL_HIGH;
72 odata |= bit;
73 intmode &= ~bit;
74 break;
75 default:
76 ret = -EINVAL;
77 goto err;
78 }
79
80 writel(odata, priv->base + GPIO_ODATA);
81 writel(intmode, priv->base + GPIO_INTMODE);
82 irq_set_irq_type(offset, intc_type);
83
84 ret = irq_chip_set_type_parent(d, type);
85err:
86 spin_unlock_irqrestore(&priv->lock, flags);
87 return ret;
88}
89
90static int visconti_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
91 unsigned int child,
92 unsigned int child_type,
93 unsigned int *parent,
94 unsigned int *parent_type)
95{
96 /* Interrupts 0..15 mapped to interrupts 24..39 on the GIC */
97 if (child < 16) {
98 /* All these interrupts are level high in the CPU */
99 *parent_type = IRQ_TYPE_LEVEL_HIGH;
100 *parent = child + BASE_HW_IRQ;
101 return 0;
102 }
103 return -EINVAL;
104}
105
106static int visconti_gpio_populate_parent_fwspec(struct gpio_chip *chip,
107 union gpio_irq_fwspec *gfwspec,
108 unsigned int parent_hwirq,
109 unsigned int parent_type)
110{
111 struct irq_fwspec *fwspec = &gfwspec->fwspec;
112
113 fwspec->fwnode = chip->irq.parent_domain->fwnode;
114 fwspec->param_count = 3;
115 fwspec->param[0] = 0;
116 fwspec->param[1] = parent_hwirq;
117 fwspec->param[2] = parent_type;
118
119 return 0;
120}
121
122static int visconti_gpio_probe(struct platform_device *pdev)
123{
124 struct device *dev = &pdev->dev;
125 struct visconti_gpio *priv;
126 struct irq_chip *irq_chip;
127 struct gpio_irq_chip *girq;
128 struct irq_domain *parent;
129 struct device_node *irq_parent;
130 int ret;
131
132 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
133 if (!priv)
134 return -ENOMEM;
135
136 spin_lock_init(&priv->lock);
137
138 priv->base = devm_platform_ioremap_resource(pdev, 0);
139 if (IS_ERR(priv->base))
140 return PTR_ERR(priv->base);
141
142 irq_parent = of_irq_find_parent(dev->of_node);
143 if (!irq_parent) {
144 dev_err(dev, "No IRQ parent node\n");
145 return -ENODEV;
146 }
147
148 parent = irq_find_host(irq_parent);
149 of_node_put(irq_parent);
150 if (!parent) {
151 dev_err(dev, "No IRQ parent domain\n");
152 return -ENODEV;
153 }
154
155 ret = bgpio_init(&priv->gpio_chip, dev, 4,
156 priv->base + GPIO_IDATA,
157 priv->base + GPIO_OSET,
158 priv->base + GPIO_OCLR,
159 priv->base + GPIO_DIR,
160 NULL,
161 0);
162 if (ret) {
163 dev_err(dev, "unable to init generic GPIO\n");
164 return ret;
165 }
166
167 irq_chip = &priv->irq_chip;
168 irq_chip->name = dev_name(dev);
169 irq_chip->irq_mask = irq_chip_mask_parent;
170 irq_chip->irq_unmask = irq_chip_unmask_parent;
171 irq_chip->irq_eoi = irq_chip_eoi_parent;
172 irq_chip->irq_set_type = visconti_gpio_irq_set_type;
173 irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
174
175 girq = &priv->gpio_chip.irq;
176 girq->chip = irq_chip;
177 girq->fwnode = of_node_to_fwnode(dev->of_node);
178 girq->parent_domain = parent;
179 girq->child_to_parent_hwirq = visconti_gpio_child_to_parent_hwirq;
180 girq->populate_parent_alloc_arg = visconti_gpio_populate_parent_fwspec;
181 girq->default_type = IRQ_TYPE_NONE;
182 girq->handler = handle_level_irq;
183
184 return devm_gpiochip_add_data(dev, &priv->gpio_chip, priv);
185}
186
187static const struct of_device_id visconti_gpio_of_match[] = {
188 { .compatible = "toshiba,gpio-tmpv7708", },
189 { /* end of table */ }
190};
191MODULE_DEVICE_TABLE(of, visconti_gpio_of_match);
192
193static struct platform_driver visconti_gpio_driver = {
194 .probe = visconti_gpio_probe,
195 .driver = {
196 .name = "visconti_gpio",
197 .of_match_table = of_match_ptr(visconti_gpio_of_match),
198 }
199};
200module_platform_driver(visconti_gpio_driver);
201
202MODULE_AUTHOR("Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>");
203MODULE_DESCRIPTION("Toshiba Visconti GPIO Driver");
204MODULE_LICENSE("GPL v2");