1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 2/*
 3 * Device Tree Source for the RZ/Five SoC
 4 *
 5 * Copyright (C) 2022 Renesas Electronics Corp.
 6 */
 7
 8#include <dt-bindings/interrupt-controller/irq.h>
 9
10#define SOC_PERIPHERAL_IRQ(nr)	(nr + 32)
11
12#include <arm64/renesas/r9a07g043.dtsi>
13
14/ {
15	cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18		timebase-frequency = <12000000>;
19
20		cpu0: cpu@0 {
21			compatible = "andestech,ax45mp", "riscv";
22			device_type = "cpu";
23			#cooling-cells = <2>;
24			reg = <0x0>;
25			status = "okay";
26			riscv,isa = "rv64imafdc";
27			riscv,isa-base = "rv64i";
28			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
29					       "zicntr", "zicsr", "zifencei",
30					       "zihpm";
31			mmu-type = "riscv,sv39";
32			i-cache-size = <0x8000>;
33			i-cache-line-size = <0x40>;
34			d-cache-size = <0x8000>;
35			d-cache-line-size = <0x40>;
36			next-level-cache = <&l2cache>;
37			clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
38			operating-points-v2 = <&cluster0_opp>;
39
40			cpu0_intc: interrupt-controller {
41				#interrupt-cells = <1>;
42				compatible = "riscv,cpu-intc";
43				interrupt-controller;
44			};
45		};
46	};
47};
48
49&soc {
50	dma-noncoherent;
51	interrupt-parent = <&plic>;
52
53	plic: interrupt-controller@12c00000 {
54		compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
55		#interrupt-cells = <2>;
56		#address-cells = <0>;
57		riscv,ndev = <511>;
58		interrupt-controller;
59		reg = <0x0 0x12c00000 0 0x400000>;
60		clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
61		power-domains = <&cpg>;
62		resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
63		interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
64	};
65
66	l2cache: cache-controller@13400000 {
67		compatible = "andestech,ax45mp-cache", "cache";
68		reg = <0x0 0x13400000 0x0 0x100000>;
69		interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
70		cache-size = <0x40000>;
71		cache-line-size = <64>;
72		cache-sets = <1024>;
73		cache-unified;
74		cache-level = <2>;
75	};
76};

 1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 2/*
 3 * Device Tree Source for the RZ/Five SoC
 4 *
 5 * Copyright (C) 2022 Renesas Electronics Corp.
 6 */
 7
 8#include <dt-bindings/interrupt-controller/irq.h>
 9
10#define SOC_PERIPHERAL_IRQ(nr)	(nr + 32)
11
12#include <arm64/renesas/r9a07g043.dtsi>
13
14/ {
15	cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18		timebase-frequency = <12000000>;
19
20		cpu0: cpu@0 {
21			compatible = "andestech,ax45mp", "riscv";
22			device_type = "cpu";
23			#cooling-cells = <2>;
24			reg = <0x0>;
25			status = "okay";
26			riscv,isa = "rv64imafdc";
 
 
 
 
27			mmu-type = "riscv,sv39";
28			i-cache-size = <0x8000>;
29			i-cache-line-size = <0x40>;
30			d-cache-size = <0x8000>;
31			d-cache-line-size = <0x40>;
 
32			clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
33			operating-points-v2 = <&cluster0_opp>;
34
35			cpu0_intc: interrupt-controller {
36				#interrupt-cells = <1>;
37				compatible = "riscv,cpu-intc";
38				interrupt-controller;
39			};
40		};
41	};
42};
43
44&soc {
 
45	interrupt-parent = <&plic>;
46
47	plic: interrupt-controller@12c00000 {
48		compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
49		#interrupt-cells = <2>;
50		#address-cells = <0>;
51		riscv,ndev = <511>;
52		interrupt-controller;
53		reg = <0x0 0x12c00000 0 0x400000>;
54		clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
55		power-domains = <&cpg>;
56		resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
57		interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
 
 
 
 
 
 
 
 
 
 
 
58	};
59};