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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Common time service routines for LoongArch machines.
4 *
5 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
6 */
7#include <linux/clockchips.h>
8#include <linux/delay.h>
9#include <linux/export.h>
10#include <linux/init.h>
11#include <linux/interrupt.h>
12#include <linux/kernel.h>
13#include <linux/sched_clock.h>
14#include <linux/spinlock.h>
15
16#include <asm/cpu-features.h>
17#include <asm/loongarch.h>
18#include <asm/time.h>
19
20u64 cpu_clock_freq;
21EXPORT_SYMBOL(cpu_clock_freq);
22u64 const_clock_freq;
23EXPORT_SYMBOL(const_clock_freq);
24
25static DEFINE_RAW_SPINLOCK(state_lock);
26static DEFINE_PER_CPU(struct clock_event_device, constant_clockevent_device);
27
28static void constant_event_handler(struct clock_event_device *dev)
29{
30}
31
32static irqreturn_t constant_timer_interrupt(int irq, void *data)
33{
34 int cpu = smp_processor_id();
35 struct clock_event_device *cd;
36
37 /* Clear Timer Interrupt */
38 write_csr_tintclear(CSR_TINTCLR_TI);
39 cd = &per_cpu(constant_clockevent_device, cpu);
40 cd->event_handler(cd);
41
42 return IRQ_HANDLED;
43}
44
45static int constant_set_state_oneshot(struct clock_event_device *evt)
46{
47 unsigned long timer_config;
48
49 raw_spin_lock(&state_lock);
50
51 timer_config = csr_read64(LOONGARCH_CSR_TCFG);
52 timer_config |= CSR_TCFG_EN;
53 timer_config &= ~CSR_TCFG_PERIOD;
54 csr_write64(timer_config, LOONGARCH_CSR_TCFG);
55
56 raw_spin_unlock(&state_lock);
57
58 return 0;
59}
60
61static int constant_set_state_periodic(struct clock_event_device *evt)
62{
63 unsigned long period;
64 unsigned long timer_config;
65
66 raw_spin_lock(&state_lock);
67
68 period = const_clock_freq / HZ;
69 timer_config = period & CSR_TCFG_VAL;
70 timer_config |= (CSR_TCFG_PERIOD | CSR_TCFG_EN);
71 csr_write64(timer_config, LOONGARCH_CSR_TCFG);
72
73 raw_spin_unlock(&state_lock);
74
75 return 0;
76}
77
78static int constant_set_state_shutdown(struct clock_event_device *evt)
79{
80 unsigned long timer_config;
81
82 raw_spin_lock(&state_lock);
83
84 timer_config = csr_read64(LOONGARCH_CSR_TCFG);
85 timer_config &= ~CSR_TCFG_EN;
86 csr_write64(timer_config, LOONGARCH_CSR_TCFG);
87
88 raw_spin_unlock(&state_lock);
89
90 return 0;
91}
92
93static int constant_timer_next_event(unsigned long delta, struct clock_event_device *evt)
94{
95 unsigned long timer_config;
96
97 delta &= CSR_TCFG_VAL;
98 timer_config = delta | CSR_TCFG_EN;
99 csr_write64(timer_config, LOONGARCH_CSR_TCFG);
100
101 return 0;
102}
103
104static unsigned long __init get_loops_per_jiffy(void)
105{
106 unsigned long lpj = (unsigned long)const_clock_freq;
107
108 do_div(lpj, HZ);
109
110 return lpj;
111}
112
113static long init_offset __nosavedata;
114
115void save_counter(void)
116{
117 init_offset = drdtime();
118}
119
120void sync_counter(void)
121{
122 /* Ensure counter begin at 0 */
123 csr_write64(init_offset, LOONGARCH_CSR_CNTC);
124}
125
126static int get_timer_irq(void)
127{
128 struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
129
130 if (d)
131 return irq_create_mapping(d, INT_TI);
132
133 return -EINVAL;
134}
135
136int constant_clockevent_init(void)
137{
138 unsigned int cpu = smp_processor_id();
139 unsigned long min_delta = 0x600;
140 unsigned long max_delta = (1UL << 48) - 1;
141 struct clock_event_device *cd;
142 static int irq = 0, timer_irq_installed = 0;
143
144 if (!timer_irq_installed) {
145 irq = get_timer_irq();
146 if (irq < 0)
147 pr_err("Failed to map irq %d (timer)\n", irq);
148 }
149
150 cd = &per_cpu(constant_clockevent_device, cpu);
151
152 cd->name = "Constant";
153 cd->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_PERCPU;
154
155 cd->irq = irq;
156 cd->rating = 320;
157 cd->cpumask = cpumask_of(cpu);
158 cd->set_state_oneshot = constant_set_state_oneshot;
159 cd->set_state_oneshot_stopped = constant_set_state_shutdown;
160 cd->set_state_periodic = constant_set_state_periodic;
161 cd->set_state_shutdown = constant_set_state_shutdown;
162 cd->set_next_event = constant_timer_next_event;
163 cd->event_handler = constant_event_handler;
164
165 clockevents_config_and_register(cd, const_clock_freq, min_delta, max_delta);
166
167 if (timer_irq_installed)
168 return 0;
169
170 timer_irq_installed = 1;
171
172 sync_counter();
173
174 if (request_irq(irq, constant_timer_interrupt, IRQF_PERCPU | IRQF_TIMER, "timer", NULL))
175 pr_err("Failed to request irq %d (timer)\n", irq);
176
177 lpj_fine = get_loops_per_jiffy();
178 pr_info("Constant clock event device register\n");
179
180 return 0;
181}
182
183static u64 read_const_counter(struct clocksource *clk)
184{
185 return drdtime();
186}
187
188static noinstr u64 sched_clock_read(void)
189{
190 return drdtime();
191}
192
193static struct clocksource clocksource_const = {
194 .name = "Constant",
195 .rating = 400,
196 .read = read_const_counter,
197 .mask = CLOCKSOURCE_MASK(64),
198 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
199 .vdso_clock_mode = VDSO_CLOCKMODE_CPU,
200};
201
202int __init constant_clocksource_init(void)
203{
204 int res;
205 unsigned long freq = const_clock_freq;
206
207 res = clocksource_register_hz(&clocksource_const, freq);
208
209 sched_clock_register(sched_clock_read, 64, freq);
210
211 pr_info("Constant clock source device register\n");
212
213 return res;
214}
215
216void __init time_init(void)
217{
218 if (!cpu_has_cpucfg)
219 const_clock_freq = cpu_clock_freq;
220 else
221 const_clock_freq = calc_const_freq();
222
223 init_offset = -(drdtime() - csr_read64(LOONGARCH_CSR_CNTC));
224
225 constant_clockevent_init();
226 constant_clocksource_init();
227}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Common time service routines for LoongArch machines.
4 *
5 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
6 */
7#include <linux/clockchips.h>
8#include <linux/delay.h>
9#include <linux/export.h>
10#include <linux/init.h>
11#include <linux/interrupt.h>
12#include <linux/kernel.h>
13#include <linux/sched_clock.h>
14#include <linux/spinlock.h>
15
16#include <asm/cpu-features.h>
17#include <asm/loongarch.h>
18#include <asm/time.h>
19
20u64 cpu_clock_freq;
21EXPORT_SYMBOL(cpu_clock_freq);
22u64 const_clock_freq;
23EXPORT_SYMBOL(const_clock_freq);
24
25static DEFINE_RAW_SPINLOCK(state_lock);
26static DEFINE_PER_CPU(struct clock_event_device, constant_clockevent_device);
27
28static void constant_event_handler(struct clock_event_device *dev)
29{
30}
31
32irqreturn_t constant_timer_interrupt(int irq, void *data)
33{
34 int cpu = smp_processor_id();
35 struct clock_event_device *cd;
36
37 /* Clear Timer Interrupt */
38 write_csr_tintclear(CSR_TINTCLR_TI);
39 cd = &per_cpu(constant_clockevent_device, cpu);
40 cd->event_handler(cd);
41
42 return IRQ_HANDLED;
43}
44
45static int constant_set_state_oneshot(struct clock_event_device *evt)
46{
47 unsigned long timer_config;
48
49 raw_spin_lock(&state_lock);
50
51 timer_config = csr_read64(LOONGARCH_CSR_TCFG);
52 timer_config |= CSR_TCFG_EN;
53 timer_config &= ~CSR_TCFG_PERIOD;
54 csr_write64(timer_config, LOONGARCH_CSR_TCFG);
55
56 raw_spin_unlock(&state_lock);
57
58 return 0;
59}
60
61static int constant_set_state_oneshot_stopped(struct clock_event_device *evt)
62{
63 unsigned long timer_config;
64
65 raw_spin_lock(&state_lock);
66
67 timer_config = csr_read64(LOONGARCH_CSR_TCFG);
68 timer_config &= ~CSR_TCFG_EN;
69 csr_write64(timer_config, LOONGARCH_CSR_TCFG);
70
71 raw_spin_unlock(&state_lock);
72
73 return 0;
74}
75
76static int constant_set_state_periodic(struct clock_event_device *evt)
77{
78 unsigned long period;
79 unsigned long timer_config;
80
81 raw_spin_lock(&state_lock);
82
83 period = const_clock_freq / HZ;
84 timer_config = period & CSR_TCFG_VAL;
85 timer_config |= (CSR_TCFG_PERIOD | CSR_TCFG_EN);
86 csr_write64(timer_config, LOONGARCH_CSR_TCFG);
87
88 raw_spin_unlock(&state_lock);
89
90 return 0;
91}
92
93static int constant_set_state_shutdown(struct clock_event_device *evt)
94{
95 return 0;
96}
97
98static int constant_timer_next_event(unsigned long delta, struct clock_event_device *evt)
99{
100 unsigned long timer_config;
101
102 delta &= CSR_TCFG_VAL;
103 timer_config = delta | CSR_TCFG_EN;
104 csr_write64(timer_config, LOONGARCH_CSR_TCFG);
105
106 return 0;
107}
108
109static unsigned long __init get_loops_per_jiffy(void)
110{
111 unsigned long lpj = (unsigned long)const_clock_freq;
112
113 do_div(lpj, HZ);
114
115 return lpj;
116}
117
118static long init_offset __nosavedata;
119
120void save_counter(void)
121{
122 init_offset = drdtime();
123}
124
125void sync_counter(void)
126{
127 /* Ensure counter begin at 0 */
128 csr_write64(init_offset, LOONGARCH_CSR_CNTC);
129}
130
131static int get_timer_irq(void)
132{
133 struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
134
135 if (d)
136 return irq_create_mapping(d, EXCCODE_TIMER - EXCCODE_INT_START);
137
138 return -EINVAL;
139}
140
141int constant_clockevent_init(void)
142{
143 int irq;
144 unsigned int cpu = smp_processor_id();
145 unsigned long min_delta = 0x600;
146 unsigned long max_delta = (1UL << 48) - 1;
147 struct clock_event_device *cd;
148 static int timer_irq_installed = 0;
149
150 irq = get_timer_irq();
151 if (irq < 0)
152 pr_err("Failed to map irq %d (timer)\n", irq);
153
154 cd = &per_cpu(constant_clockevent_device, cpu);
155
156 cd->name = "Constant";
157 cd->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_PERCPU;
158
159 cd->irq = irq;
160 cd->rating = 320;
161 cd->cpumask = cpumask_of(cpu);
162 cd->set_state_oneshot = constant_set_state_oneshot;
163 cd->set_state_oneshot_stopped = constant_set_state_oneshot_stopped;
164 cd->set_state_periodic = constant_set_state_periodic;
165 cd->set_state_shutdown = constant_set_state_shutdown;
166 cd->set_next_event = constant_timer_next_event;
167 cd->event_handler = constant_event_handler;
168
169 clockevents_config_and_register(cd, const_clock_freq, min_delta, max_delta);
170
171 if (timer_irq_installed)
172 return 0;
173
174 timer_irq_installed = 1;
175
176 sync_counter();
177
178 if (request_irq(irq, constant_timer_interrupt, IRQF_PERCPU | IRQF_TIMER, "timer", NULL))
179 pr_err("Failed to request irq %d (timer)\n", irq);
180
181 lpj_fine = get_loops_per_jiffy();
182 pr_info("Constant clock event device register\n");
183
184 return 0;
185}
186
187static u64 read_const_counter(struct clocksource *clk)
188{
189 return drdtime();
190}
191
192static u64 native_sched_clock(void)
193{
194 return read_const_counter(NULL);
195}
196
197static struct clocksource clocksource_const = {
198 .name = "Constant",
199 .rating = 400,
200 .read = read_const_counter,
201 .mask = CLOCKSOURCE_MASK(64),
202 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
203 .vdso_clock_mode = VDSO_CLOCKMODE_CPU,
204};
205
206int __init constant_clocksource_init(void)
207{
208 int res;
209 unsigned long freq = const_clock_freq;
210
211 res = clocksource_register_hz(&clocksource_const, freq);
212
213 sched_clock_register(native_sched_clock, 64, freq);
214
215 pr_info("Constant clock source device register\n");
216
217 return res;
218}
219
220void __init time_init(void)
221{
222 if (!cpu_has_cpucfg)
223 const_clock_freq = cpu_clock_freq;
224 else
225 const_clock_freq = calc_const_freq();
226
227 init_offset = -(drdtime() - csr_read64(LOONGARCH_CSR_CNTC));
228
229 constant_clockevent_init();
230 constant_clocksource_init();
231}