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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dwc3-pci.c - PCI Specific glue layer
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/slab.h>
14#include <linux/pci.h>
15#include <linux/workqueue.h>
16#include <linux/pm_runtime.h>
17#include <linux/platform_device.h>
18#include <linux/gpio/consumer.h>
19#include <linux/gpio/machine.h>
20#include <linux/acpi.h>
21#include <linux/delay.h>
22
23#define PCI_DEVICE_ID_INTEL_BYT 0x0f37
24#define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
25#define PCI_DEVICE_ID_INTEL_BSW 0x22b7
26#define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
27#define PCI_DEVICE_ID_INTEL_SPTH 0xa130
28#define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
29#define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
30#define PCI_DEVICE_ID_INTEL_APL 0x5aaa
31#define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
32#define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee
33#define PCI_DEVICE_ID_INTEL_CMLH 0x06ee
34#define PCI_DEVICE_ID_INTEL_GLK 0x31aa
35#define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee
36#define PCI_DEVICE_ID_INTEL_CNPH 0xa36e
37#define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0
38#define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee
39#define PCI_DEVICE_ID_INTEL_EHL 0x4b7e
40#define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee
41#define PCI_DEVICE_ID_INTEL_TGPH 0x43ee
42#define PCI_DEVICE_ID_INTEL_JSP 0x4dee
43#define PCI_DEVICE_ID_INTEL_ADL 0x460e
44#define PCI_DEVICE_ID_INTEL_ADL_PCH 0x51ee
45#define PCI_DEVICE_ID_INTEL_ADLN 0x465e
46#define PCI_DEVICE_ID_INTEL_ADLN_PCH 0x54ee
47#define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1
48#define PCI_DEVICE_ID_INTEL_RPL 0xa70e
49#define PCI_DEVICE_ID_INTEL_RPLS 0x7a61
50#define PCI_DEVICE_ID_INTEL_MTLM 0x7eb1
51#define PCI_DEVICE_ID_INTEL_MTLP 0x7ec1
52#define PCI_DEVICE_ID_INTEL_MTLS 0x7f6f
53#define PCI_DEVICE_ID_INTEL_MTL 0x7e7e
54#define PCI_DEVICE_ID_INTEL_ARLH 0x7ec1
55#define PCI_DEVICE_ID_INTEL_ARLH_PCH 0x777e
56#define PCI_DEVICE_ID_INTEL_TGL 0x9a15
57#define PCI_DEVICE_ID_AMD_MR 0x163a
58
59#define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
60#define PCI_INTEL_BXT_FUNC_PMU_PWR 4
61#define PCI_INTEL_BXT_STATE_D0 0
62#define PCI_INTEL_BXT_STATE_D3 3
63
64#define GP_RWBAR 1
65#define GP_RWREG1 0xa0
66#define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17)
67
68/**
69 * struct dwc3_pci - Driver private structure
70 * @dwc3: child dwc3 platform_device
71 * @pci: our link to PCI bus
72 * @guid: _DSM GUID
73 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
74 * @wakeup_work: work for asynchronous resume
75 */
76struct dwc3_pci {
77 struct platform_device *dwc3;
78 struct pci_dev *pci;
79
80 guid_t guid;
81
82 unsigned int has_dsm_for_pm:1;
83 struct work_struct wakeup_work;
84};
85
86static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
87static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
88
89static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
90 { "reset-gpios", &reset_gpios, 1 },
91 { "cs-gpios", &cs_gpios, 1 },
92 { },
93};
94
95static struct gpiod_lookup_table platform_bytcr_gpios = {
96 .dev_id = "0000:00:16.0",
97 .table = {
98 GPIO_LOOKUP("INT33FC:00", 54, "cs", GPIO_ACTIVE_HIGH),
99 GPIO_LOOKUP("INT33FC:02", 14, "reset", GPIO_ACTIVE_HIGH),
100 {}
101 },
102};
103
104static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
105{
106 void __iomem *reg;
107 u32 value;
108
109 reg = pcim_iomap(pci, GP_RWBAR, 0);
110 if (!reg)
111 return -ENOMEM;
112
113 value = readl(reg + GP_RWREG1);
114 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
115 goto unmap; /* ULPI refclk already enabled */
116
117 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
118 writel(value, reg + GP_RWREG1);
119 /* This comes from the Intel Android x86 tree w/o any explanation */
120 msleep(100);
121unmap:
122 pcim_iounmap(pci, reg);
123 return 0;
124}
125
126static const struct property_entry dwc3_pci_intel_properties[] = {
127 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
128 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
129 {}
130};
131
132static const struct property_entry dwc3_pci_intel_phy_charger_detect_properties[] = {
133 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
134 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
135 PROPERTY_ENTRY_BOOL("linux,phy_charger_detect"),
136 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
137 {}
138};
139
140static const struct property_entry dwc3_pci_intel_byt_properties[] = {
141 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
142 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
143 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
144 {}
145};
146
147static const struct property_entry dwc3_pci_mrfld_properties[] = {
148 PROPERTY_ENTRY_STRING("dr_mode", "otg"),
149 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"),
150 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
151 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
152 PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"),
153 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
154 {}
155};
156
157static const struct property_entry dwc3_pci_amd_properties[] = {
158 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
159 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
160 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
161 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
162 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
163 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
164 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
165 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
166 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
167 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
168 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
169 /* FIXME these quirks should be removed when AMD NL tapes out */
170 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
171 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
172 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
173 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
174 {}
175};
176
177static const struct property_entry dwc3_pci_mr_properties[] = {
178 PROPERTY_ENTRY_STRING("dr_mode", "otg"),
179 PROPERTY_ENTRY_BOOL("usb-role-switch"),
180 PROPERTY_ENTRY_STRING("role-switch-default-mode", "host"),
181 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
182 {}
183};
184
185static const struct software_node dwc3_pci_intel_swnode = {
186 .properties = dwc3_pci_intel_properties,
187};
188
189static const struct software_node dwc3_pci_intel_phy_charger_detect_swnode = {
190 .properties = dwc3_pci_intel_phy_charger_detect_properties,
191};
192
193static const struct software_node dwc3_pci_intel_byt_swnode = {
194 .properties = dwc3_pci_intel_byt_properties,
195};
196
197static const struct software_node dwc3_pci_intel_mrfld_swnode = {
198 .properties = dwc3_pci_mrfld_properties,
199};
200
201static const struct software_node dwc3_pci_amd_swnode = {
202 .properties = dwc3_pci_amd_properties,
203};
204
205static const struct software_node dwc3_pci_amd_mr_swnode = {
206 .properties = dwc3_pci_mr_properties,
207};
208
209static int dwc3_pci_quirks(struct dwc3_pci *dwc,
210 const struct software_node *swnode)
211{
212 struct pci_dev *pdev = dwc->pci;
213
214 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
215 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
216 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M ||
217 pdev->device == PCI_DEVICE_ID_INTEL_EHL) {
218 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
219 dwc->has_dsm_for_pm = true;
220 }
221
222 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
223 struct gpio_desc *gpio;
224 int ret;
225
226 /* On BYT the FW does not always enable the refclock */
227 ret = dwc3_byt_enable_ulpi_refclock(pdev);
228 if (ret)
229 return ret;
230
231 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
232 acpi_dwc3_byt_gpios);
233 if (ret)
234 dev_dbg(&pdev->dev, "failed to add mapping table\n");
235
236 /*
237 * A lot of BYT devices lack ACPI resource entries for
238 * the GPIOs. If the ACPI entry for the GPIO controller
239 * is present add a fallback mapping to the reference
240 * design GPIOs which all boards seem to use.
241 */
242 if (acpi_dev_present("INT33FC", NULL, -1))
243 gpiod_add_lookup_table(&platform_bytcr_gpios);
244
245 /*
246 * These GPIOs will turn on the USB2 PHY. Note that we have to
247 * put the gpio descriptors again here because the phy driver
248 * might want to grab them, too.
249 */
250 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
251 if (IS_ERR(gpio))
252 return PTR_ERR(gpio);
253
254 gpiod_set_value_cansleep(gpio, 1);
255 gpiod_put(gpio);
256
257 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
258 if (IS_ERR(gpio))
259 return PTR_ERR(gpio);
260
261 if (gpio) {
262 gpiod_set_value_cansleep(gpio, 1);
263 gpiod_put(gpio);
264 usleep_range(10000, 11000);
265 }
266
267 /*
268 * Make the pdev name predictable (only 1 DWC3 on BYT)
269 * and patch the phy dev-name into the lookup table so
270 * that the phy-driver can get the GPIOs.
271 */
272 dwc->dwc3->id = PLATFORM_DEVID_NONE;
273 platform_bytcr_gpios.dev_id = "dwc3.ulpi";
274
275 /*
276 * Some Android tablets with a Crystal Cove PMIC
277 * (INT33FD), rely on the TUSB1211 phy for charger
278 * detection. These can be identified by them _not_
279 * using the standard ACPI battery and ac drivers.
280 */
281 if (acpi_dev_present("INT33FD", "1", 2) &&
282 acpi_quirk_skip_acpi_ac_and_battery()) {
283 dev_info(&pdev->dev, "Using TUSB1211 phy for charger detection\n");
284 swnode = &dwc3_pci_intel_phy_charger_detect_swnode;
285 }
286 }
287 }
288
289 return device_add_software_node(&dwc->dwc3->dev, swnode);
290}
291
292#ifdef CONFIG_PM
293static void dwc3_pci_resume_work(struct work_struct *work)
294{
295 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
296 struct platform_device *dwc3 = dwc->dwc3;
297 int ret;
298
299 ret = pm_runtime_get_sync(&dwc3->dev);
300 if (ret < 0) {
301 pm_runtime_put_sync_autosuspend(&dwc3->dev);
302 return;
303 }
304
305 pm_runtime_mark_last_busy(&dwc3->dev);
306 pm_runtime_put_sync_autosuspend(&dwc3->dev);
307}
308#endif
309
310static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
311{
312 struct dwc3_pci *dwc;
313 struct resource res[2];
314 int ret;
315 struct device *dev = &pci->dev;
316
317 ret = pcim_enable_device(pci);
318 if (ret) {
319 dev_err(dev, "failed to enable pci device\n");
320 return -ENODEV;
321 }
322
323 pci_set_master(pci);
324
325 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
326 if (!dwc)
327 return -ENOMEM;
328
329 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
330 if (!dwc->dwc3)
331 return -ENOMEM;
332
333 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
334
335 res[0].start = pci_resource_start(pci, 0);
336 res[0].end = pci_resource_end(pci, 0);
337 res[0].name = "dwc_usb3";
338 res[0].flags = IORESOURCE_MEM;
339
340 res[1].start = pci->irq;
341 res[1].name = "dwc_usb3";
342 res[1].flags = IORESOURCE_IRQ;
343
344 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
345 if (ret) {
346 dev_err(dev, "couldn't add resources to dwc3 device\n");
347 goto err;
348 }
349
350 dwc->pci = pci;
351 dwc->dwc3->dev.parent = dev;
352 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
353
354 ret = dwc3_pci_quirks(dwc, (void *)id->driver_data);
355 if (ret)
356 goto err;
357
358 ret = platform_device_add(dwc->dwc3);
359 if (ret) {
360 dev_err(dev, "failed to register dwc3 device\n");
361 goto err;
362 }
363
364 device_init_wakeup(dev, true);
365 pci_set_drvdata(pci, dwc);
366 pm_runtime_put(dev);
367#ifdef CONFIG_PM
368 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
369#endif
370
371 return 0;
372err:
373 device_remove_software_node(&dwc->dwc3->dev);
374 platform_device_put(dwc->dwc3);
375 return ret;
376}
377
378static void dwc3_pci_remove(struct pci_dev *pci)
379{
380 struct dwc3_pci *dwc = pci_get_drvdata(pci);
381 struct pci_dev *pdev = dwc->pci;
382
383 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
384 gpiod_remove_lookup_table(&platform_bytcr_gpios);
385#ifdef CONFIG_PM
386 cancel_work_sync(&dwc->wakeup_work);
387#endif
388 device_init_wakeup(&pci->dev, false);
389 pm_runtime_get(&pci->dev);
390 device_remove_software_node(&dwc->dwc3->dev);
391 platform_device_unregister(dwc->dwc3);
392}
393
394static const struct pci_device_id dwc3_pci_id_table[] = {
395 { PCI_DEVICE_DATA(INTEL, BSW, &dwc3_pci_intel_swnode) },
396 { PCI_DEVICE_DATA(INTEL, BYT, &dwc3_pci_intel_byt_swnode) },
397 { PCI_DEVICE_DATA(INTEL, MRFLD, &dwc3_pci_intel_mrfld_swnode) },
398 { PCI_DEVICE_DATA(INTEL, CMLLP, &dwc3_pci_intel_swnode) },
399 { PCI_DEVICE_DATA(INTEL, CMLH, &dwc3_pci_intel_swnode) },
400 { PCI_DEVICE_DATA(INTEL, SPTLP, &dwc3_pci_intel_swnode) },
401 { PCI_DEVICE_DATA(INTEL, SPTH, &dwc3_pci_intel_swnode) },
402 { PCI_DEVICE_DATA(INTEL, BXT, &dwc3_pci_intel_swnode) },
403 { PCI_DEVICE_DATA(INTEL, BXT_M, &dwc3_pci_intel_swnode) },
404 { PCI_DEVICE_DATA(INTEL, APL, &dwc3_pci_intel_swnode) },
405 { PCI_DEVICE_DATA(INTEL, KBP, &dwc3_pci_intel_swnode) },
406 { PCI_DEVICE_DATA(INTEL, GLK, &dwc3_pci_intel_swnode) },
407 { PCI_DEVICE_DATA(INTEL, CNPLP, &dwc3_pci_intel_swnode) },
408 { PCI_DEVICE_DATA(INTEL, CNPH, &dwc3_pci_intel_swnode) },
409 { PCI_DEVICE_DATA(INTEL, CNPV, &dwc3_pci_intel_swnode) },
410 { PCI_DEVICE_DATA(INTEL, ICLLP, &dwc3_pci_intel_swnode) },
411 { PCI_DEVICE_DATA(INTEL, EHL, &dwc3_pci_intel_swnode) },
412 { PCI_DEVICE_DATA(INTEL, TGPLP, &dwc3_pci_intel_swnode) },
413 { PCI_DEVICE_DATA(INTEL, TGPH, &dwc3_pci_intel_swnode) },
414 { PCI_DEVICE_DATA(INTEL, JSP, &dwc3_pci_intel_swnode) },
415 { PCI_DEVICE_DATA(INTEL, ADL, &dwc3_pci_intel_swnode) },
416 { PCI_DEVICE_DATA(INTEL, ADL_PCH, &dwc3_pci_intel_swnode) },
417 { PCI_DEVICE_DATA(INTEL, ADLN, &dwc3_pci_intel_swnode) },
418 { PCI_DEVICE_DATA(INTEL, ADLN_PCH, &dwc3_pci_intel_swnode) },
419 { PCI_DEVICE_DATA(INTEL, ADLS, &dwc3_pci_intel_swnode) },
420 { PCI_DEVICE_DATA(INTEL, RPL, &dwc3_pci_intel_swnode) },
421 { PCI_DEVICE_DATA(INTEL, RPLS, &dwc3_pci_intel_swnode) },
422 { PCI_DEVICE_DATA(INTEL, MTLM, &dwc3_pci_intel_swnode) },
423 { PCI_DEVICE_DATA(INTEL, MTLP, &dwc3_pci_intel_swnode) },
424 { PCI_DEVICE_DATA(INTEL, MTL, &dwc3_pci_intel_swnode) },
425 { PCI_DEVICE_DATA(INTEL, MTLS, &dwc3_pci_intel_swnode) },
426 { PCI_DEVICE_DATA(INTEL, ARLH, &dwc3_pci_intel_swnode) },
427 { PCI_DEVICE_DATA(INTEL, ARLH_PCH, &dwc3_pci_intel_swnode) },
428 { PCI_DEVICE_DATA(INTEL, TGL, &dwc3_pci_intel_swnode) },
429
430 { PCI_DEVICE_DATA(AMD, NL_USB, &dwc3_pci_amd_swnode) },
431 { PCI_DEVICE_DATA(AMD, MR, &dwc3_pci_amd_mr_swnode) },
432
433 { } /* Terminating Entry */
434};
435MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
436
437#if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
438static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
439{
440 union acpi_object *obj;
441 union acpi_object tmp;
442 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
443
444 if (!dwc->has_dsm_for_pm)
445 return 0;
446
447 tmp.type = ACPI_TYPE_INTEGER;
448 tmp.integer.value = param;
449
450 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
451 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
452 if (!obj) {
453 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
454 return -EIO;
455 }
456
457 ACPI_FREE(obj);
458
459 return 0;
460}
461#endif /* CONFIG_PM || CONFIG_PM_SLEEP */
462
463#ifdef CONFIG_PM
464static int dwc3_pci_runtime_suspend(struct device *dev)
465{
466 struct dwc3_pci *dwc = dev_get_drvdata(dev);
467
468 if (device_can_wakeup(dev))
469 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
470
471 return -EBUSY;
472}
473
474static int dwc3_pci_runtime_resume(struct device *dev)
475{
476 struct dwc3_pci *dwc = dev_get_drvdata(dev);
477 int ret;
478
479 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
480 if (ret)
481 return ret;
482
483 queue_work(pm_wq, &dwc->wakeup_work);
484
485 return 0;
486}
487#endif /* CONFIG_PM */
488
489#ifdef CONFIG_PM_SLEEP
490static int dwc3_pci_suspend(struct device *dev)
491{
492 struct dwc3_pci *dwc = dev_get_drvdata(dev);
493
494 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
495}
496
497static int dwc3_pci_resume(struct device *dev)
498{
499 struct dwc3_pci *dwc = dev_get_drvdata(dev);
500
501 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
502}
503#endif /* CONFIG_PM_SLEEP */
504
505static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
506 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
507 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
508 NULL)
509};
510
511static struct pci_driver dwc3_pci_driver = {
512 .name = "dwc3-pci",
513 .id_table = dwc3_pci_id_table,
514 .probe = dwc3_pci_probe,
515 .remove = dwc3_pci_remove,
516 .driver = {
517 .pm = &dwc3_pci_dev_pm_ops,
518 }
519};
520
521MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
522MODULE_LICENSE("GPL v2");
523MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
524
525module_pci_driver(dwc3_pci_driver);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dwc3-pci.c - PCI Specific glue layer
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/dmi.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/slab.h>
15#include <linux/pci.h>
16#include <linux/workqueue.h>
17#include <linux/pm_runtime.h>
18#include <linux/platform_device.h>
19#include <linux/gpio/consumer.h>
20#include <linux/gpio/machine.h>
21#include <linux/acpi.h>
22#include <linux/delay.h>
23
24#define PCI_DEVICE_ID_INTEL_BYT 0x0f37
25#define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
26#define PCI_DEVICE_ID_INTEL_BSW 0x22b7
27#define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
28#define PCI_DEVICE_ID_INTEL_SPTH 0xa130
29#define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
30#define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
31#define PCI_DEVICE_ID_INTEL_APL 0x5aaa
32#define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
33#define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee
34#define PCI_DEVICE_ID_INTEL_CMLH 0x06ee
35#define PCI_DEVICE_ID_INTEL_GLK 0x31aa
36#define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee
37#define PCI_DEVICE_ID_INTEL_CNPH 0xa36e
38#define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0
39#define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee
40#define PCI_DEVICE_ID_INTEL_EHL 0x4b7e
41#define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee
42#define PCI_DEVICE_ID_INTEL_TGPH 0x43ee
43#define PCI_DEVICE_ID_INTEL_JSP 0x4dee
44#define PCI_DEVICE_ID_INTEL_ADL 0x460e
45#define PCI_DEVICE_ID_INTEL_ADL_PCH 0x51ee
46#define PCI_DEVICE_ID_INTEL_ADLN 0x465e
47#define PCI_DEVICE_ID_INTEL_ADLN_PCH 0x54ee
48#define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1
49#define PCI_DEVICE_ID_INTEL_RPL 0xa70e
50#define PCI_DEVICE_ID_INTEL_RPLS 0x7a61
51#define PCI_DEVICE_ID_INTEL_MTLM 0x7eb1
52#define PCI_DEVICE_ID_INTEL_MTLP 0x7ec1
53#define PCI_DEVICE_ID_INTEL_MTLS 0x7f6f
54#define PCI_DEVICE_ID_INTEL_MTL 0x7e7e
55#define PCI_DEVICE_ID_INTEL_ARLH_PCH 0x777e
56#define PCI_DEVICE_ID_INTEL_TGL 0x9a15
57#define PCI_DEVICE_ID_INTEL_PTLH 0xe332
58#define PCI_DEVICE_ID_INTEL_PTLH_PCH 0xe37e
59#define PCI_DEVICE_ID_INTEL_PTLU 0xe432
60#define PCI_DEVICE_ID_INTEL_PTLU_PCH 0xe47e
61#define PCI_DEVICE_ID_AMD_MR 0x163a
62
63#define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
64#define PCI_INTEL_BXT_FUNC_PMU_PWR 4
65#define PCI_INTEL_BXT_STATE_D0 0
66#define PCI_INTEL_BXT_STATE_D3 3
67
68#define GP_RWBAR 1
69#define GP_RWREG1 0xa0
70#define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17)
71
72/**
73 * struct dwc3_pci - Driver private structure
74 * @dwc3: child dwc3 platform_device
75 * @pci: our link to PCI bus
76 * @guid: _DSM GUID
77 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
78 * @wakeup_work: work for asynchronous resume
79 */
80struct dwc3_pci {
81 struct platform_device *dwc3;
82 struct pci_dev *pci;
83
84 guid_t guid;
85
86 unsigned int has_dsm_for_pm:1;
87 struct work_struct wakeup_work;
88};
89
90static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
91static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
92
93static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
94 { "reset-gpios", &reset_gpios, 1 },
95 { "cs-gpios", &cs_gpios, 1 },
96 { },
97};
98
99static struct gpiod_lookup_table platform_bytcr_gpios = {
100 .dev_id = "0000:00:16.0",
101 .table = {
102 GPIO_LOOKUP("INT33FC:00", 54, "cs", GPIO_ACTIVE_HIGH),
103 GPIO_LOOKUP("INT33FC:02", 14, "reset", GPIO_ACTIVE_HIGH),
104 {}
105 },
106};
107
108static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
109{
110 void __iomem *reg;
111 u32 value;
112
113 reg = pcim_iomap(pci, GP_RWBAR, 0);
114 if (!reg)
115 return -ENOMEM;
116
117 value = readl(reg + GP_RWREG1);
118 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
119 goto unmap; /* ULPI refclk already enabled */
120
121 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
122 writel(value, reg + GP_RWREG1);
123 /* This comes from the Intel Android x86 tree w/o any explanation */
124 msleep(100);
125unmap:
126 pcim_iounmap(pci, reg);
127 return 0;
128}
129
130static const struct property_entry dwc3_pci_intel_properties[] = {
131 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
132 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
133 {}
134};
135
136static const struct property_entry dwc3_pci_intel_phy_charger_detect_properties[] = {
137 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
138 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
139 PROPERTY_ENTRY_BOOL("linux,phy_charger_detect"),
140 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
141 {}
142};
143
144static const struct property_entry dwc3_pci_intel_byt_properties[] = {
145 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
146 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
147 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
148 {}
149};
150
151static const struct property_entry dwc3_pci_mrfld_properties[] = {
152 PROPERTY_ENTRY_STRING("dr_mode", "otg"),
153 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"),
154 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
155 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
156 PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"),
157 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
158 {}
159};
160
161static const struct property_entry dwc3_pci_amd_properties[] = {
162 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
163 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
164 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
165 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
166 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
167 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
168 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
169 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
170 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
171 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
172 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
173 /* FIXME these quirks should be removed when AMD NL tapes out */
174 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
175 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
176 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
177 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
178 {}
179};
180
181static const struct property_entry dwc3_pci_mr_properties[] = {
182 PROPERTY_ENTRY_STRING("dr_mode", "otg"),
183 PROPERTY_ENTRY_BOOL("usb-role-switch"),
184 PROPERTY_ENTRY_STRING("role-switch-default-mode", "host"),
185 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
186 {}
187};
188
189static const struct software_node dwc3_pci_intel_swnode = {
190 .properties = dwc3_pci_intel_properties,
191};
192
193static const struct software_node dwc3_pci_intel_phy_charger_detect_swnode = {
194 .properties = dwc3_pci_intel_phy_charger_detect_properties,
195};
196
197static const struct software_node dwc3_pci_intel_byt_swnode = {
198 .properties = dwc3_pci_intel_byt_properties,
199};
200
201static const struct software_node dwc3_pci_intel_mrfld_swnode = {
202 .properties = dwc3_pci_mrfld_properties,
203};
204
205static const struct software_node dwc3_pci_amd_swnode = {
206 .properties = dwc3_pci_amd_properties,
207};
208
209static const struct software_node dwc3_pci_amd_mr_swnode = {
210 .properties = dwc3_pci_mr_properties,
211};
212
213static int dwc3_pci_quirks(struct dwc3_pci *dwc,
214 const struct software_node *swnode)
215{
216 struct pci_dev *pdev = dwc->pci;
217
218 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
219 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
220 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M ||
221 pdev->device == PCI_DEVICE_ID_INTEL_EHL) {
222 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
223 dwc->has_dsm_for_pm = true;
224 }
225
226 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
227 struct gpio_desc *gpio;
228 const char *bios_ver;
229 int ret;
230
231 /* On BYT the FW does not always enable the refclock */
232 ret = dwc3_byt_enable_ulpi_refclock(pdev);
233 if (ret)
234 return ret;
235
236 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
237 acpi_dwc3_byt_gpios);
238 if (ret)
239 dev_dbg(&pdev->dev, "failed to add mapping table\n");
240
241 /*
242 * A lot of BYT devices lack ACPI resource entries for
243 * the GPIOs. If the ACPI entry for the GPIO controller
244 * is present add a fallback mapping to the reference
245 * design GPIOs which all boards seem to use.
246 */
247 if (acpi_dev_present("INT33FC", NULL, -1))
248 gpiod_add_lookup_table(&platform_bytcr_gpios);
249
250 /*
251 * These GPIOs will turn on the USB2 PHY. Note that we have to
252 * put the gpio descriptors again here because the phy driver
253 * might want to grab them, too.
254 */
255 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
256 if (IS_ERR(gpio))
257 return PTR_ERR(gpio);
258
259 gpiod_set_value_cansleep(gpio, 1);
260 gpiod_put(gpio);
261
262 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
263 if (IS_ERR(gpio))
264 return PTR_ERR(gpio);
265
266 if (gpio) {
267 gpiod_set_value_cansleep(gpio, 1);
268 gpiod_put(gpio);
269 usleep_range(10000, 11000);
270 }
271
272 /*
273 * Make the pdev name predictable (only 1 DWC3 on BYT)
274 * and patch the phy dev-name into the lookup table so
275 * that the phy-driver can get the GPIOs.
276 */
277 dwc->dwc3->id = PLATFORM_DEVID_NONE;
278 platform_bytcr_gpios.dev_id = "dwc3.ulpi";
279
280 /*
281 * Some Android tablets with a Crystal Cove PMIC
282 * (INT33FD), rely on the TUSB1211 phy for charger
283 * detection. These can be identified by them _not_
284 * using the standard ACPI battery and ac drivers.
285 */
286 bios_ver = dmi_get_system_info(DMI_BIOS_VERSION);
287 if (acpi_dev_present("INT33FD", "1", 2) &&
288 acpi_quirk_skip_acpi_ac_and_battery() &&
289 /* Lenovo Yoga Tablet 2 Pro 1380 uses LC824206XA instead */
290 !(bios_ver &&
291 strstarts(bios_ver, "BLADE_21.X64.0005.R00.1504101516"))) {
292 dev_info(&pdev->dev, "Using TUSB1211 phy for charger detection\n");
293 swnode = &dwc3_pci_intel_phy_charger_detect_swnode;
294 }
295 }
296 }
297
298 return device_add_software_node(&dwc->dwc3->dev, swnode);
299}
300
301#ifdef CONFIG_PM
302static void dwc3_pci_resume_work(struct work_struct *work)
303{
304 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
305 struct platform_device *dwc3 = dwc->dwc3;
306 int ret;
307
308 ret = pm_runtime_get_sync(&dwc3->dev);
309 if (ret < 0) {
310 pm_runtime_put_sync_autosuspend(&dwc3->dev);
311 return;
312 }
313
314 pm_runtime_mark_last_busy(&dwc3->dev);
315 pm_runtime_put_sync_autosuspend(&dwc3->dev);
316}
317#endif
318
319static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
320{
321 struct dwc3_pci *dwc;
322 struct resource res[2];
323 int ret;
324 struct device *dev = &pci->dev;
325
326 ret = pcim_enable_device(pci);
327 if (ret) {
328 dev_err(dev, "failed to enable pci device\n");
329 return -ENODEV;
330 }
331
332 pci_set_master(pci);
333
334 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
335 if (!dwc)
336 return -ENOMEM;
337
338 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
339 if (!dwc->dwc3)
340 return -ENOMEM;
341
342 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
343
344 res[0].start = pci_resource_start(pci, 0);
345 res[0].end = pci_resource_end(pci, 0);
346 res[0].name = "dwc_usb3";
347 res[0].flags = IORESOURCE_MEM;
348
349 res[1].start = pci->irq;
350 res[1].name = "dwc_usb3";
351 res[1].flags = IORESOURCE_IRQ;
352
353 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
354 if (ret) {
355 dev_err(dev, "couldn't add resources to dwc3 device\n");
356 goto err;
357 }
358
359 dwc->pci = pci;
360 dwc->dwc3->dev.parent = dev;
361 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
362
363 ret = dwc3_pci_quirks(dwc, (void *)id->driver_data);
364 if (ret)
365 goto err;
366
367 ret = platform_device_add(dwc->dwc3);
368 if (ret) {
369 dev_err(dev, "failed to register dwc3 device\n");
370 goto err;
371 }
372
373 device_init_wakeup(dev, true);
374 pci_set_drvdata(pci, dwc);
375 pm_runtime_put(dev);
376#ifdef CONFIG_PM
377 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
378#endif
379
380 return 0;
381err:
382 device_remove_software_node(&dwc->dwc3->dev);
383 platform_device_put(dwc->dwc3);
384 return ret;
385}
386
387static void dwc3_pci_remove(struct pci_dev *pci)
388{
389 struct dwc3_pci *dwc = pci_get_drvdata(pci);
390 struct pci_dev *pdev = dwc->pci;
391
392 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
393 gpiod_remove_lookup_table(&platform_bytcr_gpios);
394#ifdef CONFIG_PM
395 cancel_work_sync(&dwc->wakeup_work);
396#endif
397 device_init_wakeup(&pci->dev, false);
398 pm_runtime_get(&pci->dev);
399 device_remove_software_node(&dwc->dwc3->dev);
400 platform_device_unregister(dwc->dwc3);
401}
402
403static const struct pci_device_id dwc3_pci_id_table[] = {
404 { PCI_DEVICE_DATA(INTEL, BSW, &dwc3_pci_intel_swnode) },
405 { PCI_DEVICE_DATA(INTEL, BYT, &dwc3_pci_intel_byt_swnode) },
406 { PCI_DEVICE_DATA(INTEL, MRFLD, &dwc3_pci_intel_mrfld_swnode) },
407 { PCI_DEVICE_DATA(INTEL, CMLLP, &dwc3_pci_intel_swnode) },
408 { PCI_DEVICE_DATA(INTEL, CMLH, &dwc3_pci_intel_swnode) },
409 { PCI_DEVICE_DATA(INTEL, SPTLP, &dwc3_pci_intel_swnode) },
410 { PCI_DEVICE_DATA(INTEL, SPTH, &dwc3_pci_intel_swnode) },
411 { PCI_DEVICE_DATA(INTEL, BXT, &dwc3_pci_intel_swnode) },
412 { PCI_DEVICE_DATA(INTEL, BXT_M, &dwc3_pci_intel_swnode) },
413 { PCI_DEVICE_DATA(INTEL, APL, &dwc3_pci_intel_swnode) },
414 { PCI_DEVICE_DATA(INTEL, KBP, &dwc3_pci_intel_swnode) },
415 { PCI_DEVICE_DATA(INTEL, GLK, &dwc3_pci_intel_swnode) },
416 { PCI_DEVICE_DATA(INTEL, CNPLP, &dwc3_pci_intel_swnode) },
417 { PCI_DEVICE_DATA(INTEL, CNPH, &dwc3_pci_intel_swnode) },
418 { PCI_DEVICE_DATA(INTEL, CNPV, &dwc3_pci_intel_swnode) },
419 { PCI_DEVICE_DATA(INTEL, ICLLP, &dwc3_pci_intel_swnode) },
420 { PCI_DEVICE_DATA(INTEL, EHL, &dwc3_pci_intel_swnode) },
421 { PCI_DEVICE_DATA(INTEL, TGPLP, &dwc3_pci_intel_swnode) },
422 { PCI_DEVICE_DATA(INTEL, TGPH, &dwc3_pci_intel_swnode) },
423 { PCI_DEVICE_DATA(INTEL, JSP, &dwc3_pci_intel_swnode) },
424 { PCI_DEVICE_DATA(INTEL, ADL, &dwc3_pci_intel_swnode) },
425 { PCI_DEVICE_DATA(INTEL, ADL_PCH, &dwc3_pci_intel_swnode) },
426 { PCI_DEVICE_DATA(INTEL, ADLN, &dwc3_pci_intel_swnode) },
427 { PCI_DEVICE_DATA(INTEL, ADLN_PCH, &dwc3_pci_intel_swnode) },
428 { PCI_DEVICE_DATA(INTEL, ADLS, &dwc3_pci_intel_swnode) },
429 { PCI_DEVICE_DATA(INTEL, RPL, &dwc3_pci_intel_swnode) },
430 { PCI_DEVICE_DATA(INTEL, RPLS, &dwc3_pci_intel_swnode) },
431 { PCI_DEVICE_DATA(INTEL, MTLM, &dwc3_pci_intel_swnode) },
432 { PCI_DEVICE_DATA(INTEL, MTLP, &dwc3_pci_intel_swnode) },
433 { PCI_DEVICE_DATA(INTEL, MTL, &dwc3_pci_intel_swnode) },
434 { PCI_DEVICE_DATA(INTEL, MTLS, &dwc3_pci_intel_swnode) },
435 { PCI_DEVICE_DATA(INTEL, ARLH_PCH, &dwc3_pci_intel_swnode) },
436 { PCI_DEVICE_DATA(INTEL, TGL, &dwc3_pci_intel_swnode) },
437 { PCI_DEVICE_DATA(INTEL, PTLH, &dwc3_pci_intel_swnode) },
438 { PCI_DEVICE_DATA(INTEL, PTLH_PCH, &dwc3_pci_intel_swnode) },
439 { PCI_DEVICE_DATA(INTEL, PTLU, &dwc3_pci_intel_swnode) },
440 { PCI_DEVICE_DATA(INTEL, PTLU_PCH, &dwc3_pci_intel_swnode) },
441
442 { PCI_DEVICE_DATA(AMD, NL_USB, &dwc3_pci_amd_swnode) },
443 { PCI_DEVICE_DATA(AMD, MR, &dwc3_pci_amd_mr_swnode) },
444
445 { } /* Terminating Entry */
446};
447MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
448
449#if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
450static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
451{
452 union acpi_object *obj;
453 union acpi_object tmp;
454 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
455
456 if (!dwc->has_dsm_for_pm)
457 return 0;
458
459 tmp.type = ACPI_TYPE_INTEGER;
460 tmp.integer.value = param;
461
462 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
463 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
464 if (!obj) {
465 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
466 return -EIO;
467 }
468
469 ACPI_FREE(obj);
470
471 return 0;
472}
473#endif /* CONFIG_PM || CONFIG_PM_SLEEP */
474
475#ifdef CONFIG_PM
476static int dwc3_pci_runtime_suspend(struct device *dev)
477{
478 struct dwc3_pci *dwc = dev_get_drvdata(dev);
479
480 if (device_can_wakeup(dev))
481 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
482
483 return -EBUSY;
484}
485
486static int dwc3_pci_runtime_resume(struct device *dev)
487{
488 struct dwc3_pci *dwc = dev_get_drvdata(dev);
489 int ret;
490
491 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
492 if (ret)
493 return ret;
494
495 queue_work(pm_wq, &dwc->wakeup_work);
496
497 return 0;
498}
499#endif /* CONFIG_PM */
500
501#ifdef CONFIG_PM_SLEEP
502static int dwc3_pci_suspend(struct device *dev)
503{
504 struct dwc3_pci *dwc = dev_get_drvdata(dev);
505
506 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
507}
508
509static int dwc3_pci_resume(struct device *dev)
510{
511 struct dwc3_pci *dwc = dev_get_drvdata(dev);
512
513 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
514}
515#endif /* CONFIG_PM_SLEEP */
516
517static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
518 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
519 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
520 NULL)
521};
522
523static struct pci_driver dwc3_pci_driver = {
524 .name = "dwc3-pci",
525 .id_table = dwc3_pci_id_table,
526 .probe = dwc3_pci_probe,
527 .remove = dwc3_pci_remove,
528 .driver = {
529 .pm = &dwc3_pci_dev_pm_ops,
530 }
531};
532
533MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
534MODULE_LICENSE("GPL v2");
535MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
536
537module_pci_driver(dwc3_pci_driver);