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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * On-Chip RTC Support available on RZ/G3S SoC
4 *
5 * Copyright (C) 2024 Renesas Electronics Corp.
6 */
7#include <linux/bcd.h>
8#include <linux/bitfield.h>
9#include <linux/cleanup.h>
10#include <linux/clk.h>
11#include <linux/completion.h>
12#include <linux/delay.h>
13#include <linux/iopoll.h>
14#include <linux/interrupt.h>
15#include <linux/jiffies.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/reset.h>
20#include <linux/rtc.h>
21
22/* Counter registers. */
23#define RTCA3_RSECCNT 0x2
24#define RTCA3_RSECCNT_SEC GENMASK(6, 0)
25#define RTCA3_RMINCNT 0x4
26#define RTCA3_RMINCNT_MIN GENMASK(6, 0)
27#define RTCA3_RHRCNT 0x6
28#define RTCA3_RHRCNT_HR GENMASK(5, 0)
29#define RTCA3_RHRCNT_PM BIT(6)
30#define RTCA3_RWKCNT 0x8
31#define RTCA3_RWKCNT_WK GENMASK(2, 0)
32#define RTCA3_RDAYCNT 0xa
33#define RTCA3_RDAYCNT_DAY GENMASK(5, 0)
34#define RTCA3_RMONCNT 0xc
35#define RTCA3_RMONCNT_MONTH GENMASK(4, 0)
36#define RTCA3_RYRCNT 0xe
37#define RTCA3_RYRCNT_YEAR GENMASK(7, 0)
38
39/* Alarm registers. */
40#define RTCA3_RSECAR 0x10
41#define RTCA3_RSECAR_SEC GENMASK(6, 0)
42#define RTCA3_RMINAR 0x12
43#define RTCA3_RMINAR_MIN GENMASK(6, 0)
44#define RTCA3_RHRAR 0x14
45#define RTCA3_RHRAR_HR GENMASK(5, 0)
46#define RTCA3_RHRAR_PM BIT(6)
47#define RTCA3_RWKAR 0x16
48#define RTCA3_RWKAR_DAYW GENMASK(2, 0)
49#define RTCA3_RDAYAR 0x18
50#define RTCA3_RDAYAR_DATE GENMASK(5, 0)
51#define RTCA3_RMONAR 0x1a
52#define RTCA3_RMONAR_MON GENMASK(4, 0)
53#define RTCA3_RYRAR 0x1c
54#define RTCA3_RYRAR_YR GENMASK(7, 0)
55#define RTCA3_RYRAREN 0x1e
56
57/* Alarm enable bit (for all alarm registers). */
58#define RTCA3_AR_ENB BIT(7)
59
60/* Control registers. */
61#define RTCA3_RCR1 0x22
62#define RTCA3_RCR1_AIE BIT(0)
63#define RTCA3_RCR1_CIE BIT(1)
64#define RTCA3_RCR1_PIE BIT(2)
65#define RTCA3_RCR1_PES GENMASK(7, 4)
66#define RTCA3_RCR1_PES_1_64_SEC 0x8
67#define RTCA3_RCR2 0x24
68#define RTCA3_RCR2_START BIT(0)
69#define RTCA3_RCR2_RESET BIT(1)
70#define RTCA3_RCR2_AADJE BIT(4)
71#define RTCA3_RCR2_ADJP BIT(5)
72#define RTCA3_RCR2_HR24 BIT(6)
73#define RTCA3_RCR2_CNTMD BIT(7)
74#define RTCA3_RSR 0x20
75#define RTCA3_RSR_AF BIT(0)
76#define RTCA3_RSR_CF BIT(1)
77#define RTCA3_RSR_PF BIT(2)
78#define RTCA3_RADJ 0x2e
79#define RTCA3_RADJ_ADJ GENMASK(5, 0)
80#define RTCA3_RADJ_ADJ_MAX 0x3f
81#define RTCA3_RADJ_PMADJ GENMASK(7, 6)
82#define RTCA3_RADJ_PMADJ_NONE 0
83#define RTCA3_RADJ_PMADJ_ADD 1
84#define RTCA3_RADJ_PMADJ_SUB 2
85
86/* Polling operation timeouts. */
87#define RTCA3_DEFAULT_TIMEOUT_US 150
88#define RTCA3_IRQSET_TIMEOUT_US 5000
89#define RTCA3_START_TIMEOUT_US 150000
90#define RTCA3_RESET_TIMEOUT_US 200000
91
92/**
93 * enum rtca3_alrm_set_step - RTCA3 alarm set steps
94 * @RTCA3_ALRM_SSTEP_DONE: alarm setup done step
95 * @RTCA3_ALRM_SSTEP_IRQ: two 1/64 periodic IRQs were generated step
96 * @RTCA3_ALRM_SSTEP_INIT: alarm setup initialization step
97 */
98enum rtca3_alrm_set_step {
99 RTCA3_ALRM_SSTEP_DONE = 0,
100 RTCA3_ALRM_SSTEP_IRQ = 1,
101 RTCA3_ALRM_SSTEP_INIT = 3,
102};
103
104/**
105 * struct rtca3_ppb_per_cycle - PPB per cycle
106 * @ten_sec: PPB per cycle in 10 seconds adjutment mode
107 * @sixty_sec: PPB per cycle in 60 seconds adjustment mode
108 */
109struct rtca3_ppb_per_cycle {
110 int ten_sec;
111 int sixty_sec;
112};
113
114/**
115 * struct rtca3_priv - RTCA3 private data structure
116 * @base: base address
117 * @rtc_dev: RTC device
118 * @rstc: reset control
119 * @set_alarm_completion: alarm setup completion
120 * @alrm_sstep: alarm setup step (see enum rtca3_alrm_set_step)
121 * @lock: device lock
122 * @ppb: ppb per cycle for each the available adjustment modes
123 * @wakeup_irq: wakeup IRQ
124 */
125struct rtca3_priv {
126 void __iomem *base;
127 struct rtc_device *rtc_dev;
128 struct reset_control *rstc;
129 struct completion set_alarm_completion;
130 atomic_t alrm_sstep;
131 spinlock_t lock;
132 struct rtca3_ppb_per_cycle ppb;
133 int wakeup_irq;
134};
135
136static void rtca3_byte_update_bits(struct rtca3_priv *priv, u8 off, u8 mask, u8 val)
137{
138 u8 tmp;
139
140 tmp = readb(priv->base + off);
141 tmp &= ~mask;
142 tmp |= (val & mask);
143 writeb(tmp, priv->base + off);
144}
145
146static u8 rtca3_alarm_handler_helper(struct rtca3_priv *priv)
147{
148 u8 val, pending;
149
150 val = readb(priv->base + RTCA3_RSR);
151 pending = val & RTCA3_RSR_AF;
152 writeb(val & ~pending, priv->base + RTCA3_RSR);
153
154 if (pending)
155 rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF);
156
157 return pending;
158}
159
160static irqreturn_t rtca3_alarm_handler(int irq, void *dev_id)
161{
162 struct rtca3_priv *priv = dev_id;
163 u8 pending;
164
165 guard(spinlock)(&priv->lock);
166
167 pending = rtca3_alarm_handler_helper(priv);
168
169 return IRQ_RETVAL(pending);
170}
171
172static irqreturn_t rtca3_periodic_handler(int irq, void *dev_id)
173{
174 struct rtca3_priv *priv = dev_id;
175 u8 val, pending;
176
177 guard(spinlock)(&priv->lock);
178
179 val = readb(priv->base + RTCA3_RSR);
180 pending = val & RTCA3_RSR_PF;
181
182 if (pending) {
183 writeb(val & ~pending, priv->base + RTCA3_RSR);
184
185 if (atomic_read(&priv->alrm_sstep) > RTCA3_ALRM_SSTEP_IRQ) {
186 /* Alarm setup in progress. */
187 atomic_dec(&priv->alrm_sstep);
188
189 if (atomic_read(&priv->alrm_sstep) == RTCA3_ALRM_SSTEP_IRQ) {
190 /*
191 * We got 2 * 1/64 periodic interrupts. Disable
192 * interrupt and let alarm setup continue.
193 */
194 rtca3_byte_update_bits(priv, RTCA3_RCR1,
195 RTCA3_RCR1_PIE, 0);
196 readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, val,
197 !(val & RTCA3_RCR1_PIE),
198 10, RTCA3_DEFAULT_TIMEOUT_US);
199 complete(&priv->set_alarm_completion);
200 }
201 }
202 }
203
204 return IRQ_RETVAL(pending);
205}
206
207static void rtca3_prepare_cntalrm_regs_for_read(struct rtca3_priv *priv, bool cnt)
208{
209 /* Offset b/w time and alarm registers. */
210 u8 offset = cnt ? 0 : 0xe;
211
212 /*
213 * According to HW manual (section 22.6.4. Notes on writing to and
214 * reading from registers) after writing to count registers, alarm
215 * registers, year alarm enable register, bits RCR2.AADJE, AADJP,
216 * and HR24 register, we need to do 3 empty reads before being
217 * able to fetch the registers content.
218 */
219 for (u8 i = 0; i < 3; i++) {
220 readb(priv->base + RTCA3_RSECCNT + offset);
221 readb(priv->base + RTCA3_RMINCNT + offset);
222 readb(priv->base + RTCA3_RHRCNT + offset);
223 readb(priv->base + RTCA3_RWKCNT + offset);
224 readb(priv->base + RTCA3_RDAYCNT + offset);
225 readw(priv->base + RTCA3_RYRCNT + offset);
226 if (!cnt)
227 readb(priv->base + RTCA3_RYRAREN);
228 }
229}
230
231static int rtca3_read_time(struct device *dev, struct rtc_time *tm)
232{
233 struct rtca3_priv *priv = dev_get_drvdata(dev);
234 u8 sec, min, hour, wday, mday, month, tmp;
235 u8 trials = 0;
236 u32 year100;
237 u16 year;
238
239 guard(spinlock_irqsave)(&priv->lock);
240
241 tmp = readb(priv->base + RTCA3_RCR2);
242 if (!(tmp & RTCA3_RCR2_START))
243 return -EINVAL;
244
245 do {
246 /* Clear carry interrupt. */
247 rtca3_byte_update_bits(priv, RTCA3_RSR, RTCA3_RSR_CF, 0);
248
249 /* Read counters. */
250 sec = readb(priv->base + RTCA3_RSECCNT);
251 min = readb(priv->base + RTCA3_RMINCNT);
252 hour = readb(priv->base + RTCA3_RHRCNT);
253 wday = readb(priv->base + RTCA3_RWKCNT);
254 mday = readb(priv->base + RTCA3_RDAYCNT);
255 month = readb(priv->base + RTCA3_RMONCNT);
256 year = readw(priv->base + RTCA3_RYRCNT);
257
258 tmp = readb(priv->base + RTCA3_RSR);
259
260 /*
261 * We cannot generate carries due to reading 64Hz counter as
262 * the driver doesn't implement carry, thus, carries will be
263 * generated once per seconds. Add a timeout of 5 trials here
264 * to avoid infinite loop, if any.
265 */
266 } while ((tmp & RTCA3_RSR_CF) && ++trials < 5);
267
268 if (trials >= 5)
269 return -ETIMEDOUT;
270
271 tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECCNT_SEC, sec));
272 tm->tm_min = bcd2bin(FIELD_GET(RTCA3_RMINCNT_MIN, min));
273 tm->tm_hour = bcd2bin(FIELD_GET(RTCA3_RHRCNT_HR, hour));
274 tm->tm_wday = bcd2bin(FIELD_GET(RTCA3_RWKCNT_WK, wday));
275 tm->tm_mday = bcd2bin(FIELD_GET(RTCA3_RDAYCNT_DAY, mday));
276 tm->tm_mon = bcd2bin(FIELD_GET(RTCA3_RMONCNT_MONTH, month)) - 1;
277 year = FIELD_GET(RTCA3_RYRCNT_YEAR, year);
278 year100 = bcd2bin((year == 0x99) ? 0x19 : 0x20);
279 tm->tm_year = (year100 * 100 + bcd2bin(year)) - 1900;
280
281 return 0;
282}
283
284static int rtca3_set_time(struct device *dev, struct rtc_time *tm)
285{
286 struct rtca3_priv *priv = dev_get_drvdata(dev);
287 u8 rcr2, tmp;
288 int ret;
289
290 guard(spinlock_irqsave)(&priv->lock);
291
292 /* Stop the RTC. */
293 rcr2 = readb(priv->base + RTCA3_RCR2);
294 writeb(rcr2 & ~RTCA3_RCR2_START, priv->base + RTCA3_RCR2);
295 ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp,
296 !(tmp & RTCA3_RCR2_START),
297 10, RTCA3_DEFAULT_TIMEOUT_US);
298 if (ret)
299 return ret;
300
301 /* Update time. */
302 writeb(bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECCNT);
303 writeb(bin2bcd(tm->tm_min), priv->base + RTCA3_RMINCNT);
304 writeb(bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRCNT);
305 writeb(bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKCNT);
306 writeb(bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYCNT);
307 writeb(bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONCNT);
308 writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRCNT);
309
310 /* Make sure we can read back the counters. */
311 rtca3_prepare_cntalrm_regs_for_read(priv, true);
312
313 /* Start RTC. */
314 writeb(rcr2 | RTCA3_RCR2_START, priv->base + RTCA3_RCR2);
315 return readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp,
316 (tmp & RTCA3_RCR2_START),
317 10, RTCA3_DEFAULT_TIMEOUT_US);
318}
319
320static int rtca3_alarm_irq_set_helper(struct rtca3_priv *priv,
321 u8 interrupts,
322 unsigned int enabled)
323{
324 u8 tmp, val;
325
326 if (enabled) {
327 /*
328 * AIE, CIE, PIE bit indexes in RSR corresponds with
329 * those on RCR1. Same interrupts mask can be used.
330 */
331 rtca3_byte_update_bits(priv, RTCA3_RSR, interrupts, 0);
332 val = interrupts;
333 } else {
334 val = 0;
335 }
336
337 rtca3_byte_update_bits(priv, RTCA3_RCR1, interrupts, val);
338 return readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp,
339 ((tmp & interrupts) == val),
340 10, RTCA3_IRQSET_TIMEOUT_US);
341}
342
343static int rtca3_alarm_irq_enable(struct device *dev, unsigned int enabled)
344{
345 struct rtca3_priv *priv = dev_get_drvdata(dev);
346
347 guard(spinlock_irqsave)(&priv->lock);
348
349 return rtca3_alarm_irq_set_helper(priv, RTCA3_RCR1_AIE, enabled);
350}
351
352static int rtca3_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
353{
354 struct rtca3_priv *priv = dev_get_drvdata(dev);
355 u8 sec, min, hour, wday, mday, month;
356 struct rtc_time *tm = &wkalrm->time;
357 u32 year100;
358 u16 year;
359
360 guard(spinlock_irqsave)(&priv->lock);
361
362 sec = readb(priv->base + RTCA3_RSECAR);
363 min = readb(priv->base + RTCA3_RMINAR);
364 hour = readb(priv->base + RTCA3_RHRAR);
365 wday = readb(priv->base + RTCA3_RWKAR);
366 mday = readb(priv->base + RTCA3_RDAYAR);
367 month = readb(priv->base + RTCA3_RMONAR);
368 year = readw(priv->base + RTCA3_RYRAR);
369
370 tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECAR_SEC, sec));
371 tm->tm_min = bcd2bin(FIELD_GET(RTCA3_RMINAR_MIN, min));
372 tm->tm_hour = bcd2bin(FIELD_GET(RTCA3_RHRAR_HR, hour));
373 tm->tm_wday = bcd2bin(FIELD_GET(RTCA3_RWKAR_DAYW, wday));
374 tm->tm_mday = bcd2bin(FIELD_GET(RTCA3_RDAYAR_DATE, mday));
375 tm->tm_mon = bcd2bin(FIELD_GET(RTCA3_RMONAR_MON, month)) - 1;
376 year = FIELD_GET(RTCA3_RYRAR_YR, year);
377 year100 = bcd2bin((year == 0x99) ? 0x19 : 0x20);
378 tm->tm_year = (year100 * 100 + bcd2bin(year)) - 1900;
379
380 wkalrm->enabled = !!(readb(priv->base + RTCA3_RCR1) & RTCA3_RCR1_AIE);
381
382 return 0;
383}
384
385static int rtca3_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
386{
387 struct rtca3_priv *priv = dev_get_drvdata(dev);
388 struct rtc_time *tm = &wkalrm->time;
389 u8 rcr1, tmp;
390 int ret;
391
392 scoped_guard(spinlock_irqsave, &priv->lock) {
393 tmp = readb(priv->base + RTCA3_RCR2);
394 if (!(tmp & RTCA3_RCR2_START))
395 return -EPERM;
396
397 /* Disable AIE to prevent false interrupts. */
398 rcr1 = readb(priv->base + RTCA3_RCR1);
399 rcr1 &= ~RTCA3_RCR1_AIE;
400 writeb(rcr1, priv->base + RTCA3_RCR1);
401 ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp,
402 !(tmp & RTCA3_RCR1_AIE),
403 10, RTCA3_DEFAULT_TIMEOUT_US);
404 if (ret)
405 return ret;
406
407 /* Set the time and enable the alarm. */
408 writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECAR);
409 writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_min), priv->base + RTCA3_RMINAR);
410 writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRAR);
411 writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKAR);
412 writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYAR);
413 writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONAR);
414
415 writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRAR);
416 writeb(RTCA3_AR_ENB, priv->base + RTCA3_RYRAREN);
417
418 /* Make sure we can read back the counters. */
419 rtca3_prepare_cntalrm_regs_for_read(priv, false);
420
421 /* Need to wait for 2 * 1/64 periodic interrupts to be generated. */
422 atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_INIT);
423 reinit_completion(&priv->set_alarm_completion);
424
425 /* Enable periodic interrupt. */
426 rcr1 |= RTCA3_RCR1_PIE;
427 writeb(rcr1, priv->base + RTCA3_RCR1);
428 ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp,
429 (tmp & RTCA3_RCR1_PIE),
430 10, RTCA3_IRQSET_TIMEOUT_US);
431 }
432
433 if (ret)
434 goto setup_failed;
435
436 /* Wait for the 2 * 1/64 periodic interrupts. */
437 ret = wait_for_completion_interruptible_timeout(&priv->set_alarm_completion,
438 msecs_to_jiffies(500));
439 if (ret <= 0) {
440 ret = -ETIMEDOUT;
441 goto setup_failed;
442 }
443
444 scoped_guard(spinlock_irqsave, &priv->lock) {
445 ret = rtca3_alarm_irq_set_helper(priv, RTCA3_RCR1_AIE, wkalrm->enabled);
446 atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE);
447 }
448
449 return ret;
450
451setup_failed:
452 scoped_guard(spinlock_irqsave, &priv->lock) {
453 /*
454 * Disable PIE to avoid interrupt storm in case HW needed more than
455 * specified timeout for setup.
456 */
457 writeb(rcr1 & ~RTCA3_RCR1_PIE, priv->base + RTCA3_RCR1);
458 readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, !(tmp & ~RTCA3_RCR1_PIE),
459 10, RTCA3_DEFAULT_TIMEOUT_US);
460 atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE);
461 }
462
463 return ret;
464}
465
466static int rtca3_read_offset(struct device *dev, long *offset)
467{
468 struct rtca3_priv *priv = dev_get_drvdata(dev);
469 u8 val, radj, cycles;
470 u32 ppb_per_cycle;
471
472 scoped_guard(spinlock_irqsave, &priv->lock) {
473 radj = readb(priv->base + RTCA3_RADJ);
474 val = readb(priv->base + RTCA3_RCR2);
475 }
476
477 cycles = FIELD_GET(RTCA3_RADJ_ADJ, radj);
478
479 if (!cycles) {
480 *offset = 0;
481 return 0;
482 }
483
484 if (val & RTCA3_RCR2_ADJP)
485 ppb_per_cycle = priv->ppb.ten_sec;
486 else
487 ppb_per_cycle = priv->ppb.sixty_sec;
488
489 *offset = cycles * ppb_per_cycle;
490 val = FIELD_GET(RTCA3_RADJ_PMADJ, radj);
491 if (val == RTCA3_RADJ_PMADJ_SUB)
492 *offset = -(*offset);
493
494 return 0;
495}
496
497static int rtca3_set_offset(struct device *dev, long offset)
498{
499 struct rtca3_priv *priv = dev_get_drvdata(dev);
500 int cycles, cycles10, cycles60;
501 u8 radj, adjp, tmp;
502 int ret;
503
504 /*
505 * Automatic time error adjustment could be set at intervals of 10
506 * or 60 seconds.
507 */
508 cycles10 = DIV_ROUND_CLOSEST(offset, priv->ppb.ten_sec);
509 cycles60 = DIV_ROUND_CLOSEST(offset, priv->ppb.sixty_sec);
510
511 /* We can set b/w 1 and 63 clock cycles. */
512 if (cycles60 >= -RTCA3_RADJ_ADJ_MAX &&
513 cycles60 <= RTCA3_RADJ_ADJ_MAX) {
514 cycles = cycles60;
515 adjp = 0;
516 } else if (cycles10 >= -RTCA3_RADJ_ADJ_MAX &&
517 cycles10 <= RTCA3_RADJ_ADJ_MAX) {
518 cycles = cycles10;
519 adjp = RTCA3_RCR2_ADJP;
520 } else {
521 return -ERANGE;
522 }
523
524 radj = FIELD_PREP(RTCA3_RADJ_ADJ, abs(cycles));
525 if (!cycles)
526 radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_NONE);
527 else if (cycles > 0)
528 radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_ADD);
529 else
530 radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_SUB);
531
532 guard(spinlock_irqsave)(&priv->lock);
533
534 tmp = readb(priv->base + RTCA3_RCR2);
535
536 if ((tmp & RTCA3_RCR2_ADJP) != adjp) {
537 /* RADJ.PMADJ need to be set to zero before setting RCR2.ADJP. */
538 writeb(0, priv->base + RTCA3_RADJ);
539 ret = readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, !tmp,
540 10, RTCA3_DEFAULT_TIMEOUT_US);
541 if (ret)
542 return ret;
543
544 rtca3_byte_update_bits(priv, RTCA3_RCR2, RTCA3_RCR2_ADJP, adjp);
545 ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp,
546 ((tmp & RTCA3_RCR2_ADJP) == adjp),
547 10, RTCA3_DEFAULT_TIMEOUT_US);
548 if (ret)
549 return ret;
550 }
551
552 writeb(radj, priv->base + RTCA3_RADJ);
553 return readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, (tmp == radj),
554 10, RTCA3_DEFAULT_TIMEOUT_US);
555}
556
557static const struct rtc_class_ops rtca3_ops = {
558 .read_time = rtca3_read_time,
559 .set_time = rtca3_set_time,
560 .read_alarm = rtca3_read_alarm,
561 .set_alarm = rtca3_set_alarm,
562 .alarm_irq_enable = rtca3_alarm_irq_enable,
563 .set_offset = rtca3_set_offset,
564 .read_offset = rtca3_read_offset,
565};
566
567static int rtca3_initial_setup(struct clk *clk, struct rtca3_priv *priv)
568{
569 unsigned long osc32k_rate;
570 u8 val, tmp, mask;
571 u32 sleep_us;
572 int ret;
573
574 osc32k_rate = clk_get_rate(clk);
575 if (!osc32k_rate)
576 return -EINVAL;
577
578 sleep_us = DIV_ROUND_UP_ULL(1000000ULL, osc32k_rate) * 6;
579
580 priv->ppb.ten_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 10));
581 priv->ppb.sixty_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 60));
582
583 /*
584 * According to HW manual (section 22.4.2. Clock and count mode setting procedure)
585 * we need to wait at least 6 cycles of the 32KHz clock after clock was enabled.
586 */
587 usleep_range(sleep_us, sleep_us + 10);
588
589 /* Disable all interrupts. */
590 mask = RTCA3_RCR1_AIE | RTCA3_RCR1_CIE | RTCA3_RCR1_PIE;
591 ret = rtca3_alarm_irq_set_helper(priv, mask, 0);
592 if (ret)
593 return ret;
594
595 mask = RTCA3_RCR2_START | RTCA3_RCR2_HR24;
596 val = readb(priv->base + RTCA3_RCR2);
597 /* Nothing to do if already started in 24 hours and calendar count mode. */
598 if ((val & mask) == mask)
599 return 0;
600
601 /* Reconfigure the RTC in 24 hours and calendar count mode. */
602 mask = RTCA3_RCR2_START | RTCA3_RCR2_CNTMD;
603 writeb(0, priv->base + RTCA3_RCR2);
604 ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask),
605 10, RTCA3_DEFAULT_TIMEOUT_US);
606 if (ret)
607 return ret;
608
609 /*
610 * Set 24 hours mode. According to HW manual (section 22.3.19. RTC Control
611 * Register 2) this needs to be done separate from stop operation.
612 */
613 mask = RTCA3_RCR2_HR24;
614 val = RTCA3_RCR2_HR24;
615 writeb(val, priv->base + RTCA3_RCR2);
616 ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, (tmp & mask),
617 10, RTCA3_DEFAULT_TIMEOUT_US);
618 if (ret)
619 return ret;
620
621 /* Execute reset. */
622 mask = RTCA3_RCR2_RESET;
623 writeb(val | RTCA3_RCR2_RESET, priv->base + RTCA3_RCR2);
624 ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask),
625 10, RTCA3_RESET_TIMEOUT_US);
626 if (ret)
627 return ret;
628
629 /*
630 * According to HW manual (section 22.6.3. Notes on writing to and reading
631 * from registers) after reset we need to wait 6 clock cycles before
632 * writing to RTC registers.
633 */
634 usleep_range(sleep_us, sleep_us + 10);
635
636 /* Set no adjustment. */
637 writeb(0, priv->base + RTCA3_RADJ);
638 ret = readb_poll_timeout(priv->base + RTCA3_RADJ, tmp, !tmp, 10,
639 RTCA3_DEFAULT_TIMEOUT_US);
640
641 /* Start the RTC and enable automatic time error adjustment. */
642 mask = RTCA3_RCR2_START | RTCA3_RCR2_AADJE;
643 val |= RTCA3_RCR2_START | RTCA3_RCR2_AADJE;
644 writeb(val, priv->base + RTCA3_RCR2);
645 ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, ((tmp & mask) == mask),
646 10, RTCA3_START_TIMEOUT_US);
647 if (ret)
648 return ret;
649
650 /*
651 * According to HW manual (section 22.6.4. Notes on writing to and reading
652 * from registers) we need to wait 1/128 seconds while the clock is operating
653 * (RCR2.START bit = 1) to be able to read the counters after a return from
654 * reset.
655 */
656 usleep_range(8000, 9000);
657
658 /* Set period interrupt to 1/64 seconds. It is necessary for alarm setup. */
659 val = FIELD_PREP(RTCA3_RCR1_PES, RTCA3_RCR1_PES_1_64_SEC);
660 rtca3_byte_update_bits(priv, RTCA3_RCR1, RTCA3_RCR1_PES, val);
661 return readb_poll_timeout(priv->base + RTCA3_RCR1, tmp, ((tmp & RTCA3_RCR1_PES) == val),
662 10, RTCA3_DEFAULT_TIMEOUT_US);
663}
664
665static int rtca3_request_irqs(struct platform_device *pdev, struct rtca3_priv *priv)
666{
667 struct device *dev = &pdev->dev;
668 int ret, irq;
669
670 irq = platform_get_irq_byname(pdev, "alarm");
671 if (irq < 0)
672 return dev_err_probe(dev, irq, "Failed to get alarm IRQ!\n");
673
674 ret = devm_request_irq(dev, irq, rtca3_alarm_handler, 0, "rtca3-alarm", priv);
675 if (ret)
676 return dev_err_probe(dev, ret, "Failed to request alarm IRQ!\n");
677 priv->wakeup_irq = irq;
678
679 irq = platform_get_irq_byname(pdev, "period");
680 if (irq < 0)
681 return dev_err_probe(dev, irq, "Failed to get period IRQ!\n");
682
683 ret = devm_request_irq(dev, irq, rtca3_periodic_handler, 0, "rtca3-period", priv);
684 if (ret)
685 return dev_err_probe(dev, ret, "Failed to request period IRQ!\n");
686
687 /*
688 * Driver doesn't implement carry handler. Just get the IRQ here
689 * for backward compatibility, in case carry support will be added later.
690 */
691 irq = platform_get_irq_byname(pdev, "carry");
692 if (irq < 0)
693 return dev_err_probe(dev, irq, "Failed to get carry IRQ!\n");
694
695 return 0;
696}
697
698static void rtca3_action(void *data)
699{
700 struct device *dev = data;
701 struct rtca3_priv *priv = dev_get_drvdata(dev);
702 int ret;
703
704 ret = reset_control_assert(priv->rstc);
705 if (ret)
706 dev_err(dev, "Failed to de-assert reset!");
707
708 ret = pm_runtime_put_sync(dev);
709 if (ret < 0)
710 dev_err(dev, "Failed to runtime suspend!");
711}
712
713static int rtca3_probe(struct platform_device *pdev)
714{
715 struct device *dev = &pdev->dev;
716 struct rtca3_priv *priv;
717 struct clk *clk;
718 int ret;
719
720 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
721 if (!priv)
722 return -ENOMEM;
723
724 priv->base = devm_platform_ioremap_resource(pdev, 0);
725 if (IS_ERR(priv->base))
726 return PTR_ERR(priv->base);
727
728 ret = devm_pm_runtime_enable(dev);
729 if (ret)
730 return ret;
731
732 priv->rstc = devm_reset_control_get_shared(dev, NULL);
733 if (IS_ERR(priv->rstc))
734 return PTR_ERR(priv->rstc);
735
736 ret = pm_runtime_resume_and_get(dev);
737 if (ret)
738 return ret;
739
740 ret = reset_control_deassert(priv->rstc);
741 if (ret) {
742 pm_runtime_put_sync(dev);
743 return ret;
744 }
745
746 dev_set_drvdata(dev, priv);
747 ret = devm_add_action_or_reset(dev, rtca3_action, dev);
748 if (ret)
749 return ret;
750
751 /*
752 * This must be an always-on clock to keep the RTC running even after
753 * driver is unbinded.
754 */
755 clk = devm_clk_get_enabled(dev, "counter");
756 if (IS_ERR(clk))
757 return PTR_ERR(clk);
758
759 spin_lock_init(&priv->lock);
760 atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE);
761 init_completion(&priv->set_alarm_completion);
762
763 ret = rtca3_initial_setup(clk, priv);
764 if (ret)
765 return dev_err_probe(dev, ret, "Failed to setup the RTC!\n");
766
767 ret = rtca3_request_irqs(pdev, priv);
768 if (ret)
769 return ret;
770
771 device_init_wakeup(&pdev->dev, 1);
772
773 priv->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
774 if (IS_ERR(priv->rtc_dev))
775 return PTR_ERR(priv->rtc_dev);
776
777 priv->rtc_dev->ops = &rtca3_ops;
778 priv->rtc_dev->max_user_freq = 256;
779 priv->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000;
780 priv->rtc_dev->range_max = RTC_TIMESTAMP_END_2099;
781
782 return devm_rtc_register_device(priv->rtc_dev);
783}
784
785static void rtca3_remove(struct platform_device *pdev)
786{
787 struct rtca3_priv *priv = platform_get_drvdata(pdev);
788
789 guard(spinlock_irqsave)(&priv->lock);
790
791 /*
792 * Disable alarm, periodic interrupts. The RTC device cannot
793 * power up the system.
794 */
795 rtca3_alarm_irq_set_helper(priv, RTCA3_RCR1_AIE | RTCA3_RCR1_PIE, 0);
796}
797
798static int rtca3_suspend(struct device *dev)
799{
800 struct rtca3_priv *priv = dev_get_drvdata(dev);
801
802 if (!device_may_wakeup(dev))
803 return 0;
804
805 /* Alarm setup in progress. */
806 if (atomic_read(&priv->alrm_sstep) != RTCA3_ALRM_SSTEP_DONE)
807 return -EBUSY;
808
809 enable_irq_wake(priv->wakeup_irq);
810
811 return 0;
812}
813
814static int rtca3_clean_alarm(struct rtca3_priv *priv)
815{
816 struct rtc_device *rtc_dev = priv->rtc_dev;
817 time64_t alarm_time, now;
818 struct rtc_wkalrm alarm;
819 struct rtc_time tm;
820 u8 pending;
821 int ret;
822
823 ret = rtc_read_alarm(rtc_dev, &alarm);
824 if (ret)
825 return ret;
826
827 if (!alarm.enabled)
828 return 0;
829
830 ret = rtc_read_time(rtc_dev, &tm);
831 if (ret)
832 return ret;
833
834 alarm_time = rtc_tm_to_time64(&alarm.time);
835 now = rtc_tm_to_time64(&tm);
836 if (alarm_time >= now)
837 return 0;
838
839 /*
840 * Heuristically, it has been determined that when returning from deep
841 * sleep state the RTCA3_RSR.AF is zero even though the alarm expired.
842 * Call again the rtc_update_irq() if alarm helper detects this.
843 */
844
845 guard(spinlock_irqsave)(&priv->lock);
846
847 pending = rtca3_alarm_handler_helper(priv);
848 if (!pending)
849 rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF);
850
851 return 0;
852}
853
854static int rtca3_resume(struct device *dev)
855{
856 struct rtca3_priv *priv = dev_get_drvdata(dev);
857
858 if (!device_may_wakeup(dev))
859 return 0;
860
861 disable_irq_wake(priv->wakeup_irq);
862
863 /*
864 * According to the HW manual (section 22.6.4 Notes on writing to
865 * and reading from registers) we need to wait 1/128 seconds while
866 * RCR2.START = 1 to be able to read the counters after a return from low
867 * power consumption state.
868 */
869 mdelay(8);
870
871 /*
872 * The alarm cannot wake the system from deep sleep states. In case
873 * we return from deep sleep states and the alarm expired we need
874 * to disable it to avoid failures when setting another alarm.
875 */
876 return rtca3_clean_alarm(priv);
877}
878
879static DEFINE_SIMPLE_DEV_PM_OPS(rtca3_pm_ops, rtca3_suspend, rtca3_resume);
880
881static const struct of_device_id rtca3_of_match[] = {
882 { .compatible = "renesas,rz-rtca3", },
883 { /* sentinel */ }
884};
885MODULE_DEVICE_TABLE(of, rtca3_of_match);
886
887static struct platform_driver rtca3_platform_driver = {
888 .driver = {
889 .name = "rtc-rtca3",
890 .pm = pm_ptr(&rtca3_pm_ops),
891 .of_match_table = rtca3_of_match,
892 },
893 .probe = rtca3_probe,
894 .remove = rtca3_remove,
895};
896module_platform_driver(rtca3_platform_driver);
897
898MODULE_DESCRIPTION("Renesas RTCA-3 RTC driver");
899MODULE_AUTHOR("Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>");
900MODULE_LICENSE("GPL");