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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for the Intel SCU IPC mechanism
4 *
5 * (C) Copyright 2008-2010,2015 Intel Corporation
6 * Author: Sreedhara DS (sreedhara.ds@intel.com)
7 *
8 * SCU running in ARC processor communicates with other entity running in IA
9 * core through IPC mechanism which in turn messaging between IA core ad SCU.
10 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
11 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
12 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
13 * along with other APIs.
14 */
15
16#include <linux/delay.h>
17#include <linux/device.h>
18#include <linux/errno.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/iopoll.h>
23#include <linux/module.h>
24#include <linux/slab.h>
25
26#include <asm/intel_scu_ipc.h>
27
28/* IPC defines the following message types */
29#define IPCMSG_PCNTRL 0xff /* Power controller unit read/write */
30
31/* Command id associated with message IPCMSG_PCNTRL */
32#define IPC_CMD_PCNTRL_W 0 /* Register write */
33#define IPC_CMD_PCNTRL_R 1 /* Register read */
34#define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */
35
36/*
37 * IPC register summary
38 *
39 * IPC register blocks are memory mapped at fixed address of PCI BAR 0.
40 * To read or write information to the SCU, driver writes to IPC-1 memory
41 * mapped registers. The following is the IPC mechanism
42 *
43 * 1. IA core cDMI interface claims this transaction and converts it to a
44 * Transaction Layer Packet (TLP) message which is sent across the cDMI.
45 *
46 * 2. South Complex cDMI block receives this message and writes it to
47 * the IPC-1 register block, causing an interrupt to the SCU
48 *
49 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate
50 * message handler is called within firmware.
51 */
52
53#define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */
54#define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */
55#define IPC_IOC 0x100 /* IPC command register IOC bit */
56
57struct intel_scu_ipc_dev {
58 struct device dev;
59 struct resource mem;
60 struct module *owner;
61 int irq;
62 void __iomem *ipc_base;
63 struct completion cmd_complete;
64};
65
66#define IPC_STATUS 0x04
67#define IPC_STATUS_IRQ BIT(2)
68#define IPC_STATUS_ERR BIT(1)
69#define IPC_STATUS_BUSY BIT(0)
70
71/*
72 * IPC Write/Read Buffers:
73 * 16 byte buffer for sending and receiving data to and from SCU.
74 */
75#define IPC_WRITE_BUFFER 0x80
76#define IPC_READ_BUFFER 0x90
77
78/* Timeout in jiffies */
79#define IPC_TIMEOUT (10 * HZ)
80
81static struct intel_scu_ipc_dev *ipcdev; /* Only one for now */
82static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
83
84static struct class intel_scu_ipc_class = {
85 .name = "intel_scu_ipc",
86};
87
88/**
89 * intel_scu_ipc_dev_get() - Get SCU IPC instance
90 *
91 * The recommended new API takes SCU IPC instance as parameter and this
92 * function can be called by driver to get the instance. This also makes
93 * sure the driver providing the IPC functionality cannot be unloaded
94 * while the caller has the instance.
95 *
96 * Call intel_scu_ipc_dev_put() to release the instance.
97 *
98 * Returns %NULL if SCU IPC is not currently available.
99 */
100struct intel_scu_ipc_dev *intel_scu_ipc_dev_get(void)
101{
102 struct intel_scu_ipc_dev *scu = NULL;
103
104 mutex_lock(&ipclock);
105 if (ipcdev) {
106 get_device(&ipcdev->dev);
107 /*
108 * Prevent the IPC provider from being unloaded while it
109 * is being used.
110 */
111 if (!try_module_get(ipcdev->owner))
112 put_device(&ipcdev->dev);
113 else
114 scu = ipcdev;
115 }
116
117 mutex_unlock(&ipclock);
118 return scu;
119}
120EXPORT_SYMBOL_GPL(intel_scu_ipc_dev_get);
121
122/**
123 * intel_scu_ipc_dev_put() - Put SCU IPC instance
124 * @scu: SCU IPC instance
125 *
126 * This function releases the SCU IPC instance retrieved from
127 * intel_scu_ipc_dev_get() and allows the driver providing IPC to be
128 * unloaded.
129 */
130void intel_scu_ipc_dev_put(struct intel_scu_ipc_dev *scu)
131{
132 if (scu) {
133 module_put(scu->owner);
134 put_device(&scu->dev);
135 }
136}
137EXPORT_SYMBOL_GPL(intel_scu_ipc_dev_put);
138
139struct intel_scu_ipc_devres {
140 struct intel_scu_ipc_dev *scu;
141};
142
143static void devm_intel_scu_ipc_dev_release(struct device *dev, void *res)
144{
145 struct intel_scu_ipc_devres *dr = res;
146 struct intel_scu_ipc_dev *scu = dr->scu;
147
148 intel_scu_ipc_dev_put(scu);
149}
150
151/**
152 * devm_intel_scu_ipc_dev_get() - Allocate managed SCU IPC device
153 * @dev: Device requesting the SCU IPC device
154 *
155 * The recommended new API takes SCU IPC instance as parameter and this
156 * function can be called by driver to get the instance. This also makes
157 * sure the driver providing the IPC functionality cannot be unloaded
158 * while the caller has the instance.
159 *
160 * Returns %NULL if SCU IPC is not currently available.
161 */
162struct intel_scu_ipc_dev *devm_intel_scu_ipc_dev_get(struct device *dev)
163{
164 struct intel_scu_ipc_devres *dr;
165 struct intel_scu_ipc_dev *scu;
166
167 dr = devres_alloc(devm_intel_scu_ipc_dev_release, sizeof(*dr), GFP_KERNEL);
168 if (!dr)
169 return NULL;
170
171 scu = intel_scu_ipc_dev_get();
172 if (!scu) {
173 devres_free(dr);
174 return NULL;
175 }
176
177 dr->scu = scu;
178 devres_add(dev, dr);
179
180 return scu;
181}
182EXPORT_SYMBOL_GPL(devm_intel_scu_ipc_dev_get);
183
184/*
185 * Send ipc command
186 * Command Register (Write Only):
187 * A write to this register results in an interrupt to the SCU core processor
188 * Format:
189 * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
190 */
191static inline void ipc_command(struct intel_scu_ipc_dev *scu, u32 cmd)
192{
193 reinit_completion(&scu->cmd_complete);
194 writel(cmd | IPC_IOC, scu->ipc_base);
195}
196
197/*
198 * Write ipc data
199 * IPC Write Buffer (Write Only):
200 * 16-byte buffer for sending data associated with IPC command to
201 * SCU. Size of the data is specified in the IPC_COMMAND_REG register
202 */
203static inline void ipc_data_writel(struct intel_scu_ipc_dev *scu, u32 data, u32 offset)
204{
205 writel(data, scu->ipc_base + IPC_WRITE_BUFFER + offset);
206}
207
208/*
209 * Status Register (Read Only):
210 * Driver will read this register to get the ready/busy status of the IPC
211 * block and error status of the IPC command that was just processed by SCU
212 * Format:
213 * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
214 */
215static inline u8 ipc_read_status(struct intel_scu_ipc_dev *scu)
216{
217 return __raw_readl(scu->ipc_base + IPC_STATUS);
218}
219
220/* Read ipc byte data */
221static inline u8 ipc_data_readb(struct intel_scu_ipc_dev *scu, u32 offset)
222{
223 return readb(scu->ipc_base + IPC_READ_BUFFER + offset);
224}
225
226/* Read ipc u32 data */
227static inline u32 ipc_data_readl(struct intel_scu_ipc_dev *scu, u32 offset)
228{
229 return readl(scu->ipc_base + IPC_READ_BUFFER + offset);
230}
231
232/* Wait till scu status is busy */
233static inline int busy_loop(struct intel_scu_ipc_dev *scu)
234{
235 u8 status;
236 int err;
237
238 err = readx_poll_timeout(ipc_read_status, scu, status, !(status & IPC_STATUS_BUSY),
239 100, jiffies_to_usecs(IPC_TIMEOUT));
240 if (err)
241 return err;
242
243 return (status & IPC_STATUS_ERR) ? -EIO : 0;
244}
245
246/* Wait till ipc ioc interrupt is received or timeout in 10 HZ */
247static inline int ipc_wait_for_interrupt(struct intel_scu_ipc_dev *scu)
248{
249 int status;
250
251 wait_for_completion_timeout(&scu->cmd_complete, IPC_TIMEOUT);
252
253 status = ipc_read_status(scu);
254 if (status & IPC_STATUS_BUSY)
255 return -ETIMEDOUT;
256
257 if (status & IPC_STATUS_ERR)
258 return -EIO;
259
260 return 0;
261}
262
263static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev *scu)
264{
265 return scu->irq > 0 ? ipc_wait_for_interrupt(scu) : busy_loop(scu);
266}
267
268static struct intel_scu_ipc_dev *intel_scu_ipc_get(struct intel_scu_ipc_dev *scu)
269{
270 u8 status;
271
272 if (!scu)
273 scu = ipcdev;
274 if (!scu)
275 return ERR_PTR(-ENODEV);
276
277 status = ipc_read_status(scu);
278 if (status & IPC_STATUS_BUSY) {
279 dev_dbg(&scu->dev, "device is busy\n");
280 return ERR_PTR(-EBUSY);
281 }
282
283 return scu;
284}
285
286/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
287static int pwr_reg_rdwr(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
288 u32 count, u32 op, u32 id)
289{
290 int nc;
291 u32 offset = 0;
292 int err;
293 u8 cbuf[IPC_WWBUF_SIZE];
294 u32 *wbuf = (u32 *)&cbuf;
295
296 memset(cbuf, 0, sizeof(cbuf));
297
298 mutex_lock(&ipclock);
299 scu = intel_scu_ipc_get(scu);
300 if (IS_ERR(scu)) {
301 mutex_unlock(&ipclock);
302 return PTR_ERR(scu);
303 }
304
305 for (nc = 0; nc < count; nc++, offset += 2) {
306 cbuf[offset] = addr[nc];
307 cbuf[offset + 1] = addr[nc] >> 8;
308 }
309
310 if (id == IPC_CMD_PCNTRL_R) {
311 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
312 ipc_data_writel(scu, wbuf[nc], offset);
313 ipc_command(scu, (count * 2) << 16 | id << 12 | 0 << 8 | op);
314 } else if (id == IPC_CMD_PCNTRL_W) {
315 for (nc = 0; nc < count; nc++, offset += 1)
316 cbuf[offset] = data[nc];
317 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
318 ipc_data_writel(scu, wbuf[nc], offset);
319 ipc_command(scu, (count * 3) << 16 | id << 12 | 0 << 8 | op);
320 } else if (id == IPC_CMD_PCNTRL_M) {
321 cbuf[offset] = data[0];
322 cbuf[offset + 1] = data[1];
323 ipc_data_writel(scu, wbuf[0], 0); /* Write wbuff */
324 ipc_command(scu, 4 << 16 | id << 12 | 0 << 8 | op);
325 }
326
327 err = intel_scu_ipc_check_status(scu);
328 if (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
329 /* Workaround: values are read as 0 without memcpy_fromio */
330 memcpy_fromio(cbuf, scu->ipc_base + 0x90, 16);
331 for (nc = 0; nc < count; nc++)
332 data[nc] = ipc_data_readb(scu, nc);
333 }
334 mutex_unlock(&ipclock);
335 return err;
336}
337
338/**
339 * intel_scu_ipc_dev_ioread8() - Read a byte via the SCU
340 * @scu: Optional SCU IPC instance
341 * @addr: Register on SCU
342 * @data: Return pointer for read byte
343 *
344 * Read a single register. Returns %0 on success or an error code. All
345 * locking between SCU accesses is handled for the caller.
346 *
347 * This function may sleep.
348 */
349int intel_scu_ipc_dev_ioread8(struct intel_scu_ipc_dev *scu, u16 addr, u8 *data)
350{
351 return pwr_reg_rdwr(scu, &addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
352}
353EXPORT_SYMBOL(intel_scu_ipc_dev_ioread8);
354
355/**
356 * intel_scu_ipc_dev_iowrite8() - Write a byte via the SCU
357 * @scu: Optional SCU IPC instance
358 * @addr: Register on SCU
359 * @data: Byte to write
360 *
361 * Write a single register. Returns %0 on success or an error code. All
362 * locking between SCU accesses is handled for the caller.
363 *
364 * This function may sleep.
365 */
366int intel_scu_ipc_dev_iowrite8(struct intel_scu_ipc_dev *scu, u16 addr, u8 data)
367{
368 return pwr_reg_rdwr(scu, &addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
369}
370EXPORT_SYMBOL(intel_scu_ipc_dev_iowrite8);
371
372/**
373 * intel_scu_ipc_dev_readv() - Read a set of registers
374 * @scu: Optional SCU IPC instance
375 * @addr: Register list
376 * @data: Bytes to return
377 * @len: Length of array
378 *
379 * Read registers. Returns %0 on success or an error code. All locking
380 * between SCU accesses is handled for the caller.
381 *
382 * The largest array length permitted by the hardware is 5 items.
383 *
384 * This function may sleep.
385 */
386int intel_scu_ipc_dev_readv(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
387 size_t len)
388{
389 return pwr_reg_rdwr(scu, addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
390}
391EXPORT_SYMBOL(intel_scu_ipc_dev_readv);
392
393/**
394 * intel_scu_ipc_dev_writev() - Write a set of registers
395 * @scu: Optional SCU IPC instance
396 * @addr: Register list
397 * @data: Bytes to write
398 * @len: Length of array
399 *
400 * Write registers. Returns %0 on success or an error code. All locking
401 * between SCU accesses is handled for the caller.
402 *
403 * The largest array length permitted by the hardware is 5 items.
404 *
405 * This function may sleep.
406 */
407int intel_scu_ipc_dev_writev(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
408 size_t len)
409{
410 return pwr_reg_rdwr(scu, addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
411}
412EXPORT_SYMBOL(intel_scu_ipc_dev_writev);
413
414/**
415 * intel_scu_ipc_dev_update() - Update a register
416 * @scu: Optional SCU IPC instance
417 * @addr: Register address
418 * @data: Bits to update
419 * @mask: Mask of bits to update
420 *
421 * Read-modify-write power control unit register. The first data argument
422 * must be register value and second is mask value mask is a bitmap that
423 * indicates which bits to update. %0 = masked. Don't modify this bit, %1 =
424 * modify this bit. returns %0 on success or an error code.
425 *
426 * This function may sleep. Locking between SCU accesses is handled
427 * for the caller.
428 */
429int intel_scu_ipc_dev_update(struct intel_scu_ipc_dev *scu, u16 addr, u8 data,
430 u8 mask)
431{
432 u8 tmp[2] = { data, mask };
433 return pwr_reg_rdwr(scu, &addr, tmp, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
434}
435EXPORT_SYMBOL(intel_scu_ipc_dev_update);
436
437/**
438 * intel_scu_ipc_dev_simple_command() - Send a simple command
439 * @scu: Optional SCU IPC instance
440 * @cmd: Command
441 * @sub: Sub type
442 *
443 * Issue a simple command to the SCU. Do not use this interface if you must
444 * then access data as any data values may be overwritten by another SCU
445 * access by the time this function returns.
446 *
447 * This function may sleep. Locking for SCU accesses is handled for the
448 * caller.
449 */
450int intel_scu_ipc_dev_simple_command(struct intel_scu_ipc_dev *scu, int cmd,
451 int sub)
452{
453 u32 cmdval;
454 int err;
455
456 mutex_lock(&ipclock);
457 scu = intel_scu_ipc_get(scu);
458 if (IS_ERR(scu)) {
459 mutex_unlock(&ipclock);
460 return PTR_ERR(scu);
461 }
462
463 cmdval = sub << 12 | cmd;
464 ipc_command(scu, cmdval);
465 err = intel_scu_ipc_check_status(scu);
466 mutex_unlock(&ipclock);
467 if (err)
468 dev_err(&scu->dev, "IPC command %#x failed with %d\n", cmdval, err);
469 return err;
470}
471EXPORT_SYMBOL(intel_scu_ipc_dev_simple_command);
472
473/**
474 * intel_scu_ipc_dev_command_with_size() - Command with data
475 * @scu: Optional SCU IPC instance
476 * @cmd: Command
477 * @sub: Sub type
478 * @in: Input data
479 * @inlen: Input length in bytes
480 * @size: Input size written to the IPC command register in whatever
481 * units (dword, byte) the particular firmware requires. Normally
482 * should be the same as @inlen.
483 * @out: Output data
484 * @outlen: Output length in bytes
485 *
486 * Issue a command to the SCU which involves data transfers. Do the
487 * data copies under the lock but leave it for the caller to interpret.
488 */
489int intel_scu_ipc_dev_command_with_size(struct intel_scu_ipc_dev *scu, int cmd,
490 int sub, const void *in, size_t inlen,
491 size_t size, void *out, size_t outlen)
492{
493 size_t outbuflen = DIV_ROUND_UP(outlen, sizeof(u32));
494 size_t inbuflen = DIV_ROUND_UP(inlen, sizeof(u32));
495 u32 cmdval, inbuf[4] = {};
496 int i, err;
497
498 if (inbuflen > 4 || outbuflen > 4)
499 return -EINVAL;
500
501 mutex_lock(&ipclock);
502 scu = intel_scu_ipc_get(scu);
503 if (IS_ERR(scu)) {
504 mutex_unlock(&ipclock);
505 return PTR_ERR(scu);
506 }
507
508 memcpy(inbuf, in, inlen);
509 for (i = 0; i < inbuflen; i++)
510 ipc_data_writel(scu, inbuf[i], 4 * i);
511
512 cmdval = (size << 16) | (sub << 12) | cmd;
513 ipc_command(scu, cmdval);
514 err = intel_scu_ipc_check_status(scu);
515
516 if (!err) {
517 u32 outbuf[4] = {};
518
519 for (i = 0; i < outbuflen; i++)
520 outbuf[i] = ipc_data_readl(scu, 4 * i);
521
522 memcpy(out, outbuf, outlen);
523 }
524
525 mutex_unlock(&ipclock);
526 if (err)
527 dev_err(&scu->dev, "IPC command %#x failed with %d\n", cmdval, err);
528 return err;
529}
530EXPORT_SYMBOL(intel_scu_ipc_dev_command_with_size);
531
532/*
533 * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
534 * When ioc bit is set to 1, caller api must wait for interrupt handler called
535 * which in turn unlocks the caller api. Currently this is not used
536 *
537 * This is edge triggered so we need take no action to clear anything
538 */
539static irqreturn_t ioc(int irq, void *dev_id)
540{
541 struct intel_scu_ipc_dev *scu = dev_id;
542 int status = ipc_read_status(scu);
543
544 writel(status | IPC_STATUS_IRQ, scu->ipc_base + IPC_STATUS);
545 complete(&scu->cmd_complete);
546
547 return IRQ_HANDLED;
548}
549
550static void intel_scu_ipc_release(struct device *dev)
551{
552 struct intel_scu_ipc_dev *scu;
553
554 scu = container_of(dev, struct intel_scu_ipc_dev, dev);
555 if (scu->irq > 0)
556 free_irq(scu->irq, scu);
557 iounmap(scu->ipc_base);
558 release_mem_region(scu->mem.start, resource_size(&scu->mem));
559 kfree(scu);
560}
561
562/**
563 * __intel_scu_ipc_register() - Register SCU IPC device
564 * @parent: Parent device
565 * @scu_data: Data used to configure SCU IPC
566 * @owner: Module registering the SCU IPC device
567 *
568 * Call this function to register SCU IPC mechanism under @parent.
569 * Returns pointer to the new SCU IPC device or ERR_PTR() in case of
570 * failure. The caller may use the returned instance if it needs to do
571 * SCU IPC calls itself.
572 */
573struct intel_scu_ipc_dev *
574__intel_scu_ipc_register(struct device *parent,
575 const struct intel_scu_ipc_data *scu_data,
576 struct module *owner)
577{
578 int err;
579 struct intel_scu_ipc_dev *scu;
580 void __iomem *ipc_base;
581
582 mutex_lock(&ipclock);
583 /* We support only one IPC */
584 if (ipcdev) {
585 err = -EBUSY;
586 goto err_unlock;
587 }
588
589 scu = kzalloc(sizeof(*scu), GFP_KERNEL);
590 if (!scu) {
591 err = -ENOMEM;
592 goto err_unlock;
593 }
594
595 scu->owner = owner;
596 scu->dev.parent = parent;
597 scu->dev.class = &intel_scu_ipc_class;
598 scu->dev.release = intel_scu_ipc_release;
599
600 if (!request_mem_region(scu_data->mem.start, resource_size(&scu_data->mem),
601 "intel_scu_ipc")) {
602 err = -EBUSY;
603 goto err_free;
604 }
605
606 ipc_base = ioremap(scu_data->mem.start, resource_size(&scu_data->mem));
607 if (!ipc_base) {
608 err = -ENOMEM;
609 goto err_release;
610 }
611
612 scu->ipc_base = ipc_base;
613 scu->mem = scu_data->mem;
614 scu->irq = scu_data->irq;
615 init_completion(&scu->cmd_complete);
616
617 if (scu->irq > 0) {
618 err = request_irq(scu->irq, ioc, 0, "intel_scu_ipc", scu);
619 if (err)
620 goto err_unmap;
621 }
622
623 /*
624 * After this point intel_scu_ipc_release() takes care of
625 * releasing the SCU IPC resources once refcount drops to zero.
626 */
627 dev_set_name(&scu->dev, "intel_scu_ipc");
628 err = device_register(&scu->dev);
629 if (err) {
630 put_device(&scu->dev);
631 goto err_unlock;
632 }
633
634 /* Assign device at last */
635 ipcdev = scu;
636 mutex_unlock(&ipclock);
637
638 return scu;
639
640err_unmap:
641 iounmap(ipc_base);
642err_release:
643 release_mem_region(scu_data->mem.start, resource_size(&scu_data->mem));
644err_free:
645 kfree(scu);
646err_unlock:
647 mutex_unlock(&ipclock);
648
649 return ERR_PTR(err);
650}
651EXPORT_SYMBOL_GPL(__intel_scu_ipc_register);
652
653/**
654 * intel_scu_ipc_unregister() - Unregister SCU IPC
655 * @scu: SCU IPC handle
656 *
657 * This unregisters the SCU IPC device and releases the acquired
658 * resources once the refcount goes to zero.
659 */
660void intel_scu_ipc_unregister(struct intel_scu_ipc_dev *scu)
661{
662 mutex_lock(&ipclock);
663 if (!WARN_ON(!ipcdev)) {
664 ipcdev = NULL;
665 device_unregister(&scu->dev);
666 }
667 mutex_unlock(&ipclock);
668}
669EXPORT_SYMBOL_GPL(intel_scu_ipc_unregister);
670
671static void devm_intel_scu_ipc_unregister(struct device *dev, void *res)
672{
673 struct intel_scu_ipc_devres *dr = res;
674 struct intel_scu_ipc_dev *scu = dr->scu;
675
676 intel_scu_ipc_unregister(scu);
677}
678
679/**
680 * __devm_intel_scu_ipc_register() - Register managed SCU IPC device
681 * @parent: Parent device
682 * @scu_data: Data used to configure SCU IPC
683 * @owner: Module registering the SCU IPC device
684 *
685 * Call this function to register managed SCU IPC mechanism under
686 * @parent. Returns pointer to the new SCU IPC device or ERR_PTR() in
687 * case of failure. The caller may use the returned instance if it needs
688 * to do SCU IPC calls itself.
689 */
690struct intel_scu_ipc_dev *
691__devm_intel_scu_ipc_register(struct device *parent,
692 const struct intel_scu_ipc_data *scu_data,
693 struct module *owner)
694{
695 struct intel_scu_ipc_devres *dr;
696 struct intel_scu_ipc_dev *scu;
697
698 dr = devres_alloc(devm_intel_scu_ipc_unregister, sizeof(*dr), GFP_KERNEL);
699 if (!dr)
700 return NULL;
701
702 scu = __intel_scu_ipc_register(parent, scu_data, owner);
703 if (IS_ERR(scu)) {
704 devres_free(dr);
705 return scu;
706 }
707
708 dr->scu = scu;
709 devres_add(parent, dr);
710
711 return scu;
712}
713EXPORT_SYMBOL_GPL(__devm_intel_scu_ipc_register);
714
715static int __init intel_scu_ipc_init(void)
716{
717 return class_register(&intel_scu_ipc_class);
718}
719subsys_initcall(intel_scu_ipc_init);
720
721static void __exit intel_scu_ipc_exit(void)
722{
723 class_unregister(&intel_scu_ipc_class);
724}
725module_exit(intel_scu_ipc_exit);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for the Intel SCU IPC mechanism
4 *
5 * (C) Copyright 2008-2010,2015 Intel Corporation
6 * Author: Sreedhara DS (sreedhara.ds@intel.com)
7 *
8 * SCU running in ARC processor communicates with other entity running in IA
9 * core through IPC mechanism which in turn messaging between IA core ad SCU.
10 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
11 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
12 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
13 * along with other APIs.
14 */
15
16#include <linux/cleanup.h>
17#include <linux/delay.h>
18#include <linux/device.h>
19#include <linux/errno.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
23#include <linux/iopoll.h>
24#include <linux/module.h>
25#include <linux/slab.h>
26
27#include <linux/platform_data/x86/intel_scu_ipc.h>
28
29/* IPC defines the following message types */
30#define IPCMSG_PCNTRL 0xff /* Power controller unit read/write */
31
32/* Command id associated with message IPCMSG_PCNTRL */
33#define IPC_CMD_PCNTRL_W 0 /* Register write */
34#define IPC_CMD_PCNTRL_R 1 /* Register read */
35#define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */
36
37/*
38 * IPC register summary
39 *
40 * IPC register blocks are memory mapped at fixed address of PCI BAR 0.
41 * To read or write information to the SCU, driver writes to IPC-1 memory
42 * mapped registers. The following is the IPC mechanism
43 *
44 * 1. IA core cDMI interface claims this transaction and converts it to a
45 * Transaction Layer Packet (TLP) message which is sent across the cDMI.
46 *
47 * 2. South Complex cDMI block receives this message and writes it to
48 * the IPC-1 register block, causing an interrupt to the SCU
49 *
50 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate
51 * message handler is called within firmware.
52 */
53
54#define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */
55#define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */
56#define IPC_IOC 0x100 /* IPC command register IOC bit */
57
58struct intel_scu_ipc_dev {
59 struct device dev;
60 struct module *owner;
61 void __iomem *ipc_base;
62 struct completion cmd_complete;
63
64 struct intel_scu_ipc_data data;
65};
66
67#define IPC_STATUS 0x04
68#define IPC_STATUS_IRQ BIT(2)
69#define IPC_STATUS_ERR BIT(1)
70#define IPC_STATUS_BUSY BIT(0)
71
72/*
73 * IPC Write/Read Buffers:
74 * 16 byte buffer for sending and receiving data to and from SCU.
75 */
76#define IPC_WRITE_BUFFER 0x80
77#define IPC_READ_BUFFER 0x90
78
79/* Timeout in jiffies */
80#define IPC_TIMEOUT (10 * HZ)
81
82static struct intel_scu_ipc_dev *ipcdev; /* Only one for now */
83static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
84
85static struct class intel_scu_ipc_class = {
86 .name = "intel_scu_ipc",
87};
88
89/**
90 * intel_scu_ipc_dev_get() - Get SCU IPC instance
91 *
92 * The recommended new API takes SCU IPC instance as parameter and this
93 * function can be called by driver to get the instance. This also makes
94 * sure the driver providing the IPC functionality cannot be unloaded
95 * while the caller has the instance.
96 *
97 * Call intel_scu_ipc_dev_put() to release the instance.
98 *
99 * Returns %NULL if SCU IPC is not currently available.
100 */
101struct intel_scu_ipc_dev *intel_scu_ipc_dev_get(void)
102{
103 guard(mutex)(&ipclock);
104
105 if (ipcdev) {
106 get_device(&ipcdev->dev);
107 /*
108 * Prevent the IPC provider from being unloaded while it
109 * is being used.
110 */
111 if (try_module_get(ipcdev->owner))
112 return ipcdev;
113
114 put_device(&ipcdev->dev);
115 }
116
117 return NULL;
118}
119EXPORT_SYMBOL_GPL(intel_scu_ipc_dev_get);
120
121/**
122 * intel_scu_ipc_dev_put() - Put SCU IPC instance
123 * @scu: SCU IPC instance
124 *
125 * This function releases the SCU IPC instance retrieved from
126 * intel_scu_ipc_dev_get() and allows the driver providing IPC to be
127 * unloaded.
128 */
129void intel_scu_ipc_dev_put(struct intel_scu_ipc_dev *scu)
130{
131 if (scu) {
132 module_put(scu->owner);
133 put_device(&scu->dev);
134 }
135}
136EXPORT_SYMBOL_GPL(intel_scu_ipc_dev_put);
137
138struct intel_scu_ipc_devres {
139 struct intel_scu_ipc_dev *scu;
140};
141
142static void devm_intel_scu_ipc_dev_release(struct device *dev, void *res)
143{
144 struct intel_scu_ipc_devres *dr = res;
145 struct intel_scu_ipc_dev *scu = dr->scu;
146
147 intel_scu_ipc_dev_put(scu);
148}
149
150/**
151 * devm_intel_scu_ipc_dev_get() - Allocate managed SCU IPC device
152 * @dev: Device requesting the SCU IPC device
153 *
154 * The recommended new API takes SCU IPC instance as parameter and this
155 * function can be called by driver to get the instance. This also makes
156 * sure the driver providing the IPC functionality cannot be unloaded
157 * while the caller has the instance.
158 *
159 * Returns %NULL if SCU IPC is not currently available.
160 */
161struct intel_scu_ipc_dev *devm_intel_scu_ipc_dev_get(struct device *dev)
162{
163 struct intel_scu_ipc_devres *dr;
164 struct intel_scu_ipc_dev *scu;
165
166 dr = devres_alloc(devm_intel_scu_ipc_dev_release, sizeof(*dr), GFP_KERNEL);
167 if (!dr)
168 return NULL;
169
170 scu = intel_scu_ipc_dev_get();
171 if (!scu) {
172 devres_free(dr);
173 return NULL;
174 }
175
176 dr->scu = scu;
177 devres_add(dev, dr);
178
179 return scu;
180}
181EXPORT_SYMBOL_GPL(devm_intel_scu_ipc_dev_get);
182
183/*
184 * Send ipc command
185 * Command Register (Write Only):
186 * A write to this register results in an interrupt to the SCU core processor
187 * Format:
188 * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
189 */
190static inline void ipc_command(struct intel_scu_ipc_dev *scu, u32 cmd)
191{
192 reinit_completion(&scu->cmd_complete);
193 writel(cmd | IPC_IOC, scu->ipc_base);
194}
195
196/*
197 * Write ipc data
198 * IPC Write Buffer (Write Only):
199 * 16-byte buffer for sending data associated with IPC command to
200 * SCU. Size of the data is specified in the IPC_COMMAND_REG register
201 */
202static inline void ipc_data_writel(struct intel_scu_ipc_dev *scu, u32 data, u32 offset)
203{
204 writel(data, scu->ipc_base + IPC_WRITE_BUFFER + offset);
205}
206
207/*
208 * Status Register (Read Only):
209 * Driver will read this register to get the ready/busy status of the IPC
210 * block and error status of the IPC command that was just processed by SCU
211 * Format:
212 * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
213 */
214static inline u8 ipc_read_status(struct intel_scu_ipc_dev *scu)
215{
216 return __raw_readl(scu->ipc_base + IPC_STATUS);
217}
218
219/* Read ipc u32 data */
220static inline u32 ipc_data_readl(struct intel_scu_ipc_dev *scu, u32 offset)
221{
222 return readl(scu->ipc_base + IPC_READ_BUFFER + offset);
223}
224
225/* Wait till scu status is busy */
226static inline int busy_loop(struct intel_scu_ipc_dev *scu)
227{
228 u8 status;
229 int err;
230
231 err = readx_poll_timeout(ipc_read_status, scu, status, !(status & IPC_STATUS_BUSY),
232 100, jiffies_to_usecs(IPC_TIMEOUT));
233 if (err)
234 return err;
235
236 return (status & IPC_STATUS_ERR) ? -EIO : 0;
237}
238
239/* Wait till ipc ioc interrupt is received or timeout in 10 HZ */
240static inline int ipc_wait_for_interrupt(struct intel_scu_ipc_dev *scu)
241{
242 int status;
243
244 wait_for_completion_timeout(&scu->cmd_complete, IPC_TIMEOUT);
245
246 status = ipc_read_status(scu);
247 if (status & IPC_STATUS_BUSY)
248 return -ETIMEDOUT;
249
250 if (status & IPC_STATUS_ERR)
251 return -EIO;
252
253 return 0;
254}
255
256static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev *scu)
257{
258 return scu->data.irq > 0 ? ipc_wait_for_interrupt(scu) : busy_loop(scu);
259}
260
261static struct intel_scu_ipc_dev *intel_scu_ipc_get(struct intel_scu_ipc_dev *scu)
262{
263 u8 status;
264
265 if (!scu)
266 scu = ipcdev;
267 if (!scu)
268 return ERR_PTR(-ENODEV);
269
270 status = ipc_read_status(scu);
271 if (status & IPC_STATUS_BUSY) {
272 dev_dbg(&scu->dev, "device is busy\n");
273 return ERR_PTR(-EBUSY);
274 }
275
276 return scu;
277}
278
279/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
280static int pwr_reg_rdwr(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
281 u32 count, u32 op, u32 id)
282{
283 int nc;
284 u32 offset = 0;
285 int err;
286 u8 cbuf[IPC_WWBUF_SIZE];
287 u32 *wbuf = (u32 *)&cbuf;
288
289 memset(cbuf, 0, sizeof(cbuf));
290
291 guard(mutex)(&ipclock);
292
293 scu = intel_scu_ipc_get(scu);
294 if (IS_ERR(scu))
295 return PTR_ERR(scu);
296
297 for (nc = 0; nc < count; nc++, offset += 2) {
298 cbuf[offset] = addr[nc];
299 cbuf[offset + 1] = addr[nc] >> 8;
300 }
301
302 if (id == IPC_CMD_PCNTRL_R) {
303 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
304 ipc_data_writel(scu, wbuf[nc], offset);
305 ipc_command(scu, (count * 2) << 16 | id << 12 | 0 << 8 | op);
306 } else if (id == IPC_CMD_PCNTRL_W) {
307 for (nc = 0; nc < count; nc++, offset += 1)
308 cbuf[offset] = data[nc];
309 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
310 ipc_data_writel(scu, wbuf[nc], offset);
311 ipc_command(scu, (count * 3) << 16 | id << 12 | 0 << 8 | op);
312 } else if (id == IPC_CMD_PCNTRL_M) {
313 cbuf[offset] = data[0];
314 cbuf[offset + 1] = data[1];
315 ipc_data_writel(scu, wbuf[0], 0); /* Write wbuff */
316 ipc_command(scu, 4 << 16 | id << 12 | 0 << 8 | op);
317 }
318
319 err = intel_scu_ipc_check_status(scu);
320 if (err)
321 return err;
322
323 /* Read rbuf */
324 for (nc = 0, offset = 0; nc < 4; nc++, offset += 4)
325 wbuf[nc] = ipc_data_readl(scu, offset);
326 memcpy(data, wbuf, count);
327
328 return 0;
329}
330
331/**
332 * intel_scu_ipc_dev_ioread8() - Read a byte via the SCU
333 * @scu: Optional SCU IPC instance
334 * @addr: Register on SCU
335 * @data: Return pointer for read byte
336 *
337 * Read a single register. Returns %0 on success or an error code. All
338 * locking between SCU accesses is handled for the caller.
339 *
340 * This function may sleep.
341 */
342int intel_scu_ipc_dev_ioread8(struct intel_scu_ipc_dev *scu, u16 addr, u8 *data)
343{
344 return pwr_reg_rdwr(scu, &addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
345}
346EXPORT_SYMBOL(intel_scu_ipc_dev_ioread8);
347
348/**
349 * intel_scu_ipc_dev_iowrite8() - Write a byte via the SCU
350 * @scu: Optional SCU IPC instance
351 * @addr: Register on SCU
352 * @data: Byte to write
353 *
354 * Write a single register. Returns %0 on success or an error code. All
355 * locking between SCU accesses is handled for the caller.
356 *
357 * This function may sleep.
358 */
359int intel_scu_ipc_dev_iowrite8(struct intel_scu_ipc_dev *scu, u16 addr, u8 data)
360{
361 return pwr_reg_rdwr(scu, &addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
362}
363EXPORT_SYMBOL(intel_scu_ipc_dev_iowrite8);
364
365/**
366 * intel_scu_ipc_dev_readv() - Read a set of registers
367 * @scu: Optional SCU IPC instance
368 * @addr: Register list
369 * @data: Bytes to return
370 * @len: Length of array
371 *
372 * Read registers. Returns %0 on success or an error code. All locking
373 * between SCU accesses is handled for the caller.
374 *
375 * The largest array length permitted by the hardware is 5 items.
376 *
377 * This function may sleep.
378 */
379int intel_scu_ipc_dev_readv(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
380 size_t len)
381{
382 return pwr_reg_rdwr(scu, addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
383}
384EXPORT_SYMBOL(intel_scu_ipc_dev_readv);
385
386/**
387 * intel_scu_ipc_dev_writev() - Write a set of registers
388 * @scu: Optional SCU IPC instance
389 * @addr: Register list
390 * @data: Bytes to write
391 * @len: Length of array
392 *
393 * Write registers. Returns %0 on success or an error code. All locking
394 * between SCU accesses is handled for the caller.
395 *
396 * The largest array length permitted by the hardware is 5 items.
397 *
398 * This function may sleep.
399 */
400int intel_scu_ipc_dev_writev(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
401 size_t len)
402{
403 return pwr_reg_rdwr(scu, addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
404}
405EXPORT_SYMBOL(intel_scu_ipc_dev_writev);
406
407/**
408 * intel_scu_ipc_dev_update() - Update a register
409 * @scu: Optional SCU IPC instance
410 * @addr: Register address
411 * @data: Bits to update
412 * @mask: Mask of bits to update
413 *
414 * Read-modify-write power control unit register. The first data argument
415 * must be register value and second is mask value mask is a bitmap that
416 * indicates which bits to update. %0 = masked. Don't modify this bit, %1 =
417 * modify this bit. returns %0 on success or an error code.
418 *
419 * This function may sleep. Locking between SCU accesses is handled
420 * for the caller.
421 */
422int intel_scu_ipc_dev_update(struct intel_scu_ipc_dev *scu, u16 addr, u8 data,
423 u8 mask)
424{
425 u8 tmp[2] = { data, mask };
426 return pwr_reg_rdwr(scu, &addr, tmp, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
427}
428EXPORT_SYMBOL(intel_scu_ipc_dev_update);
429
430/**
431 * intel_scu_ipc_dev_simple_command() - Send a simple command
432 * @scu: Optional SCU IPC instance
433 * @cmd: Command
434 * @sub: Sub type
435 *
436 * Issue a simple command to the SCU. Do not use this interface if you must
437 * then access data as any data values may be overwritten by another SCU
438 * access by the time this function returns.
439 *
440 * This function may sleep. Locking for SCU accesses is handled for the
441 * caller.
442 */
443int intel_scu_ipc_dev_simple_command(struct intel_scu_ipc_dev *scu, int cmd,
444 int sub)
445{
446 u32 cmdval;
447 int err;
448
449 guard(mutex)(&ipclock);
450
451 scu = intel_scu_ipc_get(scu);
452 if (IS_ERR(scu))
453 return PTR_ERR(scu);
454
455 cmdval = sub << 12 | cmd;
456 ipc_command(scu, cmdval);
457 err = intel_scu_ipc_check_status(scu);
458 if (err)
459 dev_err(&scu->dev, "IPC command %#x failed with %d\n", cmdval, err);
460 return err;
461}
462EXPORT_SYMBOL(intel_scu_ipc_dev_simple_command);
463
464/**
465 * intel_scu_ipc_dev_command_with_size() - Command with data
466 * @scu: Optional SCU IPC instance
467 * @cmd: Command
468 * @sub: Sub type
469 * @in: Input data
470 * @inlen: Input length in bytes
471 * @size: Input size written to the IPC command register in whatever
472 * units (dword, byte) the particular firmware requires. Normally
473 * should be the same as @inlen.
474 * @out: Output data
475 * @outlen: Output length in bytes
476 *
477 * Issue a command to the SCU which involves data transfers. Do the
478 * data copies under the lock but leave it for the caller to interpret.
479 */
480int intel_scu_ipc_dev_command_with_size(struct intel_scu_ipc_dev *scu, int cmd,
481 int sub, const void *in, size_t inlen,
482 size_t size, void *out, size_t outlen)
483{
484 size_t outbuflen = DIV_ROUND_UP(outlen, sizeof(u32));
485 size_t inbuflen = DIV_ROUND_UP(inlen, sizeof(u32));
486 u32 cmdval, inbuf[4] = {}, outbuf[4] = {};
487 int i, err;
488
489 if (inbuflen > 4 || outbuflen > 4)
490 return -EINVAL;
491
492 guard(mutex)(&ipclock);
493
494 scu = intel_scu_ipc_get(scu);
495 if (IS_ERR(scu))
496 return PTR_ERR(scu);
497
498 memcpy(inbuf, in, inlen);
499 for (i = 0; i < inbuflen; i++)
500 ipc_data_writel(scu, inbuf[i], 4 * i);
501
502 cmdval = (size << 16) | (sub << 12) | cmd;
503 ipc_command(scu, cmdval);
504 err = intel_scu_ipc_check_status(scu);
505 if (err) {
506 dev_err(&scu->dev, "IPC command %#x failed with %d\n", cmdval, err);
507 return err;
508 }
509
510 for (i = 0; i < outbuflen; i++)
511 outbuf[i] = ipc_data_readl(scu, 4 * i);
512
513 memcpy(out, outbuf, outlen);
514
515 return 0;
516}
517EXPORT_SYMBOL(intel_scu_ipc_dev_command_with_size);
518
519/*
520 * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
521 * When ioc bit is set to 1, caller api must wait for interrupt handler called
522 * which in turn unlocks the caller api. Currently this is not used
523 *
524 * This is edge triggered so we need take no action to clear anything
525 */
526static irqreturn_t ioc(int irq, void *dev_id)
527{
528 struct intel_scu_ipc_dev *scu = dev_id;
529 int status = ipc_read_status(scu);
530
531 writel(status | IPC_STATUS_IRQ, scu->ipc_base + IPC_STATUS);
532 complete(&scu->cmd_complete);
533
534 return IRQ_HANDLED;
535}
536
537static void intel_scu_ipc_release(struct device *dev)
538{
539 struct intel_scu_ipc_dev *scu = container_of(dev, struct intel_scu_ipc_dev, dev);
540 struct intel_scu_ipc_data *data = &scu->data;
541
542 if (data->irq > 0)
543 free_irq(data->irq, scu);
544 iounmap(scu->ipc_base);
545 release_mem_region(data->mem.start, resource_size(&data->mem));
546 kfree(scu);
547}
548
549/**
550 * __intel_scu_ipc_register() - Register SCU IPC device
551 * @parent: Parent device
552 * @scu_data: Data used to configure SCU IPC
553 * @owner: Module registering the SCU IPC device
554 *
555 * Call this function to register SCU IPC mechanism under @parent.
556 * Returns pointer to the new SCU IPC device or ERR_PTR() in case of
557 * failure. The caller may use the returned instance if it needs to do
558 * SCU IPC calls itself.
559 */
560struct intel_scu_ipc_dev *
561__intel_scu_ipc_register(struct device *parent,
562 const struct intel_scu_ipc_data *scu_data,
563 struct module *owner)
564{
565 int err;
566 struct intel_scu_ipc_data *data;
567 struct intel_scu_ipc_dev *scu;
568 void __iomem *ipc_base;
569
570 guard(mutex)(&ipclock);
571
572 /* We support only one IPC */
573 if (ipcdev)
574 return ERR_PTR(-EBUSY);
575
576 scu = kzalloc(sizeof(*scu), GFP_KERNEL);
577 if (!scu)
578 return ERR_PTR(-ENOMEM);
579
580 scu->owner = owner;
581 scu->dev.parent = parent;
582 scu->dev.class = &intel_scu_ipc_class;
583 scu->dev.release = intel_scu_ipc_release;
584
585 memcpy(&scu->data, scu_data, sizeof(scu->data));
586 data = &scu->data;
587
588 if (!request_mem_region(data->mem.start, resource_size(&data->mem), "intel_scu_ipc")) {
589 err = -EBUSY;
590 goto err_free;
591 }
592
593 ipc_base = ioremap(data->mem.start, resource_size(&data->mem));
594 if (!ipc_base) {
595 err = -ENOMEM;
596 goto err_release;
597 }
598
599 scu->ipc_base = ipc_base;
600 init_completion(&scu->cmd_complete);
601
602 if (data->irq > 0) {
603 err = request_irq(data->irq, ioc, 0, "intel_scu_ipc", scu);
604 if (err)
605 goto err_unmap;
606 }
607
608 /*
609 * After this point intel_scu_ipc_release() takes care of
610 * releasing the SCU IPC resources once refcount drops to zero.
611 */
612 dev_set_name(&scu->dev, "intel_scu_ipc");
613 err = device_register(&scu->dev);
614 if (err) {
615 put_device(&scu->dev);
616 return ERR_PTR(err);
617 }
618
619 /* Assign device at last */
620 ipcdev = scu;
621 return scu;
622
623err_unmap:
624 iounmap(ipc_base);
625err_release:
626 release_mem_region(data->mem.start, resource_size(&data->mem));
627err_free:
628 kfree(scu);
629 return ERR_PTR(err);
630}
631EXPORT_SYMBOL_GPL(__intel_scu_ipc_register);
632
633/**
634 * intel_scu_ipc_unregister() - Unregister SCU IPC
635 * @scu: SCU IPC handle
636 *
637 * This unregisters the SCU IPC device and releases the acquired
638 * resources once the refcount goes to zero.
639 */
640void intel_scu_ipc_unregister(struct intel_scu_ipc_dev *scu)
641{
642 guard(mutex)(&ipclock);
643
644 if (!WARN_ON(!ipcdev)) {
645 ipcdev = NULL;
646 device_unregister(&scu->dev);
647 }
648}
649EXPORT_SYMBOL_GPL(intel_scu_ipc_unregister);
650
651static void devm_intel_scu_ipc_unregister(struct device *dev, void *res)
652{
653 struct intel_scu_ipc_devres *dr = res;
654 struct intel_scu_ipc_dev *scu = dr->scu;
655
656 intel_scu_ipc_unregister(scu);
657}
658
659/**
660 * __devm_intel_scu_ipc_register() - Register managed SCU IPC device
661 * @parent: Parent device
662 * @scu_data: Data used to configure SCU IPC
663 * @owner: Module registering the SCU IPC device
664 *
665 * Call this function to register managed SCU IPC mechanism under
666 * @parent. Returns pointer to the new SCU IPC device or ERR_PTR() in
667 * case of failure. The caller may use the returned instance if it needs
668 * to do SCU IPC calls itself.
669 */
670struct intel_scu_ipc_dev *
671__devm_intel_scu_ipc_register(struct device *parent,
672 const struct intel_scu_ipc_data *scu_data,
673 struct module *owner)
674{
675 struct intel_scu_ipc_devres *dr;
676 struct intel_scu_ipc_dev *scu;
677
678 dr = devres_alloc(devm_intel_scu_ipc_unregister, sizeof(*dr), GFP_KERNEL);
679 if (!dr)
680 return NULL;
681
682 scu = __intel_scu_ipc_register(parent, scu_data, owner);
683 if (IS_ERR(scu)) {
684 devres_free(dr);
685 return scu;
686 }
687
688 dr->scu = scu;
689 devres_add(parent, dr);
690
691 return scu;
692}
693EXPORT_SYMBOL_GPL(__devm_intel_scu_ipc_register);
694
695static int __init intel_scu_ipc_init(void)
696{
697 return class_register(&intel_scu_ipc_class);
698}
699subsys_initcall(intel_scu_ipc_init);
700
701static void __exit intel_scu_ipc_exit(void)
702{
703 class_unregister(&intel_scu_ipc_class);
704}
705module_exit(intel_scu_ipc_exit);