1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Support routines for initializing a PCI subsystem
   4 *
   5 * Extruded from code written by
   6 *      Dave Rusling (david.rusling@reo.mts.dec.com)
   7 *      David Mosberger (davidm@cs.arizona.edu)
   8 *	David Miller (davem@redhat.com)
   9 *
  10 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  11 *	     PCI-PCI bridges cleanup, sorted resource allocation.
  12 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  13 *	     Converted to allocation in 3 passes, which gives
  14 *	     tighter packing. Prefetchable range support.
  15 */
  16
 
  17#include <linux/init.h>
  18#include <linux/kernel.h>
  19#include <linux/module.h>
  20#include <linux/pci.h>
  21#include <linux/errno.h>
  22#include <linux/ioport.h>
  23#include <linux/cache.h>
 
 
  24#include <linux/slab.h>
  25#include <linux/acpi.h>
  26#include "pci.h"
  27
  28unsigned int pci_flags;
  29EXPORT_SYMBOL_GPL(pci_flags);
  30
  31struct pci_dev_resource {
  32	struct list_head list;
  33	struct resource *res;
  34	struct pci_dev *dev;
  35	resource_size_t start;
  36	resource_size_t end;
  37	resource_size_t add_size;
  38	resource_size_t min_align;
  39	unsigned long flags;
  40};
  41
  42static void free_list(struct list_head *head)
  43{
  44	struct pci_dev_resource *dev_res, *tmp;
  45
  46	list_for_each_entry_safe(dev_res, tmp, head, list) {
  47		list_del(&dev_res->list);
  48		kfree(dev_res);
  49	}
  50}
  51
  52/**
  53 * add_to_list() - Add a new resource tracker to the list
  54 * @head:	Head of the list
  55 * @dev:	Device to which the resource belongs
  56 * @res:	Resource to be tracked
  57 * @add_size:	Additional size to be optionally added to the resource
  58 * @min_align:	Minimum memory window alignment
  59 */
  60static int add_to_list(struct list_head *head, struct pci_dev *dev,
  61		       struct resource *res, resource_size_t add_size,
  62		       resource_size_t min_align)
  63{
  64	struct pci_dev_resource *tmp;
  65
  66	tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
  67	if (!tmp)
  68		return -ENOMEM;
  69
  70	tmp->res = res;
  71	tmp->dev = dev;
  72	tmp->start = res->start;
  73	tmp->end = res->end;
  74	tmp->flags = res->flags;
  75	tmp->add_size = add_size;
  76	tmp->min_align = min_align;
  77
  78	list_add(&tmp->list, head);
  79
  80	return 0;
  81}
  82
  83static void remove_from_list(struct list_head *head, struct resource *res)
  84{
  85	struct pci_dev_resource *dev_res, *tmp;
  86
  87	list_for_each_entry_safe(dev_res, tmp, head, list) {
  88		if (dev_res->res == res) {
  89			list_del(&dev_res->list);
  90			kfree(dev_res);
  91			break;
  92		}
  93	}
  94}
  95
  96static struct pci_dev_resource *res_to_dev_res(struct list_head *head,
  97					       struct resource *res)
  98{
  99	struct pci_dev_resource *dev_res;
 100
 101	list_for_each_entry(dev_res, head, list) {
 102		if (dev_res->res == res)
 103			return dev_res;
 104	}
 105
 106	return NULL;
 107}
 108
 109static resource_size_t get_res_add_size(struct list_head *head,
 110					struct resource *res)
 111{
 112	struct pci_dev_resource *dev_res;
 113
 114	dev_res = res_to_dev_res(head, res);
 115	return dev_res ? dev_res->add_size : 0;
 116}
 117
 118static resource_size_t get_res_add_align(struct list_head *head,
 119					 struct resource *res)
 120{
 121	struct pci_dev_resource *dev_res;
 122
 123	dev_res = res_to_dev_res(head, res);
 124	return dev_res ? dev_res->min_align : 0;
 125}
 126
 127/* Sort resources by alignment */
 128static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
 129{
 130	struct resource *r;
 131	int i;
 132
 133	pci_dev_for_each_resource(dev, r, i) {
 
 134		struct pci_dev_resource *dev_res, *tmp;
 135		resource_size_t r_align;
 136		struct list_head *n;
 137
 138		if (r->flags & IORESOURCE_PCI_FIXED)
 139			continue;
 140
 141		if (!(r->flags) || r->parent)
 142			continue;
 143
 144		r_align = pci_resource_alignment(dev, r);
 145		if (!r_align) {
 146			pci_warn(dev, "BAR %d: %pR has bogus alignment\n",
 147				 i, r);
 148			continue;
 149		}
 150
 151		tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
 152		if (!tmp)
 153			panic("%s: kzalloc() failed!\n", __func__);
 154		tmp->res = r;
 155		tmp->dev = dev;
 156
 157		/* Fallback is smallest one or list is empty */
 158		n = head;
 159		list_for_each_entry(dev_res, head, list) {
 160			resource_size_t align;
 161
 162			align = pci_resource_alignment(dev_res->dev,
 163							 dev_res->res);
 164
 165			if (r_align > align) {
 166				n = &dev_res->list;
 167				break;
 168			}
 169		}
 170		/* Insert it just before n */
 171		list_add_tail(&tmp->list, n);
 172	}
 173}
 174
 175static void __dev_sort_resources(struct pci_dev *dev, struct list_head *head)
 176{
 177	u16 class = dev->class >> 8;
 178
 179	/* Don't touch classless devices or host bridges or IOAPICs */
 180	if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
 181		return;
 182
 183	/* Don't touch IOAPIC devices already enabled by firmware */
 184	if (class == PCI_CLASS_SYSTEM_PIC) {
 185		u16 command;
 186		pci_read_config_word(dev, PCI_COMMAND, &command);
 187		if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
 188			return;
 189	}
 190
 191	pdev_sort_resources(dev, head);
 192}
 193
 194static inline void reset_resource(struct resource *res)
 195{
 196	res->start = 0;
 197	res->end = 0;
 198	res->flags = 0;
 199}
 200
 201/**
 202 * reassign_resources_sorted() - Satisfy any additional resource requests
 203 *
 204 * @realloc_head:	Head of the list tracking requests requiring
 205 *			additional resources
 206 * @head:		Head of the list tracking requests with allocated
 207 *			resources
 208 *
 209 * Walk through each element of the realloc_head and try to procure additional
 210 * resources for the element, provided the element is in the head list.
 211 */
 212static void reassign_resources_sorted(struct list_head *realloc_head,
 213				      struct list_head *head)
 214{
 215	struct resource *res;
 216	const char *res_name;
 217	struct pci_dev_resource *add_res, *tmp;
 218	struct pci_dev_resource *dev_res;
 219	resource_size_t add_size, align;
 220	int idx;
 221
 222	list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
 223		bool found_match = false;
 224
 225		res = add_res->res;
 226
 227		/* Skip resource that has been reset */
 228		if (!res->flags)
 229			goto out;
 230
 231		/* Skip this resource if not found in head list */
 232		list_for_each_entry(dev_res, head, list) {
 233			if (dev_res->res == res) {
 234				found_match = true;
 235				break;
 236			}
 237		}
 238		if (!found_match) /* Just skip */
 239			continue;
 240
 241		idx = res - &add_res->dev->resource[0];
 242		res_name = pci_resource_name(add_res->dev, idx);
 243		add_size = add_res->add_size;
 244		align = add_res->min_align;
 245		if (!resource_size(res)) {
 246			res->start = align;
 247			res->end = res->start + add_size - 1;
 248			if (pci_assign_resource(add_res->dev, idx))
 249				reset_resource(res);
 250		} else {
 251			res->flags |= add_res->flags &
 252				 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
 253			if (pci_reassign_resource(add_res->dev, idx,
 254						  add_size, align))
 255				pci_info(add_res->dev, "%s %pR: failed to add %llx\n",
 256					 res_name, res,
 257					 (unsigned long long) add_size);
 258		}
 259out:
 260		list_del(&add_res->list);
 261		kfree(add_res);
 262	}
 263}
 264
 265/**
 266 * assign_requested_resources_sorted() - Satisfy resource requests
 267 *
 268 * @head:	Head of the list tracking requests for resources
 269 * @fail_head:	Head of the list tracking requests that could not be
 270 *		allocated
 271 *
 272 * Satisfy resource requests of each element in the list.  Add requests that
 273 * could not be satisfied to the failed_list.
 274 */
 275static void assign_requested_resources_sorted(struct list_head *head,
 276				 struct list_head *fail_head)
 277{
 278	struct resource *res;
 279	struct pci_dev_resource *dev_res;
 280	int idx;
 281
 282	list_for_each_entry(dev_res, head, list) {
 283		res = dev_res->res;
 284		idx = res - &dev_res->dev->resource[0];
 285		if (resource_size(res) &&
 286		    pci_assign_resource(dev_res->dev, idx)) {
 287			if (fail_head) {
 288				/*
 289				 * If the failed resource is a ROM BAR and
 290				 * it will be enabled later, don't add it
 291				 * to the list.
 292				 */
 293				if (!((idx == PCI_ROM_RESOURCE) &&
 294				      (!(res->flags & IORESOURCE_ROM_ENABLE))))
 295					add_to_list(fail_head,
 296						    dev_res->dev, res,
 297						    0 /* don't care */,
 298						    0 /* don't care */);
 299			}
 300			reset_resource(res);
 301		}
 302	}
 303}
 304
 305static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
 306{
 307	struct pci_dev_resource *fail_res;
 308	unsigned long mask = 0;
 309
 310	/* Check failed type */
 311	list_for_each_entry(fail_res, fail_head, list)
 312		mask |= fail_res->flags;
 313
 314	/*
 315	 * One pref failed resource will set IORESOURCE_MEM, as we can
 316	 * allocate pref in non-pref range.  Will release all assigned
 317	 * non-pref sibling resources according to that bit.
 318	 */
 319	return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
 320}
 321
 322static bool pci_need_to_release(unsigned long mask, struct resource *res)
 323{
 324	if (res->flags & IORESOURCE_IO)
 325		return !!(mask & IORESOURCE_IO);
 326
 327	/* Check pref at first */
 328	if (res->flags & IORESOURCE_PREFETCH) {
 329		if (mask & IORESOURCE_PREFETCH)
 330			return true;
 331		/* Count pref if its parent is non-pref */
 332		else if ((mask & IORESOURCE_MEM) &&
 333			 !(res->parent->flags & IORESOURCE_PREFETCH))
 334			return true;
 335		else
 336			return false;
 337	}
 338
 339	if (res->flags & IORESOURCE_MEM)
 340		return !!(mask & IORESOURCE_MEM);
 341
 342	return false;	/* Should not get here */
 343}
 344
 345static void __assign_resources_sorted(struct list_head *head,
 346				      struct list_head *realloc_head,
 347				      struct list_head *fail_head)
 348{
 349	/*
 350	 * Should not assign requested resources at first.  They could be
 351	 * adjacent, so later reassign can not reallocate them one by one in
 352	 * parent resource window.
 353	 *
 354	 * Try to assign requested + add_size at beginning.  If could do that,
 355	 * could get out early.  If could not do that, we still try to assign
 356	 * requested at first, then try to reassign add_size for some resources.
 357	 *
 358	 * Separate three resource type checking if we need to release
 359	 * assigned resource after requested + add_size try.
 360	 *
 361	 *	1. If IO port assignment fails, will release assigned IO
 362	 *	   port.
 363	 *	2. If pref MMIO assignment fails, release assigned pref
 364	 *	   MMIO.  If assigned pref MMIO's parent is non-pref MMIO
 365	 *	   and non-pref MMIO assignment fails, will release that
 366	 *	   assigned pref MMIO.
 367	 *	3. If non-pref MMIO assignment fails or pref MMIO
 368	 *	   assignment fails, will release assigned non-pref MMIO.
 369	 */
 370	LIST_HEAD(save_head);
 371	LIST_HEAD(local_fail_head);
 372	struct pci_dev_resource *save_res;
 373	struct pci_dev_resource *dev_res, *tmp_res, *dev_res2;
 374	unsigned long fail_type;
 375	resource_size_t add_align, align;
 376
 377	/* Check if optional add_size is there */
 378	if (!realloc_head || list_empty(realloc_head))
 379		goto requested_and_reassign;
 380
 381	/* Save original start, end, flags etc at first */
 382	list_for_each_entry(dev_res, head, list) {
 383		if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
 384			free_list(&save_head);
 385			goto requested_and_reassign;
 386		}
 387	}
 388
 389	/* Update res in head list with add_size in realloc_head list */
 390	list_for_each_entry_safe(dev_res, tmp_res, head, list) {
 391		dev_res->res->end += get_res_add_size(realloc_head,
 392							dev_res->res);
 393
 394		/*
 395		 * There are two kinds of additional resources in the list:
 396		 * 1. bridge resource  -- IORESOURCE_STARTALIGN
 397		 * 2. SR-IOV resource  -- IORESOURCE_SIZEALIGN
 398		 * Here just fix the additional alignment for bridge
 399		 */
 400		if (!(dev_res->res->flags & IORESOURCE_STARTALIGN))
 401			continue;
 402
 403		add_align = get_res_add_align(realloc_head, dev_res->res);
 404
 405		/*
 406		 * The "head" list is sorted by alignment so resources with
 407		 * bigger alignment will be assigned first.  After we
 408		 * change the alignment of a dev_res in "head" list, we
 409		 * need to reorder the list by alignment to make it
 410		 * consistent.
 411		 */
 412		if (add_align > dev_res->res->start) {
 413			resource_size_t r_size = resource_size(dev_res->res);
 414
 415			dev_res->res->start = add_align;
 416			dev_res->res->end = add_align + r_size - 1;
 417
 418			list_for_each_entry(dev_res2, head, list) {
 419				align = pci_resource_alignment(dev_res2->dev,
 420							       dev_res2->res);
 421				if (add_align > align) {
 422					list_move_tail(&dev_res->list,
 423						       &dev_res2->list);
 424					break;
 425				}
 426			}
 427		}
 428
 429	}
 430
 431	/* Try updated head list with add_size added */
 432	assign_requested_resources_sorted(head, &local_fail_head);
 433
 434	/* All assigned with add_size? */
 435	if (list_empty(&local_fail_head)) {
 436		/* Remove head list from realloc_head list */
 437		list_for_each_entry(dev_res, head, list)
 438			remove_from_list(realloc_head, dev_res->res);
 439		free_list(&save_head);
 440		free_list(head);
 441		return;
 442	}
 443
 444	/* Check failed type */
 445	fail_type = pci_fail_res_type_mask(&local_fail_head);
 446	/* Remove not need to be released assigned res from head list etc */
 447	list_for_each_entry_safe(dev_res, tmp_res, head, list)
 448		if (dev_res->res->parent &&
 449		    !pci_need_to_release(fail_type, dev_res->res)) {
 450			/* Remove it from realloc_head list */
 451			remove_from_list(realloc_head, dev_res->res);
 452			remove_from_list(&save_head, dev_res->res);
 453			list_del(&dev_res->list);
 454			kfree(dev_res);
 455		}
 456
 457	free_list(&local_fail_head);
 458	/* Release assigned resource */
 459	list_for_each_entry(dev_res, head, list)
 460		if (dev_res->res->parent)
 461			release_resource(dev_res->res);
 462	/* Restore start/end/flags from saved list */
 463	list_for_each_entry(save_res, &save_head, list) {
 464		struct resource *res = save_res->res;
 465
 466		res->start = save_res->start;
 467		res->end = save_res->end;
 468		res->flags = save_res->flags;
 469	}
 470	free_list(&save_head);
 471
 472requested_and_reassign:
 473	/* Satisfy the must-have resource requests */
 474	assign_requested_resources_sorted(head, fail_head);
 475
 476	/* Try to satisfy any additional optional resource requests */
 477	if (realloc_head)
 478		reassign_resources_sorted(realloc_head, head);
 479	free_list(head);
 480}
 481
 482static void pdev_assign_resources_sorted(struct pci_dev *dev,
 483					 struct list_head *add_head,
 484					 struct list_head *fail_head)
 485{
 486	LIST_HEAD(head);
 487
 488	__dev_sort_resources(dev, &head);
 489	__assign_resources_sorted(&head, add_head, fail_head);
 490
 491}
 492
 493static void pbus_assign_resources_sorted(const struct pci_bus *bus,
 494					 struct list_head *realloc_head,
 495					 struct list_head *fail_head)
 496{
 497	struct pci_dev *dev;
 498	LIST_HEAD(head);
 499
 500	list_for_each_entry(dev, &bus->devices, bus_list)
 501		__dev_sort_resources(dev, &head);
 502
 503	__assign_resources_sorted(&head, realloc_head, fail_head);
 504}
 505
 506void pci_setup_cardbus(struct pci_bus *bus)
 507{
 508	struct pci_dev *bridge = bus->self;
 509	struct resource *res;
 510	struct pci_bus_region region;
 511
 512	pci_info(bridge, "CardBus bridge to %pR\n",
 513		 &bus->busn_res);
 514
 515	res = bus->resource[0];
 516	pcibios_resource_to_bus(bridge->bus, &region, res);
 517	if (res->flags & IORESOURCE_IO) {
 518		/*
 519		 * The IO resource is allocated a range twice as large as it
 520		 * would normally need.  This allows us to set both IO regs.
 521		 */
 522		pci_info(bridge, "  bridge window %pR\n", res);
 523		pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
 524					region.start);
 525		pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
 526					region.end);
 527	}
 528
 529	res = bus->resource[1];
 530	pcibios_resource_to_bus(bridge->bus, &region, res);
 531	if (res->flags & IORESOURCE_IO) {
 532		pci_info(bridge, "  bridge window %pR\n", res);
 533		pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
 534					region.start);
 535		pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
 536					region.end);
 537	}
 538
 539	res = bus->resource[2];
 540	pcibios_resource_to_bus(bridge->bus, &region, res);
 541	if (res->flags & IORESOURCE_MEM) {
 542		pci_info(bridge, "  bridge window %pR\n", res);
 543		pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
 544					region.start);
 545		pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
 546					region.end);
 547	}
 548
 549	res = bus->resource[3];
 550	pcibios_resource_to_bus(bridge->bus, &region, res);
 551	if (res->flags & IORESOURCE_MEM) {
 552		pci_info(bridge, "  bridge window %pR\n", res);
 553		pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
 554					region.start);
 555		pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
 556					region.end);
 557	}
 558}
 559EXPORT_SYMBOL(pci_setup_cardbus);
 560
 561/*
 562 * Initialize bridges with base/limit values we have collected.  PCI-to-PCI
 563 * Bridge Architecture Specification rev. 1.1 (1998) requires that if there
 564 * are no I/O ports or memory behind the bridge, the corresponding range
 565 * must be turned off by writing base value greater than limit to the
 566 * bridge's base/limit registers.
 567 *
 568 * Note: care must be taken when updating I/O base/limit registers of
 569 * bridges which support 32-bit I/O.  This update requires two config space
 570 * writes, so it's quite possible that an I/O window of the bridge will
 571 * have some undesirable address (e.g. 0) after the first write.  Ditto
 572 * 64-bit prefetchable MMIO.
 573 */
 574static void pci_setup_bridge_io(struct pci_dev *bridge)
 575{
 576	struct resource *res;
 577	const char *res_name;
 578	struct pci_bus_region region;
 579	unsigned long io_mask;
 580	u8 io_base_lo, io_limit_lo;
 581	u16 l;
 582	u32 io_upper16;
 583
 584	io_mask = PCI_IO_RANGE_MASK;
 585	if (bridge->io_window_1k)
 586		io_mask = PCI_IO_1K_RANGE_MASK;
 587
 588	/* Set up the top and bottom of the PCI I/O segment for this bus */
 589	res = &bridge->resource[PCI_BRIDGE_IO_WINDOW];
 590	res_name = pci_resource_name(bridge, PCI_BRIDGE_IO_WINDOW);
 591	pcibios_resource_to_bus(bridge->bus, &region, res);
 592	if (res->flags & IORESOURCE_IO) {
 593		pci_read_config_word(bridge, PCI_IO_BASE, &l);
 594		io_base_lo = (region.start >> 8) & io_mask;
 595		io_limit_lo = (region.end >> 8) & io_mask;
 596		l = ((u16) io_limit_lo << 8) | io_base_lo;
 597		/* Set up upper 16 bits of I/O base/limit */
 598		io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
 599		pci_info(bridge, "  %s %pR\n", res_name, res);
 600	} else {
 601		/* Clear upper 16 bits of I/O base/limit */
 602		io_upper16 = 0;
 603		l = 0x00f0;
 604	}
 605	/* Temporarily disable the I/O range before updating PCI_IO_BASE */
 606	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
 607	/* Update lower 16 bits of I/O base/limit */
 608	pci_write_config_word(bridge, PCI_IO_BASE, l);
 609	/* Update upper 16 bits of I/O base/limit */
 610	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
 611}
 612
 613static void pci_setup_bridge_mmio(struct pci_dev *bridge)
 614{
 615	struct resource *res;
 616	const char *res_name;
 617	struct pci_bus_region region;
 618	u32 l;
 619
 620	/* Set up the top and bottom of the PCI Memory segment for this bus */
 621	res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW];
 622	res_name = pci_resource_name(bridge, PCI_BRIDGE_MEM_WINDOW);
 623	pcibios_resource_to_bus(bridge->bus, &region, res);
 624	if (res->flags & IORESOURCE_MEM) {
 625		l = (region.start >> 16) & 0xfff0;
 626		l |= region.end & 0xfff00000;
 627		pci_info(bridge, "  %s %pR\n", res_name, res);
 628	} else {
 629		l = 0x0000fff0;
 630	}
 631	pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
 632}
 633
 634static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
 635{
 636	struct resource *res;
 637	const char *res_name;
 638	struct pci_bus_region region;
 639	u32 l, bu, lu;
 640
 641	/*
 642	 * Clear out the upper 32 bits of PREF limit.  If
 643	 * PCI_PREF_BASE_UPPER32 was non-zero, this temporarily disables
 644	 * PREF range, which is ok.
 645	 */
 646	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
 647
 648	/* Set up PREF base/limit */
 649	bu = lu = 0;
 650	res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
 651	res_name = pci_resource_name(bridge, PCI_BRIDGE_PREF_MEM_WINDOW);
 652	pcibios_resource_to_bus(bridge->bus, &region, res);
 653	if (res->flags & IORESOURCE_PREFETCH) {
 654		l = (region.start >> 16) & 0xfff0;
 655		l |= region.end & 0xfff00000;
 656		if (res->flags & IORESOURCE_MEM_64) {
 657			bu = upper_32_bits(region.start);
 658			lu = upper_32_bits(region.end);
 659		}
 660		pci_info(bridge, "  %s %pR\n", res_name, res);
 661	} else {
 662		l = 0x0000fff0;
 663	}
 664	pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
 665
 666	/* Set the upper 32 bits of PREF base & limit */
 667	pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
 668	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
 669}
 670
 671static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
 672{
 673	struct pci_dev *bridge = bus->self;
 674
 675	pci_info(bridge, "PCI bridge to %pR\n",
 676		 &bus->busn_res);
 677
 678	if (type & IORESOURCE_IO)
 679		pci_setup_bridge_io(bridge);
 680
 681	if (type & IORESOURCE_MEM)
 682		pci_setup_bridge_mmio(bridge);
 683
 684	if (type & IORESOURCE_PREFETCH)
 685		pci_setup_bridge_mmio_pref(bridge);
 686
 687	pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
 688}
 689
 690void __weak pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
 691{
 692}
 693
 694void pci_setup_bridge(struct pci_bus *bus)
 695{
 696	unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
 697				  IORESOURCE_PREFETCH;
 698
 699	pcibios_setup_bridge(bus, type);
 700	__pci_setup_bridge(bus, type);
 701}
 702
 703
 704int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
 705{
 706	if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END)
 707		return 0;
 708
 709	if (pci_claim_resource(bridge, i) == 0)
 710		return 0;	/* Claimed the window */
 711
 712	if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
 713		return 0;
 714
 715	if (!pci_bus_clip_resource(bridge, i))
 716		return -EINVAL;	/* Clipping didn't change anything */
 717
 718	switch (i) {
 719	case PCI_BRIDGE_IO_WINDOW:
 720		pci_setup_bridge_io(bridge);
 721		break;
 722	case PCI_BRIDGE_MEM_WINDOW:
 723		pci_setup_bridge_mmio(bridge);
 724		break;
 725	case PCI_BRIDGE_PREF_MEM_WINDOW:
 726		pci_setup_bridge_mmio_pref(bridge);
 727		break;
 728	default:
 729		return -EINVAL;
 730	}
 731
 732	if (pci_claim_resource(bridge, i) == 0)
 733		return 0;	/* Claimed a smaller window */
 734
 735	return -EINVAL;
 736}
 737
 738/*
 739 * Check whether the bridge supports optional I/O and prefetchable memory
 740 * ranges.  If not, the respective base/limit registers must be read-only
 741 * and read as 0.
 742 */
 743static void pci_bridge_check_ranges(struct pci_bus *bus)
 744{
 745	struct pci_dev *bridge = bus->self;
 746	struct resource *b_res;
 747
 748	b_res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW];
 749	b_res->flags |= IORESOURCE_MEM;
 750
 751	if (bridge->io_window) {
 752		b_res = &bridge->resource[PCI_BRIDGE_IO_WINDOW];
 753		b_res->flags |= IORESOURCE_IO;
 754	}
 755
 756	if (bridge->pref_window) {
 757		b_res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
 758		b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
 759		if (bridge->pref_64_window) {
 760			b_res->flags |= IORESOURCE_MEM_64 |
 761					PCI_PREF_RANGE_TYPE_64;
 762		}
 763	}
 764}
 765
 766/*
 767 * Helper function for sizing routines.  Assigned resources have non-NULL
 768 * parent resource.
 769 *
 770 * Return first unassigned resource of the correct type.  If there is none,
 771 * return first assigned resource of the correct type.  If none of the
 772 * above, return NULL.
 773 *
 774 * Returning an assigned resource of the correct type allows the caller to
 775 * distinguish between already assigned and no resource of the correct type.
 776 */
 777static struct resource *find_bus_resource_of_type(struct pci_bus *bus,
 778						  unsigned long type_mask,
 779						  unsigned long type)
 780{
 781	struct resource *r, *r_assigned = NULL;
 782
 783	pci_bus_for_each_resource(bus, r) {
 784		if (r == &ioport_resource || r == &iomem_resource)
 785			continue;
 786		if (r && (r->flags & type_mask) == type && !r->parent)
 787			return r;
 788		if (r && (r->flags & type_mask) == type && !r_assigned)
 789			r_assigned = r;
 790	}
 791	return r_assigned;
 792}
 793
 794static resource_size_t calculate_iosize(resource_size_t size,
 795					resource_size_t min_size,
 796					resource_size_t size1,
 797					resource_size_t add_size,
 798					resource_size_t children_add_size,
 799					resource_size_t old_size,
 800					resource_size_t align)
 801{
 802	if (size < min_size)
 803		size = min_size;
 804	if (old_size == 1)
 805		old_size = 0;
 806	/*
 807	 * To be fixed in 2.5: we should have sort of HAVE_ISA flag in the
 808	 * struct pci_bus.
 809	 */
 810#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
 811	size = (size & 0xff) + ((size & ~0xffUL) << 2);
 812#endif
 813	size = size + size1;
 814	if (size < old_size)
 815		size = old_size;
 816
 817	size = ALIGN(max(size, add_size) + children_add_size, align);
 818	return size;
 819}
 820
 821static resource_size_t calculate_memsize(resource_size_t size,
 822					 resource_size_t min_size,
 823					 resource_size_t add_size,
 824					 resource_size_t children_add_size,
 825					 resource_size_t old_size,
 826					 resource_size_t align)
 827{
 828	if (size < min_size)
 829		size = min_size;
 830	if (old_size == 1)
 831		old_size = 0;
 832	if (size < old_size)
 833		size = old_size;
 834
 835	size = ALIGN(max(size, add_size) + children_add_size, align);
 836	return size;
 837}
 838
 839resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
 840						unsigned long type)
 841{
 842	return 1;
 843}
 844
 845#define PCI_P2P_DEFAULT_MEM_ALIGN	0x100000	/* 1MiB */
 846#define PCI_P2P_DEFAULT_IO_ALIGN	0x1000		/* 4KiB */
 847#define PCI_P2P_DEFAULT_IO_ALIGN_1K	0x400		/* 1KiB */
 848
 849static resource_size_t window_alignment(struct pci_bus *bus, unsigned long type)
 850{
 851	resource_size_t align = 1, arch_align;
 852
 853	if (type & IORESOURCE_MEM)
 854		align = PCI_P2P_DEFAULT_MEM_ALIGN;
 855	else if (type & IORESOURCE_IO) {
 856		/*
 857		 * Per spec, I/O windows are 4K-aligned, but some bridges have
 858		 * an extension to support 1K alignment.
 859		 */
 860		if (bus->self && bus->self->io_window_1k)
 861			align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
 862		else
 863			align = PCI_P2P_DEFAULT_IO_ALIGN;
 864	}
 865
 866	arch_align = pcibios_window_alignment(bus, type);
 867	return max(align, arch_align);
 868}
 869
 870/**
 871 * pbus_size_io() - Size the I/O window of a given bus
 872 *
 873 * @bus:		The bus
 874 * @min_size:		The minimum I/O window that must be allocated
 875 * @add_size:		Additional optional I/O window
 876 * @realloc_head:	Track the additional I/O window on this list
 877 *
 878 * Sizing the I/O windows of the PCI-PCI bridge is trivial, since these
 879 * windows have 1K or 4K granularity and the I/O ranges of non-bridge PCI
 880 * devices are limited to 256 bytes.  We must be careful with the ISA
 881 * aliasing though.
 882 */
 883static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
 884			 resource_size_t add_size,
 885			 struct list_head *realloc_head)
 886{
 887	struct pci_dev *dev;
 888	struct resource *b_res = find_bus_resource_of_type(bus, IORESOURCE_IO,
 889							   IORESOURCE_IO);
 890	resource_size_t size = 0, size0 = 0, size1 = 0;
 891	resource_size_t children_add_size = 0;
 892	resource_size_t min_align, align;
 893
 894	if (!b_res)
 895		return;
 896
 897	/* If resource is already assigned, nothing more to do */
 898	if (b_res->parent)
 899		return;
 900
 901	min_align = window_alignment(bus, IORESOURCE_IO);
 902	list_for_each_entry(dev, &bus->devices, bus_list) {
 903		struct resource *r;
 904
 905		pci_dev_for_each_resource(dev, r) {
 906			unsigned long r_size;
 907
 908			if (r->parent || !(r->flags & IORESOURCE_IO))
 909				continue;
 910			r_size = resource_size(r);
 911
 912			if (r_size < 0x400)
 913				/* Might be re-aligned for ISA */
 914				size += r_size;
 915			else
 916				size1 += r_size;
 917
 918			align = pci_resource_alignment(dev, r);
 919			if (align > min_align)
 920				min_align = align;
 921
 922			if (realloc_head)
 923				children_add_size += get_res_add_size(realloc_head, r);
 924		}
 925	}
 926
 927	size0 = calculate_iosize(size, min_size, size1, 0, 0,
 928			resource_size(b_res), min_align);
 929	size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 :
 930		calculate_iosize(size, min_size, size1, add_size, children_add_size,
 931			resource_size(b_res), min_align);
 932	if (!size0 && !size1) {
 933		if (bus->self && (b_res->start || b_res->end))
 934			pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
 935				 b_res, &bus->busn_res);
 936		b_res->flags = 0;
 937		return;
 938	}
 939
 940	b_res->start = min_align;
 941	b_res->end = b_res->start + size0 - 1;
 942	b_res->flags |= IORESOURCE_STARTALIGN;
 943	if (bus->self && size1 > size0 && realloc_head) {
 944		add_to_list(realloc_head, bus->self, b_res, size1-size0,
 945			    min_align);
 946		pci_info(bus->self, "bridge window %pR to %pR add_size %llx\n",
 947			 b_res, &bus->busn_res,
 948			 (unsigned long long) size1 - size0);
 949	}
 950}
 951
 952static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
 953						  int max_order)
 954{
 955	resource_size_t align = 0;
 956	resource_size_t min_align = 0;
 957	int order;
 958
 959	for (order = 0; order <= max_order; order++) {
 960		resource_size_t align1 = 1;
 961
 962		align1 <<= (order + 20);
 963
 964		if (!align)
 965			min_align = align1;
 966		else if (ALIGN(align + min_align, min_align) < align1)
 967			min_align = align1 >> 1;
 968		align += aligns[order];
 969	}
 970
 971	return min_align;
 972}
 973
 974/**
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 975 * pbus_size_mem() - Size the memory window of a given bus
 976 *
 977 * @bus:		The bus
 978 * @mask:		Mask the resource flag, then compare it with type
 979 * @type:		The type of free resource from bridge
 980 * @type2:		Second match type
 981 * @type3:		Third match type
 982 * @min_size:		The minimum memory window that must be allocated
 983 * @add_size:		Additional optional memory window
 984 * @realloc_head:	Track the additional memory window on this list
 985 *
 986 * Calculate the size of the bus and minimal alignment which guarantees
 987 * that all child resources fit in this size.
 988 *
 989 * Return -ENOSPC if there's no available bus resource of the desired
 990 * type.  Otherwise, set the bus resource start/end to indicate the
 991 * required size, add things to realloc_head (if supplied), and return 0.
 992 */
 993static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
 994			 unsigned long type, unsigned long type2,
 995			 unsigned long type3, resource_size_t min_size,
 996			 resource_size_t add_size,
 997			 struct list_head *realloc_head)
 998{
 999	struct pci_dev *dev;
1000	resource_size_t min_align, align, size, size0, size1;
1001	resource_size_t aligns[24]; /* Alignments from 1MB to 8TB */
1002	int order, max_order;
1003	struct resource *b_res = find_bus_resource_of_type(bus,
1004					mask | IORESOURCE_PREFETCH, type);
1005	resource_size_t children_add_size = 0;
1006	resource_size_t children_add_align = 0;
1007	resource_size_t add_align = 0;
1008
1009	if (!b_res)
1010		return -ENOSPC;
1011
1012	/* If resource is already assigned, nothing more to do */
1013	if (b_res->parent)
1014		return 0;
1015
1016	memset(aligns, 0, sizeof(aligns));
1017	max_order = 0;
1018	size = 0;
1019
1020	list_for_each_entry(dev, &bus->devices, bus_list) {
1021		struct resource *r;
1022		int i;
1023
1024		pci_dev_for_each_resource(dev, r, i) {
1025			const char *r_name = pci_resource_name(dev, i);
1026			resource_size_t r_size;
1027
1028			if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) ||
1029			    ((r->flags & mask) != type &&
1030			     (r->flags & mask) != type2 &&
1031			     (r->flags & mask) != type3))
1032				continue;
1033			r_size = resource_size(r);
1034#ifdef CONFIG_PCI_IOV
1035			/* Put SRIOV requested res to the optional list */
1036			if (realloc_head && i >= PCI_IOV_RESOURCES &&
1037					i <= PCI_IOV_RESOURCE_END) {
1038				add_align = max(pci_resource_alignment(dev, r), add_align);
1039				r->end = r->start - 1;
1040				add_to_list(realloc_head, dev, r, r_size, 0 /* Don't care */);
1041				children_add_size += r_size;
1042				continue;
1043			}
1044#endif
1045			/*
1046			 * aligns[0] is for 1MB (since bridge memory
1047			 * windows are always at least 1MB aligned), so
1048			 * keep "order" from being negative for smaller
1049			 * resources.
1050			 */
1051			align = pci_resource_alignment(dev, r);
1052			order = __ffs(align) - 20;
1053			if (order < 0)
1054				order = 0;
1055			if (order >= ARRAY_SIZE(aligns)) {
1056				pci_warn(dev, "%s %pR: disabling; bad alignment %#llx\n",
1057					 r_name, r, (unsigned long long) align);
1058				r->flags = 0;
1059				continue;
1060			}
1061			size += max(r_size, align);
1062			/*
1063			 * Exclude ranges with size > align from calculation of
1064			 * the alignment.
1065			 */
1066			if (r_size <= align)
1067				aligns[order] += align;
1068			if (order > max_order)
1069				max_order = order;
1070
1071			if (realloc_head) {
1072				children_add_size += get_res_add_size(realloc_head, r);
1073				children_add_align = get_res_add_align(realloc_head, r);
1074				add_align = max(add_align, children_add_align);
1075			}
1076		}
1077	}
1078
 
1079	min_align = calculate_mem_align(aligns, max_order);
1080	min_align = max(min_align, window_alignment(bus, b_res->flags));
1081	size0 = calculate_memsize(size, min_size, 0, 0, resource_size(b_res), min_align);
1082	add_align = max(min_align, add_align);
 
 
 
 
 
 
 
 
 
 
 
 
1083	size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 :
1084		calculate_memsize(size, min_size, add_size, children_add_size,
1085				resource_size(b_res), add_align);
1086	if (!size0 && !size1) {
1087		if (bus->self && (b_res->start || b_res->end))
1088			pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
1089				 b_res, &bus->busn_res);
1090		b_res->flags = 0;
1091		return 0;
1092	}
1093	b_res->start = min_align;
1094	b_res->end = size0 + min_align - 1;
1095	b_res->flags |= IORESOURCE_STARTALIGN;
1096	if (bus->self && size1 > size0 && realloc_head) {
1097		add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align);
1098		pci_info(bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n",
1099			   b_res, &bus->busn_res,
1100			   (unsigned long long) (size1 - size0),
1101			   (unsigned long long) add_align);
1102	}
1103	return 0;
1104}
1105
1106unsigned long pci_cardbus_resource_alignment(struct resource *res)
1107{
1108	if (res->flags & IORESOURCE_IO)
1109		return pci_cardbus_io_size;
1110	if (res->flags & IORESOURCE_MEM)
1111		return pci_cardbus_mem_size;
1112	return 0;
1113}
1114
1115static void pci_bus_size_cardbus(struct pci_bus *bus,
1116				 struct list_head *realloc_head)
1117{
1118	struct pci_dev *bridge = bus->self;
1119	struct resource *b_res;
1120	resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
1121	u16 ctrl;
1122
1123	b_res = &bridge->resource[PCI_CB_BRIDGE_IO_0_WINDOW];
1124	if (b_res->parent)
1125		goto handle_b_res_1;
1126	/*
1127	 * Reserve some resources for CardBus.  We reserve a fixed amount
1128	 * of bus space for CardBus bridges.
1129	 */
1130	b_res->start = pci_cardbus_io_size;
1131	b_res->end = b_res->start + pci_cardbus_io_size - 1;
1132	b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1133	if (realloc_head) {
1134		b_res->end -= pci_cardbus_io_size;
1135		add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
1136			    pci_cardbus_io_size);
1137	}
1138
1139handle_b_res_1:
1140	b_res = &bridge->resource[PCI_CB_BRIDGE_IO_1_WINDOW];
1141	if (b_res->parent)
1142		goto handle_b_res_2;
1143	b_res->start = pci_cardbus_io_size;
1144	b_res->end = b_res->start + pci_cardbus_io_size - 1;
1145	b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1146	if (realloc_head) {
1147		b_res->end -= pci_cardbus_io_size;
1148		add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
1149			    pci_cardbus_io_size);
1150	}
1151
1152handle_b_res_2:
1153	/* MEM1 must not be pref MMIO */
1154	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1155	if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
1156		ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
1157		pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1158		pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1159	}
1160
1161	/* Check whether prefetchable memory is supported by this bridge. */
1162	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1163	if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
1164		ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
1165		pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1166		pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1167	}
1168
1169	b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_0_WINDOW];
1170	if (b_res->parent)
1171		goto handle_b_res_3;
1172	/*
1173	 * If we have prefetchable memory support, allocate two regions.
1174	 * Otherwise, allocate one region of twice the size.
1175	 */
1176	if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
1177		b_res->start = pci_cardbus_mem_size;
1178		b_res->end = b_res->start + pci_cardbus_mem_size - 1;
1179		b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
1180				    IORESOURCE_STARTALIGN;
1181		if (realloc_head) {
1182			b_res->end -= pci_cardbus_mem_size;
1183			add_to_list(realloc_head, bridge, b_res,
1184				    pci_cardbus_mem_size, pci_cardbus_mem_size);
1185		}
1186
1187		/* Reduce that to half */
1188		b_res_3_size = pci_cardbus_mem_size;
1189	}
1190
1191handle_b_res_3:
1192	b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_1_WINDOW];
1193	if (b_res->parent)
1194		goto handle_done;
1195	b_res->start = pci_cardbus_mem_size;
1196	b_res->end = b_res->start + b_res_3_size - 1;
1197	b_res->flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
1198	if (realloc_head) {
1199		b_res->end -= b_res_3_size;
1200		add_to_list(realloc_head, bridge, b_res, b_res_3_size,
1201			    pci_cardbus_mem_size);
1202	}
1203
1204handle_done:
1205	;
1206}
1207
1208void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
1209{
1210	struct pci_dev *dev;
1211	unsigned long mask, prefmask, type2 = 0, type3 = 0;
1212	resource_size_t additional_io_size = 0, additional_mmio_size = 0,
1213			additional_mmio_pref_size = 0;
1214	struct resource *pref;
1215	struct pci_host_bridge *host;
1216	int hdr_type, ret;
1217
1218	list_for_each_entry(dev, &bus->devices, bus_list) {
1219		struct pci_bus *b = dev->subordinate;
1220		if (!b)
1221			continue;
1222
1223		switch (dev->hdr_type) {
1224		case PCI_HEADER_TYPE_CARDBUS:
1225			pci_bus_size_cardbus(b, realloc_head);
1226			break;
1227
1228		case PCI_HEADER_TYPE_BRIDGE:
1229		default:
1230			__pci_bus_size_bridges(b, realloc_head);
1231			break;
1232		}
1233	}
1234
1235	/* The root bus? */
1236	if (pci_is_root_bus(bus)) {
1237		host = to_pci_host_bridge(bus->bridge);
1238		if (!host->size_windows)
1239			return;
1240		pci_bus_for_each_resource(bus, pref)
1241			if (pref && (pref->flags & IORESOURCE_PREFETCH))
1242				break;
1243		hdr_type = -1;	/* Intentionally invalid - not a PCI device. */
1244	} else {
1245		pref = &bus->self->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
1246		hdr_type = bus->self->hdr_type;
1247	}
1248
1249	switch (hdr_type) {
1250	case PCI_HEADER_TYPE_CARDBUS:
1251		/* Don't size CardBuses yet */
1252		break;
1253
1254	case PCI_HEADER_TYPE_BRIDGE:
1255		pci_bridge_check_ranges(bus);
1256		if (bus->self->is_hotplug_bridge) {
1257			additional_io_size  = pci_hotplug_io_size;
1258			additional_mmio_size = pci_hotplug_mmio_size;
1259			additional_mmio_pref_size = pci_hotplug_mmio_pref_size;
1260		}
1261		fallthrough;
1262	default:
1263		pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1264			     additional_io_size, realloc_head);
1265
1266		/*
1267		 * If there's a 64-bit prefetchable MMIO window, compute
1268		 * the size required to put all 64-bit prefetchable
1269		 * resources in it.
1270		 */
1271		mask = IORESOURCE_MEM;
1272		prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
1273		if (pref && (pref->flags & IORESOURCE_MEM_64)) {
1274			prefmask |= IORESOURCE_MEM_64;
1275			ret = pbus_size_mem(bus, prefmask, prefmask,
1276				prefmask, prefmask,
1277				realloc_head ? 0 : additional_mmio_pref_size,
1278				additional_mmio_pref_size, realloc_head);
1279
1280			/*
1281			 * If successful, all non-prefetchable resources
1282			 * and any 32-bit prefetchable resources will go in
1283			 * the non-prefetchable window.
1284			 */
1285			if (ret == 0) {
1286				mask = prefmask;
1287				type2 = prefmask & ~IORESOURCE_MEM_64;
1288				type3 = prefmask & ~IORESOURCE_PREFETCH;
1289			}
1290		}
1291
1292		/*
1293		 * If there is no 64-bit prefetchable window, compute the
1294		 * size required to put all prefetchable resources in the
1295		 * 32-bit prefetchable window (if there is one).
1296		 */
1297		if (!type2) {
1298			prefmask &= ~IORESOURCE_MEM_64;
1299			ret = pbus_size_mem(bus, prefmask, prefmask,
1300				prefmask, prefmask,
1301				realloc_head ? 0 : additional_mmio_pref_size,
1302				additional_mmio_pref_size, realloc_head);
1303
1304			/*
1305			 * If successful, only non-prefetchable resources
1306			 * will go in the non-prefetchable window.
1307			 */
1308			if (ret == 0)
1309				mask = prefmask;
1310			else
1311				additional_mmio_size += additional_mmio_pref_size;
1312
1313			type2 = type3 = IORESOURCE_MEM;
1314		}
1315
1316		/*
1317		 * Compute the size required to put everything else in the
1318		 * non-prefetchable window. This includes:
1319		 *
1320		 *   - all non-prefetchable resources
1321		 *   - 32-bit prefetchable resources if there's a 64-bit
1322		 *     prefetchable window or no prefetchable window at all
1323		 *   - 64-bit prefetchable resources if there's no prefetchable
1324		 *     window at all
1325		 *
1326		 * Note that the strategy in __pci_assign_resource() must match
1327		 * that used here. Specifically, we cannot put a 32-bit
1328		 * prefetchable resource in a 64-bit prefetchable window.
1329		 */
1330		pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3,
1331			      realloc_head ? 0 : additional_mmio_size,
1332			      additional_mmio_size, realloc_head);
1333		break;
1334	}
1335}
1336
1337void pci_bus_size_bridges(struct pci_bus *bus)
1338{
1339	__pci_bus_size_bridges(bus, NULL);
1340}
1341EXPORT_SYMBOL(pci_bus_size_bridges);
1342
1343static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r)
1344{
1345	struct resource *parent_r;
1346	unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM |
1347			     IORESOURCE_PREFETCH;
1348
1349	pci_bus_for_each_resource(b, parent_r) {
1350		if (!parent_r)
1351			continue;
1352
1353		if ((r->flags & mask) == (parent_r->flags & mask) &&
1354		    resource_contains(parent_r, r))
1355			request_resource(parent_r, r);
1356	}
1357}
1358
1359/*
1360 * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they are
1361 * skipped by pbus_assign_resources_sorted().
1362 */
1363static void pdev_assign_fixed_resources(struct pci_dev *dev)
1364{
1365	struct resource *r;
1366
1367	pci_dev_for_each_resource(dev, r) {
1368		struct pci_bus *b;
1369
1370		if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) ||
1371		    !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
1372			continue;
1373
1374		b = dev->bus;
1375		while (b && !r->parent) {
1376			assign_fixed_resource_on_bus(b, r);
1377			b = b->parent;
1378		}
1379	}
1380}
1381
1382void __pci_bus_assign_resources(const struct pci_bus *bus,
1383				struct list_head *realloc_head,
1384				struct list_head *fail_head)
1385{
1386	struct pci_bus *b;
1387	struct pci_dev *dev;
1388
1389	pbus_assign_resources_sorted(bus, realloc_head, fail_head);
1390
1391	list_for_each_entry(dev, &bus->devices, bus_list) {
1392		pdev_assign_fixed_resources(dev);
1393
1394		b = dev->subordinate;
1395		if (!b)
1396			continue;
1397
1398		__pci_bus_assign_resources(b, realloc_head, fail_head);
1399
1400		switch (dev->hdr_type) {
1401		case PCI_HEADER_TYPE_BRIDGE:
1402			if (!pci_is_enabled(dev))
1403				pci_setup_bridge(b);
1404			break;
1405
1406		case PCI_HEADER_TYPE_CARDBUS:
1407			pci_setup_cardbus(b);
1408			break;
1409
1410		default:
1411			pci_info(dev, "not setting up bridge for bus %04x:%02x\n",
1412				 pci_domain_nr(b), b->number);
1413			break;
1414		}
1415	}
1416}
1417
1418void pci_bus_assign_resources(const struct pci_bus *bus)
1419{
1420	__pci_bus_assign_resources(bus, NULL, NULL);
1421}
1422EXPORT_SYMBOL(pci_bus_assign_resources);
1423
1424static void pci_claim_device_resources(struct pci_dev *dev)
1425{
1426	int i;
1427
1428	for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
1429		struct resource *r = &dev->resource[i];
1430
1431		if (!r->flags || r->parent)
1432			continue;
1433
1434		pci_claim_resource(dev, i);
1435	}
1436}
1437
1438static void pci_claim_bridge_resources(struct pci_dev *dev)
1439{
1440	int i;
1441
1442	for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
1443		struct resource *r = &dev->resource[i];
1444
1445		if (!r->flags || r->parent)
1446			continue;
1447
1448		pci_claim_bridge_resource(dev, i);
1449	}
1450}
1451
1452static void pci_bus_allocate_dev_resources(struct pci_bus *b)
1453{
1454	struct pci_dev *dev;
1455	struct pci_bus *child;
1456
1457	list_for_each_entry(dev, &b->devices, bus_list) {
1458		pci_claim_device_resources(dev);
1459
1460		child = dev->subordinate;
1461		if (child)
1462			pci_bus_allocate_dev_resources(child);
1463	}
1464}
1465
1466static void pci_bus_allocate_resources(struct pci_bus *b)
1467{
1468	struct pci_bus *child;
1469
1470	/*
1471	 * Carry out a depth-first search on the PCI bus tree to allocate
1472	 * bridge apertures.  Read the programmed bridge bases and
1473	 * recursively claim the respective bridge resources.
1474	 */
1475	if (b->self) {
1476		pci_read_bridge_bases(b);
1477		pci_claim_bridge_resources(b->self);
1478	}
1479
1480	list_for_each_entry(child, &b->children, node)
1481		pci_bus_allocate_resources(child);
1482}
1483
1484void pci_bus_claim_resources(struct pci_bus *b)
1485{
1486	pci_bus_allocate_resources(b);
1487	pci_bus_allocate_dev_resources(b);
1488}
1489EXPORT_SYMBOL(pci_bus_claim_resources);
1490
1491static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
1492					  struct list_head *add_head,
1493					  struct list_head *fail_head)
1494{
1495	struct pci_bus *b;
1496
1497	pdev_assign_resources_sorted((struct pci_dev *)bridge,
1498					 add_head, fail_head);
1499
1500	b = bridge->subordinate;
1501	if (!b)
1502		return;
1503
1504	__pci_bus_assign_resources(b, add_head, fail_head);
1505
1506	switch (bridge->class >> 8) {
1507	case PCI_CLASS_BRIDGE_PCI:
1508		pci_setup_bridge(b);
1509		break;
1510
1511	case PCI_CLASS_BRIDGE_CARDBUS:
1512		pci_setup_cardbus(b);
1513		break;
1514
1515	default:
1516		pci_info(bridge, "not setting up bridge for bus %04x:%02x\n",
1517			 pci_domain_nr(b), b->number);
1518		break;
1519	}
1520}
1521
1522#define PCI_RES_TYPE_MASK \
1523	(IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\
1524	 IORESOURCE_MEM_64)
1525
1526static void pci_bridge_release_resources(struct pci_bus *bus,
1527					 unsigned long type)
1528{
1529	struct pci_dev *dev = bus->self;
1530	struct resource *r;
1531	unsigned int old_flags;
1532	struct resource *b_res;
1533	int idx = 1;
1534
1535	b_res = &dev->resource[PCI_BRIDGE_RESOURCES];
1536
1537	/*
1538	 * 1. If IO port assignment fails, release bridge IO port.
1539	 * 2. If non pref MMIO assignment fails, release bridge nonpref MMIO.
1540	 * 3. If 64bit pref MMIO assignment fails, and bridge pref is 64bit,
1541	 *    release bridge pref MMIO.
1542	 * 4. If pref MMIO assignment fails, and bridge pref is 32bit,
1543	 *    release bridge pref MMIO.
1544	 * 5. If pref MMIO assignment fails, and bridge pref is not
1545	 *    assigned, release bridge nonpref MMIO.
1546	 */
1547	if (type & IORESOURCE_IO)
1548		idx = 0;
1549	else if (!(type & IORESOURCE_PREFETCH))
1550		idx = 1;
1551	else if ((type & IORESOURCE_MEM_64) &&
1552		 (b_res[2].flags & IORESOURCE_MEM_64))
1553		idx = 2;
1554	else if (!(b_res[2].flags & IORESOURCE_MEM_64) &&
1555		 (b_res[2].flags & IORESOURCE_PREFETCH))
1556		idx = 2;
1557	else
1558		idx = 1;
1559
1560	r = &b_res[idx];
1561
1562	if (!r->parent)
1563		return;
1564
1565	/* If there are children, release them all */
1566	release_child_resources(r);
1567	if (!release_resource(r)) {
1568		type = old_flags = r->flags & PCI_RES_TYPE_MASK;
1569		pci_info(dev, "resource %d %pR released\n",
1570			 PCI_BRIDGE_RESOURCES + idx, r);
1571		/* Keep the old size */
1572		r->end = resource_size(r) - 1;
1573		r->start = 0;
1574		r->flags = 0;
1575
1576		/* Avoiding touch the one without PREF */
1577		if (type & IORESOURCE_PREFETCH)
1578			type = IORESOURCE_PREFETCH;
1579		__pci_setup_bridge(bus, type);
1580		/* For next child res under same bridge */
1581		r->flags = old_flags;
1582	}
1583}
1584
1585enum release_type {
1586	leaf_only,
1587	whole_subtree,
1588};
1589
1590/*
1591 * Try to release PCI bridge resources from leaf bridge, so we can allocate
1592 * a larger window later.
1593 */
1594static void pci_bus_release_bridge_resources(struct pci_bus *bus,
1595					     unsigned long type,
1596					     enum release_type rel_type)
1597{
1598	struct pci_dev *dev;
1599	bool is_leaf_bridge = true;
1600
1601	list_for_each_entry(dev, &bus->devices, bus_list) {
1602		struct pci_bus *b = dev->subordinate;
1603		if (!b)
1604			continue;
1605
1606		is_leaf_bridge = false;
1607
1608		if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1609			continue;
1610
1611		if (rel_type == whole_subtree)
1612			pci_bus_release_bridge_resources(b, type,
1613						 whole_subtree);
1614	}
1615
1616	if (pci_is_root_bus(bus))
1617		return;
1618
1619	if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1620		return;
1621
1622	if ((rel_type == whole_subtree) || is_leaf_bridge)
1623		pci_bridge_release_resources(bus, type);
1624}
1625
1626static void pci_bus_dump_res(struct pci_bus *bus)
1627{
1628	struct resource *res;
1629	int i;
1630
1631	pci_bus_for_each_resource(bus, res, i) {
1632		if (!res || !res->end || !res->flags)
1633			continue;
1634
1635		dev_info(&bus->dev, "resource %d %pR\n", i, res);
1636	}
1637}
1638
1639static void pci_bus_dump_resources(struct pci_bus *bus)
1640{
1641	struct pci_bus *b;
1642	struct pci_dev *dev;
1643
1644
1645	pci_bus_dump_res(bus);
1646
1647	list_for_each_entry(dev, &bus->devices, bus_list) {
1648		b = dev->subordinate;
1649		if (!b)
1650			continue;
1651
1652		pci_bus_dump_resources(b);
1653	}
1654}
1655
1656static int pci_bus_get_depth(struct pci_bus *bus)
1657{
1658	int depth = 0;
1659	struct pci_bus *child_bus;
1660
1661	list_for_each_entry(child_bus, &bus->children, node) {
1662		int ret;
1663
1664		ret = pci_bus_get_depth(child_bus);
1665		if (ret + 1 > depth)
1666			depth = ret + 1;
1667	}
1668
1669	return depth;
1670}
1671
1672/*
1673 * -1: undefined, will auto detect later
1674 *  0: disabled by user
1675 *  1: disabled by auto detect
1676 *  2: enabled by user
1677 *  3: enabled by auto detect
1678 */
1679enum enable_type {
1680	undefined = -1,
1681	user_disabled,
1682	auto_disabled,
1683	user_enabled,
1684	auto_enabled,
1685};
1686
1687static enum enable_type pci_realloc_enable = undefined;
1688void __init pci_realloc_get_opt(char *str)
1689{
1690	if (!strncmp(str, "off", 3))
1691		pci_realloc_enable = user_disabled;
1692	else if (!strncmp(str, "on", 2))
1693		pci_realloc_enable = user_enabled;
1694}
1695static bool pci_realloc_enabled(enum enable_type enable)
1696{
1697	return enable >= user_enabled;
1698}
1699
1700#if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1701static int iov_resources_unassigned(struct pci_dev *dev, void *data)
1702{
1703	int i;
1704	bool *unassigned = data;
1705
1706	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1707		struct resource *r = &dev->resource[i + PCI_IOV_RESOURCES];
1708		struct pci_bus_region region;
1709
1710		/* Not assigned or rejected by kernel? */
1711		if (!r->flags)
1712			continue;
1713
1714		pcibios_resource_to_bus(dev->bus, &region, r);
1715		if (!region.start) {
1716			*unassigned = true;
1717			return 1; /* Return early from pci_walk_bus() */
1718		}
1719	}
1720
1721	return 0;
1722}
1723
1724static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1725					   enum enable_type enable_local)
1726{
1727	bool unassigned = false;
1728	struct pci_host_bridge *host;
1729
1730	if (enable_local != undefined)
1731		return enable_local;
1732
1733	host = pci_find_host_bridge(bus);
1734	if (host->preserve_config)
1735		return auto_disabled;
1736
1737	pci_walk_bus(bus, iov_resources_unassigned, &unassigned);
1738	if (unassigned)
1739		return auto_enabled;
1740
1741	return enable_local;
1742}
1743#else
1744static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1745					   enum enable_type enable_local)
1746{
1747	return enable_local;
1748}
1749#endif
1750
1751static void adjust_bridge_window(struct pci_dev *bridge, struct resource *res,
1752				 struct list_head *add_list,
1753				 resource_size_t new_size)
1754{
1755	resource_size_t add_size, size = resource_size(res);
1756
1757	if (res->parent)
1758		return;
1759
1760	if (!new_size)
1761		return;
1762
1763	if (new_size > size) {
1764		add_size = new_size - size;
1765		pci_dbg(bridge, "bridge window %pR extended by %pa\n", res,
1766			&add_size);
1767	} else if (new_size < size) {
1768		add_size = size - new_size;
1769		pci_dbg(bridge, "bridge window %pR shrunken by %pa\n", res,
1770			&add_size);
1771	} else {
1772		return;
1773	}
1774
1775	res->end = res->start + new_size - 1;
1776
1777	/* If the resource is part of the add_list, remove it now */
1778	if (add_list)
1779		remove_from_list(add_list, res);
1780}
1781
1782static void remove_dev_resource(struct resource *avail, struct pci_dev *dev,
1783				struct resource *res)
1784{
1785	resource_size_t size, align, tmp;
1786
1787	size = resource_size(res);
1788	if (!size)
1789		return;
1790
1791	align = pci_resource_alignment(dev, res);
1792	align = align ? ALIGN(avail->start, align) - avail->start : 0;
1793	tmp = align + size;
1794	avail->start = min(avail->start + tmp, avail->end + 1);
1795}
1796
1797static void remove_dev_resources(struct pci_dev *dev, struct resource *io,
1798				 struct resource *mmio,
1799				 struct resource *mmio_pref)
1800{
1801	struct resource *res;
1802
1803	pci_dev_for_each_resource(dev, res) {
1804		if (resource_type(res) == IORESOURCE_IO) {
1805			remove_dev_resource(io, dev, res);
1806		} else if (resource_type(res) == IORESOURCE_MEM) {
1807
1808			/*
1809			 * Make sure prefetchable memory is reduced from
1810			 * the correct resource. Specifically we put 32-bit
1811			 * prefetchable memory in non-prefetchable window
1812			 * if there is an 64-bit prefetchable window.
1813			 *
1814			 * See comments in __pci_bus_size_bridges() for
1815			 * more information.
1816			 */
1817			if ((res->flags & IORESOURCE_PREFETCH) &&
1818			    ((res->flags & IORESOURCE_MEM_64) ==
1819			     (mmio_pref->flags & IORESOURCE_MEM_64)))
1820				remove_dev_resource(mmio_pref, dev, res);
1821			else
1822				remove_dev_resource(mmio, dev, res);
1823		}
1824	}
1825}
1826
 
 
 
1827/*
1828 * io, mmio and mmio_pref contain the total amount of bridge window space
1829 * available. This includes the minimal space needed to cover all the
1830 * existing devices on the bus and the possible extra space that can be
1831 * shared with the bridges.
1832 */
1833static void pci_bus_distribute_available_resources(struct pci_bus *bus,
1834					    struct list_head *add_list,
1835					    struct resource io,
1836					    struct resource mmio,
1837					    struct resource mmio_pref)
1838{
1839	unsigned int normal_bridges = 0, hotplug_bridges = 0;
1840	struct resource *io_res, *mmio_res, *mmio_pref_res;
1841	struct pci_dev *dev, *bridge = bus->self;
1842	resource_size_t io_per_b, mmio_per_b, mmio_pref_per_b, align;
1843
1844	io_res = &bridge->resource[PCI_BRIDGE_IO_WINDOW];
1845	mmio_res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW];
1846	mmio_pref_res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
1847
1848	/*
1849	 * The alignment of this bridge is yet to be considered, hence it must
1850	 * be done now before extending its bridge window.
1851	 */
1852	align = pci_resource_alignment(bridge, io_res);
1853	if (!io_res->parent && align)
1854		io.start = min(ALIGN(io.start, align), io.end + 1);
1855
1856	align = pci_resource_alignment(bridge, mmio_res);
1857	if (!mmio_res->parent && align)
1858		mmio.start = min(ALIGN(mmio.start, align), mmio.end + 1);
1859
1860	align = pci_resource_alignment(bridge, mmio_pref_res);
1861	if (!mmio_pref_res->parent && align)
1862		mmio_pref.start = min(ALIGN(mmio_pref.start, align),
1863			mmio_pref.end + 1);
1864
1865	/*
1866	 * Now that we have adjusted for alignment, update the bridge window
1867	 * resources to fill as much remaining resource space as possible.
1868	 */
1869	adjust_bridge_window(bridge, io_res, add_list, resource_size(&io));
1870	adjust_bridge_window(bridge, mmio_res, add_list, resource_size(&mmio));
1871	adjust_bridge_window(bridge, mmio_pref_res, add_list,
1872			     resource_size(&mmio_pref));
1873
1874	/*
1875	 * Calculate how many hotplug bridges and normal bridges there
1876	 * are on this bus.  We will distribute the additional available
1877	 * resources between hotplug bridges.
1878	 */
1879	for_each_pci_bridge(dev, bus) {
1880		if (dev->is_hotplug_bridge)
1881			hotplug_bridges++;
1882		else
1883			normal_bridges++;
1884	}
1885
1886	if (!(hotplug_bridges + normal_bridges))
1887		return;
1888
1889	/*
1890	 * Calculate the amount of space we can forward from "bus" to any
1891	 * downstream buses, i.e., the space left over after assigning the
1892	 * BARs and windows on "bus".
1893	 */
1894	list_for_each_entry(dev, &bus->devices, bus_list) {
1895		if (!dev->is_virtfn)
1896			remove_dev_resources(dev, &io, &mmio, &mmio_pref);
1897	}
1898
1899	/*
1900	 * If there is at least one hotplug bridge on this bus it gets all
1901	 * the extra resource space that was left after the reductions
1902	 * above.
1903	 *
1904	 * If there are no hotplug bridges the extra resource space is
1905	 * split between non-hotplug bridges. This is to allow possible
1906	 * hotplug bridges below them to get the extra space as well.
1907	 */
1908	if (hotplug_bridges) {
1909		io_per_b = div64_ul(resource_size(&io), hotplug_bridges);
1910		mmio_per_b = div64_ul(resource_size(&mmio), hotplug_bridges);
1911		mmio_pref_per_b = div64_ul(resource_size(&mmio_pref),
1912					   hotplug_bridges);
1913	} else {
1914		io_per_b = div64_ul(resource_size(&io), normal_bridges);
1915		mmio_per_b = div64_ul(resource_size(&mmio), normal_bridges);
1916		mmio_pref_per_b = div64_ul(resource_size(&mmio_pref),
1917					   normal_bridges);
1918	}
1919
1920	for_each_pci_bridge(dev, bus) {
1921		struct resource *res;
1922		struct pci_bus *b;
1923
1924		b = dev->subordinate;
1925		if (!b)
1926			continue;
1927		if (hotplug_bridges && !dev->is_hotplug_bridge)
1928			continue;
1929
1930		res = &dev->resource[PCI_BRIDGE_IO_WINDOW];
1931
1932		/*
1933		 * Make sure the split resource space is properly aligned
1934		 * for bridge windows (align it down to avoid going above
1935		 * what is available).
1936		 */
1937		align = pci_resource_alignment(dev, res);
1938		io.end = align ? io.start + ALIGN_DOWN(io_per_b, align) - 1
1939			       : io.start + io_per_b - 1;
1940
1941		/*
1942		 * The x_per_b holds the extra resource space that can be
1943		 * added for each bridge but there is the minimal already
1944		 * reserved as well so adjust x.start down accordingly to
1945		 * cover the whole space.
1946		 */
1947		io.start -= resource_size(res);
1948
1949		res = &dev->resource[PCI_BRIDGE_MEM_WINDOW];
1950		align = pci_resource_alignment(dev, res);
1951		mmio.end = align ? mmio.start + ALIGN_DOWN(mmio_per_b, align) - 1
1952				 : mmio.start + mmio_per_b - 1;
1953		mmio.start -= resource_size(res);
1954
1955		res = &dev->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
1956		align = pci_resource_alignment(dev, res);
1957		mmio_pref.end = align ? mmio_pref.start +
1958					ALIGN_DOWN(mmio_pref_per_b, align) - 1
1959				      : mmio_pref.start + mmio_pref_per_b - 1;
1960		mmio_pref.start -= resource_size(res);
1961
1962		pci_bus_distribute_available_resources(b, add_list, io, mmio,
1963						       mmio_pref);
1964
1965		io.start += io.end + 1;
1966		mmio.start += mmio.end + 1;
1967		mmio_pref.start += mmio_pref.end + 1;
1968	}
1969}
1970
1971static void pci_bridge_distribute_available_resources(struct pci_dev *bridge,
1972						      struct list_head *add_list)
1973{
1974	struct resource available_io, available_mmio, available_mmio_pref;
1975
1976	if (!bridge->is_hotplug_bridge)
1977		return;
1978
1979	pci_dbg(bridge, "distributing available resources\n");
1980
1981	/* Take the initial extra resources from the hotplug port */
1982	available_io = bridge->resource[PCI_BRIDGE_IO_WINDOW];
1983	available_mmio = bridge->resource[PCI_BRIDGE_MEM_WINDOW];
1984	available_mmio_pref = bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
1985
1986	pci_bus_distribute_available_resources(bridge->subordinate,
1987					       add_list, available_io,
1988					       available_mmio,
1989					       available_mmio_pref);
1990}
1991
1992static bool pci_bridge_resources_not_assigned(struct pci_dev *dev)
1993{
1994	const struct resource *r;
1995
1996	/*
1997	 * If the child device's resources are not yet assigned it means we
1998	 * are configuring them (not the boot firmware), so we should be
1999	 * able to extend the upstream bridge resources in the same way we
2000	 * do with the normal hotplug case.
2001	 */
2002	r = &dev->resource[PCI_BRIDGE_IO_WINDOW];
2003	if (r->flags && !(r->flags & IORESOURCE_STARTALIGN))
2004		return false;
2005	r = &dev->resource[PCI_BRIDGE_MEM_WINDOW];
2006	if (r->flags && !(r->flags & IORESOURCE_STARTALIGN))
2007		return false;
2008	r = &dev->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
2009	if (r->flags && !(r->flags & IORESOURCE_STARTALIGN))
2010		return false;
2011
2012	return true;
2013}
2014
2015static void
2016pci_root_bus_distribute_available_resources(struct pci_bus *bus,
2017					    struct list_head *add_list)
2018{
2019	struct pci_dev *dev, *bridge = bus->self;
2020
2021	for_each_pci_bridge(dev, bus) {
2022		struct pci_bus *b;
2023
2024		b = dev->subordinate;
2025		if (!b)
2026			continue;
2027
2028		/*
2029		 * Need to check "bridge" here too because it is NULL
2030		 * in case of root bus.
2031		 */
2032		if (bridge && pci_bridge_resources_not_assigned(dev))
2033			pci_bridge_distribute_available_resources(bridge,
2034								  add_list);
2035		else
2036			pci_root_bus_distribute_available_resources(b, add_list);
2037	}
2038}
2039
2040/*
2041 * First try will not touch PCI bridge res.
2042 * Second and later try will clear small leaf bridge res.
2043 * Will stop till to the max depth if can not find good one.
2044 */
2045void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
2046{
2047	LIST_HEAD(realloc_head);
2048	/* List of resources that want additional resources */
2049	struct list_head *add_list = NULL;
2050	int tried_times = 0;
2051	enum release_type rel_type = leaf_only;
2052	LIST_HEAD(fail_head);
2053	struct pci_dev_resource *fail_res;
2054	int pci_try_num = 1;
2055	enum enable_type enable_local;
2056
2057	/* Don't realloc if asked to do so */
2058	enable_local = pci_realloc_detect(bus, pci_realloc_enable);
2059	if (pci_realloc_enabled(enable_local)) {
2060		int max_depth = pci_bus_get_depth(bus);
2061
2062		pci_try_num = max_depth + 1;
2063		dev_info(&bus->dev, "max bus depth: %d pci_try_num: %d\n",
2064			 max_depth, pci_try_num);
2065	}
2066
2067again:
2068	/*
2069	 * Last try will use add_list, otherwise will try good to have as must
2070	 * have, so can realloc parent bridge resource
2071	 */
2072	if (tried_times + 1 == pci_try_num)
2073		add_list = &realloc_head;
2074	/*
2075	 * Depth first, calculate sizes and alignments of all subordinate buses.
2076	 */
2077	__pci_bus_size_bridges(bus, add_list);
2078
2079	pci_root_bus_distribute_available_resources(bus, add_list);
2080
2081	/* Depth last, allocate resources and update the hardware. */
2082	__pci_bus_assign_resources(bus, add_list, &fail_head);
2083	if (add_list)
2084		BUG_ON(!list_empty(add_list));
2085	tried_times++;
2086
2087	/* Any device complain? */
2088	if (list_empty(&fail_head))
2089		goto dump;
2090
2091	if (tried_times >= pci_try_num) {
2092		if (enable_local == undefined)
2093			dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n");
2094		else if (enable_local == auto_enabled)
2095			dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
2096
2097		free_list(&fail_head);
2098		goto dump;
2099	}
2100
2101	dev_info(&bus->dev, "No. %d try to assign unassigned res\n",
2102		 tried_times + 1);
2103
2104	/* Third times and later will not check if it is leaf */
2105	if ((tried_times + 1) > 2)
2106		rel_type = whole_subtree;
2107
2108	/*
2109	 * Try to release leaf bridge's resources that doesn't fit resource of
2110	 * child device under that bridge.
2111	 */
2112	list_for_each_entry(fail_res, &fail_head, list)
2113		pci_bus_release_bridge_resources(fail_res->dev->bus,
2114						 fail_res->flags & PCI_RES_TYPE_MASK,
2115						 rel_type);
2116
2117	/* Restore size and flags */
2118	list_for_each_entry(fail_res, &fail_head, list) {
2119		struct resource *res = fail_res->res;
2120		int idx;
2121
2122		res->start = fail_res->start;
2123		res->end = fail_res->end;
2124		res->flags = fail_res->flags;
2125
2126		if (pci_is_bridge(fail_res->dev)) {
2127			idx = res - &fail_res->dev->resource[0];
2128			if (idx >= PCI_BRIDGE_RESOURCES &&
2129			    idx <= PCI_BRIDGE_RESOURCE_END)
2130				res->flags = 0;
2131		}
2132	}
2133	free_list(&fail_head);
2134
2135	goto again;
2136
2137dump:
2138	/* Dump the resource on buses */
2139	pci_bus_dump_resources(bus);
2140}
2141
2142void pci_assign_unassigned_resources(void)
2143{
2144	struct pci_bus *root_bus;
2145
2146	list_for_each_entry(root_bus, &pci_root_buses, node) {
2147		pci_assign_unassigned_root_bus_resources(root_bus);
2148
2149		/* Make sure the root bridge has a companion ACPI device */
2150		if (ACPI_HANDLE(root_bus->bridge))
2151			acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge));
2152	}
2153}
2154
2155void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
2156{
2157	struct pci_bus *parent = bridge->subordinate;
2158	/* List of resources that want additional resources */
2159	LIST_HEAD(add_list);
2160
2161	int tried_times = 0;
2162	LIST_HEAD(fail_head);
2163	struct pci_dev_resource *fail_res;
2164	int retval;
2165
2166again:
2167	__pci_bus_size_bridges(parent, &add_list);
2168
2169	/*
2170	 * Distribute remaining resources (if any) equally between hotplug
2171	 * bridges below.  This makes it possible to extend the hierarchy
2172	 * later without running out of resources.
2173	 */
2174	pci_bridge_distribute_available_resources(bridge, &add_list);
2175
2176	__pci_bridge_assign_resources(bridge, &add_list, &fail_head);
2177	BUG_ON(!list_empty(&add_list));
2178	tried_times++;
2179
2180	if (list_empty(&fail_head))
2181		goto enable_all;
2182
2183	if (tried_times >= 2) {
2184		/* Still fail, don't need to try more */
2185		free_list(&fail_head);
2186		goto enable_all;
2187	}
2188
2189	printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
2190			 tried_times + 1);
2191
2192	/*
2193	 * Try to release leaf bridge's resources that aren't big enough
2194	 * to contain child device resources.
2195	 */
2196	list_for_each_entry(fail_res, &fail_head, list)
2197		pci_bus_release_bridge_resources(fail_res->dev->bus,
2198						 fail_res->flags & PCI_RES_TYPE_MASK,
2199						 whole_subtree);
2200
2201	/* Restore size and flags */
2202	list_for_each_entry(fail_res, &fail_head, list) {
2203		struct resource *res = fail_res->res;
2204		int idx;
2205
2206		res->start = fail_res->start;
2207		res->end = fail_res->end;
2208		res->flags = fail_res->flags;
2209
2210		if (pci_is_bridge(fail_res->dev)) {
2211			idx = res - &fail_res->dev->resource[0];
2212			if (idx >= PCI_BRIDGE_RESOURCES &&
2213			    idx <= PCI_BRIDGE_RESOURCE_END)
2214				res->flags = 0;
2215		}
2216	}
2217	free_list(&fail_head);
2218
2219	goto again;
2220
2221enable_all:
2222	retval = pci_reenable_device(bridge);
2223	if (retval)
2224		pci_err(bridge, "Error reenabling bridge (%d)\n", retval);
2225	pci_set_master(bridge);
2226}
2227EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
2228
2229int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type)
2230{
2231	struct pci_dev_resource *dev_res;
2232	struct pci_dev *next;
2233	LIST_HEAD(saved);
2234	LIST_HEAD(added);
2235	LIST_HEAD(failed);
2236	unsigned int i;
2237	int ret;
2238
2239	down_read(&pci_bus_sem);
2240
2241	/* Walk to the root hub, releasing bridge BARs when possible */
2242	next = bridge;
2243	do {
2244		bridge = next;
2245		for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END;
2246		     i++) {
2247			struct resource *res = &bridge->resource[i];
2248			const char *res_name = pci_resource_name(bridge, i);
2249
2250			if ((res->flags ^ type) & PCI_RES_TYPE_MASK)
2251				continue;
2252
2253			/* Ignore BARs which are still in use */
2254			if (res->child)
2255				continue;
2256
2257			ret = add_to_list(&saved, bridge, res, 0, 0);
2258			if (ret)
2259				goto cleanup;
2260
2261			pci_info(bridge, "%s %pR: releasing\n", res_name, res);
2262
2263			if (res->parent)
2264				release_resource(res);
2265			res->start = 0;
2266			res->end = 0;
2267			break;
2268		}
2269		if (i == PCI_BRIDGE_RESOURCE_END)
2270			break;
2271
2272		next = bridge->bus ? bridge->bus->self : NULL;
2273	} while (next);
2274
2275	if (list_empty(&saved)) {
2276		up_read(&pci_bus_sem);
2277		return -ENOENT;
2278	}
2279
2280	__pci_bus_size_bridges(bridge->subordinate, &added);
2281	__pci_bridge_assign_resources(bridge, &added, &failed);
2282	BUG_ON(!list_empty(&added));
2283
2284	if (!list_empty(&failed)) {
2285		ret = -ENOSPC;
2286		goto cleanup;
2287	}
2288
2289	list_for_each_entry(dev_res, &saved, list) {
2290		/* Skip the bridge we just assigned resources for */
2291		if (bridge == dev_res->dev)
2292			continue;
2293
2294		bridge = dev_res->dev;
2295		pci_setup_bridge(bridge->subordinate);
2296	}
2297
2298	free_list(&saved);
2299	up_read(&pci_bus_sem);
2300	return 0;
2301
2302cleanup:
2303	/* Restore size and flags */
2304	list_for_each_entry(dev_res, &failed, list) {
2305		struct resource *res = dev_res->res;
2306
2307		res->start = dev_res->start;
2308		res->end = dev_res->end;
2309		res->flags = dev_res->flags;
2310	}
2311	free_list(&failed);
2312
2313	/* Revert to the old configuration */
2314	list_for_each_entry(dev_res, &saved, list) {
2315		struct resource *res = dev_res->res;
2316
2317		bridge = dev_res->dev;
2318		i = res - bridge->resource;
2319
2320		res->start = dev_res->start;
2321		res->end = dev_res->end;
2322		res->flags = dev_res->flags;
2323
2324		pci_claim_resource(bridge, i);
2325		pci_setup_bridge(bridge->subordinate);
2326	}
2327	free_list(&saved);
2328	up_read(&pci_bus_sem);
2329
2330	return ret;
2331}
2332
2333void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
2334{
2335	struct pci_dev *dev;
2336	/* List of resources that want additional resources */
2337	LIST_HEAD(add_list);
2338
2339	down_read(&pci_bus_sem);
2340	for_each_pci_bridge(dev, bus)
2341		if (pci_has_subordinate(dev))
2342			__pci_bus_size_bridges(dev->subordinate, &add_list);
2343	up_read(&pci_bus_sem);
2344	__pci_bus_assign_resources(bus, &add_list, NULL);
2345	BUG_ON(!list_empty(&add_list));
2346}
2347EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);