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1// SPDX-License-Identifier: ISC
2/* Copyright (C) 2023 MediaTek Inc. */
3
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/pci.h>
7
8#include "mt7925.h"
9#include "mac.h"
10#include "mcu.h"
11#include "../dma.h"
12
13static const struct pci_device_id mt7925_pci_device_table[] = {
14 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7925),
15 .driver_data = (kernel_ulong_t)MT7925_FIRMWARE_WM },
16 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0717),
17 .driver_data = (kernel_ulong_t)MT7925_FIRMWARE_WM },
18 { },
19};
20
21static bool mt7925_disable_aspm;
22module_param_named(disable_aspm, mt7925_disable_aspm, bool, 0644);
23MODULE_PARM_DESC(disable_aspm, "disable PCI ASPM support");
24
25static int mt7925e_init_reset(struct mt792x_dev *dev)
26{
27 return mt792x_wpdma_reset(dev, true);
28}
29
30static void mt7925e_unregister_device(struct mt792x_dev *dev)
31{
32 int i;
33 struct mt76_connac_pm *pm = &dev->pm;
34
35 cancel_work_sync(&dev->init_work);
36 mt76_unregister_device(&dev->mt76);
37 mt76_for_each_q_rx(&dev->mt76, i)
38 napi_disable(&dev->mt76.napi[i]);
39 cancel_delayed_work_sync(&pm->ps_work);
40 cancel_work_sync(&pm->wake_work);
41 cancel_work_sync(&dev->reset_work);
42
43 mt7925_tx_token_put(dev);
44 __mt792x_mcu_drv_pmctrl(dev);
45 mt792x_dma_cleanup(dev);
46 mt792x_wfsys_reset(dev);
47 skb_queue_purge(&dev->mt76.mcu.res_q);
48
49 tasklet_disable(&dev->mt76.irq_tasklet);
50}
51
52static void mt7925_reg_remap_restore(struct mt792x_dev *dev)
53{
54 /* remap to ori status */
55 if (unlikely(dev->backup_l1)) {
56 dev->bus_ops->wr(&dev->mt76, MT_HIF_REMAP_L1, dev->backup_l1);
57 dev->backup_l1 = 0;
58 }
59
60 if (dev->backup_l2) {
61 dev->bus_ops->wr(&dev->mt76, MT_HIF_REMAP_L2, dev->backup_l2);
62 dev->backup_l2 = 0;
63 }
64}
65
66static u32 mt7925_reg_map_l1(struct mt792x_dev *dev, u32 addr)
67{
68 u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr);
69 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr);
70
71 dev->backup_l1 = dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1);
72
73 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1,
74 MT_HIF_REMAP_L1_MASK,
75 FIELD_PREP(MT_HIF_REMAP_L1_MASK, base));
76
77 /* use read to push write */
78 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1);
79
80 return MT_HIF_REMAP_BASE_L1 + offset;
81}
82
83static u32 mt7925_reg_map_l2(struct mt792x_dev *dev, u32 addr)
84{
85 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, MT_HIF_REMAP_BASE_L2);
86
87 dev->backup_l2 = dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1);
88
89 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1,
90 MT_HIF_REMAP_L1_MASK,
91 FIELD_PREP(MT_HIF_REMAP_L1_MASK, base));
92
93 dev->bus_ops->wr(&dev->mt76, MT_HIF_REMAP_L2, addr);
94 /* use read to push write */
95 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1);
96
97 return MT_HIF_REMAP_BASE_L1;
98}
99
100static u32 __mt7925_reg_addr(struct mt792x_dev *dev, u32 addr)
101{
102 static const struct mt76_connac_reg_map fixed_map[] = {
103 { 0x830c0000, 0x000000, 0x0001000 }, /* WF_MCU_BUS_CR_REMAP */
104 { 0x54000000, 0x002000, 0x0001000 }, /* WFDMA PCIE0 MCU DMA0 */
105 { 0x55000000, 0x003000, 0x0001000 }, /* WFDMA PCIE0 MCU DMA1 */
106 { 0x56000000, 0x004000, 0x0001000 }, /* WFDMA reserved */
107 { 0x57000000, 0x005000, 0x0001000 }, /* WFDMA MCU wrap CR */
108 { 0x58000000, 0x006000, 0x0001000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
109 { 0x59000000, 0x007000, 0x0001000 }, /* WFDMA PCIE1 MCU DMA1 */
110 { 0x820c0000, 0x008000, 0x0004000 }, /* WF_UMAC_TOP (PLE) */
111 { 0x820c8000, 0x00c000, 0x0002000 }, /* WF_UMAC_TOP (PSE) */
112 { 0x820cc000, 0x00e000, 0x0002000 }, /* WF_UMAC_TOP (PP) */
113 { 0x74030000, 0x010000, 0x0001000 }, /* PCIe MAC */
114 { 0x820e0000, 0x020000, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
115 { 0x820e1000, 0x020400, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
116 { 0x820e2000, 0x020800, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
117 { 0x820e3000, 0x020c00, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
118 { 0x820e4000, 0x021000, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
119 { 0x820e5000, 0x021400, 0x0000800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
120 { 0x820ce000, 0x021c00, 0x0000200 }, /* WF_LMAC_TOP (WF_SEC) */
121 { 0x820e7000, 0x021e00, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
122 { 0x820cf000, 0x022000, 0x0001000 }, /* WF_LMAC_TOP (WF_PF) */
123 { 0x820e9000, 0x023400, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
124 { 0x820ea000, 0x024000, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
125 { 0x820eb000, 0x024200, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
126 { 0x820ec000, 0x024600, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
127 { 0x820ed000, 0x024800, 0x0000800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
128 { 0x820ca000, 0x026000, 0x0002000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
129 { 0x820d0000, 0x030000, 0x0010000 }, /* WF_LMAC_TOP (WF_WTBLON) */
130 { 0x40000000, 0x070000, 0x0010000 }, /* WF_UMAC_SYSRAM */
131 { 0x00400000, 0x080000, 0x0010000 }, /* WF_MCU_SYSRAM */
132 { 0x00410000, 0x090000, 0x0010000 }, /* WF_MCU_SYSRAM (configure register) */
133 { 0x820f0000, 0x0a0000, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
134 { 0x820f1000, 0x0a0600, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
135 { 0x820f2000, 0x0a0800, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
136 { 0x820f3000, 0x0a0c00, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
137 { 0x820f4000, 0x0a1000, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
138 { 0x820f5000, 0x0a1400, 0x0000800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
139 { 0x820f7000, 0x0a1e00, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
140 { 0x820f9000, 0x0a3400, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
141 { 0x820fa000, 0x0a4000, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
142 { 0x820fb000, 0x0a4200, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
143 { 0x820fc000, 0x0a4600, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
144 { 0x820fd000, 0x0a4800, 0x0000800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
145 { 0x820c4000, 0x0a8000, 0x0004000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
146 { 0x820b0000, 0x0ae000, 0x0001000 }, /* [APB2] WFSYS_ON */
147 { 0x80020000, 0x0b0000, 0x0010000 }, /* WF_TOP_MISC_OFF */
148 { 0x81020000, 0x0c0000, 0x0010000 }, /* WF_TOP_MISC_ON */
149 { 0x7c020000, 0x0d0000, 0x0010000 }, /* CONN_INFRA, wfdma */
150 { 0x7c060000, 0x0e0000, 0x0010000 }, /* CONN_INFRA, conn_host_csr_top */
151 { 0x7c000000, 0x0f0000, 0x0010000 }, /* CONN_INFRA */
152 { 0x70020000, 0x1f0000, 0x0010000 }, /* Reserved for CBTOP, can't switch */
153 { 0x7c500000, 0x060000, 0x2000000 }, /* remap */
154 { 0x0, 0x0, 0x0 } /* End */
155 };
156 int i;
157
158 if (addr < 0x200000)
159 return addr;
160
161 mt7925_reg_remap_restore(dev);
162
163 for (i = 0; i < ARRAY_SIZE(fixed_map); i++) {
164 u32 ofs;
165
166 if (addr < fixed_map[i].phys)
167 continue;
168
169 ofs = addr - fixed_map[i].phys;
170 if (ofs > fixed_map[i].size)
171 continue;
172
173 return fixed_map[i].maps + ofs;
174 }
175
176 if ((addr >= 0x18000000 && addr < 0x18c00000) ||
177 (addr >= 0x70000000 && addr < 0x78000000) ||
178 (addr >= 0x7c000000 && addr < 0x7c400000))
179 return mt7925_reg_map_l1(dev, addr);
180
181 return mt7925_reg_map_l2(dev, addr);
182}
183
184static u32 mt7925_rr(struct mt76_dev *mdev, u32 offset)
185{
186 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
187 u32 addr = __mt7925_reg_addr(dev, offset);
188
189 return dev->bus_ops->rr(mdev, addr);
190}
191
192static void mt7925_wr(struct mt76_dev *mdev, u32 offset, u32 val)
193{
194 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
195 u32 addr = __mt7925_reg_addr(dev, offset);
196
197 dev->bus_ops->wr(mdev, addr, val);
198}
199
200static u32 mt7925_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
201{
202 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
203 u32 addr = __mt7925_reg_addr(dev, offset);
204
205 return dev->bus_ops->rmw(mdev, addr, mask, val);
206}
207
208static int mt7925_dma_init(struct mt792x_dev *dev)
209{
210 int ret;
211
212 mt76_dma_attach(&dev->mt76);
213
214 ret = mt792x_dma_disable(dev, true);
215 if (ret)
216 return ret;
217
218 /* init tx queue */
219 ret = mt76_connac_init_tx_queues(dev->phy.mt76, MT7925_TXQ_BAND0,
220 MT7925_TX_RING_SIZE,
221 MT_TX_RING_BASE, NULL, 0);
222 if (ret)
223 return ret;
224
225 mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, 0x4);
226
227 /* command to WM */
228 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7925_TXQ_MCU_WM,
229 MT7925_TX_MCU_RING_SIZE, MT_TX_RING_BASE);
230 if (ret)
231 return ret;
232
233 /* firmware download */
234 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7925_TXQ_FWDL,
235 MT7925_TX_FWDL_RING_SIZE, MT_TX_RING_BASE);
236 if (ret)
237 return ret;
238
239 /* rx event */
240 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU],
241 MT7925_RXQ_MCU_WM, MT7925_RX_MCU_RING_SIZE,
242 MT_RX_BUF_SIZE, MT_RX_EVENT_RING_BASE);
243 if (ret)
244 return ret;
245
246 /* rx data */
247 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
248 MT7925_RXQ_BAND0, MT7925_RX_RING_SIZE,
249 MT_RX_BUF_SIZE, MT_RX_DATA_RING_BASE);
250 if (ret)
251 return ret;
252
253 ret = mt76_init_queues(dev, mt792x_poll_rx);
254 if (ret < 0)
255 return ret;
256
257 netif_napi_add_tx(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
258 mt792x_poll_tx);
259 napi_enable(&dev->mt76.tx_napi);
260
261 return mt792x_dma_enable(dev);
262}
263
264static int mt7925_pci_probe(struct pci_dev *pdev,
265 const struct pci_device_id *id)
266{
267 static const struct mt76_driver_ops drv_ops = {
268 /* txwi_size = txd size + txp size */
269 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_hw_txp),
270 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ |
271 MT_DRV_AMSDU_OFFLOAD,
272 .survey_flags = SURVEY_INFO_TIME_TX |
273 SURVEY_INFO_TIME_RX |
274 SURVEY_INFO_TIME_BSS_RX,
275 .token_size = MT7925_TOKEN_SIZE,
276 .tx_prepare_skb = mt7925e_tx_prepare_skb,
277 .tx_complete_skb = mt76_connac_tx_complete_skb,
278 .rx_check = mt7925_rx_check,
279 .rx_skb = mt7925_queue_rx_skb,
280 .rx_poll_complete = mt792x_rx_poll_complete,
281 .sta_add = mt7925_mac_sta_add,
282 .sta_assoc = mt7925_mac_sta_assoc,
283 .sta_remove = mt7925_mac_sta_remove,
284 .update_survey = mt792x_update_channel,
285 };
286 static const struct mt792x_hif_ops mt7925_pcie_ops = {
287 .init_reset = mt7925e_init_reset,
288 .reset = mt7925e_mac_reset,
289 .mcu_init = mt7925e_mcu_init,
290 .drv_own = mt792xe_mcu_drv_pmctrl,
291 .fw_own = mt792xe_mcu_fw_pmctrl,
292 };
293 static const struct mt792x_irq_map irq_map = {
294 .host_irq_enable = MT_WFDMA0_HOST_INT_ENA,
295 .tx = {
296 .all_complete_mask = MT_INT_TX_DONE_ALL,
297 .mcu_complete_mask = MT_INT_TX_DONE_MCU,
298 },
299 .rx = {
300 .data_complete_mask = HOST_RX_DONE_INT_ENA2,
301 .wm_complete_mask = HOST_RX_DONE_INT_ENA0,
302 },
303 };
304 struct ieee80211_ops *ops;
305 struct mt76_bus_ops *bus_ops;
306 struct mt792x_dev *dev;
307 struct mt76_dev *mdev;
308 u8 features;
309 int ret;
310 u16 cmd;
311
312 ret = pcim_enable_device(pdev);
313 if (ret)
314 return ret;
315
316 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
317 if (ret)
318 return ret;
319
320 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
321 if (!(cmd & PCI_COMMAND_MEMORY)) {
322 cmd |= PCI_COMMAND_MEMORY;
323 pci_write_config_word(pdev, PCI_COMMAND, cmd);
324 }
325 pci_set_master(pdev);
326
327 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
328 if (ret < 0)
329 return ret;
330
331 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
332 if (ret)
333 goto err_free_pci_vec;
334
335 if (mt7925_disable_aspm)
336 mt76_pci_disable_aspm(pdev);
337
338 ops = mt792x_get_mac80211_ops(&pdev->dev, &mt7925_ops,
339 (void *)id->driver_data, &features);
340 if (!ops) {
341 ret = -ENOMEM;
342 goto err_free_pci_vec;
343 }
344
345 mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), ops, &drv_ops);
346 if (!mdev) {
347 ret = -ENOMEM;
348 goto err_free_pci_vec;
349 }
350
351 pci_set_drvdata(pdev, mdev);
352
353 dev = container_of(mdev, struct mt792x_dev, mt76);
354 dev->fw_features = features;
355 dev->hif_ops = &mt7925_pcie_ops;
356 dev->irq_map = &irq_map;
357 mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]);
358 tasklet_init(&mdev->irq_tasklet, mt792x_irq_tasklet, (unsigned long)dev);
359
360 dev->phy.dev = dev;
361 dev->phy.mt76 = &dev->mt76.phy;
362 dev->mt76.phy.priv = &dev->phy;
363 dev->bus_ops = dev->mt76.bus;
364 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
365 GFP_KERNEL);
366 if (!bus_ops) {
367 ret = -ENOMEM;
368 goto err_free_dev;
369 }
370
371 bus_ops->rr = mt7925_rr;
372 bus_ops->wr = mt7925_wr;
373 bus_ops->rmw = mt7925_rmw;
374 dev->mt76.bus = bus_ops;
375
376 ret = __mt792x_mcu_fw_pmctrl(dev);
377 if (ret)
378 goto err_free_dev;
379
380 ret = __mt792xe_mcu_drv_pmctrl(dev);
381 if (ret)
382 goto err_free_dev;
383
384 mdev->rev = (mt76_rr(dev, MT_HW_CHIPID) << 16) |
385 (mt76_rr(dev, MT_HW_REV) & 0xff);
386
387 dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
388
389 ret = mt792x_wfsys_reset(dev);
390 if (ret)
391 goto err_free_dev;
392
393 mt76_wr(dev, irq_map.host_irq_enable, 0);
394
395 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
396
397 ret = devm_request_irq(mdev->dev, pdev->irq, mt792x_irq_handler,
398 IRQF_SHARED, KBUILD_MODNAME, dev);
399 if (ret)
400 goto err_free_dev;
401
402 ret = mt7925_dma_init(dev);
403 if (ret)
404 goto err_free_irq;
405
406 ret = mt7925_register_device(dev);
407 if (ret)
408 goto err_free_irq;
409
410 return 0;
411
412err_free_irq:
413 devm_free_irq(&pdev->dev, pdev->irq, dev);
414err_free_dev:
415 mt76_free_device(&dev->mt76);
416err_free_pci_vec:
417 pci_free_irq_vectors(pdev);
418
419 return ret;
420}
421
422static void mt7925_pci_remove(struct pci_dev *pdev)
423{
424 struct mt76_dev *mdev = pci_get_drvdata(pdev);
425 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
426
427 mt7925e_unregister_device(dev);
428 devm_free_irq(&pdev->dev, pdev->irq, dev);
429 mt76_free_device(&dev->mt76);
430 pci_free_irq_vectors(pdev);
431}
432
433static int mt7925_pci_suspend(struct device *device)
434{
435 struct pci_dev *pdev = to_pci_dev(device);
436 struct mt76_dev *mdev = pci_get_drvdata(pdev);
437 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
438 struct mt76_connac_pm *pm = &dev->pm;
439 int i, err;
440
441 pm->suspended = true;
442 flush_work(&dev->reset_work);
443 cancel_delayed_work_sync(&pm->ps_work);
444 cancel_work_sync(&pm->wake_work);
445
446 err = mt792x_mcu_drv_pmctrl(dev);
447 if (err < 0)
448 goto restore_suspend;
449
450 /* always enable deep sleep during suspend to reduce
451 * power consumption
452 */
453 mt7925_mcu_set_deep_sleep(dev, true);
454
455 err = mt76_connac_mcu_set_hif_suspend(mdev, true);
456 if (err)
457 goto restore_suspend;
458
459 napi_disable(&mdev->tx_napi);
460 mt76_worker_disable(&mdev->tx_worker);
461
462 mt76_for_each_q_rx(mdev, i) {
463 napi_disable(&mdev->napi[i]);
464 }
465
466 /* wait until dma is idle */
467 mt76_poll(dev, MT_WFDMA0_GLO_CFG,
468 MT_WFDMA0_GLO_CFG_TX_DMA_BUSY |
469 MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000);
470
471 /* put dma disabled */
472 mt76_clear(dev, MT_WFDMA0_GLO_CFG,
473 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
474
475 /* disable interrupt */
476 mt76_wr(dev, dev->irq_map->host_irq_enable, 0);
477 mt76_wr(dev, MT_WFDMA0_HOST_INT_DIS,
478 dev->irq_map->tx.all_complete_mask |
479 MT_INT_RX_DONE_ALL | MT_INT_MCU_CMD);
480
481 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0);
482
483 synchronize_irq(pdev->irq);
484 tasklet_kill(&mdev->irq_tasklet);
485
486 err = mt792x_mcu_fw_pmctrl(dev);
487 if (err)
488 goto restore_napi;
489
490 return 0;
491
492restore_napi:
493 mt76_for_each_q_rx(mdev, i) {
494 napi_enable(&mdev->napi[i]);
495 }
496 napi_enable(&mdev->tx_napi);
497
498 if (!pm->ds_enable)
499 mt7925_mcu_set_deep_sleep(dev, false);
500
501 mt76_connac_mcu_set_hif_suspend(mdev, false);
502
503restore_suspend:
504 pm->suspended = false;
505
506 if (err < 0)
507 mt792x_reset(&dev->mt76);
508
509 return err;
510}
511
512static int mt7925_pci_resume(struct device *device)
513{
514 struct pci_dev *pdev = to_pci_dev(device);
515 struct mt76_dev *mdev = pci_get_drvdata(pdev);
516 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
517 struct mt76_connac_pm *pm = &dev->pm;
518 int i, err;
519
520 err = mt792x_mcu_drv_pmctrl(dev);
521 if (err < 0)
522 goto failed;
523
524 mt792x_wpdma_reinit_cond(dev);
525
526 /* enable interrupt */
527 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
528 mt76_connac_irq_enable(&dev->mt76,
529 dev->irq_map->tx.all_complete_mask |
530 MT_INT_RX_DONE_ALL | MT_INT_MCU_CMD);
531 mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE);
532
533 /* put dma enabled */
534 mt76_set(dev, MT_WFDMA0_GLO_CFG,
535 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
536
537 mt76_worker_enable(&mdev->tx_worker);
538
539 local_bh_disable();
540 mt76_for_each_q_rx(mdev, i) {
541 napi_enable(&mdev->napi[i]);
542 napi_schedule(&mdev->napi[i]);
543 }
544 napi_enable(&mdev->tx_napi);
545 napi_schedule(&mdev->tx_napi);
546 local_bh_enable();
547
548 err = mt76_connac_mcu_set_hif_suspend(mdev, false);
549
550 /* restore previous ds setting */
551 if (!pm->ds_enable)
552 mt7925_mcu_set_deep_sleep(dev, false);
553
554failed:
555 pm->suspended = false;
556
557 if (err < 0)
558 mt792x_reset(&dev->mt76);
559
560 return err;
561}
562
563static void mt7925_pci_shutdown(struct pci_dev *pdev)
564{
565 mt7925_pci_remove(pdev);
566}
567
568static DEFINE_SIMPLE_DEV_PM_OPS(mt7925_pm_ops, mt7925_pci_suspend, mt7925_pci_resume);
569
570static struct pci_driver mt7925_pci_driver = {
571 .name = KBUILD_MODNAME,
572 .id_table = mt7925_pci_device_table,
573 .probe = mt7925_pci_probe,
574 .remove = mt7925_pci_remove,
575 .shutdown = mt7925_pci_shutdown,
576 .driver.pm = pm_sleep_ptr(&mt7925_pm_ops),
577};
578
579module_pci_driver(mt7925_pci_driver);
580
581MODULE_DEVICE_TABLE(pci, mt7925_pci_device_table);
582MODULE_FIRMWARE(MT7925_FIRMWARE_WM);
583MODULE_FIRMWARE(MT7925_ROM_PATCH);
584MODULE_AUTHOR("Deren Wu <deren.wu@mediatek.com>");
585MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
586MODULE_DESCRIPTION("MediaTek MT7925E (PCIe) wireless driver");
587MODULE_LICENSE("Dual BSD/GPL");
1// SPDX-License-Identifier: ISC
2/* Copyright (C) 2023 MediaTek Inc. */
3
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/pci.h>
7
8#include "mt7925.h"
9#include "mac.h"
10#include "mcu.h"
11#include "../dma.h"
12
13static const struct pci_device_id mt7925_pci_device_table[] = {
14 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7925),
15 .driver_data = (kernel_ulong_t)MT7925_FIRMWARE_WM },
16 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0717),
17 .driver_data = (kernel_ulong_t)MT7925_FIRMWARE_WM },
18 { },
19};
20
21static bool mt7925_disable_aspm;
22module_param_named(disable_aspm, mt7925_disable_aspm, bool, 0644);
23MODULE_PARM_DESC(disable_aspm, "disable PCI ASPM support");
24
25static int mt7925e_init_reset(struct mt792x_dev *dev)
26{
27 return mt792x_wpdma_reset(dev, true);
28}
29
30static void mt7925e_unregister_device(struct mt792x_dev *dev)
31{
32 int i;
33 struct mt76_connac_pm *pm = &dev->pm;
34
35 cancel_work_sync(&dev->init_work);
36 mt76_unregister_device(&dev->mt76);
37 mt76_for_each_q_rx(&dev->mt76, i)
38 napi_disable(&dev->mt76.napi[i]);
39 cancel_delayed_work_sync(&pm->ps_work);
40 cancel_work_sync(&pm->wake_work);
41 cancel_work_sync(&dev->reset_work);
42
43 mt7925_tx_token_put(dev);
44 __mt792x_mcu_drv_pmctrl(dev);
45 mt792x_dma_cleanup(dev);
46 mt792x_wfsys_reset(dev);
47 skb_queue_purge(&dev->mt76.mcu.res_q);
48
49 tasklet_disable(&dev->mt76.irq_tasklet);
50}
51
52static void mt7925_reg_remap_restore(struct mt792x_dev *dev)
53{
54 /* remap to ori status */
55 if (unlikely(dev->backup_l1)) {
56 dev->bus_ops->wr(&dev->mt76, MT_HIF_REMAP_L1, dev->backup_l1);
57 dev->backup_l1 = 0;
58 }
59
60 if (dev->backup_l2) {
61 dev->bus_ops->wr(&dev->mt76, MT_HIF_REMAP_L2, dev->backup_l2);
62 dev->backup_l2 = 0;
63 }
64}
65
66static u32 mt7925_reg_map_l1(struct mt792x_dev *dev, u32 addr)
67{
68 u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr);
69 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr);
70
71 dev->backup_l1 = dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1);
72
73 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1,
74 MT_HIF_REMAP_L1_MASK,
75 FIELD_PREP(MT_HIF_REMAP_L1_MASK, base));
76
77 /* use read to push write */
78 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1);
79
80 return MT_HIF_REMAP_BASE_L1 + offset;
81}
82
83static u32 mt7925_reg_map_l2(struct mt792x_dev *dev, u32 addr)
84{
85 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, MT_HIF_REMAP_BASE_L2);
86
87 dev->backup_l2 = dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1);
88
89 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1,
90 MT_HIF_REMAP_L1_MASK,
91 FIELD_PREP(MT_HIF_REMAP_L1_MASK, base));
92
93 dev->bus_ops->wr(&dev->mt76, MT_HIF_REMAP_L2, addr);
94 /* use read to push write */
95 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1);
96
97 return MT_HIF_REMAP_BASE_L1;
98}
99
100static u32 __mt7925_reg_addr(struct mt792x_dev *dev, u32 addr)
101{
102 static const struct mt76_connac_reg_map fixed_map[] = {
103 { 0x830c0000, 0x000000, 0x0001000 }, /* WF_MCU_BUS_CR_REMAP */
104 { 0x54000000, 0x002000, 0x0001000 }, /* WFDMA PCIE0 MCU DMA0 */
105 { 0x55000000, 0x003000, 0x0001000 }, /* WFDMA PCIE0 MCU DMA1 */
106 { 0x56000000, 0x004000, 0x0001000 }, /* WFDMA reserved */
107 { 0x57000000, 0x005000, 0x0001000 }, /* WFDMA MCU wrap CR */
108 { 0x58000000, 0x006000, 0x0001000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
109 { 0x59000000, 0x007000, 0x0001000 }, /* WFDMA PCIE1 MCU DMA1 */
110 { 0x820c0000, 0x008000, 0x0004000 }, /* WF_UMAC_TOP (PLE) */
111 { 0x820c8000, 0x00c000, 0x0002000 }, /* WF_UMAC_TOP (PSE) */
112 { 0x820cc000, 0x00e000, 0x0002000 }, /* WF_UMAC_TOP (PP) */
113 { 0x74030000, 0x010000, 0x0001000 }, /* PCIe MAC */
114 { 0x820e0000, 0x020000, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
115 { 0x820e1000, 0x020400, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
116 { 0x820e2000, 0x020800, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
117 { 0x820e3000, 0x020c00, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
118 { 0x820e4000, 0x021000, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
119 { 0x820e5000, 0x021400, 0x0000800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
120 { 0x820ce000, 0x021c00, 0x0000200 }, /* WF_LMAC_TOP (WF_SEC) */
121 { 0x820e7000, 0x021e00, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
122 { 0x820cf000, 0x022000, 0x0001000 }, /* WF_LMAC_TOP (WF_PF) */
123 { 0x820e9000, 0x023400, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
124 { 0x820ea000, 0x024000, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
125 { 0x820eb000, 0x024200, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
126 { 0x820ec000, 0x024600, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
127 { 0x820ed000, 0x024800, 0x0000800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
128 { 0x820ca000, 0x026000, 0x0002000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
129 { 0x820d0000, 0x030000, 0x0010000 }, /* WF_LMAC_TOP (WF_WTBLON) */
130 { 0x40000000, 0x070000, 0x0010000 }, /* WF_UMAC_SYSRAM */
131 { 0x00400000, 0x080000, 0x0010000 }, /* WF_MCU_SYSRAM */
132 { 0x00410000, 0x090000, 0x0010000 }, /* WF_MCU_SYSRAM (configure register) */
133 { 0x820f0000, 0x0a0000, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
134 { 0x820f1000, 0x0a0600, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
135 { 0x820f2000, 0x0a0800, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
136 { 0x820f3000, 0x0a0c00, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
137 { 0x820f4000, 0x0a1000, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
138 { 0x820f5000, 0x0a1400, 0x0000800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
139 { 0x820f7000, 0x0a1e00, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
140 { 0x820f9000, 0x0a3400, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
141 { 0x820fa000, 0x0a4000, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
142 { 0x820fb000, 0x0a4200, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
143 { 0x820fc000, 0x0a4600, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
144 { 0x820fd000, 0x0a4800, 0x0000800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
145 { 0x820c4000, 0x0a8000, 0x0004000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
146 { 0x820b0000, 0x0ae000, 0x0001000 }, /* [APB2] WFSYS_ON */
147 { 0x80020000, 0x0b0000, 0x0010000 }, /* WF_TOP_MISC_OFF */
148 { 0x81020000, 0x0c0000, 0x0010000 }, /* WF_TOP_MISC_ON */
149 { 0x7c020000, 0x0d0000, 0x0010000 }, /* CONN_INFRA, wfdma */
150 { 0x7c060000, 0x0e0000, 0x0010000 }, /* CONN_INFRA, conn_host_csr_top */
151 { 0x7c000000, 0x0f0000, 0x0010000 }, /* CONN_INFRA */
152 { 0x70020000, 0x1f0000, 0x0010000 }, /* Reserved for CBTOP, can't switch */
153 { 0x7c500000, 0x060000, 0x2000000 }, /* remap */
154 { 0x0, 0x0, 0x0 } /* End */
155 };
156 int i;
157
158 if (addr < 0x200000)
159 return addr;
160
161 mt7925_reg_remap_restore(dev);
162
163 for (i = 0; i < ARRAY_SIZE(fixed_map); i++) {
164 u32 ofs;
165
166 if (addr < fixed_map[i].phys)
167 continue;
168
169 ofs = addr - fixed_map[i].phys;
170 if (ofs > fixed_map[i].size)
171 continue;
172
173 return fixed_map[i].maps + ofs;
174 }
175
176 if ((addr >= 0x18000000 && addr < 0x18c00000) ||
177 (addr >= 0x70000000 && addr < 0x78000000) ||
178 (addr >= 0x7c000000 && addr < 0x7c400000))
179 return mt7925_reg_map_l1(dev, addr);
180
181 return mt7925_reg_map_l2(dev, addr);
182}
183
184static u32 mt7925_rr(struct mt76_dev *mdev, u32 offset)
185{
186 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
187 u32 addr = __mt7925_reg_addr(dev, offset);
188
189 return dev->bus_ops->rr(mdev, addr);
190}
191
192static void mt7925_wr(struct mt76_dev *mdev, u32 offset, u32 val)
193{
194 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
195 u32 addr = __mt7925_reg_addr(dev, offset);
196
197 dev->bus_ops->wr(mdev, addr, val);
198}
199
200static u32 mt7925_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
201{
202 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
203 u32 addr = __mt7925_reg_addr(dev, offset);
204
205 return dev->bus_ops->rmw(mdev, addr, mask, val);
206}
207
208static int mt7925_dma_init(struct mt792x_dev *dev)
209{
210 int ret;
211
212 mt76_dma_attach(&dev->mt76);
213
214 ret = mt792x_dma_disable(dev, true);
215 if (ret)
216 return ret;
217
218 /* init tx queue */
219 ret = mt76_connac_init_tx_queues(dev->phy.mt76, MT7925_TXQ_BAND0,
220 MT7925_TX_RING_SIZE,
221 MT_TX_RING_BASE, NULL, 0);
222 if (ret)
223 return ret;
224
225 mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, 0x4);
226
227 /* command to WM */
228 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7925_TXQ_MCU_WM,
229 MT7925_TX_MCU_RING_SIZE, MT_TX_RING_BASE);
230 if (ret)
231 return ret;
232
233 /* firmware download */
234 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7925_TXQ_FWDL,
235 MT7925_TX_FWDL_RING_SIZE, MT_TX_RING_BASE);
236 if (ret)
237 return ret;
238
239 /* rx event */
240 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU],
241 MT7925_RXQ_MCU_WM, MT7925_RX_MCU_RING_SIZE,
242 MT_RX_BUF_SIZE, MT_RX_EVENT_RING_BASE);
243 if (ret)
244 return ret;
245
246 /* rx data */
247 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
248 MT7925_RXQ_BAND0, MT7925_RX_RING_SIZE,
249 MT_RX_BUF_SIZE, MT_RX_DATA_RING_BASE);
250 if (ret)
251 return ret;
252
253 ret = mt76_init_queues(dev, mt792x_poll_rx);
254 if (ret < 0)
255 return ret;
256
257 netif_napi_add_tx(dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
258 mt792x_poll_tx);
259 napi_enable(&dev->mt76.tx_napi);
260
261 return mt792x_dma_enable(dev);
262}
263
264static int mt7925_pci_probe(struct pci_dev *pdev,
265 const struct pci_device_id *id)
266{
267 static const struct mt76_driver_ops drv_ops = {
268 /* txwi_size = txd size + txp size */
269 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_hw_txp),
270 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ |
271 MT_DRV_AMSDU_OFFLOAD,
272 .survey_flags = SURVEY_INFO_TIME_TX |
273 SURVEY_INFO_TIME_RX |
274 SURVEY_INFO_TIME_BSS_RX,
275 .token_size = MT7925_TOKEN_SIZE,
276 .tx_prepare_skb = mt7925e_tx_prepare_skb,
277 .tx_complete_skb = mt76_connac_tx_complete_skb,
278 .rx_check = mt7925_rx_check,
279 .rx_skb = mt7925_queue_rx_skb,
280 .rx_poll_complete = mt792x_rx_poll_complete,
281 .sta_add = mt7925_mac_sta_add,
282 .sta_event = mt7925_mac_sta_event,
283 .sta_remove = mt7925_mac_sta_remove,
284 .update_survey = mt792x_update_channel,
285 };
286 static const struct mt792x_hif_ops mt7925_pcie_ops = {
287 .init_reset = mt7925e_init_reset,
288 .reset = mt7925e_mac_reset,
289 .mcu_init = mt7925e_mcu_init,
290 .drv_own = mt792xe_mcu_drv_pmctrl,
291 .fw_own = mt792xe_mcu_fw_pmctrl,
292 };
293 static const struct mt792x_irq_map irq_map = {
294 .host_irq_enable = MT_WFDMA0_HOST_INT_ENA,
295 .tx = {
296 .all_complete_mask = MT_INT_TX_DONE_ALL,
297 .mcu_complete_mask = MT_INT_TX_DONE_MCU,
298 },
299 .rx = {
300 .data_complete_mask = HOST_RX_DONE_INT_ENA2,
301 .wm_complete_mask = HOST_RX_DONE_INT_ENA0,
302 },
303 };
304 struct ieee80211_ops *ops;
305 struct mt76_bus_ops *bus_ops;
306 struct mt792x_dev *dev;
307 struct mt76_dev *mdev;
308 u8 features;
309 int ret;
310 u16 cmd;
311
312 ret = pcim_enable_device(pdev);
313 if (ret)
314 return ret;
315
316 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
317 if (ret)
318 return ret;
319
320 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
321 if (!(cmd & PCI_COMMAND_MEMORY)) {
322 cmd |= PCI_COMMAND_MEMORY;
323 pci_write_config_word(pdev, PCI_COMMAND, cmd);
324 }
325 pci_set_master(pdev);
326
327 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
328 if (ret < 0)
329 return ret;
330
331 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
332 if (ret)
333 goto err_free_pci_vec;
334
335 if (mt7925_disable_aspm)
336 mt76_pci_disable_aspm(pdev);
337
338 ops = mt792x_get_mac80211_ops(&pdev->dev, &mt7925_ops,
339 (void *)id->driver_data, &features);
340 if (!ops) {
341 ret = -ENOMEM;
342 goto err_free_pci_vec;
343 }
344
345 mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), ops, &drv_ops);
346 if (!mdev) {
347 ret = -ENOMEM;
348 goto err_free_pci_vec;
349 }
350
351 pci_set_drvdata(pdev, mdev);
352
353 dev = container_of(mdev, struct mt792x_dev, mt76);
354 dev->fw_features = features;
355 dev->hif_ops = &mt7925_pcie_ops;
356 dev->irq_map = &irq_map;
357 mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]);
358 tasklet_init(&mdev->irq_tasklet, mt792x_irq_tasklet, (unsigned long)dev);
359
360 dev->phy.dev = dev;
361 dev->phy.mt76 = &dev->mt76.phy;
362 dev->mt76.phy.priv = &dev->phy;
363 dev->bus_ops = dev->mt76.bus;
364 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
365 GFP_KERNEL);
366 if (!bus_ops) {
367 ret = -ENOMEM;
368 goto err_free_dev;
369 }
370
371 bus_ops->rr = mt7925_rr;
372 bus_ops->wr = mt7925_wr;
373 bus_ops->rmw = mt7925_rmw;
374 dev->mt76.bus = bus_ops;
375
376 if (!mt7925_disable_aspm && mt76_pci_aspm_supported(pdev))
377 dev->aspm_supported = true;
378
379 ret = __mt792x_mcu_fw_pmctrl(dev);
380 if (ret)
381 goto err_free_dev;
382
383 ret = __mt792xe_mcu_drv_pmctrl(dev);
384 if (ret)
385 goto err_free_dev;
386
387 mdev->rev = (mt76_rr(dev, MT_HW_CHIPID) << 16) |
388 (mt76_rr(dev, MT_HW_REV) & 0xff);
389
390 dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
391
392 mt76_rmw_field(dev, MT_HW_EMI_CTL, MT_HW_EMI_CTL_SLPPROT_EN, 1);
393
394 ret = mt792x_wfsys_reset(dev);
395 if (ret)
396 goto err_free_dev;
397
398 mt76_wr(dev, irq_map.host_irq_enable, 0);
399
400 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
401
402 ret = devm_request_irq(mdev->dev, pdev->irq, mt792x_irq_handler,
403 IRQF_SHARED, KBUILD_MODNAME, dev);
404 if (ret)
405 goto err_free_dev;
406
407 ret = mt7925_dma_init(dev);
408 if (ret)
409 goto err_free_irq;
410
411 ret = mt7925_register_device(dev);
412 if (ret)
413 goto err_free_irq;
414
415 return 0;
416
417err_free_irq:
418 devm_free_irq(&pdev->dev, pdev->irq, dev);
419err_free_dev:
420 mt76_free_device(&dev->mt76);
421err_free_pci_vec:
422 pci_free_irq_vectors(pdev);
423
424 return ret;
425}
426
427static void mt7925_pci_remove(struct pci_dev *pdev)
428{
429 struct mt76_dev *mdev = pci_get_drvdata(pdev);
430 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
431
432 mt7925e_unregister_device(dev);
433 set_bit(MT76_REMOVED, &mdev->phy.state);
434 devm_free_irq(&pdev->dev, pdev->irq, dev);
435 mt76_free_device(&dev->mt76);
436 pci_free_irq_vectors(pdev);
437}
438
439static int mt7925_pci_suspend(struct device *device)
440{
441 struct pci_dev *pdev = to_pci_dev(device);
442 struct mt76_dev *mdev = pci_get_drvdata(pdev);
443 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
444 struct mt76_connac_pm *pm = &dev->pm;
445 int i, err;
446
447 pm->suspended = true;
448 flush_work(&dev->reset_work);
449 cancel_delayed_work_sync(&pm->ps_work);
450 cancel_work_sync(&pm->wake_work);
451
452 mt7925_roc_abort_sync(dev);
453
454 err = mt792x_mcu_drv_pmctrl(dev);
455 if (err < 0)
456 goto restore_suspend;
457
458 /* always enable deep sleep during suspend to reduce
459 * power consumption
460 */
461 mt7925_mcu_set_deep_sleep(dev, true);
462
463 err = mt76_connac_mcu_set_hif_suspend(mdev, true);
464 if (err)
465 goto restore_suspend;
466
467 napi_disable(&mdev->tx_napi);
468 mt76_worker_disable(&mdev->tx_worker);
469
470 mt76_for_each_q_rx(mdev, i) {
471 napi_disable(&mdev->napi[i]);
472 }
473
474 /* wait until dma is idle */
475 mt76_poll(dev, MT_WFDMA0_GLO_CFG,
476 MT_WFDMA0_GLO_CFG_TX_DMA_BUSY |
477 MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000);
478
479 /* put dma disabled */
480 mt76_clear(dev, MT_WFDMA0_GLO_CFG,
481 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
482
483 /* disable interrupt */
484 mt76_wr(dev, dev->irq_map->host_irq_enable, 0);
485 mt76_wr(dev, MT_WFDMA0_HOST_INT_DIS,
486 dev->irq_map->tx.all_complete_mask |
487 MT_INT_RX_DONE_ALL | MT_INT_MCU_CMD);
488
489 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0);
490
491 synchronize_irq(pdev->irq);
492 tasklet_kill(&mdev->irq_tasklet);
493
494 err = mt792x_mcu_fw_pmctrl(dev);
495 if (err)
496 goto restore_napi;
497
498 return 0;
499
500restore_napi:
501 mt76_for_each_q_rx(mdev, i) {
502 napi_enable(&mdev->napi[i]);
503 }
504 napi_enable(&mdev->tx_napi);
505
506 if (!pm->ds_enable)
507 mt7925_mcu_set_deep_sleep(dev, false);
508
509 mt76_connac_mcu_set_hif_suspend(mdev, false);
510
511restore_suspend:
512 pm->suspended = false;
513
514 if (err < 0)
515 mt792x_reset(&dev->mt76);
516
517 return err;
518}
519
520static int mt7925_pci_resume(struct device *device)
521{
522 struct pci_dev *pdev = to_pci_dev(device);
523 struct mt76_dev *mdev = pci_get_drvdata(pdev);
524 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
525 struct mt76_connac_pm *pm = &dev->pm;
526 int i, err;
527
528 err = mt792x_mcu_drv_pmctrl(dev);
529 if (err < 0)
530 goto failed;
531
532 mt792x_wpdma_reinit_cond(dev);
533
534 /* enable interrupt */
535 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
536 mt76_connac_irq_enable(&dev->mt76,
537 dev->irq_map->tx.all_complete_mask |
538 MT_INT_RX_DONE_ALL | MT_INT_MCU_CMD);
539 mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE);
540
541 /* put dma enabled */
542 mt76_set(dev, MT_WFDMA0_GLO_CFG,
543 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
544
545 mt76_worker_enable(&mdev->tx_worker);
546
547 local_bh_disable();
548 mt76_for_each_q_rx(mdev, i) {
549 napi_enable(&mdev->napi[i]);
550 napi_schedule(&mdev->napi[i]);
551 }
552 napi_enable(&mdev->tx_napi);
553 napi_schedule(&mdev->tx_napi);
554 local_bh_enable();
555
556 err = mt76_connac_mcu_set_hif_suspend(mdev, false);
557
558 /* restore previous ds setting */
559 if (!pm->ds_enable)
560 mt7925_mcu_set_deep_sleep(dev, false);
561
562failed:
563 pm->suspended = false;
564
565 if (err < 0)
566 mt792x_reset(&dev->mt76);
567
568 return err;
569}
570
571static void mt7925_pci_shutdown(struct pci_dev *pdev)
572{
573 mt7925_pci_remove(pdev);
574}
575
576static DEFINE_SIMPLE_DEV_PM_OPS(mt7925_pm_ops, mt7925_pci_suspend, mt7925_pci_resume);
577
578static struct pci_driver mt7925_pci_driver = {
579 .name = KBUILD_MODNAME,
580 .id_table = mt7925_pci_device_table,
581 .probe = mt7925_pci_probe,
582 .remove = mt7925_pci_remove,
583 .shutdown = mt7925_pci_shutdown,
584 .driver.pm = pm_sleep_ptr(&mt7925_pm_ops),
585};
586
587module_pci_driver(mt7925_pci_driver);
588
589MODULE_DEVICE_TABLE(pci, mt7925_pci_device_table);
590MODULE_FIRMWARE(MT7925_FIRMWARE_WM);
591MODULE_FIRMWARE(MT7925_ROM_PATCH);
592MODULE_AUTHOR("Deren Wu <deren.wu@mediatek.com>");
593MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
594MODULE_DESCRIPTION("MediaTek MT7925E (PCIe) wireless driver");
595MODULE_LICENSE("Dual BSD/GPL");