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1/* SPDX-License-Identifier: ISC */
2/* Copyright (C) 2023 MediaTek Inc. */
3
4#ifndef __MT76_CONNAC3_MAC_H
5#define __MT76_CONNAC3_MAC_H
6
7enum {
8 MT_CTX0,
9 MT_HIF0 = 0x0,
10
11 MT_LMAC_AC00 = 0x0,
12 MT_LMAC_AC01,
13 MT_LMAC_AC02,
14 MT_LMAC_AC03,
15 MT_LMAC_ALTX0 = 0x10,
16 MT_LMAC_BMC0,
17 MT_LMAC_BCN0,
18 MT_LMAC_PSMP0,
19};
20
21#define MT_CT_PARSE_LEN 72
22#define MT_CT_DMA_BUF_NUM 2
23
24#define MT_RXD0_LENGTH GENMASK(15, 0)
25#define MT_RXD0_PKT_FLAG GENMASK(19, 16)
26#define MT_RXD0_PKT_TYPE GENMASK(31, 27)
27
28#define MT_RXD0_MESH BIT(18)
29#define MT_RXD0_MHCP BIT(19)
30#define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
31#define MT_RXD0_NORMAL_IP_SUM BIT(23)
32#define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
33
34#define MT_RXD0_SW_PKT_TYPE_MASK GENMASK(31, 16)
35#define MT_RXD0_SW_PKT_TYPE_MAP 0x380F
36#define MT_RXD0_SW_PKT_TYPE_FRAME 0x3801
37
38/* RXD DW1 */
39#define MT_RXD1_NORMAL_WLAN_IDX GENMASK(11, 0)
40#define MT_RXD1_NORMAL_GROUP_1 BIT(16)
41#define MT_RXD1_NORMAL_GROUP_2 BIT(17)
42#define MT_RXD1_NORMAL_GROUP_3 BIT(18)
43#define MT_RXD1_NORMAL_GROUP_4 BIT(19)
44#define MT_RXD1_NORMAL_GROUP_5 BIT(20)
45#define MT_RXD1_NORMAL_KEY_ID GENMASK(22, 21)
46#define MT_RXD1_NORMAL_CM BIT(23)
47#define MT_RXD1_NORMAL_CLM BIT(24)
48#define MT_RXD1_NORMAL_ICV_ERR BIT(25)
49#define MT_RXD1_NORMAL_TKIP_MIC_ERR BIT(26)
50#define MT_RXD1_NORMAL_BAND_IDX GENMASK(28, 27)
51#define MT_RXD1_NORMAL_SPP_EN BIT(29)
52#define MT_RXD1_NORMAL_ADD_OM BIT(30)
53#define MT_RXD1_NORMAL_SEC_DONE BIT(31)
54
55/* RXD DW2 */
56#define MT_RXD2_NORMAL_BSSID GENMASK(5, 0)
57#define MT_RXD2_NORMAL_MAC_HDR_LEN GENMASK(12, 8)
58#define MT_RXD2_NORMAL_HDR_TRANS BIT(7)
59#define MT_RXD2_NORMAL_HDR_OFFSET GENMASK(15, 13)
60#define MT_RXD2_NORMAL_SEC_MODE GENMASK(20, 16)
61#define MT_RXD2_NORMAL_MU_BAR BIT(21)
62#define MT_RXD2_NORMAL_SW_BIT BIT(22)
63#define MT_RXD2_NORMAL_AMSDU_ERR BIT(23)
64#define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
65#define MT_RXD2_NORMAL_HDR_TRANS_ERROR BIT(25)
66#define MT_RXD2_NORMAL_INT_FRAME BIT(26)
67#define MT_RXD2_NORMAL_FRAG BIT(27)
68#define MT_RXD2_NORMAL_NULL_FRAME BIT(28)
69#define MT_RXD2_NORMAL_NDATA BIT(29)
70#define MT_RXD2_NORMAL_NON_AMPDU BIT(30)
71#define MT_RXD2_NORMAL_BF_REPORT BIT(31)
72
73/* RXD DW3 */
74#define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
75#define MT_RXD3_NORMAL_CH_FREQ GENMASK(15, 8)
76#define MT_RXD3_NORMAL_ADDR_TYPE GENMASK(17, 16)
77#define MT_RXD3_NORMAL_U2M BIT(0)
78#define MT_RXD3_NORMAL_HTC_VLD BIT(18)
79#define MT_RXD3_NORMAL_BEACON_MC BIT(20)
80#define MT_RXD3_NORMAL_BEACON_UC BIT(21)
81#define MT_RXD3_NORMAL_CO_ANT BIT(22)
82#define MT_RXD3_NORMAL_FCS_ERR BIT(24)
83#define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
84
85/* RXD DW4 */
86#define MT_RXD4_NORMAL_PAYLOAD_FORMAT GENMASK(1, 0)
87#define MT_RXD4_FIRST_AMSDU_FRAME GENMASK(1, 0)
88#define MT_RXD4_MID_AMSDU_FRAME BIT(1)
89#define MT_RXD4_LAST_AMSDU_FRAME BIT(0)
90
91#define MT_RXV_HDR_BAND_IDX BIT(24)
92
93/* RXD GROUP4 */
94#define MT_RXD8_FRAME_CONTROL GENMASK(15, 0)
95
96#define MT_RXD10_SEQ_CTRL GENMASK(15, 0)
97#define MT_RXD10_QOS_CTL GENMASK(31, 16)
98
99#define MT_RXD11_HT_CONTROL GENMASK(31, 0)
100
101/* P-RXV */
102#define MT_PRXV_TX_RATE GENMASK(6, 0)
103#define MT_PRXV_TX_DCM BIT(4)
104#define MT_PRXV_TX_ER_SU_106T BIT(5)
105#define MT_PRXV_NSTS GENMASK(10, 7)
106#define MT_PRXV_TXBF BIT(11)
107#define MT_PRXV_HT_AD_CODE BIT(12)
108#define MT_PRXV_HE_RU_ALLOC GENMASK(30, 22)
109#define MT_PRXV_RCPI3 GENMASK(31, 24)
110#define MT_PRXV_RCPI2 GENMASK(23, 16)
111#define MT_PRXV_RCPI1 GENMASK(15, 8)
112#define MT_PRXV_RCPI0 GENMASK(7, 0)
113#define MT_PRXV_HT_SHORT_GI GENMASK(4, 3)
114#define MT_PRXV_HT_STBC GENMASK(10, 9)
115#define MT_PRXV_TX_MODE GENMASK(14, 11)
116#define MT_PRXV_FRAME_MODE GENMASK(2, 0)
117#define MT_PRXV_DCM BIT(5)
118
119/* C-RXV */
120#define MT_CRXV_HE_NUM_USER GENMASK(26, 20)
121#define MT_CRXV_HE_LTF_SIZE GENMASK(28, 27)
122#define MT_CRXV_HE_LDPC_EXT_SYM BIT(30)
123
124#define MT_CRXV_HE_PE_DISAMBIG BIT(1)
125#define MT_CRXV_HE_UPLINK BIT(2)
126
127#define MT_CRXV_HE_MU_AID GENMASK(27, 17)
128#define MT_CRXV_HE_BEAM_CHNG BIT(29)
129
130#define MT_CRXV_HE_DOPPLER BIT(0)
131#define MT_CRXV_HE_BSS_COLOR GENMASK(15, 10)
132#define MT_CRXV_HE_TXOP_DUR GENMASK(19, 17)
133
134#define MT_CRXV_HE_SR_MASK GENMASK(11, 8)
135#define MT_CRXV_HE_SR1_MASK GENMASK(16, 12)
136#define MT_CRXV_HE_SR2_MASK GENMASK(20, 17)
137#define MT_CRXV_HE_SR3_MASK GENMASK(24, 21)
138
139#define MT_CRXV_HE_RU0 GENMASK(8, 0)
140#define MT_CRXV_HE_RU1 GENMASK(17, 9)
141#define MT_CRXV_HE_RU2 GENMASK(26, 18)
142#define MT_CRXV_HE_RU3_L GENMASK(31, 27)
143#define MT_CRXV_HE_RU3_H GENMASK(3, 0)
144
145enum tx_header_format {
146 MT_HDR_FORMAT_802_3,
147 MT_HDR_FORMAT_CMD,
148 MT_HDR_FORMAT_802_11,
149 MT_HDR_FORMAT_802_11_EXT,
150};
151
152enum tx_pkt_type {
153 MT_TX_TYPE_CT,
154 MT_TX_TYPE_SF,
155 MT_TX_TYPE_CMD,
156 MT_TX_TYPE_FW,
157};
158
159enum tx_port_idx {
160 MT_TX_PORT_IDX_LMAC,
161 MT_TX_PORT_IDX_MCU
162};
163
164enum tx_mcu_port_q_idx {
165 MT_TX_MCU_PORT_RX_Q0 = 0x20,
166 MT_TX_MCU_PORT_RX_Q1,
167 MT_TX_MCU_PORT_RX_Q2,
168 MT_TX_MCU_PORT_RX_Q3,
169 MT_TX_MCU_PORT_RX_FWDL = 0x3e
170};
171
172enum tx_mgnt_type {
173 MT_TX_NORMAL,
174 MT_TX_TIMING,
175 MT_TX_ADDBA,
176};
177
178#define MT_CT_INFO_APPLY_TXD BIT(0)
179#define MT_CT_INFO_COPY_HOST_TXD_ALL BIT(1)
180#define MT_CT_INFO_MGMT_FRAME BIT(2)
181#define MT_CT_INFO_NONE_CIPHER_FRAME BIT(3)
182#define MT_CT_INFO_HSR2_TX BIT(4)
183#define MT_CT_INFO_FROM_HOST BIT(7)
184
185#define MT_TXD_SIZE (8 * 4)
186
187#define MT_TXD0_Q_IDX GENMASK(31, 25)
188#define MT_TXD0_PKT_FMT GENMASK(24, 23)
189#define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)
190#define MT_TXD0_TX_BYTES GENMASK(15, 0)
191
192#define MT_TXD1_FIXED_RATE BIT(31)
193#define MT_TXD1_OWN_MAC GENMASK(30, 25)
194#define MT_TXD1_TID GENMASK(24, 21)
195#define MT_TXD1_BIP BIT(24)
196#define MT_TXD1_ETH_802_3 BIT(20)
197#define MT_TXD1_HDR_INFO GENMASK(20, 16)
198#define MT_TXD1_HDR_FORMAT GENMASK(15, 14)
199#define MT_TXD1_TGID GENMASK(13, 12)
200#define MT_TXD1_WLAN_IDX GENMASK(11, 0)
201
202#define MT_TXD2_POWER_OFFSET GENMASK(31, 26)
203#define MT_TXD2_MAX_TX_TIME GENMASK(25, 16)
204#define MT_TXD2_FRAG GENMASK(15, 14)
205#define MT_TXD2_HTC_VLD BIT(13)
206#define MT_TXD2_DURATION BIT(12)
207#define MT_TXD2_HDR_PAD GENMASK(11, 10)
208#define MT_TXD2_RTS BIT(9)
209#define MT_TXD2_OWN_MAC_MAP BIT(8)
210#define MT_TXD2_BF_TYPE GENMASK(6, 7)
211#define MT_TXD2_FRAME_TYPE GENMASK(5, 4)
212#define MT_TXD2_SUB_TYPE GENMASK(3, 0)
213
214#define MT_TXD3_SN_VALID BIT(31)
215#define MT_TXD3_PN_VALID BIT(30)
216#define MT_TXD3_SW_POWER_MGMT BIT(29)
217#define MT_TXD3_BA_DISABLE BIT(28)
218#define MT_TXD3_SEQ GENMASK(27, 16)
219#define MT_TXD3_REM_TX_COUNT GENMASK(15, 11)
220#define MT_TXD3_TX_COUNT GENMASK(10, 6)
221#define MT_TXD3_HW_AMSDU BIT(5)
222#define MT_TXD3_BCM BIT(4)
223#define MT_TXD3_EEOSP BIT(3)
224#define MT_TXD3_EMRD BIT(2)
225#define MT_TXD3_PROTECT_FRAME BIT(1)
226#define MT_TXD3_NO_ACK BIT(0)
227
228#define MT_TXD4_PN_LOW GENMASK(31, 0)
229
230#define MT_TXD5_PN_HIGH GENMASK(31, 16)
231#define MT_TXD5_FL BIT(15)
232#define MT_TXD5_BYPASS_TBB BIT(14)
233#define MT_TXD5_BYPASS_RBB BIT(13)
234#define MT_TXD5_BSS_COLOR_ZERO BIT(12)
235#define MT_TXD5_TX_STATUS_HOST BIT(10)
236#define MT_TXD5_TX_STATUS_MCU BIT(9)
237#define MT_TXD5_TX_STATUS_FMT BIT(8)
238#define MT_TXD5_PID GENMASK(7, 0)
239
240#define MT_TXD6_TX_SRC GENMASK(31, 30)
241#define MT_TXD6_VTA BIT(28)
242#define MT_TXD6_FIXED_BW BIT(25)
243#define MT_TXD6_BW GENMASK(24, 22)
244#define MT_TXD6_TX_RATE GENMASK(21, 16)
245#define MT_TXD6_TIMESTAMP_OFS_EN BIT(15)
246#define MT_TXD6_TIMESTAMP_OFS_IDX GENMASK(14, 10)
247#define MT_TXD6_MSDU_CNT GENMASK(9, 4)
248#define MT_TXD6_MSDU_CNT_V2 GENMASK(15, 10)
249#define MT_TXD6_DIS_MAT BIT(3)
250#define MT_TXD6_DAS BIT(2)
251#define MT_TXD6_AMSDU_CAP BIT(1)
252
253#define MT_TXD7_TXD_LEN GENMASK(31, 30)
254#define MT_TXD7_IP_SUM BIT(29)
255#define MT_TXD7_DROP_BY_SDO BIT(28)
256#define MT_TXD7_MAC_TXD BIT(27)
257#define MT_TXD7_CTXD BIT(26)
258#define MT_TXD7_CTXD_CNT GENMASK(25, 22)
259#define MT_TXD7_UDP_TCP_SUM BIT(15)
260#define MT_TXD7_TX_TIME GENMASK(9, 0)
261
262#define MT_TXD9_WLAN_IDX GENMASK(23, 8)
263
264#define MT_TXP_BUF_LEN GENMASK(11, 0)
265#define MT_TXP_DMA_ADDR_H GENMASK(15, 12)
266
267#define MT_TX_RATE_STBC BIT(14)
268#define MT_TX_RATE_NSS GENMASK(13, 10)
269#define MT_TX_RATE_MODE GENMASK(9, 6)
270#define MT_TX_RATE_SU_EXT_TONE BIT(5)
271#define MT_TX_RATE_DCM BIT(4)
272/* VHT/HE only use bits 0-3 */
273#define MT_TX_RATE_IDX GENMASK(5, 0)
274
275#define MT_TXFREE0_PKT_TYPE GENMASK(31, 27)
276#define MT_TXFREE0_MSDU_CNT GENMASK(25, 16)
277#define MT_TXFREE0_RX_BYTE GENMASK(15, 0)
278
279#define MT_TXFREE1_VER GENMASK(19, 16)
280
281#define MT_TXFREE_INFO_PAIR BIT(31)
282#define MT_TXFREE_INFO_HEADER BIT(30)
283#define MT_TXFREE_INFO_WLAN_ID GENMASK(23, 12)
284#define MT_TXFREE_INFO_MSDU_ID GENMASK(14, 0)
285#define MT_TXFREE_INFO_COUNT GENMASK(27, 24)
286#define MT_TXFREE_INFO_STAT GENMASK(29, 28)
287
288#define MT_TXS0_BW GENMASK(31, 29)
289#define MT_TXS0_TID GENMASK(28, 26)
290#define MT_TXS0_AMPDU BIT(25)
291#define MT_TXS0_TXS_FORMAT GENMASK(24, 23)
292#define MT_TXS0_BA_ERROR BIT(22)
293#define MT_TXS0_PS_FLAG BIT(21)
294#define MT_TXS0_TXOP_TIMEOUT BIT(20)
295#define MT_TXS0_BIP_ERROR BIT(19)
296
297#define MT_TXS0_QUEUE_TIMEOUT BIT(18)
298#define MT_TXS0_RTS_TIMEOUT BIT(17)
299#define MT_TXS0_ACK_TIMEOUT BIT(16)
300#define MT_TXS0_ACK_ERROR_MASK GENMASK(18, 16)
301
302#define MT_TXS0_TX_STATUS_HOST BIT(15)
303#define MT_TXS0_TX_STATUS_MCU BIT(14)
304#define MT_TXS0_TX_RATE GENMASK(13, 0)
305
306#define MT_TXS1_SEQNO GENMASK(31, 20)
307#define MT_TXS1_RESP_RATE GENMASK(19, 16)
308#define MT_TXS1_RXV_SEQNO GENMASK(15, 8)
309#define MT_TXS1_TX_POWER_DBM GENMASK(7, 0)
310
311#define MT_TXS2_BF_STATUS GENMASK(31, 30)
312#define MT_TXS2_BAND GENMASK(29, 28)
313#define MT_TXS2_WCID GENMASK(27, 16)
314#define MT_TXS2_TX_DELAY GENMASK(15, 0)
315
316#define MT_TXS3_PID GENMASK(31, 24)
317#define MT_TXS3_RATE_STBC BIT(7)
318#define MT_TXS3_FIXED_RATE BIT(6)
319#define MT_TXS3_SRC GENMASK(5, 4)
320#define MT_TXS3_SHARED_ANTENNA BIT(3)
321#define MT_TXS3_LAST_TX_RATE GENMASK(2, 0)
322
323#define MT_TXS4_TIMESTAMP GENMASK(31, 0)
324
325/* MPDU based TXS */
326#define MT_TXS5_F0_FINAL_MPDU BIT(31)
327#define MT_TXS5_F0_QOS BIT(30)
328#define MT_TXS5_F0_TX_COUNT GENMASK(29, 25)
329#define MT_TXS5_F0_FRONT_TIME GENMASK(24, 0)
330#define MT_TXS5_F1_MPDU_TX_COUNT GENMASK(31, 24)
331#define MT_TXS5_F1_MPDU_TX_BYTES GENMASK(23, 0)
332
333#define MT_TXS6_F0_NOISE_3 GENMASK(31, 24)
334#define MT_TXS6_F0_NOISE_2 GENMASK(23, 16)
335#define MT_TXS6_F0_NOISE_1 GENMASK(15, 8)
336#define MT_TXS6_F0_NOISE_0 GENMASK(7, 0)
337#define MT_TXS6_F1_MPDU_FAIL_COUNT GENMASK(31, 24)
338#define MT_TXS6_F1_MPDU_FAIL_BYTES GENMASK(23, 0)
339
340#define MT_TXS7_F0_RCPI_3 GENMASK(31, 24)
341#define MT_TXS7_F0_RCPI_2 GENMASK(23, 16)
342#define MT_TXS7_F0_RCPI_1 GENMASK(15, 8)
343#define MT_TXS7_F0_RCPI_0 GENMASK(7, 0)
344#define MT_TXS7_F1_MPDU_RETRY_COUNT GENMASK(31, 24)
345#define MT_TXS7_F1_MPDU_RETRY_BYTES GENMASK(23, 0)
346
347/* PPDU based TXS */
348#define MT_TXS5_MPDU_TX_CNT GENMASK(30, 20)
349#define MT_TXS5_MPDU_TX_BYTE_SCALE BIT(15)
350#define MT_TXS5_MPDU_TX_BYTE GENMASK(14, 0)
351
352#define MT_TXS6_MPDU_FAIL_CNT GENMASK(30, 20)
353#define MT_TXS6_MPDU_FAIL_BYTE_SCALE BIT(15)
354#define MT_TXS6_MPDU_FAIL_BYTE GENMASK(14, 0)
355
356#define MT_TXS7_MPDU_RETRY_CNT GENMASK(30, 20)
357#define MT_TXS7_MPDU_RETRY_BYTE_SCALE BIT(15)
358#define MT_TXS7_MPDU_RETRY_BYTE GENMASK(14, 0)
359
360#endif /* __MT76_CONNAC3_MAC_H */
1/* SPDX-License-Identifier: ISC */
2/* Copyright (C) 2023 MediaTek Inc. */
3
4#ifndef __MT76_CONNAC3_MAC_H
5#define __MT76_CONNAC3_MAC_H
6
7enum {
8 MT_CTX0,
9 MT_HIF0 = 0x0,
10
11 MT_LMAC_AC00 = 0x0,
12 MT_LMAC_AC01,
13 MT_LMAC_AC02,
14 MT_LMAC_AC03,
15 MT_LMAC_ALTX0 = 0x10,
16 MT_LMAC_BMC0,
17 MT_LMAC_BCN0,
18 MT_LMAC_PSMP0,
19};
20
21#define MT_CT_PARSE_LEN 72
22#define MT_CT_DMA_BUF_NUM 2
23
24#define MT_RXD0_LENGTH GENMASK(15, 0)
25#define MT_RXD0_PKT_FLAG GENMASK(19, 16)
26#define MT_RXD0_PKT_TYPE GENMASK(31, 27)
27
28#define MT_RXD0_MESH BIT(18)
29#define MT_RXD0_MHCP BIT(19)
30#define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
31
32#define MT_RXD0_SW_PKT_TYPE_MASK GENMASK(31, 16)
33#define MT_RXD0_SW_PKT_TYPE_MAP 0x380F
34#define MT_RXD0_SW_PKT_TYPE_FRAME 0x3801
35
36/* RXD DW1 */
37#define MT_RXD1_NORMAL_WLAN_IDX GENMASK(11, 0)
38#define MT_RXD1_NORMAL_GROUP_1 BIT(16)
39#define MT_RXD1_NORMAL_GROUP_2 BIT(17)
40#define MT_RXD1_NORMAL_GROUP_3 BIT(18)
41#define MT_RXD1_NORMAL_GROUP_4 BIT(19)
42#define MT_RXD1_NORMAL_GROUP_5 BIT(20)
43#define MT_RXD1_NORMAL_KEY_ID GENMASK(22, 21)
44#define MT_RXD1_NORMAL_CM BIT(23)
45#define MT_RXD1_NORMAL_CLM BIT(24)
46#define MT_RXD1_NORMAL_ICV_ERR BIT(25)
47#define MT_RXD1_NORMAL_TKIP_MIC_ERR BIT(26)
48#define MT_RXD1_NORMAL_BAND_IDX GENMASK(28, 27)
49#define MT_RXD1_NORMAL_SPP_EN BIT(29)
50#define MT_RXD1_NORMAL_ADD_OM BIT(30)
51#define MT_RXD1_NORMAL_SEC_DONE BIT(31)
52
53/* RXD DW2 */
54#define MT_RXD2_NORMAL_BSSID GENMASK(5, 0)
55#define MT_RXD2_NORMAL_MAC_HDR_LEN GENMASK(12, 8)
56#define MT_RXD2_NORMAL_HDR_TRANS BIT(7)
57#define MT_RXD2_NORMAL_HDR_OFFSET GENMASK(15, 13)
58#define MT_RXD2_NORMAL_SEC_MODE GENMASK(20, 16)
59#define MT_RXD2_NORMAL_MU_BAR BIT(21)
60#define MT_RXD2_NORMAL_SW_BIT BIT(22)
61#define MT_RXD2_NORMAL_AMSDU_ERR BIT(23)
62#define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
63#define MT_RXD2_NORMAL_HDR_TRANS_ERROR BIT(25)
64#define MT_RXD2_NORMAL_INT_FRAME BIT(26)
65#define MT_RXD2_NORMAL_FRAG BIT(27)
66#define MT_RXD2_NORMAL_NULL_FRAME BIT(28)
67#define MT_RXD2_NORMAL_NDATA BIT(29)
68#define MT_RXD2_NORMAL_NON_AMPDU BIT(30)
69#define MT_RXD2_NORMAL_BF_REPORT BIT(31)
70
71/* RXD DW3 */
72#define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
73#define MT_RXD3_NORMAL_CH_FREQ GENMASK(15, 8)
74#define MT_RXD3_NORMAL_ADDR_TYPE GENMASK(17, 16)
75#define MT_RXD3_NORMAL_U2M BIT(0)
76#define MT_RXD3_NORMAL_HTC_VLD BIT(18)
77#define MT_RXD3_NORMAL_BEACON_MC BIT(20)
78#define MT_RXD3_NORMAL_BEACON_UC BIT(21)
79#define MT_RXD3_NORMAL_CO_ANT BIT(22)
80#define MT_RXD3_NORMAL_FCS_ERR BIT(24)
81#define MT_RXD3_NORMAL_IP_SUM BIT(26)
82#define MT_RXD3_NORMAL_UDP_TCP_SUM BIT(27)
83#define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
84
85/* RXD DW4 */
86#define MT_RXD4_NORMAL_PAYLOAD_FORMAT GENMASK(1, 0)
87#define MT_RXD4_FIRST_AMSDU_FRAME GENMASK(1, 0)
88#define MT_RXD4_MID_AMSDU_FRAME BIT(1)
89#define MT_RXD4_LAST_AMSDU_FRAME BIT(0)
90
91#define MT_RXV_HDR_BAND_IDX BIT(24)
92
93/* RXD GROUP4 */
94#define MT_RXD8_FRAME_CONTROL GENMASK(15, 0)
95
96#define MT_RXD10_SEQ_CTRL GENMASK(15, 0)
97#define MT_RXD10_QOS_CTL GENMASK(31, 16)
98
99#define MT_RXD11_HT_CONTROL GENMASK(31, 0)
100
101/* P-RXV */
102#define MT_PRXV_TX_RATE GENMASK(6, 0)
103#define MT_PRXV_TX_DCM BIT(4)
104#define MT_PRXV_TX_ER_SU_106T BIT(5)
105#define MT_PRXV_NSTS GENMASK(10, 7)
106#define MT_PRXV_TXBF BIT(11)
107#define MT_PRXV_HT_AD_CODE BIT(12)
108#define MT_PRXV_HE_RU_ALLOC GENMASK(30, 22)
109#define MT_PRXV_RCPI3 GENMASK(31, 24)
110#define MT_PRXV_RCPI2 GENMASK(23, 16)
111#define MT_PRXV_RCPI1 GENMASK(15, 8)
112#define MT_PRXV_RCPI0 GENMASK(7, 0)
113#define MT_PRXV_HT_SHORT_GI GENMASK(4, 3)
114#define MT_PRXV_HT_STBC GENMASK(10, 9)
115#define MT_PRXV_TX_MODE GENMASK(14, 11)
116#define MT_PRXV_FRAME_MODE GENMASK(2, 0)
117#define MT_PRXV_DCM BIT(5)
118
119/* C-RXV */
120#define MT_CRXV_HE_NUM_USER GENMASK(26, 20)
121#define MT_CRXV_HE_LTF_SIZE GENMASK(28, 27)
122#define MT_CRXV_HE_LDPC_EXT_SYM BIT(30)
123
124#define MT_CRXV_HE_PE_DISAMBIG BIT(1)
125#define MT_CRXV_HE_UPLINK BIT(2)
126
127#define MT_CRXV_HE_MU_AID GENMASK(27, 17)
128#define MT_CRXV_HE_BEAM_CHNG BIT(29)
129
130#define MT_CRXV_HE_DOPPLER BIT(0)
131#define MT_CRXV_HE_BSS_COLOR GENMASK(15, 10)
132#define MT_CRXV_HE_TXOP_DUR GENMASK(19, 17)
133
134#define MT_CRXV_HE_SR_MASK GENMASK(11, 8)
135#define MT_CRXV_HE_SR1_MASK GENMASK(16, 12)
136#define MT_CRXV_HE_SR2_MASK GENMASK(20, 17)
137#define MT_CRXV_HE_SR3_MASK GENMASK(24, 21)
138
139#define MT_CRXV_HE_RU0 GENMASK(8, 0)
140#define MT_CRXV_HE_RU1 GENMASK(17, 9)
141#define MT_CRXV_HE_RU2 GENMASK(26, 18)
142#define MT_CRXV_HE_RU3_L GENMASK(31, 27)
143#define MT_CRXV_HE_RU3_H GENMASK(3, 0)
144
145#define MT_CRXV_EHT_NUM_USER GENMASK(26, 20)
146#define MT_CRXV_EHT_LTF_SIZE GENMASK(28, 27)
147#define MT_CRXV_EHT_LDPC_EXT_SYM BIT(30)
148#define MT_CRXV_EHT_PE_DISAMBIG BIT(1)
149#define MT_CRXV_EHT_UPLINK BIT(2)
150#define MT_CRXV_EHT_MU_AID GENMASK(27, 17)
151#define MT_CRXV_EHT_BEAM_CHNG BIT(29)
152#define MT_CRXV_EHT_DOPPLER BIT(0)
153#define MT_CRXV_EHT_BSS_COLOR GENMASK(15, 10)
154#define MT_CRXV_EHT_TXOP_DUR GENMASK(23, 17)
155#define MT_CRXV_EHT_SR_MASK GENMASK(11, 8)
156#define MT_CRXV_EHT_SR1_MASK GENMASK(15, 12)
157#define MT_CRXV_EHT_SR2_MASK GENMASK(19, 16)
158#define MT_CRXV_EHT_SR3_MASK GENMASK(23, 20)
159#define MT_CRXV_EHT_RU0 GENMASK(8, 0)
160#define MT_CRXV_EHT_RU1 GENMASK(17, 9)
161#define MT_CRXV_EHT_RU2 GENMASK(26, 18)
162#define MT_CRXV_EHT_RU3_L GENMASK(31, 27)
163#define MT_CRXV_EHT_RU3_H GENMASK(3, 0)
164#define MT_CRXV_EHT_SIG_MCS GENMASK(19, 18)
165#define MT_CRXV_EHT_LTF_SYM GENMASK(22, 20)
166
167enum tx_header_format {
168 MT_HDR_FORMAT_802_3,
169 MT_HDR_FORMAT_CMD,
170 MT_HDR_FORMAT_802_11,
171 MT_HDR_FORMAT_802_11_EXT,
172};
173
174enum tx_pkt_type {
175 MT_TX_TYPE_CT,
176 MT_TX_TYPE_SF,
177 MT_TX_TYPE_CMD,
178 MT_TX_TYPE_FW,
179};
180
181enum tx_port_idx {
182 MT_TX_PORT_IDX_LMAC,
183 MT_TX_PORT_IDX_MCU
184};
185
186enum tx_mcu_port_q_idx {
187 MT_TX_MCU_PORT_RX_Q0 = 0x20,
188 MT_TX_MCU_PORT_RX_Q1,
189 MT_TX_MCU_PORT_RX_Q2,
190 MT_TX_MCU_PORT_RX_Q3,
191 MT_TX_MCU_PORT_RX_FWDL = 0x3e
192};
193
194enum tx_mgnt_type {
195 MT_TX_NORMAL,
196 MT_TX_TIMING,
197 MT_TX_ADDBA,
198};
199
200enum tx_frag_idx {
201 MT_TX_FRAG_NONE,
202 MT_TX_FRAG_FIRST,
203 MT_TX_FRAG_MID,
204 MT_TX_FRAG_LAST
205};
206
207#define MT_CT_INFO_APPLY_TXD BIT(0)
208#define MT_CT_INFO_COPY_HOST_TXD_ALL BIT(1)
209#define MT_CT_INFO_MGMT_FRAME BIT(2)
210#define MT_CT_INFO_NONE_CIPHER_FRAME BIT(3)
211#define MT_CT_INFO_HSR2_TX BIT(4)
212#define MT_CT_INFO_FROM_HOST BIT(7)
213
214#define MT_TXD_SIZE (8 * 4)
215
216#define MT_TXD0_Q_IDX GENMASK(31, 25)
217#define MT_TXD0_PKT_FMT GENMASK(24, 23)
218#define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)
219#define MT_TXD0_TX_BYTES GENMASK(15, 0)
220
221#define MT_TXD1_FIXED_RATE BIT(31)
222#define MT_TXD1_OWN_MAC GENMASK(30, 25)
223#define MT_TXD1_TID GENMASK(24, 21)
224#define MT_TXD1_BIP BIT(24)
225#define MT_TXD1_ETH_802_3 BIT(20)
226#define MT_TXD1_HDR_INFO GENMASK(20, 16)
227#define MT_TXD1_HDR_FORMAT GENMASK(15, 14)
228#define MT_TXD1_TGID GENMASK(13, 12)
229#define MT_TXD1_WLAN_IDX GENMASK(11, 0)
230
231#define MT_TXD2_POWER_OFFSET GENMASK(31, 26)
232#define MT_TXD2_MAX_TX_TIME GENMASK(25, 16)
233#define MT_TXD2_FRAG GENMASK(15, 14)
234#define MT_TXD2_HTC_VLD BIT(13)
235#define MT_TXD2_DURATION BIT(12)
236#define MT_TXD2_HDR_PAD GENMASK(11, 10)
237#define MT_TXD2_RTS BIT(9)
238#define MT_TXD2_OWN_MAC_MAP BIT(8)
239#define MT_TXD2_BF_TYPE GENMASK(6, 7)
240#define MT_TXD2_FRAME_TYPE GENMASK(5, 4)
241#define MT_TXD2_SUB_TYPE GENMASK(3, 0)
242
243#define MT_TXD3_SN_VALID BIT(31)
244#define MT_TXD3_PN_VALID BIT(30)
245#define MT_TXD3_SW_POWER_MGMT BIT(29)
246#define MT_TXD3_BA_DISABLE BIT(28)
247#define MT_TXD3_SEQ GENMASK(27, 16)
248#define MT_TXD3_REM_TX_COUNT GENMASK(15, 11)
249#define MT_TXD3_TX_COUNT GENMASK(10, 6)
250#define MT_TXD3_HW_AMSDU BIT(5)
251#define MT_TXD3_BCM BIT(4)
252#define MT_TXD3_EEOSP BIT(3)
253#define MT_TXD3_EMRD BIT(2)
254#define MT_TXD3_PROTECT_FRAME BIT(1)
255#define MT_TXD3_NO_ACK BIT(0)
256
257#define MT_TXD4_PN_LOW GENMASK(31, 0)
258
259#define MT_TXD5_PN_HIGH GENMASK(31, 16)
260#define MT_TXD5_FL BIT(15)
261#define MT_TXD5_BYPASS_TBB BIT(14)
262#define MT_TXD5_BYPASS_RBB BIT(13)
263#define MT_TXD5_BSS_COLOR_ZERO BIT(12)
264#define MT_TXD5_TX_STATUS_HOST BIT(10)
265#define MT_TXD5_TX_STATUS_MCU BIT(9)
266#define MT_TXD5_TX_STATUS_FMT BIT(8)
267#define MT_TXD5_PID GENMASK(7, 0)
268
269#define MT_TXD6_TX_SRC GENMASK(31, 30)
270#define MT_TXD6_VTA BIT(28)
271#define MT_TXD6_FIXED_BW BIT(25)
272#define MT_TXD6_BW GENMASK(24, 22)
273#define MT_TXD6_TX_RATE GENMASK(21, 16)
274#define MT_TXD6_TIMESTAMP_OFS_EN BIT(15)
275#define MT_TXD6_TIMESTAMP_OFS_IDX GENMASK(14, 10)
276#define MT_TXD6_MSDU_CNT GENMASK(9, 4)
277#define MT_TXD6_MSDU_CNT_V2 GENMASK(15, 10)
278#define MT_TXD6_DIS_MAT BIT(3)
279#define MT_TXD6_DAS BIT(2)
280#define MT_TXD6_AMSDU_CAP BIT(1)
281
282#define MT_TXD7_TXD_LEN GENMASK(31, 30)
283#define MT_TXD7_IP_SUM BIT(29)
284#define MT_TXD7_DROP_BY_SDO BIT(28)
285#define MT_TXD7_MAC_TXD BIT(27)
286#define MT_TXD7_CTXD BIT(26)
287#define MT_TXD7_CTXD_CNT GENMASK(25, 22)
288#define MT_TXD7_UDP_TCP_SUM BIT(15)
289#define MT_TXD7_TX_TIME GENMASK(9, 0)
290
291#define MT_TXD9_WLAN_IDX GENMASK(23, 8)
292
293#define MT_TXP_BUF_LEN GENMASK(11, 0)
294#define MT_TXP_DMA_ADDR_H GENMASK(15, 12)
295
296#define MT_TX_RATE_STBC BIT(14)
297#define MT_TX_RATE_NSS GENMASK(13, 10)
298#define MT_TX_RATE_MODE GENMASK(9, 6)
299#define MT_TX_RATE_SU_EXT_TONE BIT(5)
300#define MT_TX_RATE_DCM BIT(4)
301/* VHT/HE only use bits 0-3 */
302#define MT_TX_RATE_IDX GENMASK(5, 0)
303
304#define MT_TXFREE0_PKT_TYPE GENMASK(31, 27)
305#define MT_TXFREE0_MSDU_CNT GENMASK(25, 16)
306#define MT_TXFREE0_RX_BYTE GENMASK(15, 0)
307
308#define MT_TXFREE1_VER GENMASK(19, 16)
309
310#define MT_TXFREE_INFO_PAIR BIT(31)
311#define MT_TXFREE_INFO_HEADER BIT(30)
312#define MT_TXFREE_INFO_WLAN_ID GENMASK(23, 12)
313#define MT_TXFREE_INFO_MSDU_ID GENMASK(14, 0)
314#define MT_TXFREE_INFO_COUNT GENMASK(27, 24)
315#define MT_TXFREE_INFO_STAT GENMASK(29, 28)
316
317#define MT_TXS0_BW GENMASK(31, 29)
318#define MT_TXS0_TID GENMASK(28, 26)
319#define MT_TXS0_AMPDU BIT(25)
320#define MT_TXS0_TXS_FORMAT GENMASK(24, 23)
321#define MT_TXS0_BA_ERROR BIT(22)
322#define MT_TXS0_PS_FLAG BIT(21)
323#define MT_TXS0_TXOP_TIMEOUT BIT(20)
324#define MT_TXS0_BIP_ERROR BIT(19)
325
326#define MT_TXS0_QUEUE_TIMEOUT BIT(18)
327#define MT_TXS0_RTS_TIMEOUT BIT(17)
328#define MT_TXS0_ACK_TIMEOUT BIT(16)
329#define MT_TXS0_ACK_ERROR_MASK GENMASK(18, 16)
330
331#define MT_TXS0_TX_STATUS_HOST BIT(15)
332#define MT_TXS0_TX_STATUS_MCU BIT(14)
333#define MT_TXS0_TX_RATE GENMASK(13, 0)
334
335#define MT_TXS1_SEQNO GENMASK(31, 20)
336#define MT_TXS1_RESP_RATE GENMASK(19, 16)
337#define MT_TXS1_RXV_SEQNO GENMASK(15, 8)
338#define MT_TXS1_TX_POWER_DBM GENMASK(7, 0)
339
340#define MT_TXS2_BF_STATUS GENMASK(31, 30)
341#define MT_TXS2_BAND GENMASK(29, 28)
342#define MT_TXS2_WCID GENMASK(27, 16)
343#define MT_TXS2_TX_DELAY GENMASK(15, 0)
344
345#define MT_TXS3_PID GENMASK(31, 24)
346#define MT_TXS3_RATE_STBC BIT(7)
347#define MT_TXS3_FIXED_RATE BIT(6)
348#define MT_TXS3_SRC GENMASK(5, 4)
349#define MT_TXS3_SHARED_ANTENNA BIT(3)
350#define MT_TXS3_LAST_TX_RATE GENMASK(2, 0)
351
352#define MT_TXS4_TIMESTAMP GENMASK(31, 0)
353
354/* MPDU based TXS */
355#define MT_TXS5_F0_FINAL_MPDU BIT(31)
356#define MT_TXS5_F0_QOS BIT(30)
357#define MT_TXS5_F0_TX_COUNT GENMASK(29, 25)
358#define MT_TXS5_F0_FRONT_TIME GENMASK(24, 0)
359#define MT_TXS5_F1_MPDU_TX_COUNT GENMASK(31, 24)
360#define MT_TXS5_F1_MPDU_TX_BYTES GENMASK(23, 0)
361
362#define MT_TXS6_F0_NOISE_3 GENMASK(31, 24)
363#define MT_TXS6_F0_NOISE_2 GENMASK(23, 16)
364#define MT_TXS6_F0_NOISE_1 GENMASK(15, 8)
365#define MT_TXS6_F0_NOISE_0 GENMASK(7, 0)
366#define MT_TXS6_F1_MPDU_FAIL_COUNT GENMASK(31, 24)
367#define MT_TXS6_F1_MPDU_FAIL_BYTES GENMASK(23, 0)
368
369#define MT_TXS7_F0_RCPI_3 GENMASK(31, 24)
370#define MT_TXS7_F0_RCPI_2 GENMASK(23, 16)
371#define MT_TXS7_F0_RCPI_1 GENMASK(15, 8)
372#define MT_TXS7_F0_RCPI_0 GENMASK(7, 0)
373#define MT_TXS7_F1_MPDU_RETRY_COUNT GENMASK(31, 24)
374#define MT_TXS7_F1_MPDU_RETRY_BYTES GENMASK(23, 0)
375
376/* PPDU based TXS */
377#define MT_TXS5_MPDU_TX_CNT GENMASK(30, 20)
378#define MT_TXS5_MPDU_TX_BYTE_SCALE BIT(15)
379#define MT_TXS5_MPDU_TX_BYTE GENMASK(14, 0)
380
381#define MT_TXS6_MPDU_FAIL_CNT GENMASK(30, 20)
382#define MT_TXS6_MPDU_FAIL_BYTE_SCALE BIT(15)
383#define MT_TXS6_MPDU_FAIL_BYTE GENMASK(14, 0)
384
385#define MT_TXS7_MPDU_RETRY_CNT GENMASK(30, 20)
386#define MT_TXS7_MPDU_RETRY_BYTE_SCALE BIT(15)
387#define MT_TXS7_MPDU_RETRY_BYTE GENMASK(14, 0)
388
389#endif /* __MT76_CONNAC3_MAC_H */