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1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
2/*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6#include "core.h"
7
8#ifndef ATH12K_HAL_DESC_H
9#define ATH12K_HAL_DESC_H
10
11#define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0)
12
13#define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0)
14#define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(11, 8)
15#define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 12)
16
17struct ath12k_buffer_addr {
18 __le32 info0;
19 __le32 info1;
20} __packed;
21
22/* ath12k_buffer_addr
23 *
24 * buffer_addr_31_0
25 * Address (lower 32 bits) of the MSDU buffer or MSDU_EXTENSION
26 * descriptor or Link descriptor
27 *
28 * buffer_addr_39_32
29 * Address (upper 8 bits) of the MSDU buffer or MSDU_EXTENSION
30 * descriptor or Link descriptor
31 *
32 * return_buffer_manager (RBM)
33 * Consumer: WBM
34 * Producer: SW/FW
35 * Indicates to which buffer manager the buffer or MSDU_EXTENSION
36 * descriptor or link descriptor that is being pointed to shall be
37 * returned after the frame has been processed. It is used by WBM
38 * for routing purposes.
39 *
40 * Values are defined in enum %HAL_RX_BUF_RBM_
41 *
42 * sw_buffer_cookie
43 * Cookie field exclusively used by SW. HW ignores the contents,
44 * accept that it passes the programmed value on to other
45 * descriptors together with the physical address.
46 *
47 * Field can be used by SW to for example associate the buffers
48 * physical address with the virtual address.
49 *
50 * NOTE1:
51 * The three most significant bits can have a special meaning
52 * in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
53 * and field transmit_bw_restriction is set
54 *
55 * In case of NON punctured transmission:
56 * Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
57 * Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
58 * Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
59 * Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
60 * Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
61 * Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
62 * Sw_buffer_cookie[19:18] = 2'b11: reserved
63 *
64 * In case of punctured transmission:
65 * Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
66 * Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
67 * Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
68 * Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
69 * Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
70 * Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
71 * Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
72 * Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
73 * Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
74 * Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
75 * Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
76 * Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
77 * Sw_buffer_cookie[19:18] = 2'b11: reserved
78 *
79 * Note: a punctured transmission is indicated by the presence
80 * of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
81 *
82 * Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS control
83 * field
84 *
85 * Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
86 * indicates MPDUs with a QoS control field.
87 *
88 */
89
90enum hal_tlv_tag {
91 HAL_MACTX_CBF_START = 0 /* 0x0 */,
92 HAL_PHYRX_DATA = 1 /* 0x1 */,
93 HAL_PHYRX_CBF_DATA_RESP = 2 /* 0x2 */,
94 HAL_PHYRX_ABORT_REQUEST = 3 /* 0x3 */,
95 HAL_PHYRX_USER_ABORT_NOTIFICATION = 4 /* 0x4 */,
96 HAL_MACTX_DATA_RESP = 5 /* 0x5 */,
97 HAL_MACTX_CBF_DATA = 6 /* 0x6 */,
98 HAL_MACTX_CBF_DONE = 7 /* 0x7 */,
99 HAL_PHYRX_LMR_DATA_RESP = 8 /* 0x8 */,
100 HAL_RXPCU_TO_UCODE_START = 9 /* 0x9 */,
101 HAL_RXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU = 10 /* 0xa */,
102 HAL_RXPCU_TO_UCODE_FULL_MPDU_DATA = 11 /* 0xb */,
103 HAL_RXPCU_TO_UCODE_FCS_STATUS = 12 /* 0xc */,
104 HAL_RXPCU_TO_UCODE_MPDU_DELIMITER = 13 /* 0xd */,
105 HAL_RXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER = 14 /* 0xe */,
106 HAL_RXPCU_TO_UCODE_MPDU_HEADER_DATA = 15 /* 0xf */,
107 HAL_RXPCU_TO_UCODE_END = 16 /* 0x10 */,
108 HAL_MACRX_CBF_READ_REQUEST = 32 /* 0x20 */,
109 HAL_MACRX_CBF_DATA_REQUEST = 33 /* 0x21 */,
110 HAL_MACRXXPECT_NDP_RECEPTION = 34 /* 0x22 */,
111 HAL_MACRX_FREEZE_CAPTURE_CHANNEL = 35 /* 0x23 */,
112 HAL_MACRX_NDP_TIMEOUT = 36 /* 0x24 */,
113 HAL_MACRX_ABORT_ACK = 37 /* 0x25 */,
114 HAL_MACRX_REQ_IMPLICIT_FB = 38 /* 0x26 */,
115 HAL_MACRX_CHAIN_MASK = 39 /* 0x27 */,
116 HAL_MACRX_NAP_USER = 40 /* 0x28 */,
117 HAL_MACRX_ABORT_REQUEST = 41 /* 0x29 */,
118 HAL_PHYTX_OTHER_TRANSMIT_INFO16 = 42 /* 0x2a */,
119 HAL_PHYTX_ABORT_ACK = 43 /* 0x2b */,
120 HAL_PHYTX_ABORT_REQUEST = 44 /* 0x2c */,
121 HAL_PHYTX_PKT_END = 45 /* 0x2d */,
122 HAL_PHYTX_PPDU_HEADER_INFO_REQUEST = 46 /* 0x2e */,
123 HAL_PHYTX_REQUEST_CTRL_INFO = 47 /* 0x2f */,
124 HAL_PHYTX_DATA_REQUEST = 48 /* 0x30 */,
125 HAL_PHYTX_BF_CV_LOADING_DONE = 49 /* 0x31 */,
126 HAL_PHYTX_NAP_ACK = 50 /* 0x32 */,
127 HAL_PHYTX_NAP_DONE = 51 /* 0x33 */,
128 HAL_PHYTX_OFF_ACK = 52 /* 0x34 */,
129 HAL_PHYTX_ON_ACK = 53 /* 0x35 */,
130 HAL_PHYTX_SYNTH_OFF_ACK = 54 /* 0x36 */,
131 HAL_PHYTX_DEBUG16 = 55 /* 0x37 */,
132 HAL_MACTX_ABORT_REQUEST = 56 /* 0x38 */,
133 HAL_MACTX_ABORT_ACK = 57 /* 0x39 */,
134 HAL_MACTX_PKT_END = 58 /* 0x3a */,
135 HAL_MACTX_PRE_PHY_DESC = 59 /* 0x3b */,
136 HAL_MACTX_BF_PARAMS_COMMON = 60 /* 0x3c */,
137 HAL_MACTX_BF_PARAMS_PER_USER = 61 /* 0x3d */,
138 HAL_MACTX_PREFETCH_CV = 62 /* 0x3e */,
139 HAL_MACTX_USER_DESC_COMMON = 63 /* 0x3f */,
140 HAL_MACTX_USER_DESC_PER_USER = 64 /* 0x40 */,
141 HAL_XAMPLE_USER_TLV_16 = 65 /* 0x41 */,
142 HAL_XAMPLE_TLV_16 = 66 /* 0x42 */,
143 HAL_MACTX_PHY_OFF = 67 /* 0x43 */,
144 HAL_MACTX_PHY_ON = 68 /* 0x44 */,
145 HAL_MACTX_SYNTH_OFF = 69 /* 0x45 */,
146 HAL_MACTXXPECT_CBF_COMMON = 70 /* 0x46 */,
147 HAL_MACTXXPECT_CBF_PER_USER = 71 /* 0x47 */,
148 HAL_MACTX_PHY_DESC = 72 /* 0x48 */,
149 HAL_MACTX_L_SIG_A = 73 /* 0x49 */,
150 HAL_MACTX_L_SIG_B = 74 /* 0x4a */,
151 HAL_MACTX_HT_SIG = 75 /* 0x4b */,
152 HAL_MACTX_VHT_SIG_A = 76 /* 0x4c */,
153 HAL_MACTX_VHT_SIG_B_SU20 = 77 /* 0x4d */,
154 HAL_MACTX_VHT_SIG_B_SU40 = 78 /* 0x4e */,
155 HAL_MACTX_VHT_SIG_B_SU80 = 79 /* 0x4f */,
156 HAL_MACTX_VHT_SIG_B_SU160 = 80 /* 0x50 */,
157 HAL_MACTX_VHT_SIG_B_MU20 = 81 /* 0x51 */,
158 HAL_MACTX_VHT_SIG_B_MU40 = 82 /* 0x52 */,
159 HAL_MACTX_VHT_SIG_B_MU80 = 83 /* 0x53 */,
160 HAL_MACTX_VHT_SIG_B_MU160 = 84 /* 0x54 */,
161 HAL_MACTX_SERVICE = 85 /* 0x55 */,
162 HAL_MACTX_HE_SIG_A_SU = 86 /* 0x56 */,
163 HAL_MACTX_HE_SIG_A_MU_DL = 87 /* 0x57 */,
164 HAL_MACTX_HE_SIG_A_MU_UL = 88 /* 0x58 */,
165 HAL_MACTX_HE_SIG_B1_MU = 89 /* 0x59 */,
166 HAL_MACTX_HE_SIG_B2_MU = 90 /* 0x5a */,
167 HAL_MACTX_HE_SIG_B2_OFDMA = 91 /* 0x5b */,
168 HAL_MACTX_DELETE_CV = 92 /* 0x5c */,
169 HAL_MACTX_MU_UPLINK_COMMON = 93 /* 0x5d */,
170 HAL_MACTX_MU_UPLINK_USER_SETUP = 94 /* 0x5e */,
171 HAL_MACTX_OTHER_TRANSMIT_INFO = 95 /* 0x5f */,
172 HAL_MACTX_PHY_NAP = 96 /* 0x60 */,
173 HAL_MACTX_DEBUG = 97 /* 0x61 */,
174 HAL_PHYRX_ABORT_ACK = 98 /* 0x62 */,
175 HAL_PHYRX_GENERATED_CBF_DETAILS = 99 /* 0x63 */,
176 HAL_PHYRX_RSSI_LEGACY = 100 /* 0x64 */,
177 HAL_PHYRX_RSSI_HT = 101 /* 0x65 */,
178 HAL_PHYRX_USER_INFO = 102 /* 0x66 */,
179 HAL_PHYRX_PKT_END = 103 /* 0x67 */,
180 HAL_PHYRX_DEBUG = 104 /* 0x68 */,
181 HAL_PHYRX_CBF_TRANSFER_DONE = 105 /* 0x69 */,
182 HAL_PHYRX_CBF_TRANSFER_ABORT = 106 /* 0x6a */,
183 HAL_PHYRX_L_SIG_A = 107 /* 0x6b */,
184 HAL_PHYRX_L_SIG_B = 108 /* 0x6c */,
185 HAL_PHYRX_HT_SIG = 109 /* 0x6d */,
186 HAL_PHYRX_VHT_SIG_A = 110 /* 0x6e */,
187 HAL_PHYRX_VHT_SIG_B_SU20 = 111 /* 0x6f */,
188 HAL_PHYRX_VHT_SIG_B_SU40 = 112 /* 0x70 */,
189 HAL_PHYRX_VHT_SIG_B_SU80 = 113 /* 0x71 */,
190 HAL_PHYRX_VHT_SIG_B_SU160 = 114 /* 0x72 */,
191 HAL_PHYRX_VHT_SIG_B_MU20 = 115 /* 0x73 */,
192 HAL_PHYRX_VHT_SIG_B_MU40 = 116 /* 0x74 */,
193 HAL_PHYRX_VHT_SIG_B_MU80 = 117 /* 0x75 */,
194 HAL_PHYRX_VHT_SIG_B_MU160 = 118 /* 0x76 */,
195 HAL_PHYRX_HE_SIG_A_SU = 119 /* 0x77 */,
196 HAL_PHYRX_HE_SIG_A_MU_DL = 120 /* 0x78 */,
197 HAL_PHYRX_HE_SIG_A_MU_UL = 121 /* 0x79 */,
198 HAL_PHYRX_HE_SIG_B1_MU = 122 /* 0x7a */,
199 HAL_PHYRX_HE_SIG_B2_MU = 123 /* 0x7b */,
200 HAL_PHYRX_HE_SIG_B2_OFDMA = 124 /* 0x7c */,
201 HAL_PHYRX_OTHER_RECEIVE_INFO = 125 /* 0x7d */,
202 HAL_PHYRX_COMMON_USER_INFO = 126 /* 0x7e */,
203 HAL_PHYRX_DATA_DONE = 127 /* 0x7f */,
204 HAL_COEX_TX_REQ = 128 /* 0x80 */,
205 HAL_DUMMY = 129 /* 0x81 */,
206 HALXAMPLE_TLV_32_NAME = 130 /* 0x82 */,
207 HAL_MPDU_LIMIT = 131 /* 0x83 */,
208 HAL_NA_LENGTH_END = 132 /* 0x84 */,
209 HAL_OLE_BUF_STATUS = 133 /* 0x85 */,
210 HAL_PCU_PPDU_SETUP_DONE = 134 /* 0x86 */,
211 HAL_PCU_PPDU_SETUP_END = 135 /* 0x87 */,
212 HAL_PCU_PPDU_SETUP_INIT = 136 /* 0x88 */,
213 HAL_PCU_PPDU_SETUP_START = 137 /* 0x89 */,
214 HAL_PDG_FES_SETUP = 138 /* 0x8a */,
215 HAL_PDG_RESPONSE = 139 /* 0x8b */,
216 HAL_PDG_TX_REQ = 140 /* 0x8c */,
217 HAL_SCH_WAIT_INSTR = 141 /* 0x8d */,
218 HAL_TQM_FLOWMPTY_STATUS = 143 /* 0x8f */,
219 HAL_TQM_FLOW_NOTMPTY_STATUS = 144 /* 0x90 */,
220 HAL_TQM_GEN_MPDU_LENGTH_LIST = 145 /* 0x91 */,
221 HAL_TQM_GEN_MPDU_LENGTH_LIST_STATUS = 146 /* 0x92 */,
222 HAL_TQM_GEN_MPDUS = 147 /* 0x93 */,
223 HAL_TQM_GEN_MPDUS_STATUS = 148 /* 0x94 */,
224 HAL_TQM_REMOVE_MPDU = 149 /* 0x95 */,
225 HAL_TQM_REMOVE_MPDU_STATUS = 150 /* 0x96 */,
226 HAL_TQM_REMOVE_MSDU = 151 /* 0x97 */,
227 HAL_TQM_REMOVE_MSDU_STATUS = 152 /* 0x98 */,
228 HAL_TQM_UPDATE_TX_MPDU_COUNT = 153 /* 0x99 */,
229 HAL_TQM_WRITE_CMD = 154 /* 0x9a */,
230 HAL_OFDMA_TRIGGER_DETAILS = 155 /* 0x9b */,
231 HAL_TX_DATA = 156 /* 0x9c */,
232 HAL_TX_FES_SETUP = 157 /* 0x9d */,
233 HAL_RX_PACKET = 158 /* 0x9e */,
234 HALXPECTED_RESPONSE = 159 /* 0x9f */,
235 HAL_TX_MPDU_END = 160 /* 0xa0 */,
236 HAL_TX_MPDU_START = 161 /* 0xa1 */,
237 HAL_TX_MSDU_END = 162 /* 0xa2 */,
238 HAL_TX_MSDU_START = 163 /* 0xa3 */,
239 HAL_TX_SW_MODE_SETUP = 164 /* 0xa4 */,
240 HAL_TXPCU_BUFFER_STATUS = 165 /* 0xa5 */,
241 HAL_TXPCU_USER_BUFFER_STATUS = 166 /* 0xa6 */,
242 HAL_DATA_TO_TIME_CONFIG = 167 /* 0xa7 */,
243 HALXAMPLE_USER_TLV_32 = 168 /* 0xa8 */,
244 HAL_MPDU_INFO = 169 /* 0xa9 */,
245 HAL_PDG_USER_SETUP = 170 /* 0xaa */,
246 HAL_TX_11AH_SETUP = 171 /* 0xab */,
247 HAL_REO_UPDATE_RX_REO_QUEUE_STATUS = 172 /* 0xac */,
248 HAL_TX_PEER_ENTRY = 173 /* 0xad */,
249 HAL_TX_RAW_OR_NATIVE_FRAME_SETUP = 174 /* 0xae */,
250 HALXAMPLE_USER_TLV_44 = 175 /* 0xaf */,
251 HAL_TX_FLUSH = 176 /* 0xb0 */,
252 HAL_TX_FLUSH_REQ = 177 /* 0xb1 */,
253 HAL_TQM_WRITE_CMD_STATUS = 178 /* 0xb2 */,
254 HAL_TQM_GET_MPDU_QUEUE_STATS = 179 /* 0xb3 */,
255 HAL_TQM_GET_MSDU_FLOW_STATS = 180 /* 0xb4 */,
256 HALXAMPLE_USER_CTLV_44 = 181 /* 0xb5 */,
257 HAL_TX_FES_STATUS_START = 182 /* 0xb6 */,
258 HAL_TX_FES_STATUS_USER_PPDU = 183 /* 0xb7 */,
259 HAL_TX_FES_STATUS_USER_RESPONSE = 184 /* 0xb8 */,
260 HAL_TX_FES_STATUS_END = 185 /* 0xb9 */,
261 HAL_RX_TRIG_INFO = 186 /* 0xba */,
262 HAL_RXPCU_TX_SETUP_CLEAR = 187 /* 0xbb */,
263 HAL_RX_FRAME_BITMAP_REQ = 188 /* 0xbc */,
264 HAL_RX_FRAME_BITMAP_ACK = 189 /* 0xbd */,
265 HAL_COEX_RX_STATUS = 190 /* 0xbe */,
266 HAL_RX_START_PARAM = 191 /* 0xbf */,
267 HAL_RX_PPDU_START = 192 /* 0xc0 */,
268 HAL_RX_PPDU_END = 193 /* 0xc1 */,
269 HAL_RX_MPDU_START = 194 /* 0xc2 */,
270 HAL_RX_MPDU_END = 195 /* 0xc3 */,
271 HAL_RX_MSDU_START = 196 /* 0xc4 */,
272 HAL_RX_MSDU_END = 197 /* 0xc5 */,
273 HAL_RX_ATTENTION = 198 /* 0xc6 */,
274 HAL_RECEIVED_RESPONSE_INFO = 199 /* 0xc7 */,
275 HAL_RX_PHY_SLEEP = 200 /* 0xc8 */,
276 HAL_RX_HEADER = 201 /* 0xc9 */,
277 HAL_RX_PEER_ENTRY = 202 /* 0xca */,
278 HAL_RX_FLUSH = 203 /* 0xcb */,
279 HAL_RX_RESPONSE_REQUIRED_INFO = 204 /* 0xcc */,
280 HAL_RX_FRAMELESS_BAR_DETAILS = 205 /* 0xcd */,
281 HAL_TQM_GET_MPDU_QUEUE_STATS_STATUS = 206 /* 0xce */,
282 HAL_TQM_GET_MSDU_FLOW_STATS_STATUS = 207 /* 0xcf */,
283 HAL_TX_CBF_INFO = 208 /* 0xd0 */,
284 HAL_PCU_PPDU_SETUP_USER = 209 /* 0xd1 */,
285 HAL_RX_MPDU_PCU_START = 210 /* 0xd2 */,
286 HAL_RX_PM_INFO = 211 /* 0xd3 */,
287 HAL_RX_USER_PPDU_END = 212 /* 0xd4 */,
288 HAL_RX_PRE_PPDU_START = 213 /* 0xd5 */,
289 HAL_RX_PREAMBLE = 214 /* 0xd6 */,
290 HAL_TX_FES_SETUP_COMPLETE = 215 /* 0xd7 */,
291 HAL_TX_LAST_MPDU_FETCHED = 216 /* 0xd8 */,
292 HAL_TXDMA_STOP_REQUEST = 217 /* 0xd9 */,
293 HAL_RXPCU_SETUP = 218 /* 0xda */,
294 HAL_RXPCU_USER_SETUP = 219 /* 0xdb */,
295 HAL_TX_FES_STATUS_ACK_OR_BA = 220 /* 0xdc */,
296 HAL_TQM_ACKED_MPDU = 221 /* 0xdd */,
297 HAL_COEX_TX_RESP = 222 /* 0xde */,
298 HAL_COEX_TX_STATUS = 223 /* 0xdf */,
299 HAL_MACTX_COEX_PHY_CTRL = 224 /* 0xe0 */,
300 HAL_COEX_STATUS_BROADCAST = 225 /* 0xe1 */,
301 HAL_RESPONSE_START_STATUS = 226 /* 0xe2 */,
302 HAL_RESPONSEND_STATUS = 227 /* 0xe3 */,
303 HAL_CRYPTO_STATUS = 228 /* 0xe4 */,
304 HAL_RECEIVED_TRIGGER_INFO = 229 /* 0xe5 */,
305 HAL_COEX_TX_STOP_CTRL = 230 /* 0xe6 */,
306 HAL_RX_PPDU_ACK_REPORT = 231 /* 0xe7 */,
307 HAL_RX_PPDU_NO_ACK_REPORT = 232 /* 0xe8 */,
308 HAL_SCH_COEX_STATUS = 233 /* 0xe9 */,
309 HAL_SCHEDULER_COMMAND_STATUS = 234 /* 0xea */,
310 HAL_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS = 235 /* 0xeb */,
311 HAL_TX_FES_STATUS_PROT = 236 /* 0xec */,
312 HAL_TX_FES_STATUS_START_PPDU = 237 /* 0xed */,
313 HAL_TX_FES_STATUS_START_PROT = 238 /* 0xee */,
314 HAL_TXPCU_PHYTX_DEBUG32 = 239 /* 0xef */,
315 HAL_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 = 240 /* 0xf0 */,
316 HAL_TX_MPDU_COUNT_TRANSFERND = 241 /* 0xf1 */,
317 HAL_WHO_ANCHOR_OFFSET = 242 /* 0xf2 */,
318 HAL_WHO_ANCHOR_VALUE = 243 /* 0xf3 */,
319 HAL_WHO_CCE_INFO = 244 /* 0xf4 */,
320 HAL_WHO_COMMIT = 245 /* 0xf5 */,
321 HAL_WHO_COMMIT_DONE = 246 /* 0xf6 */,
322 HAL_WHO_FLUSH = 247 /* 0xf7 */,
323 HAL_WHO_L2_LLC = 248 /* 0xf8 */,
324 HAL_WHO_L2_PAYLOAD = 249 /* 0xf9 */,
325 HAL_WHO_L3_CHECKSUM = 250 /* 0xfa */,
326 HAL_WHO_L3_INFO = 251 /* 0xfb */,
327 HAL_WHO_L4_CHECKSUM = 252 /* 0xfc */,
328 HAL_WHO_L4_INFO = 253 /* 0xfd */,
329 HAL_WHO_MSDU = 254 /* 0xfe */,
330 HAL_WHO_MSDU_MISC = 255 /* 0xff */,
331 HAL_WHO_PACKET_DATA = 256 /* 0x100 */,
332 HAL_WHO_PACKET_HDR = 257 /* 0x101 */,
333 HAL_WHO_PPDU_END = 258 /* 0x102 */,
334 HAL_WHO_PPDU_START = 259 /* 0x103 */,
335 HAL_WHO_TSO = 260 /* 0x104 */,
336 HAL_WHO_WMAC_HEADER_PV0 = 261 /* 0x105 */,
337 HAL_WHO_WMAC_HEADER_PV1 = 262 /* 0x106 */,
338 HAL_WHO_WMAC_IV = 263 /* 0x107 */,
339 HAL_MPDU_INFO_END = 264 /* 0x108 */,
340 HAL_MPDU_INFO_BITMAP = 265 /* 0x109 */,
341 HAL_TX_QUEUE_EXTENSION = 266 /* 0x10a */,
342 HAL_SCHEDULER_SELFGEN_RESPONSE_STATUS = 267 /* 0x10b */,
343 HAL_TQM_UPDATE_TX_MPDU_COUNT_STATUS = 268 /* 0x10c */,
344 HAL_TQM_ACKED_MPDU_STATUS = 269 /* 0x10d */,
345 HAL_TQM_ADD_MSDU_STATUS = 270 /* 0x10e */,
346 HAL_TQM_LIST_GEN_DONE = 271 /* 0x10f */,
347 HAL_WHO_TERMINATE = 272 /* 0x110 */,
348 HAL_TX_LAST_MPDU_END = 273 /* 0x111 */,
349 HAL_TX_CV_DATA = 274 /* 0x112 */,
350 HAL_PPDU_TX_END = 275 /* 0x113 */,
351 HAL_PROT_TX_END = 276 /* 0x114 */,
352 HAL_MPDU_INFO_GLOBAL_END = 277 /* 0x115 */,
353 HAL_TQM_SCH_INSTR_GLOBAL_END = 278 /* 0x116 */,
354 HAL_RX_PPDU_END_USER_STATS = 279 /* 0x117 */,
355 HAL_RX_PPDU_END_USER_STATS_EXT = 280 /* 0x118 */,
356 HAL_REO_GET_QUEUE_STATS = 281 /* 0x119 */,
357 HAL_REO_FLUSH_QUEUE = 282 /* 0x11a */,
358 HAL_REO_FLUSH_CACHE = 283 /* 0x11b */,
359 HAL_REO_UNBLOCK_CACHE = 284 /* 0x11c */,
360 HAL_REO_GET_QUEUE_STATS_STATUS = 285 /* 0x11d */,
361 HAL_REO_FLUSH_QUEUE_STATUS = 286 /* 0x11e */,
362 HAL_REO_FLUSH_CACHE_STATUS = 287 /* 0x11f */,
363 HAL_REO_UNBLOCK_CACHE_STATUS = 288 /* 0x120 */,
364 HAL_TQM_FLUSH_CACHE = 289 /* 0x121 */,
365 HAL_TQM_UNBLOCK_CACHE = 290 /* 0x122 */,
366 HAL_TQM_FLUSH_CACHE_STATUS = 291 /* 0x123 */,
367 HAL_TQM_UNBLOCK_CACHE_STATUS = 292 /* 0x124 */,
368 HAL_RX_PPDU_END_STATUS_DONE = 293 /* 0x125 */,
369 HAL_RX_STATUS_BUFFER_DONE = 294 /* 0x126 */,
370 HAL_TX_DATA_SYNC = 297 /* 0x129 */,
371 HAL_PHYRX_CBF_READ_REQUEST_ACK = 298 /* 0x12a */,
372 HAL_TQM_GET_MPDU_HEAD_INFO = 299 /* 0x12b */,
373 HAL_TQM_SYNC_CMD = 300 /* 0x12c */,
374 HAL_TQM_GET_MPDU_HEAD_INFO_STATUS = 301 /* 0x12d */,
375 HAL_TQM_SYNC_CMD_STATUS = 302 /* 0x12e */,
376 HAL_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS = 303 /* 0x12f */,
377 HAL_TQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 304 /* 0x130 */,
378 HAL_REO_FLUSH_TIMEOUT_LIST = 305 /* 0x131 */,
379 HAL_REO_FLUSH_TIMEOUT_LIST_STATUS = 306 /* 0x132 */,
380 HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 307 /* 0x133 */,
381 HAL_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS = 308 /* 0x134 */,
382 HALXAMPLE_USER_TLV_32_NAME = 309 /* 0x135 */,
383 HAL_RX_PPDU_START_USER_INFO = 310 /* 0x136 */,
384 HAL_RX_RING_MASK = 311 /* 0x137 */,
385 HAL_COEX_MAC_NAP = 312 /* 0x138 */,
386 HAL_RXPCU_PPDU_END_INFO = 313 /* 0x139 */,
387 HAL_WHO_MESH_CONTROL = 314 /* 0x13a */,
388 HAL_PDG_SW_MODE_BW_START = 315 /* 0x13b */,
389 HAL_PDG_SW_MODE_BW_END = 316 /* 0x13c */,
390 HAL_PDG_WAIT_FOR_MAC_REQUEST = 317 /* 0x13d */,
391 HAL_PDG_WAIT_FOR_PHY_REQUEST = 318 /* 0x13e */,
392 HAL_SCHEDULER_END = 319 /* 0x13f */,
393 HAL_RX_PPDU_START_DROPPED = 320 /* 0x140 */,
394 HAL_RX_PPDU_END_DROPPED = 321 /* 0x141 */,
395 HAL_RX_PPDU_END_STATUS_DONE_DROPPED = 322 /* 0x142 */,
396 HAL_RX_MPDU_START_DROPPED = 323 /* 0x143 */,
397 HAL_RX_MSDU_START_DROPPED = 324 /* 0x144 */,
398 HAL_RX_MSDU_END_DROPPED = 325 /* 0x145 */,
399 HAL_RX_MPDU_END_DROPPED = 326 /* 0x146 */,
400 HAL_RX_ATTENTION_DROPPED = 327 /* 0x147 */,
401 HAL_TXPCU_USER_SETUP = 328 /* 0x148 */,
402 HAL_RXPCU_USER_SETUP_EXT = 329 /* 0x149 */,
403 HAL_CMD_PART_0_END = 330 /* 0x14a */,
404 HAL_MACTX_SYNTH_ON = 331 /* 0x14b */,
405 HAL_SCH_CRITICAL_TLV_REFERENCE = 332 /* 0x14c */,
406 HAL_TQM_MPDU_GLOBAL_START = 333 /* 0x14d */,
407 HALXAMPLE_TLV_32 = 334 /* 0x14e */,
408 HAL_TQM_UPDATE_TX_MSDU_FLOW = 335 /* 0x14f */,
409 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD = 336 /* 0x150 */,
410 HAL_TQM_UPDATE_TX_MSDU_FLOW_STATUS = 337 /* 0x151 */,
411 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS = 338 /* 0x152 */,
412 HAL_REO_UPDATE_RX_REO_QUEUE = 339 /* 0x153 */,
413 HAL_TQM_MPDU_QUEUEMPTY_STATUS = 340 /* 0x154 */,
414 HAL_TQM_2_SCH_MPDU_AVAILABLE = 341 /* 0x155 */,
415 HAL_PDG_TRIG_RESPONSE = 342 /* 0x156 */,
416 HAL_TRIGGER_RESPONSE_TX_DONE = 343 /* 0x157 */,
417 HAL_ABORT_FROM_PHYRX_DETAILS = 344 /* 0x158 */,
418 HAL_SCH_TQM_CMD_WRAPPER = 345 /* 0x159 */,
419 HAL_MPDUS_AVAILABLE = 346 /* 0x15a */,
420 HAL_RECEIVED_RESPONSE_INFO_PART2 = 347 /* 0x15b */,
421 HAL_PHYRX_TX_START_TIMING = 348 /* 0x15c */,
422 HAL_TXPCU_PREAMBLE_DONE = 349 /* 0x15d */,
423 HAL_NDP_PREAMBLE_DONE = 350 /* 0x15e */,
424 HAL_SCH_TQM_CMD_WRAPPER_RBO_DROP = 351 /* 0x15f */,
425 HAL_SCH_TQM_CMD_WRAPPER_CONT_DROP = 352 /* 0x160 */,
426 HAL_MACTX_CLEAR_PREV_TX_INFO = 353 /* 0x161 */,
427 HAL_TX_PUNCTURE_SETUP = 354 /* 0x162 */,
428 HAL_R2R_STATUS_END = 355 /* 0x163 */,
429 HAL_MACTX_PREFETCH_CV_COMMON = 356 /* 0x164 */,
430 HAL_END_OF_FLUSH_MARKER = 357 /* 0x165 */,
431 HAL_MACTX_MU_UPLINK_COMMON_PUNC = 358 /* 0x166 */,
432 HAL_MACTX_MU_UPLINK_USER_SETUP_PUNC = 359 /* 0x167 */,
433 HAL_RECEIVED_RESPONSE_USER_7_0 = 360 /* 0x168 */,
434 HAL_RECEIVED_RESPONSE_USER_15_8 = 361 /* 0x169 */,
435 HAL_RECEIVED_RESPONSE_USER_23_16 = 362 /* 0x16a */,
436 HAL_RECEIVED_RESPONSE_USER_31_24 = 363 /* 0x16b */,
437 HAL_RECEIVED_RESPONSE_USER_36_32 = 364 /* 0x16c */,
438 HAL_TX_LOOPBACK_SETUP = 365 /* 0x16d */,
439 HAL_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS = 366 /* 0x16e */,
440 HAL_SCH_WAIT_INSTR_TX_PATH = 367 /* 0x16f */,
441 HAL_MACTX_OTHER_TRANSMIT_INFO_TX2TX = 368 /* 0x170 */,
442 HAL_MACTX_OTHER_TRANSMIT_INFOMUPHY_SETUP = 369 /* 0x171 */,
443 HAL_PHYRX_OTHER_RECEIVE_INFOVM_DETAILS = 370 /* 0x172 */,
444 HAL_TX_WUR_DATA = 371 /* 0x173 */,
445 HAL_RX_PPDU_END_START = 372 /* 0x174 */,
446 HAL_RX_PPDU_END_MIDDLE = 373 /* 0x175 */,
447 HAL_RX_PPDU_END_LAST = 374 /* 0x176 */,
448 HAL_MACTX_BACKOFF_BASED_TRANSMISSION = 375 /* 0x177 */,
449 HAL_MACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX = 376 /* 0x178 */,
450 HAL_SRP_INFO = 377 /* 0x179 */,
451 HAL_OBSS_SR_INFO = 378 /* 0x17a */,
452 HAL_SCHEDULER_SW_MSG_STATUS = 379 /* 0x17b */,
453 HAL_HWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT = 380 /* 0x17c */,
454 HAL_RXPCU_SETUP_COMPLETE = 381 /* 0x17d */,
455 HAL_SNOOP_PPDU_START = 382 /* 0x17e */,
456 HAL_SNOOP_MPDU_USR_DBG_INFO = 383 /* 0x17f */,
457 HAL_SNOOP_MSDU_USR_DBG_INFO = 384 /* 0x180 */,
458 HAL_SNOOP_MSDU_USR_DATA = 385 /* 0x181 */,
459 HAL_SNOOP_MPDU_USR_STAT_INFO = 386 /* 0x182 */,
460 HAL_SNOOP_PPDU_END = 387 /* 0x183 */,
461 HAL_SNOOP_SPARE = 388 /* 0x184 */,
462 HAL_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON = 390 /* 0x186 */,
463 HAL_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER = 391 /* 0x187 */,
464 HAL_MACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS = 392 /* 0x188 */,
465 HAL_PHYRX_OTHER_RECEIVE_INFO_108PVM_DETAILS = 393 /* 0x189 */,
466 HAL_SCH_TLV_WRAPPER = 394 /* 0x18a */,
467 HAL_SCHEDULER_STATUS_WRAPPER = 395 /* 0x18b */,
468 HAL_MPDU_INFO_6X = 396 /* 0x18c */,
469 HAL_MACTX_11AZ_USER_DESC_PER_USER = 397 /* 0x18d */,
470 HAL_MACTX_U_SIGHT_SU_MU = 398 /* 0x18e */,
471 HAL_MACTX_U_SIGHT_TB = 399 /* 0x18f */,
472 HAL_PHYRX_U_SIGHT_SU_MU = 403 /* 0x193 */,
473 HAL_PHYRX_U_SIGHT_TB = 404 /* 0x194 */,
474 HAL_MACRX_LMR_READ_REQUEST = 408 /* 0x198 */,
475 HAL_MACRX_LMR_DATA_REQUEST = 409 /* 0x199 */,
476 HAL_PHYRX_LMR_TRANSFER_DONE = 410 /* 0x19a */,
477 HAL_PHYRX_LMR_TRANSFER_ABORT = 411 /* 0x19b */,
478 HAL_PHYRX_LMR_READ_REQUEST_ACK = 412 /* 0x19c */,
479 HAL_MACRX_SECURE_LTF_SEQ_PTR = 413 /* 0x19d */,
480 HAL_PHYRX_USER_INFO_MU_UL = 414 /* 0x19e */,
481 HAL_MPDU_QUEUE_OVERVIEW = 415 /* 0x19f */,
482 HAL_SCHEDULER_NAV_INFO = 416 /* 0x1a0 */,
483 HAL_LMR_PEER_ENTRY = 418 /* 0x1a2 */,
484 HAL_LMR_MPDU_START = 419 /* 0x1a3 */,
485 HAL_LMR_DATA = 420 /* 0x1a4 */,
486 HAL_LMR_MPDU_END = 421 /* 0x1a5 */,
487 HAL_REO_GET_QUEUE_1K_STATS_STATUS = 422 /* 0x1a6 */,
488 HAL_RX_FRAME_1K_BITMAP_ACK = 423 /* 0x1a7 */,
489 HAL_TX_FES_STATUS_1K_BA = 424 /* 0x1a8 */,
490 HAL_TQM_ACKED_1K_MPDU = 425 /* 0x1a9 */,
491 HAL_MACRX_INBSS_OBSS_IND = 426 /* 0x1aa */,
492 HAL_PHYRX_LOCATION = 427 /* 0x1ab */,
493 HAL_MLO_TX_NOTIFICATION_SU = 428 /* 0x1ac */,
494 HAL_MLO_TX_NOTIFICATION_MU = 429 /* 0x1ad */,
495 HAL_MLO_TX_REQ_SU = 430 /* 0x1ae */,
496 HAL_MLO_TX_REQ_MU = 431 /* 0x1af */,
497 HAL_MLO_TX_RESP = 432 /* 0x1b0 */,
498 HAL_MLO_RX_NOTIFICATION = 433 /* 0x1b1 */,
499 HAL_MLO_BKOFF_TRUNC_REQ = 434 /* 0x1b2 */,
500 HAL_MLO_TBTT_NOTIFICATION = 435 /* 0x1b3 */,
501 HAL_MLO_MESSAGE = 436 /* 0x1b4 */,
502 HAL_MLO_TS_SYNC_MSG = 437 /* 0x1b5 */,
503 HAL_MLO_FES_SETUP = 438 /* 0x1b6 */,
504 HAL_MLO_PDG_FES_SETUP_SU = 439 /* 0x1b7 */,
505 HAL_MLO_PDG_FES_SETUP_MU = 440 /* 0x1b8 */,
506 HAL_MPDU_INFO_1K_BITMAP = 441 /* 0x1b9 */,
507 HAL_MON_BUF_ADDR = 442 /* 0x1ba */,
508 HAL_TX_FRAG_STATE = 443 /* 0x1bb */,
509 HAL_MACTXHT_SIG_USR_OFDMA = 446 /* 0x1be */,
510 HAL_PHYRXHT_SIG_CMN_PUNC = 448 /* 0x1c0 */,
511 HAL_PHYRXHT_SIG_CMN_OFDMA = 450 /* 0x1c2 */,
512 HAL_PHYRXHT_SIG_USR_OFDMA = 454 /* 0x1c6 */,
513 HAL_PHYRX_PKT_END_PART1 = 456 /* 0x1c8 */,
514 HAL_MACTXXPECT_NDP_RECEPTION = 457 /* 0x1c9 */,
515 HAL_MACTX_SECURE_LTF_SEQ_PTR = 458 /* 0x1ca */,
516 HAL_MLO_PDG_BKOFF_TRUNC_NOTIFY = 460 /* 0x1cc */,
517 HAL_PHYRX_11AZ_INTEGRITY_DATA = 461 /* 0x1cd */,
518 HAL_PHYTX_LOCATION = 462 /* 0x1ce */,
519 HAL_PHYTX_11AZ_INTEGRITY_DATA = 463 /* 0x1cf */,
520 HAL_MACTXHT_SIG_USR_SU = 466 /* 0x1d2 */,
521 HAL_MACTXHT_SIG_USR_MU_MIMO = 467 /* 0x1d3 */,
522 HAL_PHYRXHT_SIG_USR_SU = 468 /* 0x1d4 */,
523 HAL_PHYRXHT_SIG_USR_MU_MIMO = 469 /* 0x1d5 */,
524 HAL_PHYRX_GENERIC_U_SIG = 470 /* 0x1d6 */,
525 HAL_PHYRX_GENERICHT_SIG = 471 /* 0x1d7 */,
526 HAL_OVERWRITE_RESP_START = 472 /* 0x1d8 */,
527 HAL_OVERWRITE_RESP_PREAMBLE_INFO = 473 /* 0x1d9 */,
528 HAL_OVERWRITE_RESP_FRAME_INFO = 474 /* 0x1da */,
529 HAL_OVERWRITE_RESP_END = 475 /* 0x1db */,
530 HAL_RXPCUARLY_RX_INDICATION = 476 /* 0x1dc */,
531 HAL_MON_DROP = 477 /* 0x1dd */,
532 HAL_MACRX_MU_UPLINK_COMMON_SNIFF = 478 /* 0x1de */,
533 HAL_MACRX_MU_UPLINK_USER_SETUP_SNIFF = 479 /* 0x1df */,
534 HAL_MACRX_MU_UPLINK_USER_SEL_SNIFF = 480 /* 0x1e0 */,
535 HAL_MACRX_MU_UPLINK_FCS_STATUS_SNIFF = 481 /* 0x1e1 */,
536 HAL_MACTX_PREFETCH_CV_DMA = 482 /* 0x1e2 */,
537 HAL_MACTX_PREFETCH_CV_PER_USER = 483 /* 0x1e3 */,
538 HAL_PHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS = 484 /* 0x1e4 */,
539 HAL_MACTX_BF_PARAMS_UPDATE_COMMON = 485 /* 0x1e5 */,
540 HAL_MACTX_BF_PARAMS_UPDATE_PER_USER = 486 /* 0x1e6 */,
541 HAL_RANGING_USER_DETAILS = 487 /* 0x1e7 */,
542 HAL_PHYTX_CV_CORR_STATUS = 488 /* 0x1e8 */,
543 HAL_PHYTX_CV_CORR_COMMON = 489 /* 0x1e9 */,
544 HAL_PHYTX_CV_CORR_USER = 490 /* 0x1ea */,
545 HAL_MACTX_CV_CORR_COMMON = 491 /* 0x1eb */,
546 HAL_MACTX_CV_CORR_MAC_INFO_GROUP = 492 /* 0x1ec */,
547 HAL_BW_PUNCTUREVAL_WRAPPER = 493 /* 0x1ed */,
548 HAL_MACTX_RX_NOTIFICATION_FOR_PHY = 494 /* 0x1ee */,
549 HAL_MACTX_TX_NOTIFICATION_FOR_PHY = 495 /* 0x1ef */,
550 HAL_MACTX_MU_UPLINK_COMMON_PER_BW = 496 /* 0x1f0 */,
551 HAL_MACTX_MU_UPLINK_USER_SETUP_PER_BW = 497 /* 0x1f1 */,
552 HAL_RX_PPDU_END_USER_STATS_EXT2 = 498 /* 0x1f2 */,
553 HAL_FW2SW_MON = 499 /* 0x1f3 */,
554 HAL_WSI_DIRECT_MESSAGE = 500 /* 0x1f4 */,
555 HAL_MACTXMLSR_PRE_SWITCH = 501 /* 0x1f5 */,
556 HAL_MACTXMLSR_SWITCH = 502 /* 0x1f6 */,
557 HAL_MACTXMLSR_SWITCH_BACK = 503 /* 0x1f7 */,
558 HAL_PHYTXMLSR_SWITCH_ACK = 504 /* 0x1f8 */,
559 HAL_PHYTXMLSR_SWITCH_BACK_ACK = 505 /* 0x1f9 */,
560 HAL_SPARE_REUSE_TAG_0 = 506 /* 0x1fa */,
561 HAL_SPARE_REUSE_TAG_1 = 507 /* 0x1fb */,
562 HAL_SPARE_REUSE_TAG_2 = 508 /* 0x1fc */,
563 HAL_SPARE_REUSE_TAG_3 = 509 /* 0x1fd */,
564 /* FIXME: Assign correct value for HAL_TCL_DATA_CMD */
565 HAL_TCL_DATA_CMD = 510,
566 HAL_TLV_BASE = 511 /* 0x1ff */,
567};
568
569#define HAL_TLV_HDR_TAG GENMASK(9, 1)
570#define HAL_TLV_HDR_LEN GENMASK(25, 10)
571#define HAL_TLV_USR_ID GENMASK(31, 26)
572
573#define HAL_TLV_ALIGN 4
574
575struct hal_tlv_hdr {
576 __le32 tl;
577 u8 value[];
578} __packed;
579
580#define HAL_TLV_64_HDR_TAG GENMASK(9, 1)
581#define HAL_TLV_64_HDR_LEN GENMASK(21, 10)
582
583struct hal_tlv_64_hdr {
584 u64 tl;
585 u8 value[];
586} __packed;
587
588#define RX_MPDU_DESC_INFO0_MSDU_COUNT GENMASK(7, 0)
589#define RX_MPDU_DESC_INFO0_FRAG_FLAG BIT(8)
590#define RX_MPDU_DESC_INFO0_MPDU_RETRY BIT(9)
591#define RX_MPDU_DESC_INFO0_AMPDU_FLAG BIT(10)
592#define RX_MPDU_DESC_INFO0_BAR_FRAME BIT(11)
593#define RX_MPDU_DESC_INFO0_VALID_PN BIT(12)
594#define RX_MPDU_DESC_INFO0_RAW_MPDU BIT(13)
595#define RX_MPDU_DESC_INFO0_MORE_FRAG_FLAG BIT(14)
596#define RX_MPDU_DESC_INFO0_SRC_INFO GENMASK(26, 15)
597#define RX_MPDU_DESC_INFO0_MPDU_QOS_CTRL_VALID BIT(27)
598#define RX_MPDU_DESC_INFO0_TID GENMASK(31, 28)
599
600/* TODO revisit after meta data is concluded */
601#define RX_MPDU_DESC_META_DATA_PEER_ID GENMASK(15, 0)
602
603struct rx_mpdu_desc {
604 __le32 info0; /* %RX_MPDU_DESC_INFO */
605 __le32 peer_meta_data;
606} __packed;
607
608/* rx_mpdu_desc
609 * Producer: RXDMA
610 * Consumer: REO/SW/FW
611 *
612 * msdu_count
613 * The number of MSDUs within the MPDU
614 *
615 * fragment_flag
616 * When set, this MPDU is a fragment and REO should forward this
617 * fragment MPDU to the REO destination ring without any reorder
618 * checks, pn checks or bitmap update. This implies that REO is
619 * forwarding the pointer to the MSDU link descriptor.
620 *
621 * mpdu_retry_bit
622 * The retry bit setting from the MPDU header of the received frame
623 *
624 * ampdu_flag
625 * Indicates the MPDU was received as part of an A-MPDU.
626 *
627 * bar_frame
628 * Indicates the received frame is a BAR frame. After processing,
629 * this frame shall be pushed to SW or deleted.
630 *
631 * valid_pn
632 * When not set, REO will not perform a PN sequence number check.
633 *
634 * raw_mpdu
635 * Field only valid when first_msdu_in_mpdu_flag is set. Indicates
636 * the contents in the MSDU buffer contains a 'RAW' MPDU. This
637 * 'RAW' MPDU might be spread out over multiple MSDU buffers.
638 *
639 * more_fragment_flag
640 * The More Fragment bit setting from the MPDU header of the
641 * received frame
642 *
643 * src_info
644 * Source (Virtual) device/interface info associated with this peer.
645 * This field gets passed on by REO to PPE in the EDMA descriptor.
646 *
647 * mpdu_qos_control_valid
648 * When set, the MPDU has a QoS control field
649 *
650 * tid
651 * Field only valid when mpdu_qos_control_valid is set
652 */
653
654enum hal_rx_msdu_desc_reo_dest_ind {
655 HAL_RX_MSDU_DESC_REO_DEST_IND_TCL,
656 HAL_RX_MSDU_DESC_REO_DEST_IND_SW1,
657 HAL_RX_MSDU_DESC_REO_DEST_IND_SW2,
658 HAL_RX_MSDU_DESC_REO_DEST_IND_SW3,
659 HAL_RX_MSDU_DESC_REO_DEST_IND_SW4,
660 HAL_RX_MSDU_DESC_REO_DEST_IND_RELEASE,
661 HAL_RX_MSDU_DESC_REO_DEST_IND_FW,
662 HAL_RX_MSDU_DESC_REO_DEST_IND_SW5,
663 HAL_RX_MSDU_DESC_REO_DEST_IND_SW6,
664 HAL_RX_MSDU_DESC_REO_DEST_IND_SW7,
665 HAL_RX_MSDU_DESC_REO_DEST_IND_SW8,
666};
667
668#define RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU BIT(0)
669#define RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU BIT(1)
670#define RX_MSDU_DESC_INFO0_MSDU_CONTINUATION BIT(2)
671#define RX_MSDU_DESC_INFO0_MSDU_LENGTH GENMASK(16, 3)
672#define RX_MSDU_DESC_INFO0_MSDU_DROP BIT(17)
673#define RX_MSDU_DESC_INFO0_VALID_SA BIT(18)
674#define RX_MSDU_DESC_INFO0_VALID_DA BIT(19)
675#define RX_MSDU_DESC_INFO0_DA_MCBC BIT(20)
676#define RX_MSDU_DESC_INFO0_L3_HDR_PAD_MSB BIT(21)
677#define RX_MSDU_DESC_INFO0_TCP_UDP_CHKSUM_FAIL BIT(22)
678#define RX_MSDU_DESC_INFO0_IP_CHKSUM_FAIL BIT(23)
679#define RX_MSDU_DESC_INFO0_FROM_DS BIT(24)
680#define RX_MSDU_DESC_INFO0_TO_DS BIT(25)
681#define RX_MSDU_DESC_INFO0_INTRA_BSS BIT(26)
682#define RX_MSDU_DESC_INFO0_DST_CHIP_ID GENMASK(28, 27)
683#define RX_MSDU_DESC_INFO0_DECAP_FORMAT GENMASK(30, 29)
684
685#define HAL_RX_MSDU_PKT_LENGTH_GET(val) \
686 (u32_get_bits((val), RX_MSDU_DESC_INFO0_MSDU_LENGTH))
687
688struct rx_msdu_desc {
689 __le32 info0;
690} __packed;
691
692/* rx_msdu_desc
693 *
694 * first_msdu_in_mpdu
695 * Indicates first msdu in mpdu.
696 *
697 * last_msdu_in_mpdu
698 * Indicates last msdu in mpdu. This flag can be true only when
699 * 'Msdu_continuation' set to 0. This implies that when an msdu
700 * is spread out over multiple buffers and thus msdu_continuation
701 * is set, only for the very last buffer of the msdu, can the
702 * 'last_msdu_in_mpdu' be set.
703 *
704 * When both first_msdu_in_mpdu and last_msdu_in_mpdu are set,
705 * the MPDU that this MSDU belongs to only contains a single MSDU.
706 *
707 * msdu_continuation
708 * When set, this MSDU buffer was not able to hold the entire MSDU.
709 * The next buffer will therefore contain additional information
710 * related to this MSDU.
711 *
712 * msdu_length
713 * Field is only valid in combination with the 'first_msdu_in_mpdu'
714 * being set. Full MSDU length in bytes after decapsulation. This
715 * field is still valid for MPDU frames without A-MSDU. It still
716 * represents MSDU length after decapsulation Or in case of RAW
717 * MPDUs, it indicates the length of the entire MPDU (without FCS
718 * field).
719 *
720 * msdu_drop
721 * Indicates that REO shall drop this MSDU and not forward it to
722 * any other ring.
723 *
724 * valid_sa
725 * Indicates OLE found a valid SA entry for this MSDU.
726 *
727 * valid_da
728 * When set, OLE found a valid DA entry for this MSDU.
729 *
730 * da_mcbc
731 * Field Only valid if valid_da is set. Indicates the DA address
732 * is a Multicast or Broadcast address for this MSDU.
733 *
734 * l3_header_padding_msb
735 * Passed on from 'RX_MSDU_END' TLV (only the MSB is reported as
736 * the LSB is always zero). Number of bytes padded to make sure
737 * that the L3 header will always start of a Dword boundary
738 *
739 * tcp_udp_checksum_fail
740 * Passed on from 'RX_ATTENTION' TLV
741 * Indicates that the computed checksum did not match the checksum
742 * in the TCP/UDP header.
743 *
744 * ip_checksum_fail
745 * Passed on from 'RX_ATTENTION' TLV
746 * Indicates that the computed checksum did not match the checksum
747 * in the IP header.
748 *
749 * from_DS
750 * Set if the 'from DS' bit is set in the frame control.
751 *
752 * to_DS
753 * Set if the 'to DS' bit is set in the frame control.
754 *
755 * intra_bss
756 * This packet needs intra-BSS routing by SW as the 'vdev_id'
757 * for the destination is the same as the 'vdev_id' that this
758 * MSDU was got in.
759 *
760 * dest_chip_id
761 * If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY'
762 * to support intra-BSS routing with multi-chip multi-link operation.
763 * This indicates into which chip's TCL the packet should be queued.
764 *
765 * decap_format
766 * Indicates the format after decapsulation:
767 */
768
769#define RX_MSDU_EXT_DESC_INFO0_REO_DEST_IND GENMASK(4, 0)
770#define RX_MSDU_EXT_DESC_INFO0_SERVICE_CODE GENMASK(13, 5)
771#define RX_MSDU_EXT_DESC_INFO0_PRIORITY_VALID BIT(14)
772#define RX_MSDU_EXT_DESC_INFO0_DATA_OFFSET GENMASK(26, 15)
773#define RX_MSDU_EXT_DESC_INFO0_SRC_LINK_ID GENMASK(29, 27)
774
775struct rx_msdu_ext_desc {
776 __le32 info0;
777} __packed;
778
779/* rx_msdu_ext_desc
780 *
781 * reo_destination_indication
782 * The ID of the REO exit ring where the MSDU frame shall push
783 * after (MPDU level) reordering has finished.
784 *
785 * service_code
786 * Opaque service code between PPE and Wi-Fi
787 *
788 * priority_valid
789 *
790 * data_offset
791 * The offset to Rx packet data within the buffer (including
792 * Rx DMA offset programming and L3 header padding inserted
793 * by Rx OLE).
794 *
795 * src_link_id
796 * Set to the link ID of the PMAC that received the frame
797 */
798
799enum hal_reo_dest_ring_buffer_type {
800 HAL_REO_DEST_RING_BUFFER_TYPE_MSDU,
801 HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC,
802};
803
804enum hal_reo_dest_ring_push_reason {
805 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED,
806 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION,
807};
808
809enum hal_reo_dest_ring_error_code {
810 HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO,
811 HAL_REO_DEST_RING_ERROR_CODE_DESC_INVALID,
812 HAL_REO_DEST_RING_ERROR_CODE_AMPDU_IN_NON_BA,
813 HAL_REO_DEST_RING_ERROR_CODE_NON_BA_DUPLICATE,
814 HAL_REO_DEST_RING_ERROR_CODE_BA_DUPLICATE,
815 HAL_REO_DEST_RING_ERROR_CODE_FRAME_2K_JUMP,
816 HAL_REO_DEST_RING_ERROR_CODE_BAR_2K_JUMP,
817 HAL_REO_DEST_RING_ERROR_CODE_FRAME_OOR,
818 HAL_REO_DEST_RING_ERROR_CODE_BAR_OOR,
819 HAL_REO_DEST_RING_ERROR_CODE_NO_BA_SESSION,
820 HAL_REO_DEST_RING_ERROR_CODE_FRAME_SN_EQUALS_SSN,
821 HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED,
822 HAL_REO_DEST_RING_ERROR_CODE_2K_ERR_FLAG_SET,
823 HAL_REO_DEST_RING_ERROR_CODE_PN_ERR_FLAG_SET,
824 HAL_REO_DEST_RING_ERROR_CODE_DESC_BLOCKED,
825 HAL_REO_DEST_RING_ERROR_CODE_MAX,
826};
827
828#define HAL_REO_DEST_RING_INFO0_BUFFER_TYPE BIT(0)
829#define HAL_REO_DEST_RING_INFO0_PUSH_REASON GENMASK(2, 1)
830#define HAL_REO_DEST_RING_INFO0_ERROR_CODE GENMASK(7, 3)
831#define HAL_REO_DEST_RING_INFO0_MSDU_DATA_SIZE GENMASK(11, 8)
832#define HAL_REO_DEST_RING_INFO0_SW_EXCEPTION BIT(12)
833#define HAL_REO_DEST_RING_INFO0_SRC_LINK_ID GENMASK(15, 13)
834#define HAL_REO_DEST_RING_INFO0_SIGNATURE GENMASK(19, 16)
835#define HAL_REO_DEST_RING_INFO0_RING_ID GENMASK(27, 20)
836#define HAL_REO_DEST_RING_INFO0_LOOPING_COUNT GENMASK(31, 28)
837
838struct hal_reo_dest_ring {
839 struct ath12k_buffer_addr buf_addr_info;
840 struct rx_mpdu_desc rx_mpdu_info;
841 struct rx_msdu_desc rx_msdu_info;
842 __le32 buf_va_lo;
843 __le32 buf_va_hi;
844 __le32 info0; /* %HAL_REO_DEST_RING_INFO0_ */
845} __packed;
846
847/* hal_reo_dest_ring
848 *
849 * Producer: RXDMA
850 * Consumer: REO/SW/FW
851 *
852 * buf_addr_info
853 * Details of the physical address of a buffer or MSDU
854 * link descriptor.
855 *
856 * rx_mpdu_info
857 * General information related to the MPDU that is passed
858 * on from REO entrance ring to the REO destination ring.
859 *
860 * rx_msdu_info
861 * General information related to the MSDU that is passed
862 * on from RXDMA all the way to the REO destination ring.
863 *
864 * buf_va_lo
865 * Field only valid if Reo_dest_buffer_type is set to MSDU_buf_address
866 * Lower 32 bits of the 64-bit virtual address corresponding
867 * to Buf_or_link_desc_addr_info
868 *
869 * buf_va_hi
870 * Address (upper 32 bits) of the REO queue descriptor.
871 * Upper 32 bits of the 64-bit virtual address corresponding
872 * to Buf_or_link_desc_addr_info
873 *
874 * buffer_type
875 * Indicates the type of address provided in the buf_addr_info.
876 * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_.
877 *
878 * push_reason
879 * Reason for pushing this frame to this exit ring. Values are
880 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_.
881 *
882 * error_code
883 * Valid only when 'push_reason' is set. All error codes are
884 * defined in enum %HAL_REO_DEST_RING_ERROR_CODE_.
885 *
886 * captured_msdu_data_size
887 * The number of following REO_DESTINATION STRUCTs that have
888 * been replaced with msdu_data extracted from the msdu_buffer
889 * and copied into the ring for easy FW/SW access.
890 *
891 * sw_exception
892 * This field has the same setting as the SW_exception field
893 * in the corresponding REO_entrance_ring descriptor.
894 * When set, the REO entrance descriptor is generated by FW,
895 * and the MPDU was processed in the following way:
896 * - NO re-order function is needed.
897 * - MPDU delinking is determined by the setting of Entrance
898 * ring field: SW_excection_mpdu_delink
899 * - Destination ring selection is based on the setting of
900 * the Entrance ring field SW_exception_destination _ring_valid
901 *
902 * src_link_id
903 * Set to the link ID of the PMAC that received the frame
904 *
905 * signature
906 * Set to value 0x8 when msdu capture mode is enabled for this ring
907 *
908 * ring_id
909 * The buffer pointer ring id.
910 * 0 - Idle ring
911 * 1 - N refers to other rings.
912 *
913 * looping_count
914 * Indicates the number of times the producer of entries into
915 * this ring has looped around the ring.
916 */
917
918#define HAL_REO_TO_PPE_RING_INFO0_DATA_LENGTH GENMASK(15, 0)
919#define HAL_REO_TO_PPE_RING_INFO0_DATA_OFFSET GENMASK(23, 16)
920#define HAL_REO_TO_PPE_RING_INFO0_POOL_ID GENMASK(28, 24)
921#define HAL_REO_TO_PPE_RING_INFO0_PREHEADER BIT(29)
922#define HAL_REO_TO_PPE_RING_INFO0_TSO_EN BIT(30)
923#define HAL_REO_TO_PPE_RING_INFO0_MORE BIT(31)
924
925struct hal_reo_to_ppe_ring {
926 __le32 buffer_addr;
927 __le32 info0; /* %HAL_REO_TO_PPE_RING_INFO0_ */
928} __packed;
929
930/* hal_reo_to_ppe_ring
931 *
932 * Producer: REO
933 * Consumer: PPE
934 *
935 * buf_addr_info
936 * Details of the physical address of a buffer or MSDU
937 * link descriptor.
938 *
939 * data_length
940 * Length of valid data in bytes
941 *
942 * data_offset
943 * Offset to the data from buffer pointer. Can be used to
944 * strip header in the data for tunnel termination etc.
945 *
946 * pool_id
947 * REO has global configuration register for this field.
948 * It may have several free buffer pools, each
949 * RX-Descriptor ring can fetch free buffer from specific
950 * buffer pool; pool id will indicate which pool the buffer
951 * will be released to; POOL_ID Zero returned to SW
952 *
953 * preheader
954 * Disabled: 0 (Default)
955 * Enabled: 1
956 *
957 * tso_en
958 * Disabled: 0 (Default)
959 * Enabled: 1
960 *
961 * more
962 * More Segments followed
963 */
964
965enum hal_reo_entr_rxdma_push_reason {
966 HAL_REO_ENTR_RING_RXDMA_PUSH_REASON_ERR_DETECTED,
967 HAL_REO_ENTR_RING_RXDMA_PUSH_REASON_ROUTING_INSTRUCTION,
968 HAL_REO_ENTR_RING_RXDMA_PUSH_REASON_RX_FLUSH,
969};
970
971enum hal_reo_entr_rxdma_ecode {
972 HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR,
973 HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR,
974 HAL_REO_ENTR_RING_RXDMA_ECODE_FCS_ERR,
975 HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR,
976 HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR,
977 HAL_REO_ENTR_RING_RXDMA_ECODE_UNECRYPTED_ERR,
978 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LEN_ERR,
979 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LIMIT_ERR,
980 HAL_REO_ENTR_RING_RXDMA_ECODE_WIFI_PARSE_ERR,
981 HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_PARSE_ERR,
982 HAL_REO_ENTR_RING_RXDMA_ECODE_SA_TIMEOUT_ERR,
983 HAL_REO_ENTR_RING_RXDMA_ECODE_DA_TIMEOUT_ERR,
984 HAL_REO_ENTR_RING_RXDMA_ECODE_FLOW_TIMEOUT_ERR,
985 HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR,
986 HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_FRAG_ERR,
987 HAL_REO_ENTR_RING_RXDMA_ECODE_MAX,
988};
989
990enum hal_rx_reo_dest_ring {
991 HAL_RX_REO_DEST_RING_TCL,
992 HAL_RX_REO_DEST_RING_SW1,
993 HAL_RX_REO_DEST_RING_SW2,
994 HAL_RX_REO_DEST_RING_SW3,
995 HAL_RX_REO_DEST_RING_SW4,
996 HAL_RX_REO_DEST_RING_RELEASE,
997 HAL_RX_REO_DEST_RING_FW,
998 HAL_RX_REO_DEST_RING_SW5,
999 HAL_RX_REO_DEST_RING_SW6,
1000 HAL_RX_REO_DEST_RING_SW7,
1001 HAL_RX_REO_DEST_RING_SW8,
1002};
1003
1004#define HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
1005#define HAL_REO_ENTR_RING_INFO0_MPDU_BYTE_COUNT GENMASK(21, 8)
1006#define HAL_REO_ENTR_RING_INFO0_DEST_IND GENMASK(26, 22)
1007#define HAL_REO_ENTR_RING_INFO0_FRAMELESS_BAR BIT(27)
1008
1009#define HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON GENMASK(1, 0)
1010#define HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE GENMASK(6, 2)
1011#define HAL_REO_ENTR_RING_INFO1_MPDU_FRAG_NUM GENMASK(10, 7)
1012#define HAL_REO_ENTR_RING_INFO1_SW_EXCEPTION BIT(11)
1013#define HAL_REO_ENTR_RING_INFO1_SW_EXCEPT_MPDU_DELINK BIT(12)
1014#define HAL_REO_ENTR_RING_INFO1_SW_EXCEPTION_RING_VLD BIT(13)
1015#define HAL_REO_ENTR_RING_INFO1_SW_EXCEPTION_RING GENMASK(18, 14)
1016#define HAL_REO_ENTR_RING_INFO1_MPDU_SEQ_NUM GENMASK(30, 19)
1017
1018#define HAL_REO_ENTR_RING_INFO2_PHY_PPDU_ID GENMASK(15, 0)
1019#define HAL_REO_ENTR_RING_INFO2_SRC_LINK_ID GENMASK(18, 16)
1020#define HAL_REO_ENTR_RING_INFO2_RING_ID GENMASK(27, 20)
1021#define HAL_REO_ENTR_RING_INFO2_LOOPING_COUNT GENMASK(31, 28)
1022
1023struct hal_reo_entrance_ring {
1024 struct ath12k_buffer_addr buf_addr_info;
1025 struct rx_mpdu_desc rx_mpdu_info;
1026 __le32 queue_addr_lo;
1027 __le32 info0; /* %HAL_REO_ENTR_RING_INFO0_ */
1028 __le32 info1; /* %HAL_REO_ENTR_RING_INFO1_ */
1029 __le32 info2; /* %HAL_REO_DEST_RING_INFO2_ */
1030
1031} __packed;
1032
1033/* hal_reo_entrance_ring
1034 *
1035 * Producer: RXDMA
1036 * Consumer: REO
1037 *
1038 * buf_addr_info
1039 * Details of the physical address of a buffer or MSDU
1040 * link descriptor.
1041 *
1042 * rx_mpdu_info
1043 * General information related to the MPDU that is passed
1044 * on from REO entrance ring to the REO destination ring.
1045 *
1046 * queue_addr_lo
1047 * Address (lower 32 bits) of the REO queue descriptor.
1048 *
1049 * queue_addr_hi
1050 * Address (upper 8 bits) of the REO queue descriptor.
1051 *
1052 * mpdu_byte_count
1053 * An approximation of the number of bytes received in this MPDU.
1054 * Used to keeps stats on the amount of data flowing
1055 * through a queue.
1056 *
1057 * reo_destination_indication
1058 * The id of the reo exit ring where the msdu frame shall push
1059 * after (MPDU level) reordering has finished. Values are defined
1060 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_.
1061 *
1062 * frameless_bar
1063 * Indicates that this REO entrance ring struct contains BAR info
1064 * from a multi TID BAR frame. The original multi TID BAR frame
1065 * itself contained all the REO info for the first TID, but all
1066 * the subsequent TID info and their linkage to the REO descriptors
1067 * is passed down as 'frameless' BAR info.
1068 *
1069 * The only fields valid in this descriptor when this bit is set
1070 * are queue_addr_lo, queue_addr_hi, mpdu_sequence_number,
1071 * bar_frame and peer_meta_data.
1072 *
1073 * rxdma_push_reason
1074 * Reason for pushing this frame to this exit ring. Values are
1075 * defined in enum %HAL_REO_ENTR_RING_RXDMA_PUSH_REASON_.
1076 *
1077 * rxdma_error_code
1078 * Valid only when 'push_reason' is set. All error codes are
1079 * defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_.
1080 *
1081 * mpdu_fragment_number
1082 * Field only valid when Reo_level_mpdu_frame_info.
1083 * Rx_mpdu_desc_info_details.Fragment_flag is set.
1084 *
1085 * sw_exception
1086 * When not set, REO is performing all its default MPDU processing
1087 * operations,
1088 * When set, this REO entrance descriptor is generated by FW, and
1089 * should be processed as an exception. This implies:
1090 * NO re-order function is needed.
1091 * MPDU delinking is determined by the setting of field
1092 * SW_excection_mpdu_delink
1093 *
1094 * sw_exception_mpdu_delink
1095 * Field only valid when SW_exception is set.
1096 * 1'b0: REO should NOT delink the MPDU, and thus pass this
1097 * MPDU on to the destination ring as is. This implies that
1098 * in the REO_DESTINATION_RING struct field
1099 * Buf_or_link_desc_addr_info should point to an MSDU link
1100 * descriptor
1101 * 1'b1: REO should perform the normal MPDU delink into MSDU operations.
1102 *
1103 * sw_exception_dest_ring
1104 * Field only valid when fields SW_exception and SW
1105 * exception_destination_ring_valid are set. values are defined
1106 * in %HAL_RX_REO_DEST_RING_.
1107 *
1108 * mpdu_seq_number
1109 * The field can have two different meanings based on the setting
1110 * of sub-field Reo level mpdu frame info.
1111 * Rx_mpdu_desc_info_details. BAR_frame
1112 * 'BAR_frame' is NOT set:
1113 * The MPDU sequence number of the received frame.
1114 * 'BAR_frame' is set.
1115 * The MPDU Start sequence number from the BAR frame
1116 *
1117 * phy_ppdu_id
1118 * A PPDU counter value that PHY increments for every PPDU received
1119 *
1120 * src_link_id
1121 * Set to the link ID of the PMAC that received the frame
1122 *
1123 * ring_id
1124 * The buffer pointer ring id.
1125 * 0 - Idle ring
1126 * 1 - N refers to other rings.
1127 *
1128 * looping_count
1129 * Indicates the number of times the producer of entries into
1130 * this ring has looped around the ring.
1131 */
1132
1133#define HAL_REO_CMD_HDR_INFO0_CMD_NUMBER GENMASK(15, 0)
1134#define HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED BIT(16)
1135
1136struct hal_reo_cmd_hdr {
1137 __le32 info0;
1138} __packed;
1139
1140#define HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
1141#define HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS BIT(8)
1142
1143struct hal_reo_get_queue_stats {
1144 struct hal_reo_cmd_hdr cmd;
1145 __le32 queue_addr_lo;
1146 __le32 info0;
1147 __le32 rsvd0[6];
1148 __le32 tlv64_pad;
1149} __packed;
1150
1151/* hal_reo_get_queue_stats
1152 * Producer: SW
1153 * Consumer: REO
1154 *
1155 * cmd
1156 * Details for command execution tracking purposes.
1157 *
1158 * queue_addr_lo
1159 * Address (lower 32 bits) of the REO queue descriptor.
1160 *
1161 * queue_addr_hi
1162 * Address (upper 8 bits) of the REO queue descriptor.
1163 *
1164 * clear_stats
1165 * Clear stats settings. When set, Clear the stats after
1166 * generating the status.
1167 *
1168 * Following stats will be cleared.
1169 * Timeout_count
1170 * Forward_due_to_bar_count
1171 * Duplicate_count
1172 * Frames_in_order_count
1173 * BAR_received_count
1174 * MPDU_Frames_processed_count
1175 * MSDU_Frames_processed_count
1176 * Total_processed_byte_count
1177 * Late_receive_MPDU_count
1178 * window_jump_2k
1179 * Hole_count
1180 */
1181
1182#define HAL_REO_FLUSH_QUEUE_INFO0_DESC_ADDR_HI GENMASK(7, 0)
1183#define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_DESC_ADDR BIT(8)
1184#define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_RESRC_IDX GENMASK(10, 9)
1185
1186struct hal_reo_flush_queue {
1187 struct hal_reo_cmd_hdr cmd;
1188 __le32 desc_addr_lo;
1189 __le32 info0;
1190 __le32 rsvd0[6];
1191} __packed;
1192
1193#define HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI GENMASK(7, 0)
1194#define HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS BIT(8)
1195#define HAL_REO_FLUSH_CACHE_INFO0_RELEASE_BLOCK_IDX BIT(9)
1196#define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX GENMASK(11, 10)
1197#define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE BIT(12)
1198#define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE BIT(13)
1199#define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL BIT(14)
1200
1201struct hal_reo_flush_cache {
1202 struct hal_reo_cmd_hdr cmd;
1203 __le32 cache_addr_lo;
1204 __le32 info0;
1205 __le32 rsvd0[6];
1206} __packed;
1207
1208#define HAL_TCL_DATA_CMD_INFO0_CMD_TYPE BIT(0)
1209#define HAL_TCL_DATA_CMD_INFO0_DESC_TYPE BIT(1)
1210#define HAL_TCL_DATA_CMD_INFO0_BANK_ID GENMASK(7, 2)
1211#define HAL_TCL_DATA_CMD_INFO0_TX_NOTIFY_FRAME GENMASK(10, 8)
1212#define HAL_TCL_DATA_CMD_INFO0_HDR_LEN_READ_SEL BIT(11)
1213#define HAL_TCL_DATA_CMD_INFO0_BUF_TIMESTAMP GENMASK(30, 12)
1214#define HAL_TCL_DATA_CMD_INFO0_BUF_TIMESTAMP_VLD BIT(31)
1215
1216#define HAL_TCL_DATA_CMD_INFO1_CMD_NUM GENMASK(31, 16)
1217
1218#define HAL_TCL_DATA_CMD_INFO2_DATA_LEN GENMASK(15, 0)
1219#define HAL_TCL_DATA_CMD_INFO2_IP4_CKSUM_EN BIT(16)
1220#define HAL_TCL_DATA_CMD_INFO2_UDP4_CKSUM_EN BIT(17)
1221#define HAL_TCL_DATA_CMD_INFO2_UDP6_CKSUM_EN BIT(18)
1222#define HAL_TCL_DATA_CMD_INFO2_TCP4_CKSUM_EN BIT(19)
1223#define HAL_TCL_DATA_CMD_INFO2_TCP6_CKSUM_EN BIT(20)
1224#define HAL_TCL_DATA_CMD_INFO2_TO_FW BIT(21)
1225#define HAL_TCL_DATA_CMD_INFO2_PKT_OFFSET GENMASK(31, 23)
1226
1227#define HAL_TCL_DATA_CMD_INFO3_TID_OVERWRITE BIT(0)
1228#define HAL_TCL_DATA_CMD_INFO3_FLOW_OVERRIDE_EN BIT(1)
1229#define HAL_TCL_DATA_CMD_INFO3_CLASSIFY_INFO_SEL GENMASK(3, 2)
1230#define HAL_TCL_DATA_CMD_INFO3_TID GENMASK(7, 4)
1231#define HAL_TCL_DATA_CMD_INFO3_FLOW_OVERRIDE BIT(8)
1232#define HAL_TCL_DATA_CMD_INFO3_PMAC_ID GENMASK(10, 9)
1233#define HAL_TCL_DATA_CMD_INFO3_MSDU_COLOR GENMASK(12, 11)
1234#define HAL_TCL_DATA_CMD_INFO3_VDEV_ID GENMASK(31, 24)
1235
1236#define HAL_TCL_DATA_CMD_INFO4_SEARCH_INDEX GENMASK(19, 0)
1237#define HAL_TCL_DATA_CMD_INFO4_CACHE_SET_NUM GENMASK(23, 20)
1238#define HAL_TCL_DATA_CMD_INFO4_IDX_LOOKUP_OVERRIDE BIT(24)
1239
1240#define HAL_TCL_DATA_CMD_INFO5_RING_ID GENMASK(27, 20)
1241#define HAL_TCL_DATA_CMD_INFO5_LOOPING_COUNT GENMASK(31, 28)
1242
1243enum hal_encrypt_type {
1244 HAL_ENCRYPT_TYPE_WEP_40,
1245 HAL_ENCRYPT_TYPE_WEP_104,
1246 HAL_ENCRYPT_TYPE_TKIP_NO_MIC,
1247 HAL_ENCRYPT_TYPE_WEP_128,
1248 HAL_ENCRYPT_TYPE_TKIP_MIC,
1249 HAL_ENCRYPT_TYPE_WAPI,
1250 HAL_ENCRYPT_TYPE_CCMP_128,
1251 HAL_ENCRYPT_TYPE_OPEN,
1252 HAL_ENCRYPT_TYPE_CCMP_256,
1253 HAL_ENCRYPT_TYPE_GCMP_128,
1254 HAL_ENCRYPT_TYPE_AES_GCMP_256,
1255 HAL_ENCRYPT_TYPE_WAPI_GCM_SM4,
1256};
1257
1258enum hal_tcl_encap_type {
1259 HAL_TCL_ENCAP_TYPE_RAW,
1260 HAL_TCL_ENCAP_TYPE_NATIVE_WIFI,
1261 HAL_TCL_ENCAP_TYPE_ETHERNET,
1262 HAL_TCL_ENCAP_TYPE_802_3 = 3,
1263};
1264
1265enum hal_tcl_desc_type {
1266 HAL_TCL_DESC_TYPE_BUFFER,
1267 HAL_TCL_DESC_TYPE_EXT_DESC,
1268};
1269
1270enum hal_wbm_htt_tx_comp_status {
1271 HAL_WBM_REL_HTT_TX_COMP_STATUS_OK,
1272 HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP,
1273 HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL,
1274 HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ,
1275 HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT,
1276 HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY,
1277 HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX,
1278};
1279
1280struct hal_tcl_data_cmd {
1281 struct ath12k_buffer_addr buf_addr_info;
1282 __le32 info0;
1283 __le32 info1;
1284 __le32 info2;
1285 __le32 info3;
1286 __le32 info4;
1287 __le32 info5;
1288} __packed;
1289
1290/* hal_tcl_data_cmd
1291 *
1292 * buf_addr_info
1293 * Details of the physical address of a buffer or MSDU
1294 * link descriptor.
1295 *
1296 * tcl_cmd_type
1297 * used to select the type of TCL Command descriptor
1298 *
1299 * desc_type
1300 * Indicates the type of address provided in the buf_addr_info.
1301 * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_.
1302 *
1303 * bank_id
1304 * used to select one of the TCL register banks for fields removed
1305 * from 'TCL_DATA_CMD' that do not change often within one virtual
1306 * device or a set of virtual devices:
1307 *
1308 * tx_notify_frame
1309 * TCL copies this value to 'TQM_ENTRANCE_RING' field FW_tx_notify_frame.
1310 *
1311 * hdr_length_read_sel
1312 * used to select the per 'encap_type' register set for MSDU header
1313 * read length
1314 *
1315 * buffer_timestamp
1316 * buffer_timestamp_valid
1317 * Frame system entrance timestamp. It shall be filled by first
1318 * module (SW, TCL or TQM) that sees the frames first.
1319 *
1320 * cmd_num
1321 * This number can be used to match against status.
1322 *
1323 * data_length
1324 * MSDU length in case of direct descriptor. Length of link
1325 * extension descriptor in case of Link extension descriptor.
1326 *
1327 * *_checksum_en
1328 * Enable checksum replacement for ipv4, udp_over_ipv4, ipv6,
1329 * udp_over_ipv6, tcp_over_ipv4 and tcp_over_ipv6.
1330 *
1331 * to_fw
1332 * Forward packet to FW along with classification result. The
1333 * packet will not be forward to TQM when this bit is set.
1334 * 1'b0: Use classification result to forward the packet.
1335 * 1'b1: Override classification result & forward packet only to fw
1336 *
1337 * packet_offset
1338 * Packet offset from Metadata in case of direct buffer descriptor.
1339 *
1340 * hlos_tid_overwrite
1341 *
1342 * When set, TCL shall ignore the IP DSCP and VLAN PCP
1343 * fields and use HLOS_TID as the final TID. Otherwise TCL
1344 * shall consider the DSCP and PCP fields as well as HLOS_TID
1345 * and choose a final TID based on the configured priority
1346 *
1347 * flow_override_enable
1348 * TCL uses this to select the flow pointer from the peer table,
1349 * which can be overridden by SW for pre-encrypted raw WiFi packets
1350 * that cannot be parsed for UDP or for other MLO
1351 * 0 - FP_PARSE_IP: Use the flow-pointer based on parsing the IPv4
1352 * or IPv6 header.
1353 * 1 - FP_USE_OVERRIDE: Use the who_classify_info_sel and
1354 * flow_override fields to select the flow-pointer
1355 *
1356 * who_classify_info_sel
1357 * Field only valid when flow_override_enable is set to FP_USE_OVERRIDE.
1358 * This field is used to select one of the 'WHO_CLASSIFY_INFO's in the
1359 * peer table in case more than 2 flows are mapped to a single TID.
1360 * 0: To choose Flow 0 and 1 of any TID use this value.
1361 * 1: To choose Flow 2 and 3 of any TID use this value.
1362 * 2: To choose Flow 4 and 5 of any TID use this value.
1363 * 3: To choose Flow 6 and 7 of any TID use this value.
1364 *
1365 * If who_classify_info sel is not in sync with the num_tx_classify_info
1366 * field from address search, then TCL will set 'who_classify_info_sel'
1367 * to 0 use flows 0 and 1.
1368 *
1369 * hlos_tid
1370 * HLOS MSDU priority
1371 * Field is used when HLOS_TID_overwrite is set.
1372 *
1373 * flow_override
1374 * Field only valid when flow_override_enable is set to FP_USE_OVERRIDE
1375 * TCL uses this to select the flow pointer from the peer table,
1376 * which can be overridden by SW for pre-encrypted raw WiFi packets
1377 * that cannot be parsed for UDP or for other MLO
1378 * 0 - FP_USE_NON_UDP: Use the non-UDP flow pointer (flow 0)
1379 * 1 - FP_USE_UDP: Use the UDP flow pointer (flow 1)
1380 *
1381 * pmac_id
1382 * TCL uses this PMAC_ID in address search, i.e, while
1383 * finding matching entry for the packet in AST corresponding
1384 * to given PMAC_ID
1385 *
1386 * If PMAC ID is all 1s (=> value 3), it indicates wildcard
1387 * match for any PMAC
1388 *
1389 * vdev_id
1390 * Virtual device ID to check against the address search entry to
1391 * avoid security issues from transmitting packets from an incorrect
1392 * virtual device
1393 *
1394 * search_index
1395 * The index that will be used for index based address or
1396 * flow search. The field is valid when 'search_type' is 1 or 2.
1397 *
1398 * cache_set_num
1399 *
1400 * Cache set number that should be used to cache the index
1401 * based search results, for address and flow search. This
1402 * value should be equal to LSB four bits of the hash value of
1403 * match data, in case of search index points to an entry which
1404 * may be used in content based search also. The value can be
1405 * anything when the entry pointed by search index will not be
1406 * used for content based search.
1407 *
1408 * index_loop_override
1409 * When set, address search and packet routing is forced to use
1410 * 'search_index' instead of following the register configuration
1411 * selected by Bank_id.
1412 *
1413 * ring_id
1414 * The buffer pointer ring ID.
1415 * 0 refers to the IDLE ring
1416 * 1 - N refers to other rings
1417 *
1418 * looping_count
1419 *
1420 * A count value that indicates the number of times the
1421 * producer of entries into the Ring has looped around the
1422 * ring.
1423 *
1424 * At initialization time, this value is set to 0. On the
1425 * first loop, this value is set to 1. After the max value is
1426 * reached allowed by the number of bits for this field, the
1427 * count value continues with 0 again.
1428 *
1429 * In case SW is the consumer of the ring entries, it can
1430 * use this field to figure out up to where the producer of
1431 * entries has created new entries. This eliminates the need to
1432 * check where the head pointer' of the ring is located once
1433 * the SW starts processing an interrupt indicating that new
1434 * entries have been put into this ring...
1435 *
1436 * Also note that SW if it wants only needs to look at the
1437 * LSB bit of this count value.
1438 */
1439
1440#define HAL_TCL_DESC_LEN sizeof(struct hal_tcl_data_cmd)
1441
1442#define HAL_TX_MSDU_EXT_INFO0_BUF_PTR_LO GENMASK(31, 0)
1443
1444#define HAL_TX_MSDU_EXT_INFO1_BUF_PTR_HI GENMASK(7, 0)
1445#define HAL_TX_MSDU_EXT_INFO1_EXTN_OVERRIDE BIT(8)
1446#define HAL_TX_MSDU_EXT_INFO1_ENCAP_TYPE GENMASK(10, 9)
1447#define HAL_TX_MSDU_EXT_INFO1_ENCRYPT_TYPE GENMASK(14, 11)
1448#define HAL_TX_MSDU_EXT_INFO1_BUF_LEN GENMASK(31, 16)
1449
1450struct hal_tx_msdu_ext_desc {
1451 __le32 rsvd0[6];
1452 __le32 info0;
1453 __le32 info1;
1454 __le32 rsvd1[10];
1455};
1456
1457struct hal_tcl_gse_cmd {
1458 __le32 ctrl_buf_addr_lo;
1459 __le32 info0;
1460 __le32 meta_data[2];
1461 __le32 rsvd0[2];
1462 __le32 info1;
1463} __packed;
1464
1465/* hal_tcl_gse_cmd
1466 *
1467 * ctrl_buf_addr_lo, ctrl_buf_addr_hi
1468 * Address of a control buffer containing additional info needed
1469 * for this command execution.
1470 *
1471 * meta_data
1472 * Meta data to be returned in the status descriptor
1473 */
1474
1475enum hal_tcl_cache_op_res {
1476 HAL_TCL_CACHE_OP_RES_DONE,
1477 HAL_TCL_CACHE_OP_RES_NOT_FOUND,
1478 HAL_TCL_CACHE_OP_RES_TIMEOUT,
1479};
1480
1481struct hal_tcl_status_ring {
1482 __le32 info0;
1483 __le32 msdu_byte_count;
1484 __le32 msdu_timestamp;
1485 __le32 meta_data[2];
1486 __le32 info1;
1487 __le32 rsvd0;
1488 __le32 info2;
1489} __packed;
1490
1491/* hal_tcl_status_ring
1492 *
1493 * msdu_cnt
1494 * msdu_byte_count
1495 * MSDU count of Entry and MSDU byte count for entry 1.
1496 *
1497 */
1498
1499#define HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0)
1500#define HAL_CE_SRC_DESC_ADDR_INFO_HASH_EN BIT(8)
1501#define HAL_CE_SRC_DESC_ADDR_INFO_BYTE_SWAP BIT(9)
1502#define HAL_CE_SRC_DESC_ADDR_INFO_DEST_SWAP BIT(10)
1503#define HAL_CE_SRC_DESC_ADDR_INFO_GATHER BIT(11)
1504#define HAL_CE_SRC_DESC_ADDR_INFO_LEN GENMASK(31, 16)
1505
1506#define HAL_CE_SRC_DESC_META_INFO_DATA GENMASK(15, 0)
1507
1508#define HAL_CE_SRC_DESC_FLAGS_RING_ID GENMASK(27, 20)
1509#define HAL_CE_SRC_DESC_FLAGS_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT
1510
1511struct hal_ce_srng_src_desc {
1512 __le32 buffer_addr_low;
1513 __le32 buffer_addr_info; /* %HAL_CE_SRC_DESC_ADDR_INFO_ */
1514 __le32 meta_info; /* %HAL_CE_SRC_DESC_META_INFO_ */
1515 __le32 flags; /* %HAL_CE_SRC_DESC_FLAGS_ */
1516} __packed;
1517
1518/* hal_ce_srng_src_desc
1519 *
1520 * buffer_addr_lo
1521 * LSB 32 bits of the 40 Bit Pointer to the source buffer
1522 *
1523 * buffer_addr_hi
1524 * MSB 8 bits of the 40 Bit Pointer to the source buffer
1525 *
1526 * toeplitz_en
1527 * Enable generation of 32-bit Toeplitz-LFSR hash for
1528 * data transfer. In case of gather field in first source
1529 * ring entry of the gather copy cycle in taken into account.
1530 *
1531 * src_swap
1532 * Treats source memory organization as big-endian. For
1533 * each dword read (4 bytes), the byte 0 is swapped with byte 3
1534 * and byte 1 is swapped with byte 2.
1535 * In case of gather field in first source ring entry of
1536 * the gather copy cycle in taken into account.
1537 *
1538 * dest_swap
1539 * Treats destination memory organization as big-endian.
1540 * For each dword write (4 bytes), the byte 0 is swapped with
1541 * byte 3 and byte 1 is swapped with byte 2.
1542 * In case of gather field in first source ring entry of
1543 * the gather copy cycle in taken into account.
1544 *
1545 * gather
1546 * Enables gather of multiple copy engine source
1547 * descriptors to one destination.
1548 *
1549 * ce_res_0
1550 * Reserved
1551 *
1552 *
1553 * length
1554 * Length of the buffer in units of octets of the current
1555 * descriptor
1556 *
1557 * fw_metadata
1558 * Meta data used by FW.
1559 * In case of gather field in first source ring entry of
1560 * the gather copy cycle in taken into account.
1561 *
1562 * ce_res_1
1563 * Reserved
1564 *
1565 * ce_res_2
1566 * Reserved
1567 *
1568 * ring_id
1569 * The buffer pointer ring ID.
1570 * 0 refers to the IDLE ring
1571 * 1 - N refers to other rings
1572 * Helps with debugging when dumping ring contents.
1573 *
1574 * looping_count
1575 * A count value that indicates the number of times the
1576 * producer of entries into the Ring has looped around the
1577 * ring.
1578 *
1579 * At initialization time, this value is set to 0. On the
1580 * first loop, this value is set to 1. After the max value is
1581 * reached allowed by the number of bits for this field, the
1582 * count value continues with 0 again.
1583 *
1584 * In case SW is the consumer of the ring entries, it can
1585 * use this field to figure out up to where the producer of
1586 * entries has created new entries. This eliminates the need to
1587 * check where the head pointer' of the ring is located once
1588 * the SW starts processing an interrupt indicating that new
1589 * entries have been put into this ring...
1590 *
1591 * Also note that SW if it wants only needs to look at the
1592 * LSB bit of this count value.
1593 */
1594
1595#define HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0)
1596#define HAL_CE_DEST_DESC_ADDR_INFO_RING_ID GENMASK(27, 20)
1597#define HAL_CE_DEST_DESC_ADDR_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT
1598
1599struct hal_ce_srng_dest_desc {
1600 __le32 buffer_addr_low;
1601 __le32 buffer_addr_info; /* %HAL_CE_DEST_DESC_ADDR_INFO_ */
1602} __packed;
1603
1604/* hal_ce_srng_dest_desc
1605 *
1606 * dst_buffer_low
1607 * LSB 32 bits of the 40 Bit Pointer to the Destination
1608 * buffer
1609 *
1610 * dst_buffer_high
1611 * MSB 8 bits of the 40 Bit Pointer to the Destination
1612 * buffer
1613 *
1614 * ce_res_4
1615 * Reserved
1616 *
1617 * ring_id
1618 * The buffer pointer ring ID.
1619 * 0 refers to the IDLE ring
1620 * 1 - N refers to other rings
1621 * Helps with debugging when dumping ring contents.
1622 *
1623 * looping_count
1624 * A count value that indicates the number of times the
1625 * producer of entries into the Ring has looped around the
1626 * ring.
1627 *
1628 * At initialization time, this value is set to 0. On the
1629 * first loop, this value is set to 1. After the max value is
1630 * reached allowed by the number of bits for this field, the
1631 * count value continues with 0 again.
1632 *
1633 * In case SW is the consumer of the ring entries, it can
1634 * use this field to figure out up to where the producer of
1635 * entries has created new entries. This eliminates the need to
1636 * check where the head pointer' of the ring is located once
1637 * the SW starts processing an interrupt indicating that new
1638 * entries have been put into this ring...
1639 *
1640 * Also note that SW if it wants only needs to look at the
1641 * LSB bit of this count value.
1642 */
1643
1644#define HAL_CE_DST_STATUS_DESC_FLAGS_HASH_EN BIT(8)
1645#define HAL_CE_DST_STATUS_DESC_FLAGS_BYTE_SWAP BIT(9)
1646#define HAL_CE_DST_STATUS_DESC_FLAGS_DEST_SWAP BIT(10)
1647#define HAL_CE_DST_STATUS_DESC_FLAGS_GATHER BIT(11)
1648#define HAL_CE_DST_STATUS_DESC_FLAGS_LEN GENMASK(31, 16)
1649
1650#define HAL_CE_DST_STATUS_DESC_META_INFO_DATA GENMASK(15, 0)
1651#define HAL_CE_DST_STATUS_DESC_META_INFO_RING_ID GENMASK(27, 20)
1652#define HAL_CE_DST_STATUS_DESC_META_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT
1653
1654struct hal_ce_srng_dst_status_desc {
1655 __le32 flags; /* %HAL_CE_DST_STATUS_DESC_FLAGS_ */
1656 __le32 toeplitz_hash0;
1657 __le32 toeplitz_hash1;
1658 __le32 meta_info; /* HAL_CE_DST_STATUS_DESC_META_INFO_ */
1659} __packed;
1660
1661/* hal_ce_srng_dst_status_desc
1662 *
1663 * ce_res_5
1664 * Reserved
1665 *
1666 * toeplitz_en
1667 *
1668 * src_swap
1669 * Source memory buffer swapped
1670 *
1671 * dest_swap
1672 * Destination memory buffer swapped
1673 *
1674 * gather
1675 * Gather of multiple copy engine source descriptors to one
1676 * destination enabled
1677 *
1678 * ce_res_6
1679 * Reserved
1680 *
1681 * length
1682 * Sum of all the Lengths of the source descriptor in the
1683 * gather chain
1684 *
1685 * toeplitz_hash_0
1686 * 32 LS bits of 64 bit Toeplitz LFSR hash result
1687 *
1688 * toeplitz_hash_1
1689 * 32 MS bits of 64 bit Toeplitz LFSR hash result
1690 *
1691 * fw_metadata
1692 * Meta data used by FW
1693 * In case of gather field in first source ring entry of
1694 * the gather copy cycle in taken into account.
1695 *
1696 * ce_res_7
1697 * Reserved
1698 *
1699 * ring_id
1700 * The buffer pointer ring ID.
1701 * 0 refers to the IDLE ring
1702 * 1 - N refers to other rings
1703 * Helps with debugging when dumping ring contents.
1704 *
1705 * looping_count
1706 * A count value that indicates the number of times the
1707 * producer of entries into the Ring has looped around the
1708 * ring.
1709 *
1710 * At initialization time, this value is set to 0. On the
1711 * first loop, this value is set to 1. After the max value is
1712 * reached allowed by the number of bits for this field, the
1713 * count value continues with 0 again.
1714 *
1715 * In case SW is the consumer of the ring entries, it can
1716 * use this field to figure out up to where the producer of
1717 * entries has created new entries. This eliminates the need to
1718 * check where the head pointer' of the ring is located once
1719 * the SW starts processing an interrupt indicating that new
1720 * entries have been put into this ring...
1721 *
1722 * Also note that SW if it wants only needs to look at the
1723 * LSB bit of this count value.
1724 */
1725
1726#define HAL_TX_RATE_STATS_INFO0_VALID BIT(0)
1727#define HAL_TX_RATE_STATS_INFO0_BW GENMASK(3, 1)
1728#define HAL_TX_RATE_STATS_INFO0_PKT_TYPE GENMASK(7, 4)
1729#define HAL_TX_RATE_STATS_INFO0_STBC BIT(8)
1730#define HAL_TX_RATE_STATS_INFO0_LDPC BIT(9)
1731#define HAL_TX_RATE_STATS_INFO0_SGI GENMASK(11, 10)
1732#define HAL_TX_RATE_STATS_INFO0_MCS GENMASK(15, 12)
1733#define HAL_TX_RATE_STATS_INFO0_OFDMA_TX BIT(16)
1734#define HAL_TX_RATE_STATS_INFO0_TONES_IN_RU GENMASK(28, 17)
1735
1736enum hal_tx_rate_stats_bw {
1737 HAL_TX_RATE_STATS_BW_20,
1738 HAL_TX_RATE_STATS_BW_40,
1739 HAL_TX_RATE_STATS_BW_80,
1740 HAL_TX_RATE_STATS_BW_160,
1741};
1742
1743enum hal_tx_rate_stats_pkt_type {
1744 HAL_TX_RATE_STATS_PKT_TYPE_11A,
1745 HAL_TX_RATE_STATS_PKT_TYPE_11B,
1746 HAL_TX_RATE_STATS_PKT_TYPE_11N,
1747 HAL_TX_RATE_STATS_PKT_TYPE_11AC,
1748 HAL_TX_RATE_STATS_PKT_TYPE_11AX,
1749 HAL_TX_RATE_STATS_PKT_TYPE_11BA,
1750 HAL_TX_RATE_STATS_PKT_TYPE_11BE,
1751};
1752
1753enum hal_tx_rate_stats_sgi {
1754 HAL_TX_RATE_STATS_SGI_08US,
1755 HAL_TX_RATE_STATS_SGI_04US,
1756 HAL_TX_RATE_STATS_SGI_16US,
1757 HAL_TX_RATE_STATS_SGI_32US,
1758};
1759
1760struct hal_tx_rate_stats {
1761 __le32 info0;
1762 __le32 tsf;
1763} __packed;
1764
1765struct hal_wbm_link_desc {
1766 struct ath12k_buffer_addr buf_addr_info;
1767} __packed;
1768
1769/* hal_wbm_link_desc
1770 *
1771 * Producer: WBM
1772 * Consumer: WBM
1773 *
1774 * buf_addr_info
1775 * Details of the physical address of a buffer or MSDU
1776 * link descriptor.
1777 */
1778
1779enum hal_wbm_rel_src_module {
1780 HAL_WBM_REL_SRC_MODULE_TQM,
1781 HAL_WBM_REL_SRC_MODULE_RXDMA,
1782 HAL_WBM_REL_SRC_MODULE_REO,
1783 HAL_WBM_REL_SRC_MODULE_FW,
1784 HAL_WBM_REL_SRC_MODULE_SW,
1785};
1786
1787enum hal_wbm_rel_desc_type {
1788 HAL_WBM_REL_DESC_TYPE_REL_MSDU,
1789 HAL_WBM_REL_DESC_TYPE_MSDU_LINK,
1790 HAL_WBM_REL_DESC_TYPE_MPDU_LINK,
1791 HAL_WBM_REL_DESC_TYPE_MSDU_EXT,
1792 HAL_WBM_REL_DESC_TYPE_QUEUE_EXT,
1793};
1794
1795/* hal_wbm_rel_desc_type
1796 *
1797 * msdu_buffer
1798 * The address points to an MSDU buffer
1799 *
1800 * msdu_link_descriptor
1801 * The address points to an Tx MSDU link descriptor
1802 *
1803 * mpdu_link_descriptor
1804 * The address points to an MPDU link descriptor
1805 *
1806 * msdu_ext_descriptor
1807 * The address points to an MSDU extension descriptor
1808 *
1809 * queue_ext_descriptor
1810 * The address points to an TQM queue extension descriptor. WBM should
1811 * treat this is the same way as a link descriptor.
1812 */
1813
1814enum hal_wbm_rel_bm_act {
1815 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE,
1816 HAL_WBM_REL_BM_ACT_REL_MSDU,
1817};
1818
1819/* hal_wbm_rel_bm_act
1820 *
1821 * put_in_idle_list
1822 * Put the buffer or descriptor back in the idle list. In case of MSDU or
1823 * MDPU link descriptor, BM does not need to check to release any
1824 * individual MSDU buffers.
1825 *
1826 * release_msdu_list
1827 * This BM action can only be used in combination with desc_type being
1828 * msdu_link_descriptor. Field first_msdu_index points out which MSDU
1829 * pointer in the MSDU link descriptor is the first of an MPDU that is
1830 * released. BM shall release all the MSDU buffers linked to this first
1831 * MSDU buffer pointer. All related MSDU buffer pointer entries shall be
1832 * set to value 0, which represents the 'NULL' pointer. When all MSDU
1833 * buffer pointers in the MSDU link descriptor are 'NULL', the MSDU link
1834 * descriptor itself shall also be released.
1835 */
1836#define HAL_WBM_COMPL_RX_INFO0_REL_SRC_MODULE GENMASK(2, 0)
1837#define HAL_WBM_COMPL_RX_INFO0_BM_ACTION GENMASK(5, 3)
1838#define HAL_WBM_COMPL_RX_INFO0_DESC_TYPE GENMASK(8, 6)
1839#define HAL_WBM_COMPL_RX_INFO0_RBM GENMASK(12, 9)
1840#define HAL_WBM_COMPL_RX_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17)
1841#define HAL_WBM_COMPL_RX_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19)
1842#define HAL_WBM_COMPL_RX_INFO0_REO_PUSH_REASON GENMASK(25, 24)
1843#define HAL_WBM_COMPL_RX_INFO0_REO_ERROR_CODE GENMASK(30, 26)
1844#define HAL_WBM_COMPL_RX_INFO0_WBM_INTERNAL_ERROR BIT(31)
1845
1846#define HAL_WBM_COMPL_RX_INFO1_PHY_ADDR_HI GENMASK(7, 0)
1847#define HAL_WBM_COMPL_RX_INFO1_SW_COOKIE GENMASK(27, 8)
1848#define HAL_WBM_COMPL_RX_INFO1_LOOPING_COUNT GENMASK(31, 28)
1849
1850struct hal_wbm_completion_ring_rx {
1851 __le32 addr_lo;
1852 __le32 addr_hi;
1853 __le32 info0;
1854 struct rx_mpdu_desc rx_mpdu_info;
1855 struct rx_msdu_desc rx_msdu_info;
1856 __le32 phy_addr_lo;
1857 __le32 info1;
1858} __packed;
1859
1860#define HAL_WBM_COMPL_TX_INFO0_REL_SRC_MODULE GENMASK(2, 0)
1861#define HAL_WBM_COMPL_TX_INFO0_DESC_TYPE GENMASK(8, 6)
1862#define HAL_WBM_COMPL_TX_INFO0_RBM GENMASK(12, 9)
1863#define HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON GENMASK(16, 13)
1864#define HAL_WBM_COMPL_TX_INFO0_RBM_OVERRIDE_VLD BIT(17)
1865#define HAL_WBM_COMPL_TX_INFO0_SW_COOKIE_LO GENMASK(29, 18)
1866#define HAL_WBM_COMPL_TX_INFO0_CC_DONE BIT(30)
1867#define HAL_WBM_COMPL_TX_INFO0_WBM_INTERNAL_ERROR BIT(31)
1868
1869#define HAL_WBM_COMPL_TX_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0)
1870#define HAL_WBM_COMPL_TX_INFO1_TRANSMIT_COUNT GENMASK(30, 24)
1871#define HAL_WBM_COMPL_TX_INFO1_SW_REL_DETAILS_VALID BIT(31)
1872
1873#define HAL_WBM_COMPL_TX_INFO2_ACK_FRAME_RSSI GENMASK(7, 0)
1874#define HAL_WBM_COMPL_TX_INFO2_FIRST_MSDU BIT(8)
1875#define HAL_WBM_COMPL_TX_INFO2_LAST_MSDU BIT(9)
1876#define HAL_WBM_COMPL_TX_INFO2_FW_TX_NOTIF_FRAME GENMASK(12, 10)
1877#define HAL_WBM_COMPL_TX_INFO2_BUFFER_TIMESTAMP GENMASK(31, 13)
1878
1879#define HAL_WBM_COMPL_TX_INFO3_PEER_ID GENMASK(15, 0)
1880#define HAL_WBM_COMPL_TX_INFO3_TID GENMASK(19, 16)
1881#define HAL_WBM_COMPL_TX_INFO3_SW_COOKIE_HI GENMASK(27, 20)
1882#define HAL_WBM_COMPL_TX_INFO3_LOOPING_COUNT GENMASK(31, 28)
1883
1884struct hal_wbm_completion_ring_tx {
1885 __le32 buf_va_lo;
1886 __le32 buf_va_hi;
1887 __le32 info0;
1888 __le32 info1;
1889 __le32 info2;
1890 struct hal_tx_rate_stats rate_stats;
1891 __le32 info3;
1892} __packed;
1893
1894#define HAL_WBM_RELEASE_TX_INFO0_REL_SRC_MODULE GENMASK(2, 0)
1895#define HAL_WBM_RELEASE_TX_INFO0_BM_ACTION GENMASK(5, 3)
1896#define HAL_WBM_RELEASE_TX_INFO0_DESC_TYPE GENMASK(8, 6)
1897#define HAL_WBM_RELEASE_TX_INFO0_FIRST_MSDU_IDX GENMASK(12, 9)
1898#define HAL_WBM_RELEASE_TX_INFO0_TQM_RELEASE_REASON GENMASK(18, 13)
1899#define HAL_WBM_RELEASE_TX_INFO0_RBM_OVERRIDE_VLD BIT(17)
1900#define HAL_WBM_RELEASE_TX_INFO0_SW_BUFFER_COOKIE_11_0 GENMASK(29, 18)
1901#define HAL_WBM_RELEASE_TX_INFO0_WBM_INTERNAL_ERROR BIT(31)
1902
1903#define HAL_WBM_RELEASE_TX_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0)
1904#define HAL_WBM_RELEASE_TX_INFO1_TRANSMIT_COUNT GENMASK(30, 24)
1905#define HAL_WBM_RELEASE_TX_INFO1_SW_REL_DETAILS_VALID BIT(31)
1906
1907#define HAL_WBM_RELEASE_TX_INFO2_ACK_FRAME_RSSI GENMASK(7, 0)
1908#define HAL_WBM_RELEASE_TX_INFO2_FIRST_MSDU BIT(8)
1909#define HAL_WBM_RELEASE_TX_INFO2_LAST_MSDU BIT(9)
1910#define HAL_WBM_RELEASE_TX_INFO2_FW_TX_NOTIF_FRAME GENMASK(12, 10)
1911#define HAL_WBM_RELEASE_TX_INFO2_BUFFER_TIMESTAMP GENMASK(31, 13)
1912
1913#define HAL_WBM_RELEASE_TX_INFO3_PEER_ID GENMASK(15, 0)
1914#define HAL_WBM_RELEASE_TX_INFO3_TID GENMASK(19, 16)
1915#define HAL_WBM_RELEASE_TX_INFO3_SW_BUFFER_COOKIE_19_12 GENMASK(27, 20)
1916#define HAL_WBM_RELEASE_TX_INFO3_LOOPING_COUNT GENMASK(31, 28)
1917
1918struct hal_wbm_release_ring_tx {
1919 struct ath12k_buffer_addr buf_addr_info;
1920 __le32 info0;
1921 __le32 info1;
1922 __le32 info2;
1923 struct hal_tx_rate_stats rate_stats;
1924 __le32 info3;
1925} __packed;
1926
1927#define HAL_WBM_RELEASE_RX_INFO0_REL_SRC_MODULE GENMASK(2, 0)
1928#define HAL_WBM_RELEASE_RX_INFO0_BM_ACTION GENMASK(5, 3)
1929#define HAL_WBM_RELEASE_RX_INFO0_DESC_TYPE GENMASK(8, 6)
1930#define HAL_WBM_RELEASE_RX_INFO0_FIRST_MSDU_IDX GENMASK(12, 9)
1931#define HAL_WBM_RELEASE_RX_INFO0_CC_STATUS BIT(16)
1932#define HAL_WBM_RELEASE_RX_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17)
1933#define HAL_WBM_RELEASE_RX_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19)
1934#define HAL_WBM_RELEASE_RX_INFO0_REO_PUSH_REASON GENMASK(25, 24)
1935#define HAL_WBM_RELEASE_RX_INFO0_REO_ERROR_CODE GENMASK(30, 26)
1936#define HAL_WBM_RELEASE_RX_INFO0_WBM_INTERNAL_ERROR BIT(31)
1937
1938#define HAL_WBM_RELEASE_RX_INFO2_RING_ID GENMASK(27, 20)
1939#define HAL_WBM_RELEASE_RX_INFO2_LOOPING_COUNT GENMASK(31, 28)
1940
1941struct hal_wbm_release_ring_rx {
1942 struct ath12k_buffer_addr buf_addr_info;
1943 __le32 info0;
1944 struct rx_mpdu_desc rx_mpdu_info;
1945 struct rx_msdu_desc rx_msdu_info;
1946 __le32 info1;
1947 __le32 info2;
1948} __packed;
1949
1950#define HAL_WBM_RELEASE_RX_CC_INFO0_RBM GENMASK(12, 9)
1951#define HAL_WBM_RELEASE_RX_CC_INFO1_COOKIE GENMASK(27, 8)
1952/* Used when hw cc is success */
1953struct hal_wbm_release_ring_cc_rx {
1954 __le32 buf_va_lo;
1955 __le32 buf_va_hi;
1956 __le32 info0;
1957 struct rx_mpdu_desc rx_mpdu_info;
1958 struct rx_msdu_desc rx_msdu_info;
1959 __le32 buf_pa_lo;
1960 __le32 info1;
1961} __packed;
1962
1963#define HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE GENMASK(2, 0)
1964#define HAL_WBM_RELEASE_INFO0_BM_ACTION GENMASK(5, 3)
1965#define HAL_WBM_RELEASE_INFO0_DESC_TYPE GENMASK(8, 6)
1966#define HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17)
1967#define HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19)
1968#define HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON GENMASK(25, 24)
1969#define HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE GENMASK(30, 26)
1970#define HAL_WBM_RELEASE_INFO0_WBM_INTERNAL_ERROR BIT(31)
1971
1972#define HAL_WBM_RELEASE_INFO3_FIRST_MSDU BIT(0)
1973#define HAL_WBM_RELEASE_INFO3_LAST_MSDU BIT(1)
1974#define HAL_WBM_RELEASE_INFO3_CONTINUATION BIT(2)
1975
1976#define HAL_WBM_RELEASE_INFO5_LOOPING_COUNT GENMASK(31, 28)
1977
1978struct hal_wbm_release_ring {
1979 struct ath12k_buffer_addr buf_addr_info;
1980 __le32 info0;
1981 __le32 info1;
1982 __le32 info2;
1983 __le32 info3;
1984 __le32 info4;
1985 __le32 info5;
1986} __packed;
1987
1988/* hal_wbm_release_ring
1989 *
1990 * Producer: SW/TQM/RXDMA/REO/SWITCH
1991 * Consumer: WBM/SW/FW
1992 *
1993 * HTT tx status is overlaid on wbm_release ring on 4-byte words 2, 3, 4 and 5
1994 * for software based completions.
1995 *
1996 * buf_addr_info
1997 * Details of the physical address of the buffer or link descriptor.
1998 *
1999 * release_source_module
2000 * Indicates which module initiated the release of this buffer/descriptor.
2001 * Values are defined in enum %HAL_WBM_REL_SRC_MODULE_.
2002 *
2003 * buffer_or_desc_type
2004 * Field only valid when WBM is marked as the return_buffer_manager in
2005 * the Released_Buffer_address_info. Indicates that type of buffer or
2006 * descriptor is being released. Values are in enum %HAL_WBM_REL_DESC_TYPE.
2007 *
2008 * wbm_internal_error
2009 * Is set when WBM got a buffer pointer but the action was to push it to
2010 * the idle link descriptor ring or do link related activity OR
2011 * Is set when WBM got a link buffer pointer but the action was to push it
2012 * to the buffer descriptor ring.
2013 *
2014 * looping_count
2015 * A count value that indicates the number of times the
2016 * producer of entries into the Buffer Manager Ring has looped
2017 * around the ring.
2018 *
2019 * At initialization time, this value is set to 0. On the
2020 * first loop, this value is set to 1. After the max value is
2021 * reached allowed by the number of bits for this field, the
2022 * count value continues with 0 again.
2023 *
2024 * In case SW is the consumer of the ring entries, it can
2025 * use this field to figure out up to where the producer of
2026 * entries has created new entries. This eliminates the need to
2027 * check where the head pointer' of the ring is located once
2028 * the SW starts processing an interrupt indicating that new
2029 * entries have been put into this ring...
2030 *
2031 * Also note that SW if it wants only needs to look at the
2032 * LSB bit of this count value.
2033 */
2034
2035/**
2036 * enum hal_wbm_tqm_rel_reason - TQM release reason code
2037 * @HAL_WBM_TQM_REL_REASON_FRAME_ACKED: ACK or BACK received for the frame
2038 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU: Command remove_mpdus initiated by SW
2039 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX: Command remove transmitted_mpdus
2040 * initiated by sw.
2041 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX: Command remove untransmitted_mpdus
2042 * initiated by sw.
2043 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES: Command remove aged msdus or
2044 * mpdus.
2045 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1: Remove command initiated by
2046 * fw with fw_reason1.
2047 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2: Remove command initiated by
2048 * fw with fw_reason2.
2049 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3: Remove command initiated by
2050 * fw with fw_reason3.
2051 */
2052enum hal_wbm_tqm_rel_reason {
2053 HAL_WBM_TQM_REL_REASON_FRAME_ACKED,
2054 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU,
2055 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX,
2056 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX,
2057 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES,
2058 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1,
2059 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2,
2060 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3,
2061};
2062
2063struct hal_wbm_buffer_ring {
2064 struct ath12k_buffer_addr buf_addr_info;
2065};
2066
2067enum hal_mon_end_reason {
2068 HAL_MON_STATUS_BUFFER_FULL,
2069 HAL_MON_FLUSH_DETECTED,
2070 HAL_MON_END_OF_PPDU,
2071 HAL_MON_PPDU_TRUNCATED,
2072};
2073
2074#define HAL_SW_MONITOR_RING_INFO0_RXDMA_PUSH_REASON GENMASK(1, 0)
2075#define HAL_SW_MONITOR_RING_INFO0_RXDMA_ERROR_CODE GENMASK(6, 2)
2076#define HAL_SW_MONITOR_RING_INFO0_MPDU_FRAGMENT_NUMBER GENMASK(10, 7)
2077#define HAL_SW_MONITOR_RING_INFO0_FRAMELESS_BAR BIT(11)
2078#define HAL_SW_MONITOR_RING_INFO0_STATUS_BUF_COUNT GENMASK(15, 12)
2079#define HAL_SW_MONITOR_RING_INFO0_END_OF_PPDU BIT(16)
2080
2081#define HAL_SW_MONITOR_RING_INFO1_PHY_PPDU_ID GENMASK(15, 0)
2082#define HAL_SW_MONITOR_RING_INFO1_RING_ID GENMASK(27, 20)
2083#define HAL_SW_MONITOR_RING_INFO1_LOOPING_COUNT GENMASK(31, 28)
2084
2085struct hal_sw_monitor_ring {
2086 struct ath12k_buffer_addr buf_addr_info;
2087 struct rx_mpdu_desc rx_mpdu_info;
2088 struct ath12k_buffer_addr status_buff_addr_info;
2089 __le32 info0; /* %HAL_SW_MONITOR_RING_INFO0 */
2090 __le32 info1; /* %HAL_SW_MONITOR_RING_INFO1 */
2091} __packed;
2092
2093/* hal_sw_monitor_ring
2094 *
2095 * Producer: RXDMA
2096 * Consumer: REO/SW/FW
2097 * buf_addr_info
2098 * Details of the physical address of a buffer or MSDU
2099 * link descriptor.
2100 *
2101 * rx_mpdu_info
2102 * Details related to the MPDU being pushed to SW, valid
2103 * only if end_of_ppdu is set to 0.
2104 *
2105 * status_buff_addr_info
2106 * Details of the physical address of the first status
2107 * buffer used for the PPDU (either the PPDU that included the
2108 * MPDU being pushed to SW if end_of_ppdu = 0, or the PPDU
2109 * whose end is indicated through end_of_ppdu = 1)
2110 *
2111 * rxdma_push_reason
2112 * Indicates why RXDMA pushed the frame to this ring
2113 *
2114 * <enum 0 rxdma_error_detected> RXDMA detected an error an
2115 * pushed this frame to this queue
2116 *
2117 * <enum 1 rxdma_routing_instruction> RXDMA pushed the
2118 * frame to this queue per received routing instructions. No
2119 * error within RXDMA was detected
2120 *
2121 * <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a
2122 * result the MSDU link descriptor might not have the
2123 * last_msdu_in_mpdu_flag set, but instead WBM might just see a
2124 * NULL pointer in the MSDU link descriptor. This is to be
2125 * considered a normal condition for this scenario.
2126 *
2127 * rxdma_error_code
2128 * Field only valid when rxdma_push_reason is set to
2129 * 'rxdma_error_detected.'
2130 *
2131 * <enum 0 rxdma_overflow_err>MPDU frame is not complete
2132 * due to a FIFO overflow error in RXPCU.
2133 *
2134 * <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
2135 * due to receiving incomplete MPDU from the PHY
2136 *
2137 * <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
2138 * error or CRYPTO received an encrypted frame, but did not get
2139 * a valid corresponding key id in the peer entry.
2140 *
2141 * <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
2142 * error
2143 *
2144 * <enum 5 rxdma_unecrypted_err>CRYPTO reported an
2145 * unencrypted frame error when encrypted was expected
2146 *
2147 * <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
2148 * length error
2149 *
2150 * <enum 7 rxdma_msdu_limit_err>RX OLE reported that max
2151 * number of MSDUs allowed in an MPDU got exceeded
2152 *
2153 * <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
2154 * error
2155 *
2156 * <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
2157 * parsing error
2158 *
2159 * <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
2160 * during SA search
2161 *
2162 * <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
2163 * during DA search
2164 *
2165 * <enum 12 rxdma_flow_timeout_err>RX OLE reported a
2166 * timeout during flow search
2167 *
2168 * <enum 13 rxdma_flush_request>RXDMA received a flush
2169 * request
2170 *
2171 * <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU
2172 * present as well as a fragmented MPDU.
2173 *
2174 * mpdu_fragment_number
2175 * Field only valid when Reo_level_mpdu_frame_info.
2176 * Rx_mpdu_desc_info_details.Fragment_flag is set and
2177 * end_of_ppdu is set to 0.
2178 *
2179 * The fragment number from the 802.11 header.
2180 *
2181 * Note that the sequence number is embedded in the field:
2182 * Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details.
2183 * Mpdu_sequence_number
2184 *
2185 * frameless_bar
2186 * When set, this SW monitor ring struct contains BAR info
2187 * from a multi TID BAR frame. The original multi TID BAR frame
2188 * itself contained all the REO info for the first TID, but all
2189 * the subsequent TID info and their linkage to the REO
2190 * descriptors is passed down as 'frameless' BAR info.
2191 *
2192 * The only fields valid in this descriptor when this bit
2193 * is within the
2194 *
2195 * Reo_level_mpdu_frame_info:
2196 * Within Rx_mpdu_desc_info_details:
2197 * Mpdu_Sequence_number
2198 * BAR_frame
2199 * Peer_meta_data
2200 * All other fields shall be set to 0.
2201 *
2202 * status_buf_count
2203 * A count of status buffers used so far for the PPDU
2204 * (either the PPDU that included the MPDU being pushed to SW
2205 * if end_of_ppdu = 0, or the PPDU whose end is indicated
2206 * through end_of_ppdu = 1)
2207 *
2208 * end_of_ppdu
2209 * Some hw RXDMA can be configured to generate a separate
2210 * 'SW_MONITOR_RING' descriptor at the end of a PPDU (either
2211 * through an 'RX_PPDU_END' TLV or through an 'RX_FLUSH') to
2212 * demarcate PPDUs.
2213 *
2214 * For such a descriptor, this bit is set to 1 and fields
2215 * Reo_level_mpdu_frame_info, mpdu_fragment_number and
2216 * Frameless_bar are all set to 0.
2217 *
2218 * Otherwise this bit is set to 0.
2219 *
2220 * phy_ppdu_id
2221 * A PPDU counter value that PHY increments for every PPDU
2222 * received
2223 *
2224 * The counter value wraps around. Some hw RXDMA can be
2225 * configured to copy this from the RX_PPDU_START TLV for every
2226 * output descriptor.
2227 *
2228 * ring_id
2229 * For debugging.
2230 * This field is filled in by the SRNG module.
2231 * It help to identify the ring that is being looked
2232 *
2233 * looping_count
2234 * For debugging.
2235 * This field is filled in by the SRNG module.
2236 *
2237 * A count value that indicates the number of times the
2238 * producer of entries into this Ring has looped around the
2239 * ring.
2240 * At initialization time, this value is set to 0. On the
2241 * first loop, this value is set to 1. After the max value is
2242 * reached allowed by the number of bits for this field, the
2243 * count value continues with 0 again.
2244 *
2245 * In case SW is the consumer of the ring entries, it can
2246 * use this field to figure out up to where the producer of
2247 * entries has created new entries. This eliminates the need to
2248 * check where the head pointer' of the ring is located once
2249 * the SW starts processing an interrupt indicating that new
2250 * entries have been put into this ring...
2251 */
2252
2253enum hal_desc_owner {
2254 HAL_DESC_OWNER_WBM,
2255 HAL_DESC_OWNER_SW,
2256 HAL_DESC_OWNER_TQM,
2257 HAL_DESC_OWNER_RXDMA,
2258 HAL_DESC_OWNER_REO,
2259 HAL_DESC_OWNER_SWITCH,
2260};
2261
2262enum hal_desc_buf_type {
2263 HAL_DESC_BUF_TYPE_TX_MSDU_LINK,
2264 HAL_DESC_BUF_TYPE_TX_MPDU_LINK,
2265 HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_HEAD,
2266 HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_EXT,
2267 HAL_DESC_BUF_TYPE_TX_FLOW,
2268 HAL_DESC_BUF_TYPE_TX_BUFFER,
2269 HAL_DESC_BUF_TYPE_RX_MSDU_LINK,
2270 HAL_DESC_BUF_TYPE_RX_MPDU_LINK,
2271 HAL_DESC_BUF_TYPE_RX_REO_QUEUE,
2272 HAL_DESC_BUF_TYPE_RX_REO_QUEUE_EXT,
2273 HAL_DESC_BUF_TYPE_RX_BUFFER,
2274 HAL_DESC_BUF_TYPE_IDLE_LINK,
2275};
2276
2277#define HAL_DESC_REO_OWNED 4
2278#define HAL_DESC_REO_QUEUE_DESC 8
2279#define HAL_DESC_REO_QUEUE_EXT_DESC 9
2280#define HAL_DESC_REO_NON_QOS_TID 16
2281
2282#define HAL_DESC_HDR_INFO0_OWNER GENMASK(3, 0)
2283#define HAL_DESC_HDR_INFO0_BUF_TYPE GENMASK(7, 4)
2284#define HAL_DESC_HDR_INFO0_DBG_RESERVED GENMASK(31, 8)
2285
2286struct hal_desc_header {
2287 __le32 info0;
2288} __packed;
2289
2290struct hal_rx_mpdu_link_ptr {
2291 struct ath12k_buffer_addr addr_info;
2292} __packed;
2293
2294struct hal_rx_msdu_details {
2295 struct ath12k_buffer_addr buf_addr_info;
2296 struct rx_msdu_desc rx_msdu_info;
2297 struct rx_msdu_ext_desc rx_msdu_ext_info;
2298} __packed;
2299
2300#define HAL_RX_MSDU_LNK_INFO0_RX_QUEUE_NUMBER GENMASK(15, 0)
2301#define HAL_RX_MSDU_LNK_INFO0_FIRST_MSDU_LNK BIT(16)
2302
2303struct hal_rx_msdu_link {
2304 struct hal_desc_header desc_hdr;
2305 struct ath12k_buffer_addr buf_addr_info;
2306 __le32 info0;
2307 __le32 pn[4];
2308 struct hal_rx_msdu_details msdu_link[6];
2309} __packed;
2310
2311struct hal_rx_reo_queue_ext {
2312 struct hal_desc_header desc_hdr;
2313 __le32 rsvd;
2314 struct hal_rx_mpdu_link_ptr mpdu_link[15];
2315} __packed;
2316
2317/* hal_rx_reo_queue_ext
2318 * Consumer: REO
2319 * Producer: REO
2320 *
2321 * descriptor_header
2322 * Details about which module owns this struct.
2323 *
2324 * mpdu_link
2325 * Pointer to the next MPDU_link descriptor in the MPDU queue.
2326 */
2327
2328enum hal_rx_reo_queue_pn_size {
2329 HAL_RX_REO_QUEUE_PN_SIZE_24,
2330 HAL_RX_REO_QUEUE_PN_SIZE_48,
2331 HAL_RX_REO_QUEUE_PN_SIZE_128,
2332};
2333
2334#define HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER GENMASK(15, 0)
2335
2336#define HAL_RX_REO_QUEUE_INFO0_VLD BIT(0)
2337#define HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER GENMASK(2, 1)
2338#define HAL_RX_REO_QUEUE_INFO0_DIS_DUP_DETECTION BIT(3)
2339#define HAL_RX_REO_QUEUE_INFO0_SOFT_REORDER_EN BIT(4)
2340#define HAL_RX_REO_QUEUE_INFO0_AC GENMASK(6, 5)
2341#define HAL_RX_REO_QUEUE_INFO0_BAR BIT(7)
2342#define HAL_RX_REO_QUEUE_INFO0_RETRY BIT(8)
2343#define HAL_RX_REO_QUEUE_INFO0_CHECK_2K_MODE BIT(9)
2344#define HAL_RX_REO_QUEUE_INFO0_OOR_MODE BIT(10)
2345#define HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE GENMASK(20, 11)
2346#define HAL_RX_REO_QUEUE_INFO0_PN_CHECK BIT(21)
2347#define HAL_RX_REO_QUEUE_INFO0_EVEN_PN BIT(22)
2348#define HAL_RX_REO_QUEUE_INFO0_UNEVEN_PN BIT(23)
2349#define HAL_RX_REO_QUEUE_INFO0_PN_HANDLE_ENABLE BIT(24)
2350#define HAL_RX_REO_QUEUE_INFO0_PN_SIZE GENMASK(26, 25)
2351#define HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG BIT(27)
2352
2353#define HAL_RX_REO_QUEUE_INFO1_SVLD BIT(0)
2354#define HAL_RX_REO_QUEUE_INFO1_SSN GENMASK(12, 1)
2355#define HAL_RX_REO_QUEUE_INFO1_CURRENT_IDX GENMASK(22, 13)
2356#define HAL_RX_REO_QUEUE_INFO1_SEQ_2K_ERR BIT(23)
2357#define HAL_RX_REO_QUEUE_INFO1_PN_ERR BIT(24)
2358#define HAL_RX_REO_QUEUE_INFO1_PN_VALID BIT(31)
2359
2360#define HAL_RX_REO_QUEUE_INFO2_MPDU_COUNT GENMASK(6, 0)
2361#define HAL_RX_REO_QUEUE_INFO2_MSDU_COUNT (31, 7)
2362
2363#define HAL_RX_REO_QUEUE_INFO3_TIMEOUT_COUNT GENMASK(9, 4)
2364#define HAL_RX_REO_QUEUE_INFO3_FWD_DUE_TO_BAR_CNT GENMASK(15, 10)
2365#define HAL_RX_REO_QUEUE_INFO3_DUPLICATE_COUNT GENMASK(31, 16)
2366
2367#define HAL_RX_REO_QUEUE_INFO4_FRAME_IN_ORD_COUNT GENMASK(23, 0)
2368#define HAL_RX_REO_QUEUE_INFO4_BAR_RECVD_COUNT GENMASK(31, 24)
2369
2370#define HAL_RX_REO_QUEUE_INFO5_LATE_RX_MPDU_COUNT GENMASK(11, 0)
2371#define HAL_RX_REO_QUEUE_INFO5_WINDOW_JUMP_2K GENMASK(15, 12)
2372#define HAL_RX_REO_QUEUE_INFO5_HOLE_COUNT GENMASK(31, 16)
2373
2374struct hal_rx_reo_queue {
2375 struct hal_desc_header desc_hdr;
2376 __le32 rx_queue_num;
2377 __le32 info0;
2378 __le32 info1;
2379 __le32 pn[4];
2380 __le32 last_rx_enqueue_timestamp;
2381 __le32 last_rx_dequeue_timestamp;
2382 __le32 next_aging_queue[2];
2383 __le32 prev_aging_queue[2];
2384 __le32 rx_bitmap[9];
2385 __le32 info2;
2386 __le32 info3;
2387 __le32 info4;
2388 __le32 processed_mpdus;
2389 __le32 processed_msdus;
2390 __le32 processed_total_bytes;
2391 __le32 info5;
2392 __le32 rsvd[2];
2393 struct hal_rx_reo_queue_ext ext_desc[];
2394} __packed;
2395
2396/* hal_rx_reo_queue
2397 *
2398 * descriptor_header
2399 * Details about which module owns this struct. Note that sub field
2400 * Buffer_type shall be set to receive_reo_queue_descriptor.
2401 *
2402 * receive_queue_number
2403 * Indicates the MPDU queue ID to which this MPDU link descriptor belongs.
2404 *
2405 * vld
2406 * Valid bit indicating a session is established and the queue descriptor
2407 * is valid.
2408 * associated_link_descriptor_counter
2409 * Indicates which of the 3 link descriptor counters shall be incremented
2410 * or decremented when link descriptors are added or removed from this
2411 * flow queue.
2412 * disable_duplicate_detection
2413 * When set, do not perform any duplicate detection.
2414 * soft_reorder_enable
2415 * When set, REO has been instructed to not perform the actual re-ordering
2416 * of frames for this queue, but just to insert the reorder opcodes.
2417 * ac
2418 * Indicates the access category of the queue descriptor.
2419 * bar
2420 * Indicates if BAR has been received.
2421 * retry
2422 * Retry bit is checked if this bit is set.
2423 * chk_2k_mode
2424 * Indicates what type of operation is expected from Reo when the received
2425 * frame SN falls within the 2K window.
2426 * oor_mode
2427 * Indicates what type of operation is expected when the received frame
2428 * falls within the OOR window.
2429 * ba_window_size
2430 * Indicates the negotiated (window size + 1). Max of 256 bits.
2431 *
2432 * A value 255 means 256 bitmap, 63 means 64 bitmap, 0 (means non-BA
2433 * session, with window size of 0). The 3 values here are the main values
2434 * validated, but other values should work as well.
2435 *
2436 * A BA window size of 0 (=> one frame entry bitmat), means that there is
2437 * no additional rx_reo_queue_ext desc. following rx_reo_queue in memory.
2438 * A BA window size of 1 - 105, means that there is 1 rx_reo_queue_ext.
2439 * A BA window size of 106 - 210, means that there are 2 rx_reo_queue_ext.
2440 * A BA window size of 211 - 256, means that there are 3 rx_reo_queue_ext.
2441 * pn_check_needed, pn_shall_be_even, pn_shall_be_uneven, pn_handling_enable,
2442 * pn_size
2443 * REO shall perform the PN increment check, even number check, uneven
2444 * number check, PN error check and size of the PN field check.
2445 * ignore_ampdu_flag
2446 * REO shall ignore the ampdu_flag on entrance descriptor for this queue.
2447 *
2448 * svld
2449 * Sequence number in next field is valid one.
2450 * ssn
2451 * Starting Sequence number of the session.
2452 * current_index
2453 * Points to last forwarded packet
2454 * seq_2k_error_detected_flag
2455 * REO has detected a 2k error jump in the sequence number and from that
2456 * moment forward, all new frames are forwarded directly to FW, without
2457 * duplicate detect, reordering, etc.
2458 * pn_error_detected_flag
2459 * REO has detected a PN error.
2460 */
2461
2462#define HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
2463#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM BIT(8)
2464#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD BIT(9)
2465#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT BIT(10)
2466#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION BIT(11)
2467#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN BIT(12)
2468#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC BIT(13)
2469#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR BIT(14)
2470#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY BIT(15)
2471#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE BIT(16)
2472#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE BIT(17)
2473#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE BIT(18)
2474#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK BIT(19)
2475#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN BIT(20)
2476#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN BIT(21)
2477#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE BIT(22)
2478#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE BIT(23)
2479#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG BIT(24)
2480#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD BIT(25)
2481#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN BIT(26)
2482#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR BIT(27)
2483#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_ERR BIT(28)
2484#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID BIT(29)
2485#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN BIT(30)
2486
2487#define HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER GENMASK(15, 0)
2488#define HAL_REO_UPD_RX_QUEUE_INFO1_VLD BIT(16)
2489#define HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER GENMASK(18, 17)
2490#define HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION BIT(19)
2491#define HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN BIT(20)
2492#define HAL_REO_UPD_RX_QUEUE_INFO1_AC GENMASK(22, 21)
2493#define HAL_REO_UPD_RX_QUEUE_INFO1_BAR BIT(23)
2494#define HAL_REO_UPD_RX_QUEUE_INFO1_RETRY BIT(24)
2495#define HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE BIT(25)
2496#define HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE BIT(26)
2497#define HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK BIT(27)
2498#define HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN BIT(28)
2499#define HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN BIT(29)
2500#define HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE BIT(30)
2501#define HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG BIT(31)
2502
2503#define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE GENMASK(7, 0)
2504#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE GENMASK(9, 8)
2505#define HAL_REO_UPD_RX_QUEUE_INFO2_SVLD BIT(10)
2506#define HAL_REO_UPD_RX_QUEUE_INFO2_SSN GENMASK(22, 11)
2507#define HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR BIT(23)
2508#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR BIT(24)
2509#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_VALID BIT(25)
2510
2511struct hal_reo_update_rx_queue {
2512 struct hal_reo_cmd_hdr cmd;
2513 __le32 queue_addr_lo;
2514 __le32 info0;
2515 __le32 info1;
2516 __le32 info2;
2517 __le32 pn[4];
2518} __packed;
2519
2520#define HAL_REO_UNBLOCK_CACHE_INFO0_UNBLK_CACHE BIT(0)
2521#define HAL_REO_UNBLOCK_CACHE_INFO0_RESOURCE_IDX GENMASK(2, 1)
2522
2523struct hal_reo_unblock_cache {
2524 struct hal_reo_cmd_hdr cmd;
2525 __le32 info0;
2526 __le32 rsvd[7];
2527} __packed;
2528
2529enum hal_reo_exec_status {
2530 HAL_REO_EXEC_STATUS_SUCCESS,
2531 HAL_REO_EXEC_STATUS_BLOCKED,
2532 HAL_REO_EXEC_STATUS_FAILED,
2533 HAL_REO_EXEC_STATUS_RESOURCE_BLOCKED,
2534};
2535
2536#define HAL_REO_STATUS_HDR_INFO0_STATUS_NUM GENMASK(15, 0)
2537#define HAL_REO_STATUS_HDR_INFO0_EXEC_TIME GENMASK(25, 16)
2538#define HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS GENMASK(27, 26)
2539
2540struct hal_reo_status_hdr {
2541 __le32 info0;
2542 __le32 timestamp;
2543} __packed;
2544
2545/* hal_reo_status_hdr
2546 * Producer: REO
2547 * Consumer: SW
2548 *
2549 * status_num
2550 * The value in this field is equal to value of the reo command
2551 * number. This field helps to correlate the statuses with the REO
2552 * commands.
2553 *
2554 * execution_time (in us)
2555 * The amount of time REO took to execute the command. Note that
2556 * this time does not include the duration of the command waiting
2557 * in the command ring, before the execution started.
2558 *
2559 * execution_status
2560 * Execution status of the command. Values are defined in
2561 * enum %HAL_REO_EXEC_STATUS_.
2562 */
2563#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN GENMASK(11, 0)
2564#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX GENMASK(21, 12)
2565
2566#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT GENMASK(6, 0)
2567#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT GENMASK(31, 7)
2568
2569#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_WINDOW_JMP2K GENMASK(3, 0)
2570#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT GENMASK(9, 4)
2571#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT GENMASK(15, 10)
2572#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT GENMASK(31, 16)
2573
2574#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT GENMASK(23, 0)
2575#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT GENMASK(31, 24)
2576
2577#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU GENMASK(11, 0)
2578#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT GENMASK(27, 12)
2579
2580#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT GENMASK(31, 28)
2581
2582struct hal_reo_get_queue_stats_status {
2583 struct hal_reo_status_hdr hdr;
2584 __le32 info0;
2585 __le32 pn[4];
2586 __le32 last_rx_enqueue_timestamp;
2587 __le32 last_rx_dequeue_timestamp;
2588 __le32 rx_bitmap[9];
2589 __le32 info1;
2590 __le32 info2;
2591 __le32 info3;
2592 __le32 num_mpdu_frames;
2593 __le32 num_msdu_frames;
2594 __le32 total_bytes;
2595 __le32 info4;
2596 __le32 info5;
2597} __packed;
2598
2599/* hal_reo_get_queue_stats_status
2600 * Producer: REO
2601 * Consumer: SW
2602 *
2603 * status_hdr
2604 * Details that can link this status with the original command. It
2605 * also contains info on how long REO took to execute this command.
2606 *
2607 * ssn
2608 * Starting Sequence number of the session, this changes whenever
2609 * window moves (can be filled by SW then maintained by REO).
2610 *
2611 * current_index
2612 * Points to last forwarded packet.
2613 *
2614 * pn
2615 * Bits of the PN number.
2616 *
2617 * last_rx_enqueue_timestamp
2618 * last_rx_dequeue_timestamp
2619 * Timestamp of arrival of the last MPDU for this queue and
2620 * Timestamp of forwarding an MPDU accordingly.
2621 *
2622 * rx_bitmap
2623 * When a bit is set, the corresponding frame is currently held
2624 * in the re-order queue. The bitmap is Fully managed by HW.
2625 *
2626 * current_mpdu_count
2627 * current_msdu_count
2628 * The number of MPDUs and MSDUs in the queue.
2629 *
2630 * timeout_count
2631 * The number of times REO started forwarding frames even though
2632 * there is a hole in the bitmap. Forwarding reason is timeout.
2633 *
2634 * forward_due_to_bar_count
2635 * The number of times REO started forwarding frames even though
2636 * there is a hole in the bitmap. Fwd reason is reception of BAR.
2637 *
2638 * duplicate_count
2639 * The number of duplicate frames that have been detected.
2640 *
2641 * frames_in_order_count
2642 * The number of frames that have been received in order (without
2643 * a hole that prevented them from being forwarded immediately).
2644 *
2645 * bar_received_count
2646 * The number of times a BAR frame is received.
2647 *
2648 * mpdu_frames_processed_count
2649 * msdu_frames_processed_count
2650 * The total number of MPDU/MSDU frames that have been processed.
2651 *
2652 * total_bytes
2653 * An approximation of the number of bytes received for this queue.
2654 *
2655 * late_receive_mpdu_count
2656 * The number of MPDUs received after the window had already moved
2657 * on. The 'late' sequence window is defined as
2658 * (Window SSN - 256) - (Window SSN - 1).
2659 *
2660 * window_jump_2k
2661 * The number of times the window moved more than 2K
2662 *
2663 * hole_count
2664 * The number of times a hole was created in the receive bitmap.
2665 *
2666 * looping_count
2667 * A count value that indicates the number of times the producer of
2668 * entries into this Ring has looped around the ring.
2669 */
2670
2671#define HAL_REO_STATUS_LOOP_CNT GENMASK(31, 28)
2672
2673#define HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED BIT(0)
2674#define HAL_REO_FLUSH_QUEUE_INFO0_RSVD GENMASK(31, 1)
2675#define HAL_REO_FLUSH_QUEUE_INFO1_RSVD GENMASK(27, 0)
2676
2677struct hal_reo_flush_queue_status {
2678 struct hal_reo_status_hdr hdr;
2679 __le32 info0;
2680 __le32 rsvd0[21];
2681 __le32 info1;
2682} __packed;
2683
2684/* hal_reo_flush_queue_status
2685 * Producer: REO
2686 * Consumer: SW
2687 *
2688 * status_hdr
2689 * Details that can link this status with the original command. It
2690 * also contains info on how long REO took to execute this command.
2691 *
2692 * error_detected
2693 * Status of blocking resource
2694 *
2695 * 0 - No error has been detected while executing this command
2696 * 1 - Error detected. The resource to be used for blocking was
2697 * already in use.
2698 *
2699 * looping_count
2700 * A count value that indicates the number of times the producer of
2701 * entries into this Ring has looped around the ring.
2702 */
2703
2704#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR BIT(0)
2705#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE GENMASK(2, 1)
2706#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT BIT(8)
2707#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE GENMASK(11, 9)
2708#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID GENMASK(15, 12)
2709#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR GENMASK(17, 16)
2710#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT GENMASK(25, 18)
2711
2712struct hal_reo_flush_cache_status {
2713 struct hal_reo_status_hdr hdr;
2714 __le32 info0;
2715 __le32 rsvd0[21];
2716 __le32 info1;
2717} __packed;
2718
2719/* hal_reo_flush_cache_status
2720 * Producer: REO
2721 * Consumer: SW
2722 *
2723 * status_hdr
2724 * Details that can link this status with the original command. It
2725 * also contains info on how long REO took to execute this command.
2726 *
2727 * error_detected
2728 * Status for blocking resource handling
2729 *
2730 * 0 - No error has been detected while executing this command
2731 * 1 - An error in the blocking resource management was detected
2732 *
2733 * block_error_details
2734 * only valid when error_detected is set
2735 *
2736 * 0 - No blocking related errors found
2737 * 1 - Blocking resource is already in use
2738 * 2 - Resource requested to be unblocked, was not blocked
2739 *
2740 * cache_controller_flush_status_hit
2741 * The status that the cache controller returned on executing the
2742 * flush command.
2743 *
2744 * 0 - miss; 1 - hit
2745 *
2746 * cache_controller_flush_status_desc_type
2747 * Flush descriptor type
2748 *
2749 * cache_controller_flush_status_client_id
2750 * Module who made the flush request
2751 *
2752 * In REO, this is always 0
2753 *
2754 * cache_controller_flush_status_error
2755 * Error condition
2756 *
2757 * 0 - No error found
2758 * 1 - HW interface is still busy
2759 * 2 - Line currently locked. Used for one line flush command
2760 * 3 - At least one line is still locked.
2761 * Used for cache flush command.
2762 *
2763 * cache_controller_flush_count
2764 * The number of lines that were actually flushed out
2765 *
2766 * looping_count
2767 * A count value that indicates the number of times the producer of
2768 * entries into this Ring has looped around the ring.
2769 */
2770
2771#define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR BIT(0)
2772#define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE BIT(1)
2773
2774struct hal_reo_unblock_cache_status {
2775 struct hal_reo_status_hdr hdr;
2776 __le32 info0;
2777 __le32 rsvd0[21];
2778 __le32 info1;
2779} __packed;
2780
2781/* hal_reo_unblock_cache_status
2782 * Producer: REO
2783 * Consumer: SW
2784 *
2785 * status_hdr
2786 * Details that can link this status with the original command. It
2787 * also contains info on how long REO took to execute this command.
2788 *
2789 * error_detected
2790 * 0 - No error has been detected while executing this command
2791 * 1 - The blocking resource was not in use, and therefore it could
2792 * not be unblocked.
2793 *
2794 * unblock_type
2795 * Reference to the type of unblock command
2796 * 0 - Unblock a blocking resource
2797 * 1 - The entire cache usage is unblock
2798 *
2799 * looping_count
2800 * A count value that indicates the number of times the producer of
2801 * entries into this Ring has looped around the ring.
2802 */
2803
2804#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR BIT(0)
2805#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY BIT(1)
2806
2807#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT GENMASK(15, 0)
2808#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT GENMASK(31, 16)
2809
2810struct hal_reo_flush_timeout_list_status {
2811 struct hal_reo_status_hdr hdr;
2812 __le32 info0;
2813 __le32 info1;
2814 __le32 rsvd0[20];
2815 __le32 info2;
2816} __packed;
2817
2818/* hal_reo_flush_timeout_list_status
2819 * Producer: REO
2820 * Consumer: SW
2821 *
2822 * status_hdr
2823 * Details that can link this status with the original command. It
2824 * also contains info on how long REO took to execute this command.
2825 *
2826 * error_detected
2827 * 0 - No error has been detected while executing this command
2828 * 1 - Command not properly executed and returned with error
2829 *
2830 * timeout_list_empty
2831 * When set, REO has depleted the timeout list and all entries are
2832 * gone.
2833 *
2834 * release_desc_count
2835 * Producer: SW; Consumer: REO
2836 * The number of link descriptor released
2837 *
2838 * forward_buf_count
2839 * Producer: SW; Consumer: REO
2840 * The number of buffers forwarded to the REO destination rings
2841 *
2842 * looping_count
2843 * A count value that indicates the number of times the producer of
2844 * entries into this Ring has looped around the ring.
2845 */
2846
2847#define HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX GENMASK(1, 0)
2848#define HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0 GENMASK(23, 0)
2849#define HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1 GENMASK(23, 0)
2850#define HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2 GENMASK(23, 0)
2851#define HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM GENMASK(25, 0)
2852
2853struct hal_reo_desc_thresh_reached_status {
2854 struct hal_reo_status_hdr hdr;
2855 __le32 info0;
2856 __le32 info1;
2857 __le32 info2;
2858 __le32 info3;
2859 __le32 info4;
2860 __le32 rsvd0[17];
2861 __le32 info5;
2862} __packed;
2863
2864/* hal_reo_desc_thresh_reached_status
2865 * Producer: REO
2866 * Consumer: SW
2867 *
2868 * status_hdr
2869 * Details that can link this status with the original command. It
2870 * also contains info on how long REO took to execute this command.
2871 *
2872 * threshold_index
2873 * The index of the threshold register whose value got reached
2874 *
2875 * link_descriptor_counter0
2876 * link_descriptor_counter1
2877 * link_descriptor_counter2
2878 * link_descriptor_counter_sum
2879 * Value of the respective counters at generation of this message
2880 *
2881 * looping_count
2882 * A count value that indicates the number of times the producer of
2883 * entries into this Ring has looped around the ring.
2884 */
2885
2886#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_DATA_LENGTH GENMASK(13, 0)
2887#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_L4_CSUM_STATUS BIT(14)
2888#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_L3_CSUM_STATUS BIT(15)
2889#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_PID GENMASK(27, 24)
2890#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_QDISC BIT(28)
2891#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_MULTICAST BIT(29)
2892#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_MORE BIT(30)
2893#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_VALID_TOGGLE BIT(31)
2894
2895struct hal_tcl_entrance_from_ppe_ring {
2896 __le32 buffer_addr;
2897 __le32 info0;
2898} __packed;
2899
2900struct hal_mon_buf_ring {
2901 __le32 paddr_lo;
2902 __le32 paddr_hi;
2903 __le64 cookie;
2904};
2905
2906/* hal_mon_buf_ring
2907 * Producer : SW
2908 * Consumer : Monitor
2909 *
2910 * paddr_lo
2911 * Lower 32-bit physical address of the buffer pointer from the source ring.
2912 * paddr_hi
2913 * bit range 7-0 : upper 8 bit of the physical address.
2914 * bit range 31-8 : reserved.
2915 * cookie
2916 * Consumer: RxMon/TxMon 64 bit cookie of the buffers.
2917 */
2918
2919#define HAL_MON_DEST_COOKIE_BUF_ID GENMASK(17, 0)
2920
2921#define HAL_MON_DEST_INFO0_END_OFFSET GENMASK(15, 0)
2922#define HAL_MON_DEST_INFO0_FLUSH_DETECTED BIT(16)
2923#define HAL_MON_DEST_INFO0_END_OF_PPDU BIT(17)
2924#define HAL_MON_DEST_INFO0_INITIATOR BIT(18)
2925#define HAL_MON_DEST_INFO0_EMPTY_DESC BIT(19)
2926#define HAL_MON_DEST_INFO0_RING_ID GENMASK(27, 20)
2927#define HAL_MON_DEST_INFO0_LOOPING_COUNT GENMASK(31, 28)
2928
2929struct hal_mon_dest_desc {
2930 __le32 cookie;
2931 __le32 reserved;
2932 __le32 ppdu_id;
2933 __le32 info0;
2934};
2935
2936/* hal_mon_dest_ring
2937 * Producer : TxMon/RxMon
2938 * Consumer : SW
2939 * cookie
2940 * bit 0 -17 buf_id to track the skb's vaddr.
2941 * ppdu_id
2942 * Phy ppdu_id
2943 * end_offset
2944 * The offset into status buffer where DMA ended, ie., offset to the last
2945 * TLV + last TLV size.
2946 * flush_detected
2947 * Indicates whether 'tx_flush' or 'rx_flush' occurred.
2948 * end_of_ppdu
2949 * Indicates end of ppdu.
2950 * pmac_id
2951 * Indicates PMAC that received from frame.
2952 * empty_descriptor
2953 * This descriptor is written on flush or end of ppdu or end of status
2954 * buffer.
2955 * ring_id
2956 * updated by SRNG.
2957 * looping_count
2958 * updated by SRNG.
2959 */
2960
2961#endif /* ATH12K_HAL_DESC_H */
1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
2/*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6#include "core.h"
7
8#ifndef ATH12K_HAL_DESC_H
9#define ATH12K_HAL_DESC_H
10
11#define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0)
12
13#define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0)
14#define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(11, 8)
15#define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 12)
16
17struct ath12k_buffer_addr {
18 __le32 info0;
19 __le32 info1;
20} __packed;
21
22/* ath12k_buffer_addr
23 *
24 * buffer_addr_31_0
25 * Address (lower 32 bits) of the MSDU buffer or MSDU_EXTENSION
26 * descriptor or Link descriptor
27 *
28 * buffer_addr_39_32
29 * Address (upper 8 bits) of the MSDU buffer or MSDU_EXTENSION
30 * descriptor or Link descriptor
31 *
32 * return_buffer_manager (RBM)
33 * Consumer: WBM
34 * Producer: SW/FW
35 * Indicates to which buffer manager the buffer or MSDU_EXTENSION
36 * descriptor or link descriptor that is being pointed to shall be
37 * returned after the frame has been processed. It is used by WBM
38 * for routing purposes.
39 *
40 * Values are defined in enum %HAL_RX_BUF_RBM_
41 *
42 * sw_buffer_cookie
43 * Cookie field exclusively used by SW. HW ignores the contents,
44 * accept that it passes the programmed value on to other
45 * descriptors together with the physical address.
46 *
47 * Field can be used by SW to for example associate the buffers
48 * physical address with the virtual address.
49 *
50 * NOTE1:
51 * The three most significant bits can have a special meaning
52 * in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
53 * and field transmit_bw_restriction is set
54 *
55 * In case of NON punctured transmission:
56 * Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
57 * Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
58 * Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
59 * Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
60 * Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
61 * Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
62 * Sw_buffer_cookie[19:18] = 2'b11: reserved
63 *
64 * In case of punctured transmission:
65 * Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
66 * Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
67 * Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
68 * Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
69 * Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
70 * Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
71 * Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
72 * Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
73 * Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
74 * Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
75 * Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
76 * Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
77 * Sw_buffer_cookie[19:18] = 2'b11: reserved
78 *
79 * Note: a punctured transmission is indicated by the presence
80 * of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
81 *
82 * Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS control
83 * field
84 *
85 * Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
86 * indicates MPDUs with a QoS control field.
87 *
88 */
89
90enum hal_tlv_tag {
91 HAL_MACTX_CBF_START = 0 /* 0x0 */,
92 HAL_PHYRX_DATA = 1 /* 0x1 */,
93 HAL_PHYRX_CBF_DATA_RESP = 2 /* 0x2 */,
94 HAL_PHYRX_ABORT_REQUEST = 3 /* 0x3 */,
95 HAL_PHYRX_USER_ABORT_NOTIFICATION = 4 /* 0x4 */,
96 HAL_MACTX_DATA_RESP = 5 /* 0x5 */,
97 HAL_MACTX_CBF_DATA = 6 /* 0x6 */,
98 HAL_MACTX_CBF_DONE = 7 /* 0x7 */,
99 HAL_PHYRX_LMR_DATA_RESP = 8 /* 0x8 */,
100 HAL_RXPCU_TO_UCODE_START = 9 /* 0x9 */,
101 HAL_RXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU = 10 /* 0xa */,
102 HAL_RXPCU_TO_UCODE_FULL_MPDU_DATA = 11 /* 0xb */,
103 HAL_RXPCU_TO_UCODE_FCS_STATUS = 12 /* 0xc */,
104 HAL_RXPCU_TO_UCODE_MPDU_DELIMITER = 13 /* 0xd */,
105 HAL_RXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER = 14 /* 0xe */,
106 HAL_RXPCU_TO_UCODE_MPDU_HEADER_DATA = 15 /* 0xf */,
107 HAL_RXPCU_TO_UCODE_END = 16 /* 0x10 */,
108 HAL_MACRX_CBF_READ_REQUEST = 32 /* 0x20 */,
109 HAL_MACRX_CBF_DATA_REQUEST = 33 /* 0x21 */,
110 HAL_MACRXXPECT_NDP_RECEPTION = 34 /* 0x22 */,
111 HAL_MACRX_FREEZE_CAPTURE_CHANNEL = 35 /* 0x23 */,
112 HAL_MACRX_NDP_TIMEOUT = 36 /* 0x24 */,
113 HAL_MACRX_ABORT_ACK = 37 /* 0x25 */,
114 HAL_MACRX_REQ_IMPLICIT_FB = 38 /* 0x26 */,
115 HAL_MACRX_CHAIN_MASK = 39 /* 0x27 */,
116 HAL_MACRX_NAP_USER = 40 /* 0x28 */,
117 HAL_MACRX_ABORT_REQUEST = 41 /* 0x29 */,
118 HAL_PHYTX_OTHER_TRANSMIT_INFO16 = 42 /* 0x2a */,
119 HAL_PHYTX_ABORT_ACK = 43 /* 0x2b */,
120 HAL_PHYTX_ABORT_REQUEST = 44 /* 0x2c */,
121 HAL_PHYTX_PKT_END = 45 /* 0x2d */,
122 HAL_PHYTX_PPDU_HEADER_INFO_REQUEST = 46 /* 0x2e */,
123 HAL_PHYTX_REQUEST_CTRL_INFO = 47 /* 0x2f */,
124 HAL_PHYTX_DATA_REQUEST = 48 /* 0x30 */,
125 HAL_PHYTX_BF_CV_LOADING_DONE = 49 /* 0x31 */,
126 HAL_PHYTX_NAP_ACK = 50 /* 0x32 */,
127 HAL_PHYTX_NAP_DONE = 51 /* 0x33 */,
128 HAL_PHYTX_OFF_ACK = 52 /* 0x34 */,
129 HAL_PHYTX_ON_ACK = 53 /* 0x35 */,
130 HAL_PHYTX_SYNTH_OFF_ACK = 54 /* 0x36 */,
131 HAL_PHYTX_DEBUG16 = 55 /* 0x37 */,
132 HAL_MACTX_ABORT_REQUEST = 56 /* 0x38 */,
133 HAL_MACTX_ABORT_ACK = 57 /* 0x39 */,
134 HAL_MACTX_PKT_END = 58 /* 0x3a */,
135 HAL_MACTX_PRE_PHY_DESC = 59 /* 0x3b */,
136 HAL_MACTX_BF_PARAMS_COMMON = 60 /* 0x3c */,
137 HAL_MACTX_BF_PARAMS_PER_USER = 61 /* 0x3d */,
138 HAL_MACTX_PREFETCH_CV = 62 /* 0x3e */,
139 HAL_MACTX_USER_DESC_COMMON = 63 /* 0x3f */,
140 HAL_MACTX_USER_DESC_PER_USER = 64 /* 0x40 */,
141 HAL_XAMPLE_USER_TLV_16 = 65 /* 0x41 */,
142 HAL_XAMPLE_TLV_16 = 66 /* 0x42 */,
143 HAL_MACTX_PHY_OFF = 67 /* 0x43 */,
144 HAL_MACTX_PHY_ON = 68 /* 0x44 */,
145 HAL_MACTX_SYNTH_OFF = 69 /* 0x45 */,
146 HAL_MACTXXPECT_CBF_COMMON = 70 /* 0x46 */,
147 HAL_MACTXXPECT_CBF_PER_USER = 71 /* 0x47 */,
148 HAL_MACTX_PHY_DESC = 72 /* 0x48 */,
149 HAL_MACTX_L_SIG_A = 73 /* 0x49 */,
150 HAL_MACTX_L_SIG_B = 74 /* 0x4a */,
151 HAL_MACTX_HT_SIG = 75 /* 0x4b */,
152 HAL_MACTX_VHT_SIG_A = 76 /* 0x4c */,
153 HAL_MACTX_VHT_SIG_B_SU20 = 77 /* 0x4d */,
154 HAL_MACTX_VHT_SIG_B_SU40 = 78 /* 0x4e */,
155 HAL_MACTX_VHT_SIG_B_SU80 = 79 /* 0x4f */,
156 HAL_MACTX_VHT_SIG_B_SU160 = 80 /* 0x50 */,
157 HAL_MACTX_VHT_SIG_B_MU20 = 81 /* 0x51 */,
158 HAL_MACTX_VHT_SIG_B_MU40 = 82 /* 0x52 */,
159 HAL_MACTX_VHT_SIG_B_MU80 = 83 /* 0x53 */,
160 HAL_MACTX_VHT_SIG_B_MU160 = 84 /* 0x54 */,
161 HAL_MACTX_SERVICE = 85 /* 0x55 */,
162 HAL_MACTX_HE_SIG_A_SU = 86 /* 0x56 */,
163 HAL_MACTX_HE_SIG_A_MU_DL = 87 /* 0x57 */,
164 HAL_MACTX_HE_SIG_A_MU_UL = 88 /* 0x58 */,
165 HAL_MACTX_HE_SIG_B1_MU = 89 /* 0x59 */,
166 HAL_MACTX_HE_SIG_B2_MU = 90 /* 0x5a */,
167 HAL_MACTX_HE_SIG_B2_OFDMA = 91 /* 0x5b */,
168 HAL_MACTX_DELETE_CV = 92 /* 0x5c */,
169 HAL_MACTX_MU_UPLINK_COMMON = 93 /* 0x5d */,
170 HAL_MACTX_MU_UPLINK_USER_SETUP = 94 /* 0x5e */,
171 HAL_MACTX_OTHER_TRANSMIT_INFO = 95 /* 0x5f */,
172 HAL_MACTX_PHY_NAP = 96 /* 0x60 */,
173 HAL_MACTX_DEBUG = 97 /* 0x61 */,
174 HAL_PHYRX_ABORT_ACK = 98 /* 0x62 */,
175 HAL_PHYRX_GENERATED_CBF_DETAILS = 99 /* 0x63 */,
176 HAL_PHYRX_RSSI_LEGACY = 100 /* 0x64 */,
177 HAL_PHYRX_RSSI_HT = 101 /* 0x65 */,
178 HAL_PHYRX_USER_INFO = 102 /* 0x66 */,
179 HAL_PHYRX_PKT_END = 103 /* 0x67 */,
180 HAL_PHYRX_DEBUG = 104 /* 0x68 */,
181 HAL_PHYRX_CBF_TRANSFER_DONE = 105 /* 0x69 */,
182 HAL_PHYRX_CBF_TRANSFER_ABORT = 106 /* 0x6a */,
183 HAL_PHYRX_L_SIG_A = 107 /* 0x6b */,
184 HAL_PHYRX_L_SIG_B = 108 /* 0x6c */,
185 HAL_PHYRX_HT_SIG = 109 /* 0x6d */,
186 HAL_PHYRX_VHT_SIG_A = 110 /* 0x6e */,
187 HAL_PHYRX_VHT_SIG_B_SU20 = 111 /* 0x6f */,
188 HAL_PHYRX_VHT_SIG_B_SU40 = 112 /* 0x70 */,
189 HAL_PHYRX_VHT_SIG_B_SU80 = 113 /* 0x71 */,
190 HAL_PHYRX_VHT_SIG_B_SU160 = 114 /* 0x72 */,
191 HAL_PHYRX_VHT_SIG_B_MU20 = 115 /* 0x73 */,
192 HAL_PHYRX_VHT_SIG_B_MU40 = 116 /* 0x74 */,
193 HAL_PHYRX_VHT_SIG_B_MU80 = 117 /* 0x75 */,
194 HAL_PHYRX_VHT_SIG_B_MU160 = 118 /* 0x76 */,
195 HAL_PHYRX_HE_SIG_A_SU = 119 /* 0x77 */,
196 HAL_PHYRX_HE_SIG_A_MU_DL = 120 /* 0x78 */,
197 HAL_PHYRX_HE_SIG_A_MU_UL = 121 /* 0x79 */,
198 HAL_PHYRX_HE_SIG_B1_MU = 122 /* 0x7a */,
199 HAL_PHYRX_HE_SIG_B2_MU = 123 /* 0x7b */,
200 HAL_PHYRX_HE_SIG_B2_OFDMA = 124 /* 0x7c */,
201 HAL_PHYRX_OTHER_RECEIVE_INFO = 125 /* 0x7d */,
202 HAL_PHYRX_COMMON_USER_INFO = 126 /* 0x7e */,
203 HAL_PHYRX_DATA_DONE = 127 /* 0x7f */,
204 HAL_COEX_TX_REQ = 128 /* 0x80 */,
205 HAL_DUMMY = 129 /* 0x81 */,
206 HALXAMPLE_TLV_32_NAME = 130 /* 0x82 */,
207 HAL_MPDU_LIMIT = 131 /* 0x83 */,
208 HAL_NA_LENGTH_END = 132 /* 0x84 */,
209 HAL_OLE_BUF_STATUS = 133 /* 0x85 */,
210 HAL_PCU_PPDU_SETUP_DONE = 134 /* 0x86 */,
211 HAL_PCU_PPDU_SETUP_END = 135 /* 0x87 */,
212 HAL_PCU_PPDU_SETUP_INIT = 136 /* 0x88 */,
213 HAL_PCU_PPDU_SETUP_START = 137 /* 0x89 */,
214 HAL_PDG_FES_SETUP = 138 /* 0x8a */,
215 HAL_PDG_RESPONSE = 139 /* 0x8b */,
216 HAL_PDG_TX_REQ = 140 /* 0x8c */,
217 HAL_SCH_WAIT_INSTR = 141 /* 0x8d */,
218 HAL_TQM_FLOWMPTY_STATUS = 143 /* 0x8f */,
219 HAL_TQM_FLOW_NOTMPTY_STATUS = 144 /* 0x90 */,
220 HAL_TQM_GEN_MPDU_LENGTH_LIST = 145 /* 0x91 */,
221 HAL_TQM_GEN_MPDU_LENGTH_LIST_STATUS = 146 /* 0x92 */,
222 HAL_TQM_GEN_MPDUS = 147 /* 0x93 */,
223 HAL_TQM_GEN_MPDUS_STATUS = 148 /* 0x94 */,
224 HAL_TQM_REMOVE_MPDU = 149 /* 0x95 */,
225 HAL_TQM_REMOVE_MPDU_STATUS = 150 /* 0x96 */,
226 HAL_TQM_REMOVE_MSDU = 151 /* 0x97 */,
227 HAL_TQM_REMOVE_MSDU_STATUS = 152 /* 0x98 */,
228 HAL_TQM_UPDATE_TX_MPDU_COUNT = 153 /* 0x99 */,
229 HAL_TQM_WRITE_CMD = 154 /* 0x9a */,
230 HAL_OFDMA_TRIGGER_DETAILS = 155 /* 0x9b */,
231 HAL_TX_DATA = 156 /* 0x9c */,
232 HAL_TX_FES_SETUP = 157 /* 0x9d */,
233 HAL_RX_PACKET = 158 /* 0x9e */,
234 HALXPECTED_RESPONSE = 159 /* 0x9f */,
235 HAL_TX_MPDU_END = 160 /* 0xa0 */,
236 HAL_TX_MPDU_START = 161 /* 0xa1 */,
237 HAL_TX_MSDU_END = 162 /* 0xa2 */,
238 HAL_TX_MSDU_START = 163 /* 0xa3 */,
239 HAL_TX_SW_MODE_SETUP = 164 /* 0xa4 */,
240 HAL_TXPCU_BUFFER_STATUS = 165 /* 0xa5 */,
241 HAL_TXPCU_USER_BUFFER_STATUS = 166 /* 0xa6 */,
242 HAL_DATA_TO_TIME_CONFIG = 167 /* 0xa7 */,
243 HALXAMPLE_USER_TLV_32 = 168 /* 0xa8 */,
244 HAL_MPDU_INFO = 169 /* 0xa9 */,
245 HAL_PDG_USER_SETUP = 170 /* 0xaa */,
246 HAL_TX_11AH_SETUP = 171 /* 0xab */,
247 HAL_REO_UPDATE_RX_REO_QUEUE_STATUS = 172 /* 0xac */,
248 HAL_TX_PEER_ENTRY = 173 /* 0xad */,
249 HAL_TX_RAW_OR_NATIVE_FRAME_SETUP = 174 /* 0xae */,
250 HALXAMPLE_USER_TLV_44 = 175 /* 0xaf */,
251 HAL_TX_FLUSH = 176 /* 0xb0 */,
252 HAL_TX_FLUSH_REQ = 177 /* 0xb1 */,
253 HAL_TQM_WRITE_CMD_STATUS = 178 /* 0xb2 */,
254 HAL_TQM_GET_MPDU_QUEUE_STATS = 179 /* 0xb3 */,
255 HAL_TQM_GET_MSDU_FLOW_STATS = 180 /* 0xb4 */,
256 HALXAMPLE_USER_CTLV_44 = 181 /* 0xb5 */,
257 HAL_TX_FES_STATUS_START = 182 /* 0xb6 */,
258 HAL_TX_FES_STATUS_USER_PPDU = 183 /* 0xb7 */,
259 HAL_TX_FES_STATUS_USER_RESPONSE = 184 /* 0xb8 */,
260 HAL_TX_FES_STATUS_END = 185 /* 0xb9 */,
261 HAL_RX_TRIG_INFO = 186 /* 0xba */,
262 HAL_RXPCU_TX_SETUP_CLEAR = 187 /* 0xbb */,
263 HAL_RX_FRAME_BITMAP_REQ = 188 /* 0xbc */,
264 HAL_RX_FRAME_BITMAP_ACK = 189 /* 0xbd */,
265 HAL_COEX_RX_STATUS = 190 /* 0xbe */,
266 HAL_RX_START_PARAM = 191 /* 0xbf */,
267 HAL_RX_PPDU_START = 192 /* 0xc0 */,
268 HAL_RX_PPDU_END = 193 /* 0xc1 */,
269 HAL_RX_MPDU_START = 194 /* 0xc2 */,
270 HAL_RX_MPDU_END = 195 /* 0xc3 */,
271 HAL_RX_MSDU_START = 196 /* 0xc4 */,
272 HAL_RX_MSDU_END = 197 /* 0xc5 */,
273 HAL_RX_ATTENTION = 198 /* 0xc6 */,
274 HAL_RECEIVED_RESPONSE_INFO = 199 /* 0xc7 */,
275 HAL_RX_PHY_SLEEP = 200 /* 0xc8 */,
276 HAL_RX_HEADER = 201 /* 0xc9 */,
277 HAL_RX_PEER_ENTRY = 202 /* 0xca */,
278 HAL_RX_FLUSH = 203 /* 0xcb */,
279 HAL_RX_RESPONSE_REQUIRED_INFO = 204 /* 0xcc */,
280 HAL_RX_FRAMELESS_BAR_DETAILS = 205 /* 0xcd */,
281 HAL_TQM_GET_MPDU_QUEUE_STATS_STATUS = 206 /* 0xce */,
282 HAL_TQM_GET_MSDU_FLOW_STATS_STATUS = 207 /* 0xcf */,
283 HAL_TX_CBF_INFO = 208 /* 0xd0 */,
284 HAL_PCU_PPDU_SETUP_USER = 209 /* 0xd1 */,
285 HAL_RX_MPDU_PCU_START = 210 /* 0xd2 */,
286 HAL_RX_PM_INFO = 211 /* 0xd3 */,
287 HAL_RX_USER_PPDU_END = 212 /* 0xd4 */,
288 HAL_RX_PRE_PPDU_START = 213 /* 0xd5 */,
289 HAL_RX_PREAMBLE = 214 /* 0xd6 */,
290 HAL_TX_FES_SETUP_COMPLETE = 215 /* 0xd7 */,
291 HAL_TX_LAST_MPDU_FETCHED = 216 /* 0xd8 */,
292 HAL_TXDMA_STOP_REQUEST = 217 /* 0xd9 */,
293 HAL_RXPCU_SETUP = 218 /* 0xda */,
294 HAL_RXPCU_USER_SETUP = 219 /* 0xdb */,
295 HAL_TX_FES_STATUS_ACK_OR_BA = 220 /* 0xdc */,
296 HAL_TQM_ACKED_MPDU = 221 /* 0xdd */,
297 HAL_COEX_TX_RESP = 222 /* 0xde */,
298 HAL_COEX_TX_STATUS = 223 /* 0xdf */,
299 HAL_MACTX_COEX_PHY_CTRL = 224 /* 0xe0 */,
300 HAL_COEX_STATUS_BROADCAST = 225 /* 0xe1 */,
301 HAL_RESPONSE_START_STATUS = 226 /* 0xe2 */,
302 HAL_RESPONSEND_STATUS = 227 /* 0xe3 */,
303 HAL_CRYPTO_STATUS = 228 /* 0xe4 */,
304 HAL_RECEIVED_TRIGGER_INFO = 229 /* 0xe5 */,
305 HAL_COEX_TX_STOP_CTRL = 230 /* 0xe6 */,
306 HAL_RX_PPDU_ACK_REPORT = 231 /* 0xe7 */,
307 HAL_RX_PPDU_NO_ACK_REPORT = 232 /* 0xe8 */,
308 HAL_SCH_COEX_STATUS = 233 /* 0xe9 */,
309 HAL_SCHEDULER_COMMAND_STATUS = 234 /* 0xea */,
310 HAL_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS = 235 /* 0xeb */,
311 HAL_TX_FES_STATUS_PROT = 236 /* 0xec */,
312 HAL_TX_FES_STATUS_START_PPDU = 237 /* 0xed */,
313 HAL_TX_FES_STATUS_START_PROT = 238 /* 0xee */,
314 HAL_TXPCU_PHYTX_DEBUG32 = 239 /* 0xef */,
315 HAL_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 = 240 /* 0xf0 */,
316 HAL_TX_MPDU_COUNT_TRANSFERND = 241 /* 0xf1 */,
317 HAL_WHO_ANCHOR_OFFSET = 242 /* 0xf2 */,
318 HAL_WHO_ANCHOR_VALUE = 243 /* 0xf3 */,
319 HAL_WHO_CCE_INFO = 244 /* 0xf4 */,
320 HAL_WHO_COMMIT = 245 /* 0xf5 */,
321 HAL_WHO_COMMIT_DONE = 246 /* 0xf6 */,
322 HAL_WHO_FLUSH = 247 /* 0xf7 */,
323 HAL_WHO_L2_LLC = 248 /* 0xf8 */,
324 HAL_WHO_L2_PAYLOAD = 249 /* 0xf9 */,
325 HAL_WHO_L3_CHECKSUM = 250 /* 0xfa */,
326 HAL_WHO_L3_INFO = 251 /* 0xfb */,
327 HAL_WHO_L4_CHECKSUM = 252 /* 0xfc */,
328 HAL_WHO_L4_INFO = 253 /* 0xfd */,
329 HAL_WHO_MSDU = 254 /* 0xfe */,
330 HAL_WHO_MSDU_MISC = 255 /* 0xff */,
331 HAL_WHO_PACKET_DATA = 256 /* 0x100 */,
332 HAL_WHO_PACKET_HDR = 257 /* 0x101 */,
333 HAL_WHO_PPDU_END = 258 /* 0x102 */,
334 HAL_WHO_PPDU_START = 259 /* 0x103 */,
335 HAL_WHO_TSO = 260 /* 0x104 */,
336 HAL_WHO_WMAC_HEADER_PV0 = 261 /* 0x105 */,
337 HAL_WHO_WMAC_HEADER_PV1 = 262 /* 0x106 */,
338 HAL_WHO_WMAC_IV = 263 /* 0x107 */,
339 HAL_MPDU_INFO_END = 264 /* 0x108 */,
340 HAL_MPDU_INFO_BITMAP = 265 /* 0x109 */,
341 HAL_TX_QUEUE_EXTENSION = 266 /* 0x10a */,
342 HAL_SCHEDULER_SELFGEN_RESPONSE_STATUS = 267 /* 0x10b */,
343 HAL_TQM_UPDATE_TX_MPDU_COUNT_STATUS = 268 /* 0x10c */,
344 HAL_TQM_ACKED_MPDU_STATUS = 269 /* 0x10d */,
345 HAL_TQM_ADD_MSDU_STATUS = 270 /* 0x10e */,
346 HAL_TQM_LIST_GEN_DONE = 271 /* 0x10f */,
347 HAL_WHO_TERMINATE = 272 /* 0x110 */,
348 HAL_TX_LAST_MPDU_END = 273 /* 0x111 */,
349 HAL_TX_CV_DATA = 274 /* 0x112 */,
350 HAL_PPDU_TX_END = 275 /* 0x113 */,
351 HAL_PROT_TX_END = 276 /* 0x114 */,
352 HAL_MPDU_INFO_GLOBAL_END = 277 /* 0x115 */,
353 HAL_TQM_SCH_INSTR_GLOBAL_END = 278 /* 0x116 */,
354 HAL_RX_PPDU_END_USER_STATS = 279 /* 0x117 */,
355 HAL_RX_PPDU_END_USER_STATS_EXT = 280 /* 0x118 */,
356 HAL_REO_GET_QUEUE_STATS = 281 /* 0x119 */,
357 HAL_REO_FLUSH_QUEUE = 282 /* 0x11a */,
358 HAL_REO_FLUSH_CACHE = 283 /* 0x11b */,
359 HAL_REO_UNBLOCK_CACHE = 284 /* 0x11c */,
360 HAL_REO_GET_QUEUE_STATS_STATUS = 285 /* 0x11d */,
361 HAL_REO_FLUSH_QUEUE_STATUS = 286 /* 0x11e */,
362 HAL_REO_FLUSH_CACHE_STATUS = 287 /* 0x11f */,
363 HAL_REO_UNBLOCK_CACHE_STATUS = 288 /* 0x120 */,
364 HAL_TQM_FLUSH_CACHE = 289 /* 0x121 */,
365 HAL_TQM_UNBLOCK_CACHE = 290 /* 0x122 */,
366 HAL_TQM_FLUSH_CACHE_STATUS = 291 /* 0x123 */,
367 HAL_TQM_UNBLOCK_CACHE_STATUS = 292 /* 0x124 */,
368 HAL_RX_PPDU_END_STATUS_DONE = 293 /* 0x125 */,
369 HAL_RX_STATUS_BUFFER_DONE = 294 /* 0x126 */,
370 HAL_TX_DATA_SYNC = 297 /* 0x129 */,
371 HAL_PHYRX_CBF_READ_REQUEST_ACK = 298 /* 0x12a */,
372 HAL_TQM_GET_MPDU_HEAD_INFO = 299 /* 0x12b */,
373 HAL_TQM_SYNC_CMD = 300 /* 0x12c */,
374 HAL_TQM_GET_MPDU_HEAD_INFO_STATUS = 301 /* 0x12d */,
375 HAL_TQM_SYNC_CMD_STATUS = 302 /* 0x12e */,
376 HAL_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS = 303 /* 0x12f */,
377 HAL_TQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 304 /* 0x130 */,
378 HAL_REO_FLUSH_TIMEOUT_LIST = 305 /* 0x131 */,
379 HAL_REO_FLUSH_TIMEOUT_LIST_STATUS = 306 /* 0x132 */,
380 HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 307 /* 0x133 */,
381 HAL_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS = 308 /* 0x134 */,
382 HALXAMPLE_USER_TLV_32_NAME = 309 /* 0x135 */,
383 HAL_RX_PPDU_START_USER_INFO = 310 /* 0x136 */,
384 HAL_RX_RING_MASK = 311 /* 0x137 */,
385 HAL_COEX_MAC_NAP = 312 /* 0x138 */,
386 HAL_RXPCU_PPDU_END_INFO = 313 /* 0x139 */,
387 HAL_WHO_MESH_CONTROL = 314 /* 0x13a */,
388 HAL_PDG_SW_MODE_BW_START = 315 /* 0x13b */,
389 HAL_PDG_SW_MODE_BW_END = 316 /* 0x13c */,
390 HAL_PDG_WAIT_FOR_MAC_REQUEST = 317 /* 0x13d */,
391 HAL_PDG_WAIT_FOR_PHY_REQUEST = 318 /* 0x13e */,
392 HAL_SCHEDULER_END = 319 /* 0x13f */,
393 HAL_RX_PPDU_START_DROPPED = 320 /* 0x140 */,
394 HAL_RX_PPDU_END_DROPPED = 321 /* 0x141 */,
395 HAL_RX_PPDU_END_STATUS_DONE_DROPPED = 322 /* 0x142 */,
396 HAL_RX_MPDU_START_DROPPED = 323 /* 0x143 */,
397 HAL_RX_MSDU_START_DROPPED = 324 /* 0x144 */,
398 HAL_RX_MSDU_END_DROPPED = 325 /* 0x145 */,
399 HAL_RX_MPDU_END_DROPPED = 326 /* 0x146 */,
400 HAL_RX_ATTENTION_DROPPED = 327 /* 0x147 */,
401 HAL_TXPCU_USER_SETUP = 328 /* 0x148 */,
402 HAL_RXPCU_USER_SETUP_EXT = 329 /* 0x149 */,
403 HAL_CMD_PART_0_END = 330 /* 0x14a */,
404 HAL_MACTX_SYNTH_ON = 331 /* 0x14b */,
405 HAL_SCH_CRITICAL_TLV_REFERENCE = 332 /* 0x14c */,
406 HAL_TQM_MPDU_GLOBAL_START = 333 /* 0x14d */,
407 HALXAMPLE_TLV_32 = 334 /* 0x14e */,
408 HAL_TQM_UPDATE_TX_MSDU_FLOW = 335 /* 0x14f */,
409 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD = 336 /* 0x150 */,
410 HAL_TQM_UPDATE_TX_MSDU_FLOW_STATUS = 337 /* 0x151 */,
411 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS = 338 /* 0x152 */,
412 HAL_REO_UPDATE_RX_REO_QUEUE = 339 /* 0x153 */,
413 HAL_TQM_MPDU_QUEUEMPTY_STATUS = 340 /* 0x154 */,
414 HAL_TQM_2_SCH_MPDU_AVAILABLE = 341 /* 0x155 */,
415 HAL_PDG_TRIG_RESPONSE = 342 /* 0x156 */,
416 HAL_TRIGGER_RESPONSE_TX_DONE = 343 /* 0x157 */,
417 HAL_ABORT_FROM_PHYRX_DETAILS = 344 /* 0x158 */,
418 HAL_SCH_TQM_CMD_WRAPPER = 345 /* 0x159 */,
419 HAL_MPDUS_AVAILABLE = 346 /* 0x15a */,
420 HAL_RECEIVED_RESPONSE_INFO_PART2 = 347 /* 0x15b */,
421 HAL_PHYRX_TX_START_TIMING = 348 /* 0x15c */,
422 HAL_TXPCU_PREAMBLE_DONE = 349 /* 0x15d */,
423 HAL_NDP_PREAMBLE_DONE = 350 /* 0x15e */,
424 HAL_SCH_TQM_CMD_WRAPPER_RBO_DROP = 351 /* 0x15f */,
425 HAL_SCH_TQM_CMD_WRAPPER_CONT_DROP = 352 /* 0x160 */,
426 HAL_MACTX_CLEAR_PREV_TX_INFO = 353 /* 0x161 */,
427 HAL_TX_PUNCTURE_SETUP = 354 /* 0x162 */,
428 HAL_R2R_STATUS_END = 355 /* 0x163 */,
429 HAL_MACTX_PREFETCH_CV_COMMON = 356 /* 0x164 */,
430 HAL_END_OF_FLUSH_MARKER = 357 /* 0x165 */,
431 HAL_MACTX_MU_UPLINK_COMMON_PUNC = 358 /* 0x166 */,
432 HAL_MACTX_MU_UPLINK_USER_SETUP_PUNC = 359 /* 0x167 */,
433 HAL_RECEIVED_RESPONSE_USER_7_0 = 360 /* 0x168 */,
434 HAL_RECEIVED_RESPONSE_USER_15_8 = 361 /* 0x169 */,
435 HAL_RECEIVED_RESPONSE_USER_23_16 = 362 /* 0x16a */,
436 HAL_RECEIVED_RESPONSE_USER_31_24 = 363 /* 0x16b */,
437 HAL_RECEIVED_RESPONSE_USER_36_32 = 364 /* 0x16c */,
438 HAL_TX_LOOPBACK_SETUP = 365 /* 0x16d */,
439 HAL_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS = 366 /* 0x16e */,
440 HAL_SCH_WAIT_INSTR_TX_PATH = 367 /* 0x16f */,
441 HAL_MACTX_OTHER_TRANSMIT_INFO_TX2TX = 368 /* 0x170 */,
442 HAL_MACTX_OTHER_TRANSMIT_INFOMUPHY_SETUP = 369 /* 0x171 */,
443 HAL_PHYRX_OTHER_RECEIVE_INFOVM_DETAILS = 370 /* 0x172 */,
444 HAL_TX_WUR_DATA = 371 /* 0x173 */,
445 HAL_RX_PPDU_END_START = 372 /* 0x174 */,
446 HAL_RX_PPDU_END_MIDDLE = 373 /* 0x175 */,
447 HAL_RX_PPDU_END_LAST = 374 /* 0x176 */,
448 HAL_MACTX_BACKOFF_BASED_TRANSMISSION = 375 /* 0x177 */,
449 HAL_MACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX = 376 /* 0x178 */,
450 HAL_SRP_INFO = 377 /* 0x179 */,
451 HAL_OBSS_SR_INFO = 378 /* 0x17a */,
452 HAL_SCHEDULER_SW_MSG_STATUS = 379 /* 0x17b */,
453 HAL_HWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT = 380 /* 0x17c */,
454 HAL_RXPCU_SETUP_COMPLETE = 381 /* 0x17d */,
455 HAL_SNOOP_PPDU_START = 382 /* 0x17e */,
456 HAL_SNOOP_MPDU_USR_DBG_INFO = 383 /* 0x17f */,
457 HAL_SNOOP_MSDU_USR_DBG_INFO = 384 /* 0x180 */,
458 HAL_SNOOP_MSDU_USR_DATA = 385 /* 0x181 */,
459 HAL_SNOOP_MPDU_USR_STAT_INFO = 386 /* 0x182 */,
460 HAL_SNOOP_PPDU_END = 387 /* 0x183 */,
461 HAL_SNOOP_SPARE = 388 /* 0x184 */,
462 HAL_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON = 390 /* 0x186 */,
463 HAL_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER = 391 /* 0x187 */,
464 HAL_MACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS = 392 /* 0x188 */,
465 HAL_PHYRX_OTHER_RECEIVE_INFO_108PVM_DETAILS = 393 /* 0x189 */,
466 HAL_SCH_TLV_WRAPPER = 394 /* 0x18a */,
467 HAL_SCHEDULER_STATUS_WRAPPER = 395 /* 0x18b */,
468 HAL_MPDU_INFO_6X = 396 /* 0x18c */,
469 HAL_MACTX_11AZ_USER_DESC_PER_USER = 397 /* 0x18d */,
470 HAL_MACTX_U_SIGHT_SU_MU = 398 /* 0x18e */,
471 HAL_MACTX_U_SIGHT_TB = 399 /* 0x18f */,
472 HAL_PHYRX_U_SIGHT_SU_MU = 403 /* 0x193 */,
473 HAL_PHYRX_U_SIGHT_TB = 404 /* 0x194 */,
474 HAL_MACRX_LMR_READ_REQUEST = 408 /* 0x198 */,
475 HAL_MACRX_LMR_DATA_REQUEST = 409 /* 0x199 */,
476 HAL_PHYRX_LMR_TRANSFER_DONE = 410 /* 0x19a */,
477 HAL_PHYRX_LMR_TRANSFER_ABORT = 411 /* 0x19b */,
478 HAL_PHYRX_LMR_READ_REQUEST_ACK = 412 /* 0x19c */,
479 HAL_MACRX_SECURE_LTF_SEQ_PTR = 413 /* 0x19d */,
480 HAL_PHYRX_USER_INFO_MU_UL = 414 /* 0x19e */,
481 HAL_MPDU_QUEUE_OVERVIEW = 415 /* 0x19f */,
482 HAL_SCHEDULER_NAV_INFO = 416 /* 0x1a0 */,
483 HAL_LMR_PEER_ENTRY = 418 /* 0x1a2 */,
484 HAL_LMR_MPDU_START = 419 /* 0x1a3 */,
485 HAL_LMR_DATA = 420 /* 0x1a4 */,
486 HAL_LMR_MPDU_END = 421 /* 0x1a5 */,
487 HAL_REO_GET_QUEUE_1K_STATS_STATUS = 422 /* 0x1a6 */,
488 HAL_RX_FRAME_1K_BITMAP_ACK = 423 /* 0x1a7 */,
489 HAL_TX_FES_STATUS_1K_BA = 424 /* 0x1a8 */,
490 HAL_TQM_ACKED_1K_MPDU = 425 /* 0x1a9 */,
491 HAL_MACRX_INBSS_OBSS_IND = 426 /* 0x1aa */,
492 HAL_PHYRX_LOCATION = 427 /* 0x1ab */,
493 HAL_MLO_TX_NOTIFICATION_SU = 428 /* 0x1ac */,
494 HAL_MLO_TX_NOTIFICATION_MU = 429 /* 0x1ad */,
495 HAL_MLO_TX_REQ_SU = 430 /* 0x1ae */,
496 HAL_MLO_TX_REQ_MU = 431 /* 0x1af */,
497 HAL_MLO_TX_RESP = 432 /* 0x1b0 */,
498 HAL_MLO_RX_NOTIFICATION = 433 /* 0x1b1 */,
499 HAL_MLO_BKOFF_TRUNC_REQ = 434 /* 0x1b2 */,
500 HAL_MLO_TBTT_NOTIFICATION = 435 /* 0x1b3 */,
501 HAL_MLO_MESSAGE = 436 /* 0x1b4 */,
502 HAL_MLO_TS_SYNC_MSG = 437 /* 0x1b5 */,
503 HAL_MLO_FES_SETUP = 438 /* 0x1b6 */,
504 HAL_MLO_PDG_FES_SETUP_SU = 439 /* 0x1b7 */,
505 HAL_MLO_PDG_FES_SETUP_MU = 440 /* 0x1b8 */,
506 HAL_MPDU_INFO_1K_BITMAP = 441 /* 0x1b9 */,
507 HAL_MON_BUF_ADDR = 442 /* 0x1ba */,
508 HAL_TX_FRAG_STATE = 443 /* 0x1bb */,
509 HAL_MACTXHT_SIG_USR_OFDMA = 446 /* 0x1be */,
510 HAL_PHYRXHT_SIG_CMN_PUNC = 448 /* 0x1c0 */,
511 HAL_PHYRXHT_SIG_CMN_OFDMA = 450 /* 0x1c2 */,
512 HAL_PHYRXHT_SIG_USR_OFDMA = 454 /* 0x1c6 */,
513 HAL_PHYRX_PKT_END_PART1 = 456 /* 0x1c8 */,
514 HAL_MACTXXPECT_NDP_RECEPTION = 457 /* 0x1c9 */,
515 HAL_MACTX_SECURE_LTF_SEQ_PTR = 458 /* 0x1ca */,
516 HAL_MLO_PDG_BKOFF_TRUNC_NOTIFY = 460 /* 0x1cc */,
517 HAL_PHYRX_11AZ_INTEGRITY_DATA = 461 /* 0x1cd */,
518 HAL_PHYTX_LOCATION = 462 /* 0x1ce */,
519 HAL_PHYTX_11AZ_INTEGRITY_DATA = 463 /* 0x1cf */,
520 HAL_MACTXHT_SIG_USR_SU = 466 /* 0x1d2 */,
521 HAL_MACTXHT_SIG_USR_MU_MIMO = 467 /* 0x1d3 */,
522 HAL_PHYRXHT_SIG_USR_SU = 468 /* 0x1d4 */,
523 HAL_PHYRXHT_SIG_USR_MU_MIMO = 469 /* 0x1d5 */,
524 HAL_PHYRX_GENERIC_U_SIG = 470 /* 0x1d6 */,
525 HAL_PHYRX_GENERICHT_SIG = 471 /* 0x1d7 */,
526 HAL_OVERWRITE_RESP_START = 472 /* 0x1d8 */,
527 HAL_OVERWRITE_RESP_PREAMBLE_INFO = 473 /* 0x1d9 */,
528 HAL_OVERWRITE_RESP_FRAME_INFO = 474 /* 0x1da */,
529 HAL_OVERWRITE_RESP_END = 475 /* 0x1db */,
530 HAL_RXPCUARLY_RX_INDICATION = 476 /* 0x1dc */,
531 HAL_MON_DROP = 477 /* 0x1dd */,
532 HAL_MACRX_MU_UPLINK_COMMON_SNIFF = 478 /* 0x1de */,
533 HAL_MACRX_MU_UPLINK_USER_SETUP_SNIFF = 479 /* 0x1df */,
534 HAL_MACRX_MU_UPLINK_USER_SEL_SNIFF = 480 /* 0x1e0 */,
535 HAL_MACRX_MU_UPLINK_FCS_STATUS_SNIFF = 481 /* 0x1e1 */,
536 HAL_MACTX_PREFETCH_CV_DMA = 482 /* 0x1e2 */,
537 HAL_MACTX_PREFETCH_CV_PER_USER = 483 /* 0x1e3 */,
538 HAL_PHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS = 484 /* 0x1e4 */,
539 HAL_MACTX_BF_PARAMS_UPDATE_COMMON = 485 /* 0x1e5 */,
540 HAL_MACTX_BF_PARAMS_UPDATE_PER_USER = 486 /* 0x1e6 */,
541 HAL_RANGING_USER_DETAILS = 487 /* 0x1e7 */,
542 HAL_PHYTX_CV_CORR_STATUS = 488 /* 0x1e8 */,
543 HAL_PHYTX_CV_CORR_COMMON = 489 /* 0x1e9 */,
544 HAL_PHYTX_CV_CORR_USER = 490 /* 0x1ea */,
545 HAL_MACTX_CV_CORR_COMMON = 491 /* 0x1eb */,
546 HAL_MACTX_CV_CORR_MAC_INFO_GROUP = 492 /* 0x1ec */,
547 HAL_BW_PUNCTUREVAL_WRAPPER = 493 /* 0x1ed */,
548 HAL_MACTX_RX_NOTIFICATION_FOR_PHY = 494 /* 0x1ee */,
549 HAL_MACTX_TX_NOTIFICATION_FOR_PHY = 495 /* 0x1ef */,
550 HAL_MACTX_MU_UPLINK_COMMON_PER_BW = 496 /* 0x1f0 */,
551 HAL_MACTX_MU_UPLINK_USER_SETUP_PER_BW = 497 /* 0x1f1 */,
552 HAL_RX_PPDU_END_USER_STATS_EXT2 = 498 /* 0x1f2 */,
553 HAL_FW2SW_MON = 499 /* 0x1f3 */,
554 HAL_WSI_DIRECT_MESSAGE = 500 /* 0x1f4 */,
555 HAL_MACTXMLSR_PRE_SWITCH = 501 /* 0x1f5 */,
556 HAL_MACTXMLSR_SWITCH = 502 /* 0x1f6 */,
557 HAL_MACTXMLSR_SWITCH_BACK = 503 /* 0x1f7 */,
558 HAL_PHYTXMLSR_SWITCH_ACK = 504 /* 0x1f8 */,
559 HAL_PHYTXMLSR_SWITCH_BACK_ACK = 505 /* 0x1f9 */,
560 HAL_SPARE_REUSE_TAG_0 = 506 /* 0x1fa */,
561 HAL_SPARE_REUSE_TAG_1 = 507 /* 0x1fb */,
562 HAL_SPARE_REUSE_TAG_2 = 508 /* 0x1fc */,
563 HAL_SPARE_REUSE_TAG_3 = 509 /* 0x1fd */,
564 /* FIXME: Assign correct value for HAL_TCL_DATA_CMD */
565 HAL_TCL_DATA_CMD = 510,
566 HAL_TLV_BASE = 511 /* 0x1ff */,
567};
568
569#define HAL_TLV_HDR_TAG GENMASK(9, 1)
570#define HAL_TLV_HDR_LEN GENMASK(25, 10)
571#define HAL_TLV_USR_ID GENMASK(31, 26)
572
573#define HAL_TLV_ALIGN 4
574
575struct hal_tlv_hdr {
576 __le32 tl;
577 u8 value[];
578} __packed;
579
580#define HAL_TLV_64_HDR_TAG GENMASK(9, 1)
581#define HAL_TLV_64_HDR_LEN GENMASK(21, 10)
582
583struct hal_tlv_64_hdr {
584 u64 tl;
585 u8 value[];
586} __packed;
587
588#define RX_MPDU_DESC_INFO0_MSDU_COUNT GENMASK(7, 0)
589#define RX_MPDU_DESC_INFO0_FRAG_FLAG BIT(8)
590#define RX_MPDU_DESC_INFO0_MPDU_RETRY BIT(9)
591#define RX_MPDU_DESC_INFO0_AMPDU_FLAG BIT(10)
592#define RX_MPDU_DESC_INFO0_BAR_FRAME BIT(11)
593#define RX_MPDU_DESC_INFO0_VALID_PN BIT(12)
594#define RX_MPDU_DESC_INFO0_RAW_MPDU BIT(13)
595#define RX_MPDU_DESC_INFO0_MORE_FRAG_FLAG BIT(14)
596#define RX_MPDU_DESC_INFO0_SRC_INFO GENMASK(26, 15)
597#define RX_MPDU_DESC_INFO0_MPDU_QOS_CTRL_VALID BIT(27)
598#define RX_MPDU_DESC_INFO0_TID GENMASK(31, 28)
599
600/* Peer Metadata classification */
601
602/* Version 0 */
603#define RX_MPDU_DESC_META_DATA_V0_PEER_ID GENMASK(15, 0)
604#define RX_MPDU_DESC_META_DATA_V0_VDEV_ID GENMASK(23, 16)
605
606/* Version 1 */
607#define RX_MPDU_DESC_META_DATA_V1_PEER_ID GENMASK(13, 0)
608#define RX_MPDU_DESC_META_DATA_V1_LOGICAL_LINK_ID GENMASK(15, 14)
609#define RX_MPDU_DESC_META_DATA_V1_VDEV_ID GENMASK(23, 16)
610#define RX_MPDU_DESC_META_DATA_V1_LMAC_ID GENMASK(25, 24)
611#define RX_MPDU_DESC_META_DATA_V1_DEVICE_ID GENMASK(28, 26)
612
613/* Version 1A */
614#define RX_MPDU_DESC_META_DATA_V1A_PEER_ID GENMASK(13, 0)
615#define RX_MPDU_DESC_META_DATA_V1A_VDEV_ID GENMASK(21, 14)
616#define RX_MPDU_DESC_META_DATA_V1A_LOGICAL_LINK_ID GENMASK(25, 22)
617#define RX_MPDU_DESC_META_DATA_V1A_DEVICE_ID GENMASK(28, 26)
618
619/* Version 1B */
620#define RX_MPDU_DESC_META_DATA_V1B_PEER_ID GENMASK(13, 0)
621#define RX_MPDU_DESC_META_DATA_V1B_VDEV_ID GENMASK(21, 14)
622#define RX_MPDU_DESC_META_DATA_V1B_HW_LINK_ID GENMASK(25, 22)
623#define RX_MPDU_DESC_META_DATA_V1B_DEVICE_ID GENMASK(28, 26)
624
625struct rx_mpdu_desc {
626 __le32 info0; /* %RX_MPDU_DESC_INFO */
627 __le32 peer_meta_data;
628} __packed;
629
630/* rx_mpdu_desc
631 * Producer: RXDMA
632 * Consumer: REO/SW/FW
633 *
634 * msdu_count
635 * The number of MSDUs within the MPDU
636 *
637 * fragment_flag
638 * When set, this MPDU is a fragment and REO should forward this
639 * fragment MPDU to the REO destination ring without any reorder
640 * checks, pn checks or bitmap update. This implies that REO is
641 * forwarding the pointer to the MSDU link descriptor.
642 *
643 * mpdu_retry_bit
644 * The retry bit setting from the MPDU header of the received frame
645 *
646 * ampdu_flag
647 * Indicates the MPDU was received as part of an A-MPDU.
648 *
649 * bar_frame
650 * Indicates the received frame is a BAR frame. After processing,
651 * this frame shall be pushed to SW or deleted.
652 *
653 * valid_pn
654 * When not set, REO will not perform a PN sequence number check.
655 *
656 * raw_mpdu
657 * Field only valid when first_msdu_in_mpdu_flag is set. Indicates
658 * the contents in the MSDU buffer contains a 'RAW' MPDU. This
659 * 'RAW' MPDU might be spread out over multiple MSDU buffers.
660 *
661 * more_fragment_flag
662 * The More Fragment bit setting from the MPDU header of the
663 * received frame
664 *
665 * src_info
666 * Source (Virtual) device/interface info associated with this peer.
667 * This field gets passed on by REO to PPE in the EDMA descriptor.
668 *
669 * mpdu_qos_control_valid
670 * When set, the MPDU has a QoS control field
671 *
672 * tid
673 * Field only valid when mpdu_qos_control_valid is set
674 */
675
676enum hal_rx_msdu_desc_reo_dest_ind {
677 HAL_RX_MSDU_DESC_REO_DEST_IND_TCL,
678 HAL_RX_MSDU_DESC_REO_DEST_IND_SW1,
679 HAL_RX_MSDU_DESC_REO_DEST_IND_SW2,
680 HAL_RX_MSDU_DESC_REO_DEST_IND_SW3,
681 HAL_RX_MSDU_DESC_REO_DEST_IND_SW4,
682 HAL_RX_MSDU_DESC_REO_DEST_IND_RELEASE,
683 HAL_RX_MSDU_DESC_REO_DEST_IND_FW,
684 HAL_RX_MSDU_DESC_REO_DEST_IND_SW5,
685 HAL_RX_MSDU_DESC_REO_DEST_IND_SW6,
686 HAL_RX_MSDU_DESC_REO_DEST_IND_SW7,
687 HAL_RX_MSDU_DESC_REO_DEST_IND_SW8,
688};
689
690#define RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU BIT(0)
691#define RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU BIT(1)
692#define RX_MSDU_DESC_INFO0_MSDU_CONTINUATION BIT(2)
693#define RX_MSDU_DESC_INFO0_MSDU_LENGTH GENMASK(16, 3)
694#define RX_MSDU_DESC_INFO0_MSDU_DROP BIT(17)
695#define RX_MSDU_DESC_INFO0_VALID_SA BIT(18)
696#define RX_MSDU_DESC_INFO0_VALID_DA BIT(19)
697#define RX_MSDU_DESC_INFO0_DA_MCBC BIT(20)
698#define RX_MSDU_DESC_INFO0_L3_HDR_PAD_MSB BIT(21)
699#define RX_MSDU_DESC_INFO0_TCP_UDP_CHKSUM_FAIL BIT(22)
700#define RX_MSDU_DESC_INFO0_IP_CHKSUM_FAIL BIT(23)
701#define RX_MSDU_DESC_INFO0_FROM_DS BIT(24)
702#define RX_MSDU_DESC_INFO0_TO_DS BIT(25)
703#define RX_MSDU_DESC_INFO0_INTRA_BSS BIT(26)
704#define RX_MSDU_DESC_INFO0_DST_CHIP_ID GENMASK(28, 27)
705#define RX_MSDU_DESC_INFO0_DECAP_FORMAT GENMASK(30, 29)
706
707#define HAL_RX_MSDU_PKT_LENGTH_GET(val) \
708 (u32_get_bits((val), RX_MSDU_DESC_INFO0_MSDU_LENGTH))
709
710struct rx_msdu_desc {
711 __le32 info0;
712} __packed;
713
714/* rx_msdu_desc
715 *
716 * first_msdu_in_mpdu
717 * Indicates first msdu in mpdu.
718 *
719 * last_msdu_in_mpdu
720 * Indicates last msdu in mpdu. This flag can be true only when
721 * 'Msdu_continuation' set to 0. This implies that when an msdu
722 * is spread out over multiple buffers and thus msdu_continuation
723 * is set, only for the very last buffer of the msdu, can the
724 * 'last_msdu_in_mpdu' be set.
725 *
726 * When both first_msdu_in_mpdu and last_msdu_in_mpdu are set,
727 * the MPDU that this MSDU belongs to only contains a single MSDU.
728 *
729 * msdu_continuation
730 * When set, this MSDU buffer was not able to hold the entire MSDU.
731 * The next buffer will therefore contain additional information
732 * related to this MSDU.
733 *
734 * msdu_length
735 * Field is only valid in combination with the 'first_msdu_in_mpdu'
736 * being set. Full MSDU length in bytes after decapsulation. This
737 * field is still valid for MPDU frames without A-MSDU. It still
738 * represents MSDU length after decapsulation Or in case of RAW
739 * MPDUs, it indicates the length of the entire MPDU (without FCS
740 * field).
741 *
742 * msdu_drop
743 * Indicates that REO shall drop this MSDU and not forward it to
744 * any other ring.
745 *
746 * valid_sa
747 * Indicates OLE found a valid SA entry for this MSDU.
748 *
749 * valid_da
750 * When set, OLE found a valid DA entry for this MSDU.
751 *
752 * da_mcbc
753 * Field Only valid if valid_da is set. Indicates the DA address
754 * is a Multicast or Broadcast address for this MSDU.
755 *
756 * l3_header_padding_msb
757 * Passed on from 'RX_MSDU_END' TLV (only the MSB is reported as
758 * the LSB is always zero). Number of bytes padded to make sure
759 * that the L3 header will always start of a Dword boundary
760 *
761 * tcp_udp_checksum_fail
762 * Passed on from 'RX_ATTENTION' TLV
763 * Indicates that the computed checksum did not match the checksum
764 * in the TCP/UDP header.
765 *
766 * ip_checksum_fail
767 * Passed on from 'RX_ATTENTION' TLV
768 * Indicates that the computed checksum did not match the checksum
769 * in the IP header.
770 *
771 * from_DS
772 * Set if the 'from DS' bit is set in the frame control.
773 *
774 * to_DS
775 * Set if the 'to DS' bit is set in the frame control.
776 *
777 * intra_bss
778 * This packet needs intra-BSS routing by SW as the 'vdev_id'
779 * for the destination is the same as the 'vdev_id' that this
780 * MSDU was got in.
781 *
782 * dest_chip_id
783 * If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY'
784 * to support intra-BSS routing with multi-chip multi-link operation.
785 * This indicates into which chip's TCL the packet should be queued.
786 *
787 * decap_format
788 * Indicates the format after decapsulation:
789 */
790
791#define RX_MSDU_EXT_DESC_INFO0_REO_DEST_IND GENMASK(4, 0)
792#define RX_MSDU_EXT_DESC_INFO0_SERVICE_CODE GENMASK(13, 5)
793#define RX_MSDU_EXT_DESC_INFO0_PRIORITY_VALID BIT(14)
794#define RX_MSDU_EXT_DESC_INFO0_DATA_OFFSET GENMASK(26, 15)
795#define RX_MSDU_EXT_DESC_INFO0_SRC_LINK_ID GENMASK(29, 27)
796
797struct rx_msdu_ext_desc {
798 __le32 info0;
799} __packed;
800
801/* rx_msdu_ext_desc
802 *
803 * reo_destination_indication
804 * The ID of the REO exit ring where the MSDU frame shall push
805 * after (MPDU level) reordering has finished.
806 *
807 * service_code
808 * Opaque service code between PPE and Wi-Fi
809 *
810 * priority_valid
811 *
812 * data_offset
813 * The offset to Rx packet data within the buffer (including
814 * Rx DMA offset programming and L3 header padding inserted
815 * by Rx OLE).
816 *
817 * src_link_id
818 * Set to the link ID of the PMAC that received the frame
819 */
820
821enum hal_reo_dest_ring_buffer_type {
822 HAL_REO_DEST_RING_BUFFER_TYPE_MSDU,
823 HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC,
824};
825
826enum hal_reo_dest_ring_push_reason {
827 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED,
828 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION,
829};
830
831enum hal_reo_dest_ring_error_code {
832 HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO,
833 HAL_REO_DEST_RING_ERROR_CODE_DESC_INVALID,
834 HAL_REO_DEST_RING_ERROR_CODE_AMPDU_IN_NON_BA,
835 HAL_REO_DEST_RING_ERROR_CODE_NON_BA_DUPLICATE,
836 HAL_REO_DEST_RING_ERROR_CODE_BA_DUPLICATE,
837 HAL_REO_DEST_RING_ERROR_CODE_FRAME_2K_JUMP,
838 HAL_REO_DEST_RING_ERROR_CODE_BAR_2K_JUMP,
839 HAL_REO_DEST_RING_ERROR_CODE_FRAME_OOR,
840 HAL_REO_DEST_RING_ERROR_CODE_BAR_OOR,
841 HAL_REO_DEST_RING_ERROR_CODE_NO_BA_SESSION,
842 HAL_REO_DEST_RING_ERROR_CODE_FRAME_SN_EQUALS_SSN,
843 HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED,
844 HAL_REO_DEST_RING_ERROR_CODE_2K_ERR_FLAG_SET,
845 HAL_REO_DEST_RING_ERROR_CODE_PN_ERR_FLAG_SET,
846 HAL_REO_DEST_RING_ERROR_CODE_DESC_BLOCKED,
847 HAL_REO_DEST_RING_ERROR_CODE_MAX,
848};
849
850#define HAL_REO_DEST_RING_INFO0_BUFFER_TYPE BIT(0)
851#define HAL_REO_DEST_RING_INFO0_PUSH_REASON GENMASK(2, 1)
852#define HAL_REO_DEST_RING_INFO0_ERROR_CODE GENMASK(7, 3)
853#define HAL_REO_DEST_RING_INFO0_MSDU_DATA_SIZE GENMASK(11, 8)
854#define HAL_REO_DEST_RING_INFO0_SW_EXCEPTION BIT(12)
855#define HAL_REO_DEST_RING_INFO0_SRC_LINK_ID GENMASK(15, 13)
856#define HAL_REO_DEST_RING_INFO0_SIGNATURE GENMASK(19, 16)
857#define HAL_REO_DEST_RING_INFO0_RING_ID GENMASK(27, 20)
858#define HAL_REO_DEST_RING_INFO0_LOOPING_COUNT GENMASK(31, 28)
859
860struct hal_reo_dest_ring {
861 struct ath12k_buffer_addr buf_addr_info;
862 struct rx_mpdu_desc rx_mpdu_info;
863 struct rx_msdu_desc rx_msdu_info;
864 __le32 buf_va_lo;
865 __le32 buf_va_hi;
866 __le32 info0; /* %HAL_REO_DEST_RING_INFO0_ */
867} __packed;
868
869/* hal_reo_dest_ring
870 *
871 * Producer: RXDMA
872 * Consumer: REO/SW/FW
873 *
874 * buf_addr_info
875 * Details of the physical address of a buffer or MSDU
876 * link descriptor.
877 *
878 * rx_mpdu_info
879 * General information related to the MPDU that is passed
880 * on from REO entrance ring to the REO destination ring.
881 *
882 * rx_msdu_info
883 * General information related to the MSDU that is passed
884 * on from RXDMA all the way to the REO destination ring.
885 *
886 * buf_va_lo
887 * Field only valid if Reo_dest_buffer_type is set to MSDU_buf_address
888 * Lower 32 bits of the 64-bit virtual address corresponding
889 * to Buf_or_link_desc_addr_info
890 *
891 * buf_va_hi
892 * Address (upper 32 bits) of the REO queue descriptor.
893 * Upper 32 bits of the 64-bit virtual address corresponding
894 * to Buf_or_link_desc_addr_info
895 *
896 * buffer_type
897 * Indicates the type of address provided in the buf_addr_info.
898 * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_.
899 *
900 * push_reason
901 * Reason for pushing this frame to this exit ring. Values are
902 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_.
903 *
904 * error_code
905 * Valid only when 'push_reason' is set. All error codes are
906 * defined in enum %HAL_REO_DEST_RING_ERROR_CODE_.
907 *
908 * captured_msdu_data_size
909 * The number of following REO_DESTINATION STRUCTs that have
910 * been replaced with msdu_data extracted from the msdu_buffer
911 * and copied into the ring for easy FW/SW access.
912 *
913 * sw_exception
914 * This field has the same setting as the SW_exception field
915 * in the corresponding REO_entrance_ring descriptor.
916 * When set, the REO entrance descriptor is generated by FW,
917 * and the MPDU was processed in the following way:
918 * - NO re-order function is needed.
919 * - MPDU delinking is determined by the setting of Entrance
920 * ring field: SW_excection_mpdu_delink
921 * - Destination ring selection is based on the setting of
922 * the Entrance ring field SW_exception_destination _ring_valid
923 *
924 * src_link_id
925 * Set to the link ID of the PMAC that received the frame
926 *
927 * signature
928 * Set to value 0x8 when msdu capture mode is enabled for this ring
929 *
930 * ring_id
931 * The buffer pointer ring id.
932 * 0 - Idle ring
933 * 1 - N refers to other rings.
934 *
935 * looping_count
936 * Indicates the number of times the producer of entries into
937 * this ring has looped around the ring.
938 */
939
940#define HAL_REO_TO_PPE_RING_INFO0_DATA_LENGTH GENMASK(15, 0)
941#define HAL_REO_TO_PPE_RING_INFO0_DATA_OFFSET GENMASK(23, 16)
942#define HAL_REO_TO_PPE_RING_INFO0_POOL_ID GENMASK(28, 24)
943#define HAL_REO_TO_PPE_RING_INFO0_PREHEADER BIT(29)
944#define HAL_REO_TO_PPE_RING_INFO0_TSO_EN BIT(30)
945#define HAL_REO_TO_PPE_RING_INFO0_MORE BIT(31)
946
947struct hal_reo_to_ppe_ring {
948 __le32 buffer_addr;
949 __le32 info0; /* %HAL_REO_TO_PPE_RING_INFO0_ */
950} __packed;
951
952/* hal_reo_to_ppe_ring
953 *
954 * Producer: REO
955 * Consumer: PPE
956 *
957 * buf_addr_info
958 * Details of the physical address of a buffer or MSDU
959 * link descriptor.
960 *
961 * data_length
962 * Length of valid data in bytes
963 *
964 * data_offset
965 * Offset to the data from buffer pointer. Can be used to
966 * strip header in the data for tunnel termination etc.
967 *
968 * pool_id
969 * REO has global configuration register for this field.
970 * It may have several free buffer pools, each
971 * RX-Descriptor ring can fetch free buffer from specific
972 * buffer pool; pool id will indicate which pool the buffer
973 * will be released to; POOL_ID Zero returned to SW
974 *
975 * preheader
976 * Disabled: 0 (Default)
977 * Enabled: 1
978 *
979 * tso_en
980 * Disabled: 0 (Default)
981 * Enabled: 1
982 *
983 * more
984 * More Segments followed
985 */
986
987enum hal_reo_entr_rxdma_push_reason {
988 HAL_REO_ENTR_RING_RXDMA_PUSH_REASON_ERR_DETECTED,
989 HAL_REO_ENTR_RING_RXDMA_PUSH_REASON_ROUTING_INSTRUCTION,
990 HAL_REO_ENTR_RING_RXDMA_PUSH_REASON_RX_FLUSH,
991};
992
993enum hal_reo_entr_rxdma_ecode {
994 HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR,
995 HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR,
996 HAL_REO_ENTR_RING_RXDMA_ECODE_FCS_ERR,
997 HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR,
998 HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR,
999 HAL_REO_ENTR_RING_RXDMA_ECODE_UNECRYPTED_ERR,
1000 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LEN_ERR,
1001 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LIMIT_ERR,
1002 HAL_REO_ENTR_RING_RXDMA_ECODE_WIFI_PARSE_ERR,
1003 HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_PARSE_ERR,
1004 HAL_REO_ENTR_RING_RXDMA_ECODE_SA_TIMEOUT_ERR,
1005 HAL_REO_ENTR_RING_RXDMA_ECODE_DA_TIMEOUT_ERR,
1006 HAL_REO_ENTR_RING_RXDMA_ECODE_FLOW_TIMEOUT_ERR,
1007 HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR,
1008 HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_FRAG_ERR,
1009 HAL_REO_ENTR_RING_RXDMA_ECODE_MAX,
1010};
1011
1012enum hal_rx_reo_dest_ring {
1013 HAL_RX_REO_DEST_RING_TCL,
1014 HAL_RX_REO_DEST_RING_SW1,
1015 HAL_RX_REO_DEST_RING_SW2,
1016 HAL_RX_REO_DEST_RING_SW3,
1017 HAL_RX_REO_DEST_RING_SW4,
1018 HAL_RX_REO_DEST_RING_RELEASE,
1019 HAL_RX_REO_DEST_RING_FW,
1020 HAL_RX_REO_DEST_RING_SW5,
1021 HAL_RX_REO_DEST_RING_SW6,
1022 HAL_RX_REO_DEST_RING_SW7,
1023 HAL_RX_REO_DEST_RING_SW8,
1024};
1025
1026#define HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
1027#define HAL_REO_ENTR_RING_INFO0_MPDU_BYTE_COUNT GENMASK(21, 8)
1028#define HAL_REO_ENTR_RING_INFO0_DEST_IND GENMASK(26, 22)
1029#define HAL_REO_ENTR_RING_INFO0_FRAMELESS_BAR BIT(27)
1030
1031#define HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON GENMASK(1, 0)
1032#define HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE GENMASK(6, 2)
1033#define HAL_REO_ENTR_RING_INFO1_MPDU_FRAG_NUM GENMASK(10, 7)
1034#define HAL_REO_ENTR_RING_INFO1_SW_EXCEPTION BIT(11)
1035#define HAL_REO_ENTR_RING_INFO1_SW_EXCEPT_MPDU_DELINK BIT(12)
1036#define HAL_REO_ENTR_RING_INFO1_SW_EXCEPTION_RING_VLD BIT(13)
1037#define HAL_REO_ENTR_RING_INFO1_SW_EXCEPTION_RING GENMASK(18, 14)
1038#define HAL_REO_ENTR_RING_INFO1_MPDU_SEQ_NUM GENMASK(30, 19)
1039
1040#define HAL_REO_ENTR_RING_INFO2_PHY_PPDU_ID GENMASK(15, 0)
1041#define HAL_REO_ENTR_RING_INFO2_SRC_LINK_ID GENMASK(18, 16)
1042#define HAL_REO_ENTR_RING_INFO2_RING_ID GENMASK(27, 20)
1043#define HAL_REO_ENTR_RING_INFO2_LOOPING_COUNT GENMASK(31, 28)
1044
1045struct hal_reo_entrance_ring {
1046 struct ath12k_buffer_addr buf_addr_info;
1047 struct rx_mpdu_desc rx_mpdu_info;
1048 __le32 queue_addr_lo;
1049 __le32 info0; /* %HAL_REO_ENTR_RING_INFO0_ */
1050 __le32 info1; /* %HAL_REO_ENTR_RING_INFO1_ */
1051 __le32 info2; /* %HAL_REO_DEST_RING_INFO2_ */
1052
1053} __packed;
1054
1055/* hal_reo_entrance_ring
1056 *
1057 * Producer: RXDMA
1058 * Consumer: REO
1059 *
1060 * buf_addr_info
1061 * Details of the physical address of a buffer or MSDU
1062 * link descriptor.
1063 *
1064 * rx_mpdu_info
1065 * General information related to the MPDU that is passed
1066 * on from REO entrance ring to the REO destination ring.
1067 *
1068 * queue_addr_lo
1069 * Address (lower 32 bits) of the REO queue descriptor.
1070 *
1071 * queue_addr_hi
1072 * Address (upper 8 bits) of the REO queue descriptor.
1073 *
1074 * mpdu_byte_count
1075 * An approximation of the number of bytes received in this MPDU.
1076 * Used to keeps stats on the amount of data flowing
1077 * through a queue.
1078 *
1079 * reo_destination_indication
1080 * The id of the reo exit ring where the msdu frame shall push
1081 * after (MPDU level) reordering has finished. Values are defined
1082 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_.
1083 *
1084 * frameless_bar
1085 * Indicates that this REO entrance ring struct contains BAR info
1086 * from a multi TID BAR frame. The original multi TID BAR frame
1087 * itself contained all the REO info for the first TID, but all
1088 * the subsequent TID info and their linkage to the REO descriptors
1089 * is passed down as 'frameless' BAR info.
1090 *
1091 * The only fields valid in this descriptor when this bit is set
1092 * are queue_addr_lo, queue_addr_hi, mpdu_sequence_number,
1093 * bar_frame and peer_meta_data.
1094 *
1095 * rxdma_push_reason
1096 * Reason for pushing this frame to this exit ring. Values are
1097 * defined in enum %HAL_REO_ENTR_RING_RXDMA_PUSH_REASON_.
1098 *
1099 * rxdma_error_code
1100 * Valid only when 'push_reason' is set. All error codes are
1101 * defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_.
1102 *
1103 * mpdu_fragment_number
1104 * Field only valid when Reo_level_mpdu_frame_info.
1105 * Rx_mpdu_desc_info_details.Fragment_flag is set.
1106 *
1107 * sw_exception
1108 * When not set, REO is performing all its default MPDU processing
1109 * operations,
1110 * When set, this REO entrance descriptor is generated by FW, and
1111 * should be processed as an exception. This implies:
1112 * NO re-order function is needed.
1113 * MPDU delinking is determined by the setting of field
1114 * SW_excection_mpdu_delink
1115 *
1116 * sw_exception_mpdu_delink
1117 * Field only valid when SW_exception is set.
1118 * 1'b0: REO should NOT delink the MPDU, and thus pass this
1119 * MPDU on to the destination ring as is. This implies that
1120 * in the REO_DESTINATION_RING struct field
1121 * Buf_or_link_desc_addr_info should point to an MSDU link
1122 * descriptor
1123 * 1'b1: REO should perform the normal MPDU delink into MSDU operations.
1124 *
1125 * sw_exception_dest_ring
1126 * Field only valid when fields SW_exception and SW
1127 * exception_destination_ring_valid are set. values are defined
1128 * in %HAL_RX_REO_DEST_RING_.
1129 *
1130 * mpdu_seq_number
1131 * The field can have two different meanings based on the setting
1132 * of sub-field Reo level mpdu frame info.
1133 * Rx_mpdu_desc_info_details. BAR_frame
1134 * 'BAR_frame' is NOT set:
1135 * The MPDU sequence number of the received frame.
1136 * 'BAR_frame' is set.
1137 * The MPDU Start sequence number from the BAR frame
1138 *
1139 * phy_ppdu_id
1140 * A PPDU counter value that PHY increments for every PPDU received
1141 *
1142 * src_link_id
1143 * Set to the link ID of the PMAC that received the frame
1144 *
1145 * ring_id
1146 * The buffer pointer ring id.
1147 * 0 - Idle ring
1148 * 1 - N refers to other rings.
1149 *
1150 * looping_count
1151 * Indicates the number of times the producer of entries into
1152 * this ring has looped around the ring.
1153 */
1154
1155#define HAL_REO_CMD_HDR_INFO0_CMD_NUMBER GENMASK(15, 0)
1156#define HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED BIT(16)
1157
1158struct hal_reo_cmd_hdr {
1159 __le32 info0;
1160} __packed;
1161
1162#define HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
1163#define HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS BIT(8)
1164
1165struct hal_reo_get_queue_stats {
1166 struct hal_reo_cmd_hdr cmd;
1167 __le32 queue_addr_lo;
1168 __le32 info0;
1169 __le32 rsvd0[6];
1170 __le32 tlv64_pad;
1171} __packed;
1172
1173/* hal_reo_get_queue_stats
1174 * Producer: SW
1175 * Consumer: REO
1176 *
1177 * cmd
1178 * Details for command execution tracking purposes.
1179 *
1180 * queue_addr_lo
1181 * Address (lower 32 bits) of the REO queue descriptor.
1182 *
1183 * queue_addr_hi
1184 * Address (upper 8 bits) of the REO queue descriptor.
1185 *
1186 * clear_stats
1187 * Clear stats settings. When set, Clear the stats after
1188 * generating the status.
1189 *
1190 * Following stats will be cleared.
1191 * Timeout_count
1192 * Forward_due_to_bar_count
1193 * Duplicate_count
1194 * Frames_in_order_count
1195 * BAR_received_count
1196 * MPDU_Frames_processed_count
1197 * MSDU_Frames_processed_count
1198 * Total_processed_byte_count
1199 * Late_receive_MPDU_count
1200 * window_jump_2k
1201 * Hole_count
1202 */
1203
1204#define HAL_REO_FLUSH_QUEUE_INFO0_DESC_ADDR_HI GENMASK(7, 0)
1205#define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_DESC_ADDR BIT(8)
1206#define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_RESRC_IDX GENMASK(10, 9)
1207
1208struct hal_reo_flush_queue {
1209 struct hal_reo_cmd_hdr cmd;
1210 __le32 desc_addr_lo;
1211 __le32 info0;
1212 __le32 rsvd0[6];
1213} __packed;
1214
1215#define HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI GENMASK(7, 0)
1216#define HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS BIT(8)
1217#define HAL_REO_FLUSH_CACHE_INFO0_RELEASE_BLOCK_IDX BIT(9)
1218#define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX GENMASK(11, 10)
1219#define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE BIT(12)
1220#define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE BIT(13)
1221#define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL BIT(14)
1222
1223struct hal_reo_flush_cache {
1224 struct hal_reo_cmd_hdr cmd;
1225 __le32 cache_addr_lo;
1226 __le32 info0;
1227 __le32 rsvd0[6];
1228} __packed;
1229
1230#define HAL_TCL_DATA_CMD_INFO0_CMD_TYPE BIT(0)
1231#define HAL_TCL_DATA_CMD_INFO0_DESC_TYPE BIT(1)
1232#define HAL_TCL_DATA_CMD_INFO0_BANK_ID GENMASK(7, 2)
1233#define HAL_TCL_DATA_CMD_INFO0_TX_NOTIFY_FRAME GENMASK(10, 8)
1234#define HAL_TCL_DATA_CMD_INFO0_HDR_LEN_READ_SEL BIT(11)
1235#define HAL_TCL_DATA_CMD_INFO0_BUF_TIMESTAMP GENMASK(30, 12)
1236#define HAL_TCL_DATA_CMD_INFO0_BUF_TIMESTAMP_VLD BIT(31)
1237
1238#define HAL_TCL_DATA_CMD_INFO1_CMD_NUM GENMASK(31, 16)
1239
1240#define HAL_TCL_DATA_CMD_INFO2_DATA_LEN GENMASK(15, 0)
1241#define HAL_TCL_DATA_CMD_INFO2_IP4_CKSUM_EN BIT(16)
1242#define HAL_TCL_DATA_CMD_INFO2_UDP4_CKSUM_EN BIT(17)
1243#define HAL_TCL_DATA_CMD_INFO2_UDP6_CKSUM_EN BIT(18)
1244#define HAL_TCL_DATA_CMD_INFO2_TCP4_CKSUM_EN BIT(19)
1245#define HAL_TCL_DATA_CMD_INFO2_TCP6_CKSUM_EN BIT(20)
1246#define HAL_TCL_DATA_CMD_INFO2_TO_FW BIT(21)
1247#define HAL_TCL_DATA_CMD_INFO2_PKT_OFFSET GENMASK(31, 23)
1248
1249#define HAL_TCL_DATA_CMD_INFO3_TID_OVERWRITE BIT(0)
1250#define HAL_TCL_DATA_CMD_INFO3_FLOW_OVERRIDE_EN BIT(1)
1251#define HAL_TCL_DATA_CMD_INFO3_CLASSIFY_INFO_SEL GENMASK(3, 2)
1252#define HAL_TCL_DATA_CMD_INFO3_TID GENMASK(7, 4)
1253#define HAL_TCL_DATA_CMD_INFO3_FLOW_OVERRIDE BIT(8)
1254#define HAL_TCL_DATA_CMD_INFO3_PMAC_ID GENMASK(10, 9)
1255#define HAL_TCL_DATA_CMD_INFO3_MSDU_COLOR GENMASK(12, 11)
1256#define HAL_TCL_DATA_CMD_INFO3_VDEV_ID GENMASK(31, 24)
1257
1258#define HAL_TCL_DATA_CMD_INFO4_SEARCH_INDEX GENMASK(19, 0)
1259#define HAL_TCL_DATA_CMD_INFO4_CACHE_SET_NUM GENMASK(23, 20)
1260#define HAL_TCL_DATA_CMD_INFO4_IDX_LOOKUP_OVERRIDE BIT(24)
1261
1262#define HAL_TCL_DATA_CMD_INFO5_RING_ID GENMASK(27, 20)
1263#define HAL_TCL_DATA_CMD_INFO5_LOOPING_COUNT GENMASK(31, 28)
1264
1265enum hal_encrypt_type {
1266 HAL_ENCRYPT_TYPE_WEP_40,
1267 HAL_ENCRYPT_TYPE_WEP_104,
1268 HAL_ENCRYPT_TYPE_TKIP_NO_MIC,
1269 HAL_ENCRYPT_TYPE_WEP_128,
1270 HAL_ENCRYPT_TYPE_TKIP_MIC,
1271 HAL_ENCRYPT_TYPE_WAPI,
1272 HAL_ENCRYPT_TYPE_CCMP_128,
1273 HAL_ENCRYPT_TYPE_OPEN,
1274 HAL_ENCRYPT_TYPE_CCMP_256,
1275 HAL_ENCRYPT_TYPE_GCMP_128,
1276 HAL_ENCRYPT_TYPE_AES_GCMP_256,
1277 HAL_ENCRYPT_TYPE_WAPI_GCM_SM4,
1278};
1279
1280enum hal_tcl_encap_type {
1281 HAL_TCL_ENCAP_TYPE_RAW,
1282 HAL_TCL_ENCAP_TYPE_NATIVE_WIFI,
1283 HAL_TCL_ENCAP_TYPE_ETHERNET,
1284 HAL_TCL_ENCAP_TYPE_802_3 = 3,
1285};
1286
1287enum hal_tcl_desc_type {
1288 HAL_TCL_DESC_TYPE_BUFFER,
1289 HAL_TCL_DESC_TYPE_EXT_DESC,
1290};
1291
1292enum hal_wbm_htt_tx_comp_status {
1293 HAL_WBM_REL_HTT_TX_COMP_STATUS_OK,
1294 HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP,
1295 HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL,
1296 HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ,
1297 HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT,
1298 HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY,
1299 HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX,
1300};
1301
1302struct hal_tcl_data_cmd {
1303 struct ath12k_buffer_addr buf_addr_info;
1304 __le32 info0;
1305 __le32 info1;
1306 __le32 info2;
1307 __le32 info3;
1308 __le32 info4;
1309 __le32 info5;
1310} __packed;
1311
1312/* hal_tcl_data_cmd
1313 *
1314 * buf_addr_info
1315 * Details of the physical address of a buffer or MSDU
1316 * link descriptor.
1317 *
1318 * tcl_cmd_type
1319 * used to select the type of TCL Command descriptor
1320 *
1321 * desc_type
1322 * Indicates the type of address provided in the buf_addr_info.
1323 * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_.
1324 *
1325 * bank_id
1326 * used to select one of the TCL register banks for fields removed
1327 * from 'TCL_DATA_CMD' that do not change often within one virtual
1328 * device or a set of virtual devices:
1329 *
1330 * tx_notify_frame
1331 * TCL copies this value to 'TQM_ENTRANCE_RING' field FW_tx_notify_frame.
1332 *
1333 * hdr_length_read_sel
1334 * used to select the per 'encap_type' register set for MSDU header
1335 * read length
1336 *
1337 * buffer_timestamp
1338 * buffer_timestamp_valid
1339 * Frame system entrance timestamp. It shall be filled by first
1340 * module (SW, TCL or TQM) that sees the frames first.
1341 *
1342 * cmd_num
1343 * This number can be used to match against status.
1344 *
1345 * data_length
1346 * MSDU length in case of direct descriptor. Length of link
1347 * extension descriptor in case of Link extension descriptor.
1348 *
1349 * *_checksum_en
1350 * Enable checksum replacement for ipv4, udp_over_ipv4, ipv6,
1351 * udp_over_ipv6, tcp_over_ipv4 and tcp_over_ipv6.
1352 *
1353 * to_fw
1354 * Forward packet to FW along with classification result. The
1355 * packet will not be forward to TQM when this bit is set.
1356 * 1'b0: Use classification result to forward the packet.
1357 * 1'b1: Override classification result & forward packet only to fw
1358 *
1359 * packet_offset
1360 * Packet offset from Metadata in case of direct buffer descriptor.
1361 *
1362 * hlos_tid_overwrite
1363 *
1364 * When set, TCL shall ignore the IP DSCP and VLAN PCP
1365 * fields and use HLOS_TID as the final TID. Otherwise TCL
1366 * shall consider the DSCP and PCP fields as well as HLOS_TID
1367 * and choose a final TID based on the configured priority
1368 *
1369 * flow_override_enable
1370 * TCL uses this to select the flow pointer from the peer table,
1371 * which can be overridden by SW for pre-encrypted raw WiFi packets
1372 * that cannot be parsed for UDP or for other MLO
1373 * 0 - FP_PARSE_IP: Use the flow-pointer based on parsing the IPv4
1374 * or IPv6 header.
1375 * 1 - FP_USE_OVERRIDE: Use the who_classify_info_sel and
1376 * flow_override fields to select the flow-pointer
1377 *
1378 * who_classify_info_sel
1379 * Field only valid when flow_override_enable is set to FP_USE_OVERRIDE.
1380 * This field is used to select one of the 'WHO_CLASSIFY_INFO's in the
1381 * peer table in case more than 2 flows are mapped to a single TID.
1382 * 0: To choose Flow 0 and 1 of any TID use this value.
1383 * 1: To choose Flow 2 and 3 of any TID use this value.
1384 * 2: To choose Flow 4 and 5 of any TID use this value.
1385 * 3: To choose Flow 6 and 7 of any TID use this value.
1386 *
1387 * If who_classify_info sel is not in sync with the num_tx_classify_info
1388 * field from address search, then TCL will set 'who_classify_info_sel'
1389 * to 0 use flows 0 and 1.
1390 *
1391 * hlos_tid
1392 * HLOS MSDU priority
1393 * Field is used when HLOS_TID_overwrite is set.
1394 *
1395 * flow_override
1396 * Field only valid when flow_override_enable is set to FP_USE_OVERRIDE
1397 * TCL uses this to select the flow pointer from the peer table,
1398 * which can be overridden by SW for pre-encrypted raw WiFi packets
1399 * that cannot be parsed for UDP or for other MLO
1400 * 0 - FP_USE_NON_UDP: Use the non-UDP flow pointer (flow 0)
1401 * 1 - FP_USE_UDP: Use the UDP flow pointer (flow 1)
1402 *
1403 * pmac_id
1404 * TCL uses this PMAC_ID in address search, i.e, while
1405 * finding matching entry for the packet in AST corresponding
1406 * to given PMAC_ID
1407 *
1408 * If PMAC ID is all 1s (=> value 3), it indicates wildcard
1409 * match for any PMAC
1410 *
1411 * vdev_id
1412 * Virtual device ID to check against the address search entry to
1413 * avoid security issues from transmitting packets from an incorrect
1414 * virtual device
1415 *
1416 * search_index
1417 * The index that will be used for index based address or
1418 * flow search. The field is valid when 'search_type' is 1 or 2.
1419 *
1420 * cache_set_num
1421 *
1422 * Cache set number that should be used to cache the index
1423 * based search results, for address and flow search. This
1424 * value should be equal to LSB four bits of the hash value of
1425 * match data, in case of search index points to an entry which
1426 * may be used in content based search also. The value can be
1427 * anything when the entry pointed by search index will not be
1428 * used for content based search.
1429 *
1430 * index_loop_override
1431 * When set, address search and packet routing is forced to use
1432 * 'search_index' instead of following the register configuration
1433 * selected by Bank_id.
1434 *
1435 * ring_id
1436 * The buffer pointer ring ID.
1437 * 0 refers to the IDLE ring
1438 * 1 - N refers to other rings
1439 *
1440 * looping_count
1441 *
1442 * A count value that indicates the number of times the
1443 * producer of entries into the Ring has looped around the
1444 * ring.
1445 *
1446 * At initialization time, this value is set to 0. On the
1447 * first loop, this value is set to 1. After the max value is
1448 * reached allowed by the number of bits for this field, the
1449 * count value continues with 0 again.
1450 *
1451 * In case SW is the consumer of the ring entries, it can
1452 * use this field to figure out up to where the producer of
1453 * entries has created new entries. This eliminates the need to
1454 * check where the head pointer' of the ring is located once
1455 * the SW starts processing an interrupt indicating that new
1456 * entries have been put into this ring...
1457 *
1458 * Also note that SW if it wants only needs to look at the
1459 * LSB bit of this count value.
1460 */
1461
1462#define HAL_TCL_DESC_LEN sizeof(struct hal_tcl_data_cmd)
1463
1464#define HAL_TX_MSDU_EXT_INFO0_BUF_PTR_LO GENMASK(31, 0)
1465
1466#define HAL_TX_MSDU_EXT_INFO1_BUF_PTR_HI GENMASK(7, 0)
1467#define HAL_TX_MSDU_EXT_INFO1_EXTN_OVERRIDE BIT(8)
1468#define HAL_TX_MSDU_EXT_INFO1_ENCAP_TYPE GENMASK(10, 9)
1469#define HAL_TX_MSDU_EXT_INFO1_ENCRYPT_TYPE GENMASK(14, 11)
1470#define HAL_TX_MSDU_EXT_INFO1_BUF_LEN GENMASK(31, 16)
1471
1472struct hal_tx_msdu_ext_desc {
1473 __le32 rsvd0[6];
1474 __le32 info0;
1475 __le32 info1;
1476 __le32 rsvd1[10];
1477};
1478
1479struct hal_tcl_gse_cmd {
1480 __le32 ctrl_buf_addr_lo;
1481 __le32 info0;
1482 __le32 meta_data[2];
1483 __le32 rsvd0[2];
1484 __le32 info1;
1485} __packed;
1486
1487/* hal_tcl_gse_cmd
1488 *
1489 * ctrl_buf_addr_lo, ctrl_buf_addr_hi
1490 * Address of a control buffer containing additional info needed
1491 * for this command execution.
1492 *
1493 * meta_data
1494 * Meta data to be returned in the status descriptor
1495 */
1496
1497enum hal_tcl_cache_op_res {
1498 HAL_TCL_CACHE_OP_RES_DONE,
1499 HAL_TCL_CACHE_OP_RES_NOT_FOUND,
1500 HAL_TCL_CACHE_OP_RES_TIMEOUT,
1501};
1502
1503struct hal_tcl_status_ring {
1504 __le32 info0;
1505 __le32 msdu_byte_count;
1506 __le32 msdu_timestamp;
1507 __le32 meta_data[2];
1508 __le32 info1;
1509 __le32 rsvd0;
1510 __le32 info2;
1511} __packed;
1512
1513/* hal_tcl_status_ring
1514 *
1515 * msdu_cnt
1516 * msdu_byte_count
1517 * MSDU count of Entry and MSDU byte count for entry 1.
1518 *
1519 */
1520
1521#define HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0)
1522#define HAL_CE_SRC_DESC_ADDR_INFO_HASH_EN BIT(8)
1523#define HAL_CE_SRC_DESC_ADDR_INFO_BYTE_SWAP BIT(9)
1524#define HAL_CE_SRC_DESC_ADDR_INFO_DEST_SWAP BIT(10)
1525#define HAL_CE_SRC_DESC_ADDR_INFO_GATHER BIT(11)
1526#define HAL_CE_SRC_DESC_ADDR_INFO_LEN GENMASK(31, 16)
1527
1528#define HAL_CE_SRC_DESC_META_INFO_DATA GENMASK(15, 0)
1529
1530#define HAL_CE_SRC_DESC_FLAGS_RING_ID GENMASK(27, 20)
1531#define HAL_CE_SRC_DESC_FLAGS_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT
1532
1533struct hal_ce_srng_src_desc {
1534 __le32 buffer_addr_low;
1535 __le32 buffer_addr_info; /* %HAL_CE_SRC_DESC_ADDR_INFO_ */
1536 __le32 meta_info; /* %HAL_CE_SRC_DESC_META_INFO_ */
1537 __le32 flags; /* %HAL_CE_SRC_DESC_FLAGS_ */
1538} __packed;
1539
1540/* hal_ce_srng_src_desc
1541 *
1542 * buffer_addr_lo
1543 * LSB 32 bits of the 40 Bit Pointer to the source buffer
1544 *
1545 * buffer_addr_hi
1546 * MSB 8 bits of the 40 Bit Pointer to the source buffer
1547 *
1548 * toeplitz_en
1549 * Enable generation of 32-bit Toeplitz-LFSR hash for
1550 * data transfer. In case of gather field in first source
1551 * ring entry of the gather copy cycle in taken into account.
1552 *
1553 * src_swap
1554 * Treats source memory organization as big-endian. For
1555 * each dword read (4 bytes), the byte 0 is swapped with byte 3
1556 * and byte 1 is swapped with byte 2.
1557 * In case of gather field in first source ring entry of
1558 * the gather copy cycle in taken into account.
1559 *
1560 * dest_swap
1561 * Treats destination memory organization as big-endian.
1562 * For each dword write (4 bytes), the byte 0 is swapped with
1563 * byte 3 and byte 1 is swapped with byte 2.
1564 * In case of gather field in first source ring entry of
1565 * the gather copy cycle in taken into account.
1566 *
1567 * gather
1568 * Enables gather of multiple copy engine source
1569 * descriptors to one destination.
1570 *
1571 * ce_res_0
1572 * Reserved
1573 *
1574 *
1575 * length
1576 * Length of the buffer in units of octets of the current
1577 * descriptor
1578 *
1579 * fw_metadata
1580 * Meta data used by FW.
1581 * In case of gather field in first source ring entry of
1582 * the gather copy cycle in taken into account.
1583 *
1584 * ce_res_1
1585 * Reserved
1586 *
1587 * ce_res_2
1588 * Reserved
1589 *
1590 * ring_id
1591 * The buffer pointer ring ID.
1592 * 0 refers to the IDLE ring
1593 * 1 - N refers to other rings
1594 * Helps with debugging when dumping ring contents.
1595 *
1596 * looping_count
1597 * A count value that indicates the number of times the
1598 * producer of entries into the Ring has looped around the
1599 * ring.
1600 *
1601 * At initialization time, this value is set to 0. On the
1602 * first loop, this value is set to 1. After the max value is
1603 * reached allowed by the number of bits for this field, the
1604 * count value continues with 0 again.
1605 *
1606 * In case SW is the consumer of the ring entries, it can
1607 * use this field to figure out up to where the producer of
1608 * entries has created new entries. This eliminates the need to
1609 * check where the head pointer' of the ring is located once
1610 * the SW starts processing an interrupt indicating that new
1611 * entries have been put into this ring...
1612 *
1613 * Also note that SW if it wants only needs to look at the
1614 * LSB bit of this count value.
1615 */
1616
1617#define HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0)
1618#define HAL_CE_DEST_DESC_ADDR_INFO_RING_ID GENMASK(27, 20)
1619#define HAL_CE_DEST_DESC_ADDR_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT
1620
1621struct hal_ce_srng_dest_desc {
1622 __le32 buffer_addr_low;
1623 __le32 buffer_addr_info; /* %HAL_CE_DEST_DESC_ADDR_INFO_ */
1624} __packed;
1625
1626/* hal_ce_srng_dest_desc
1627 *
1628 * dst_buffer_low
1629 * LSB 32 bits of the 40 Bit Pointer to the Destination
1630 * buffer
1631 *
1632 * dst_buffer_high
1633 * MSB 8 bits of the 40 Bit Pointer to the Destination
1634 * buffer
1635 *
1636 * ce_res_4
1637 * Reserved
1638 *
1639 * ring_id
1640 * The buffer pointer ring ID.
1641 * 0 refers to the IDLE ring
1642 * 1 - N refers to other rings
1643 * Helps with debugging when dumping ring contents.
1644 *
1645 * looping_count
1646 * A count value that indicates the number of times the
1647 * producer of entries into the Ring has looped around the
1648 * ring.
1649 *
1650 * At initialization time, this value is set to 0. On the
1651 * first loop, this value is set to 1. After the max value is
1652 * reached allowed by the number of bits for this field, the
1653 * count value continues with 0 again.
1654 *
1655 * In case SW is the consumer of the ring entries, it can
1656 * use this field to figure out up to where the producer of
1657 * entries has created new entries. This eliminates the need to
1658 * check where the head pointer' of the ring is located once
1659 * the SW starts processing an interrupt indicating that new
1660 * entries have been put into this ring...
1661 *
1662 * Also note that SW if it wants only needs to look at the
1663 * LSB bit of this count value.
1664 */
1665
1666#define HAL_CE_DST_STATUS_DESC_FLAGS_HASH_EN BIT(8)
1667#define HAL_CE_DST_STATUS_DESC_FLAGS_BYTE_SWAP BIT(9)
1668#define HAL_CE_DST_STATUS_DESC_FLAGS_DEST_SWAP BIT(10)
1669#define HAL_CE_DST_STATUS_DESC_FLAGS_GATHER BIT(11)
1670#define HAL_CE_DST_STATUS_DESC_FLAGS_LEN GENMASK(31, 16)
1671
1672#define HAL_CE_DST_STATUS_DESC_META_INFO_DATA GENMASK(15, 0)
1673#define HAL_CE_DST_STATUS_DESC_META_INFO_RING_ID GENMASK(27, 20)
1674#define HAL_CE_DST_STATUS_DESC_META_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT
1675
1676struct hal_ce_srng_dst_status_desc {
1677 __le32 flags; /* %HAL_CE_DST_STATUS_DESC_FLAGS_ */
1678 __le32 toeplitz_hash0;
1679 __le32 toeplitz_hash1;
1680 __le32 meta_info; /* HAL_CE_DST_STATUS_DESC_META_INFO_ */
1681} __packed;
1682
1683/* hal_ce_srng_dst_status_desc
1684 *
1685 * ce_res_5
1686 * Reserved
1687 *
1688 * toeplitz_en
1689 *
1690 * src_swap
1691 * Source memory buffer swapped
1692 *
1693 * dest_swap
1694 * Destination memory buffer swapped
1695 *
1696 * gather
1697 * Gather of multiple copy engine source descriptors to one
1698 * destination enabled
1699 *
1700 * ce_res_6
1701 * Reserved
1702 *
1703 * length
1704 * Sum of all the Lengths of the source descriptor in the
1705 * gather chain
1706 *
1707 * toeplitz_hash_0
1708 * 32 LS bits of 64 bit Toeplitz LFSR hash result
1709 *
1710 * toeplitz_hash_1
1711 * 32 MS bits of 64 bit Toeplitz LFSR hash result
1712 *
1713 * fw_metadata
1714 * Meta data used by FW
1715 * In case of gather field in first source ring entry of
1716 * the gather copy cycle in taken into account.
1717 *
1718 * ce_res_7
1719 * Reserved
1720 *
1721 * ring_id
1722 * The buffer pointer ring ID.
1723 * 0 refers to the IDLE ring
1724 * 1 - N refers to other rings
1725 * Helps with debugging when dumping ring contents.
1726 *
1727 * looping_count
1728 * A count value that indicates the number of times the
1729 * producer of entries into the Ring has looped around the
1730 * ring.
1731 *
1732 * At initialization time, this value is set to 0. On the
1733 * first loop, this value is set to 1. After the max value is
1734 * reached allowed by the number of bits for this field, the
1735 * count value continues with 0 again.
1736 *
1737 * In case SW is the consumer of the ring entries, it can
1738 * use this field to figure out up to where the producer of
1739 * entries has created new entries. This eliminates the need to
1740 * check where the head pointer' of the ring is located once
1741 * the SW starts processing an interrupt indicating that new
1742 * entries have been put into this ring...
1743 *
1744 * Also note that SW if it wants only needs to look at the
1745 * LSB bit of this count value.
1746 */
1747
1748#define HAL_TX_RATE_STATS_INFO0_VALID BIT(0)
1749#define HAL_TX_RATE_STATS_INFO0_BW GENMASK(3, 1)
1750#define HAL_TX_RATE_STATS_INFO0_PKT_TYPE GENMASK(7, 4)
1751#define HAL_TX_RATE_STATS_INFO0_STBC BIT(8)
1752#define HAL_TX_RATE_STATS_INFO0_LDPC BIT(9)
1753#define HAL_TX_RATE_STATS_INFO0_SGI GENMASK(11, 10)
1754#define HAL_TX_RATE_STATS_INFO0_MCS GENMASK(15, 12)
1755#define HAL_TX_RATE_STATS_INFO0_OFDMA_TX BIT(16)
1756#define HAL_TX_RATE_STATS_INFO0_TONES_IN_RU GENMASK(28, 17)
1757
1758enum hal_tx_rate_stats_bw {
1759 HAL_TX_RATE_STATS_BW_20,
1760 HAL_TX_RATE_STATS_BW_40,
1761 HAL_TX_RATE_STATS_BW_80,
1762 HAL_TX_RATE_STATS_BW_160,
1763};
1764
1765enum hal_tx_rate_stats_pkt_type {
1766 HAL_TX_RATE_STATS_PKT_TYPE_11A,
1767 HAL_TX_RATE_STATS_PKT_TYPE_11B,
1768 HAL_TX_RATE_STATS_PKT_TYPE_11N,
1769 HAL_TX_RATE_STATS_PKT_TYPE_11AC,
1770 HAL_TX_RATE_STATS_PKT_TYPE_11AX,
1771 HAL_TX_RATE_STATS_PKT_TYPE_11BA,
1772 HAL_TX_RATE_STATS_PKT_TYPE_11BE,
1773};
1774
1775enum hal_tx_rate_stats_sgi {
1776 HAL_TX_RATE_STATS_SGI_08US,
1777 HAL_TX_RATE_STATS_SGI_04US,
1778 HAL_TX_RATE_STATS_SGI_16US,
1779 HAL_TX_RATE_STATS_SGI_32US,
1780};
1781
1782struct hal_tx_rate_stats {
1783 __le32 info0;
1784 __le32 tsf;
1785} __packed;
1786
1787struct hal_wbm_link_desc {
1788 struct ath12k_buffer_addr buf_addr_info;
1789} __packed;
1790
1791/* hal_wbm_link_desc
1792 *
1793 * Producer: WBM
1794 * Consumer: WBM
1795 *
1796 * buf_addr_info
1797 * Details of the physical address of a buffer or MSDU
1798 * link descriptor.
1799 */
1800
1801enum hal_wbm_rel_src_module {
1802 HAL_WBM_REL_SRC_MODULE_TQM,
1803 HAL_WBM_REL_SRC_MODULE_RXDMA,
1804 HAL_WBM_REL_SRC_MODULE_REO,
1805 HAL_WBM_REL_SRC_MODULE_FW,
1806 HAL_WBM_REL_SRC_MODULE_SW,
1807};
1808
1809enum hal_wbm_rel_desc_type {
1810 HAL_WBM_REL_DESC_TYPE_REL_MSDU,
1811 HAL_WBM_REL_DESC_TYPE_MSDU_LINK,
1812 HAL_WBM_REL_DESC_TYPE_MPDU_LINK,
1813 HAL_WBM_REL_DESC_TYPE_MSDU_EXT,
1814 HAL_WBM_REL_DESC_TYPE_QUEUE_EXT,
1815};
1816
1817/* hal_wbm_rel_desc_type
1818 *
1819 * msdu_buffer
1820 * The address points to an MSDU buffer
1821 *
1822 * msdu_link_descriptor
1823 * The address points to an Tx MSDU link descriptor
1824 *
1825 * mpdu_link_descriptor
1826 * The address points to an MPDU link descriptor
1827 *
1828 * msdu_ext_descriptor
1829 * The address points to an MSDU extension descriptor
1830 *
1831 * queue_ext_descriptor
1832 * The address points to an TQM queue extension descriptor. WBM should
1833 * treat this is the same way as a link descriptor.
1834 */
1835
1836enum hal_wbm_rel_bm_act {
1837 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE,
1838 HAL_WBM_REL_BM_ACT_REL_MSDU,
1839};
1840
1841/* hal_wbm_rel_bm_act
1842 *
1843 * put_in_idle_list
1844 * Put the buffer or descriptor back in the idle list. In case of MSDU or
1845 * MDPU link descriptor, BM does not need to check to release any
1846 * individual MSDU buffers.
1847 *
1848 * release_msdu_list
1849 * This BM action can only be used in combination with desc_type being
1850 * msdu_link_descriptor. Field first_msdu_index points out which MSDU
1851 * pointer in the MSDU link descriptor is the first of an MPDU that is
1852 * released. BM shall release all the MSDU buffers linked to this first
1853 * MSDU buffer pointer. All related MSDU buffer pointer entries shall be
1854 * set to value 0, which represents the 'NULL' pointer. When all MSDU
1855 * buffer pointers in the MSDU link descriptor are 'NULL', the MSDU link
1856 * descriptor itself shall also be released.
1857 */
1858#define HAL_WBM_COMPL_RX_INFO0_REL_SRC_MODULE GENMASK(2, 0)
1859#define HAL_WBM_COMPL_RX_INFO0_BM_ACTION GENMASK(5, 3)
1860#define HAL_WBM_COMPL_RX_INFO0_DESC_TYPE GENMASK(8, 6)
1861#define HAL_WBM_COMPL_RX_INFO0_RBM GENMASK(12, 9)
1862#define HAL_WBM_COMPL_RX_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17)
1863#define HAL_WBM_COMPL_RX_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19)
1864#define HAL_WBM_COMPL_RX_INFO0_REO_PUSH_REASON GENMASK(25, 24)
1865#define HAL_WBM_COMPL_RX_INFO0_REO_ERROR_CODE GENMASK(30, 26)
1866#define HAL_WBM_COMPL_RX_INFO0_WBM_INTERNAL_ERROR BIT(31)
1867
1868#define HAL_WBM_COMPL_RX_INFO1_PHY_ADDR_HI GENMASK(7, 0)
1869#define HAL_WBM_COMPL_RX_INFO1_SW_COOKIE GENMASK(27, 8)
1870#define HAL_WBM_COMPL_RX_INFO1_LOOPING_COUNT GENMASK(31, 28)
1871
1872struct hal_wbm_completion_ring_rx {
1873 __le32 addr_lo;
1874 __le32 addr_hi;
1875 __le32 info0;
1876 struct rx_mpdu_desc rx_mpdu_info;
1877 struct rx_msdu_desc rx_msdu_info;
1878 __le32 phy_addr_lo;
1879 __le32 info1;
1880} __packed;
1881
1882#define HAL_WBM_COMPL_TX_INFO0_REL_SRC_MODULE GENMASK(2, 0)
1883#define HAL_WBM_COMPL_TX_INFO0_DESC_TYPE GENMASK(8, 6)
1884#define HAL_WBM_COMPL_TX_INFO0_RBM GENMASK(12, 9)
1885#define HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON GENMASK(16, 13)
1886#define HAL_WBM_COMPL_TX_INFO0_RBM_OVERRIDE_VLD BIT(17)
1887#define HAL_WBM_COMPL_TX_INFO0_SW_COOKIE_LO GENMASK(29, 18)
1888#define HAL_WBM_COMPL_TX_INFO0_CC_DONE BIT(30)
1889#define HAL_WBM_COMPL_TX_INFO0_WBM_INTERNAL_ERROR BIT(31)
1890
1891#define HAL_WBM_COMPL_TX_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0)
1892#define HAL_WBM_COMPL_TX_INFO1_TRANSMIT_COUNT GENMASK(30, 24)
1893#define HAL_WBM_COMPL_TX_INFO1_SW_REL_DETAILS_VALID BIT(31)
1894
1895#define HAL_WBM_COMPL_TX_INFO2_ACK_FRAME_RSSI GENMASK(7, 0)
1896#define HAL_WBM_COMPL_TX_INFO2_FIRST_MSDU BIT(8)
1897#define HAL_WBM_COMPL_TX_INFO2_LAST_MSDU BIT(9)
1898#define HAL_WBM_COMPL_TX_INFO2_FW_TX_NOTIF_FRAME GENMASK(12, 10)
1899#define HAL_WBM_COMPL_TX_INFO2_BUFFER_TIMESTAMP GENMASK(31, 13)
1900
1901#define HAL_WBM_COMPL_TX_INFO3_PEER_ID GENMASK(15, 0)
1902#define HAL_WBM_COMPL_TX_INFO3_TID GENMASK(19, 16)
1903#define HAL_WBM_COMPL_TX_INFO3_SW_COOKIE_HI GENMASK(27, 20)
1904#define HAL_WBM_COMPL_TX_INFO3_LOOPING_COUNT GENMASK(31, 28)
1905
1906struct hal_wbm_completion_ring_tx {
1907 __le32 buf_va_lo;
1908 __le32 buf_va_hi;
1909 __le32 info0;
1910 __le32 info1;
1911 __le32 info2;
1912 struct hal_tx_rate_stats rate_stats;
1913 __le32 info3;
1914} __packed;
1915
1916#define HAL_WBM_RELEASE_TX_INFO0_REL_SRC_MODULE GENMASK(2, 0)
1917#define HAL_WBM_RELEASE_TX_INFO0_BM_ACTION GENMASK(5, 3)
1918#define HAL_WBM_RELEASE_TX_INFO0_DESC_TYPE GENMASK(8, 6)
1919#define HAL_WBM_RELEASE_TX_INFO0_FIRST_MSDU_IDX GENMASK(12, 9)
1920#define HAL_WBM_RELEASE_TX_INFO0_TQM_RELEASE_REASON GENMASK(18, 13)
1921#define HAL_WBM_RELEASE_TX_INFO0_RBM_OVERRIDE_VLD BIT(17)
1922#define HAL_WBM_RELEASE_TX_INFO0_SW_BUFFER_COOKIE_11_0 GENMASK(29, 18)
1923#define HAL_WBM_RELEASE_TX_INFO0_WBM_INTERNAL_ERROR BIT(31)
1924
1925#define HAL_WBM_RELEASE_TX_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0)
1926#define HAL_WBM_RELEASE_TX_INFO1_TRANSMIT_COUNT GENMASK(30, 24)
1927#define HAL_WBM_RELEASE_TX_INFO1_SW_REL_DETAILS_VALID BIT(31)
1928
1929#define HAL_WBM_RELEASE_TX_INFO2_ACK_FRAME_RSSI GENMASK(7, 0)
1930#define HAL_WBM_RELEASE_TX_INFO2_FIRST_MSDU BIT(8)
1931#define HAL_WBM_RELEASE_TX_INFO2_LAST_MSDU BIT(9)
1932#define HAL_WBM_RELEASE_TX_INFO2_FW_TX_NOTIF_FRAME GENMASK(12, 10)
1933#define HAL_WBM_RELEASE_TX_INFO2_BUFFER_TIMESTAMP GENMASK(31, 13)
1934
1935#define HAL_WBM_RELEASE_TX_INFO3_PEER_ID GENMASK(15, 0)
1936#define HAL_WBM_RELEASE_TX_INFO3_TID GENMASK(19, 16)
1937#define HAL_WBM_RELEASE_TX_INFO3_SW_BUFFER_COOKIE_19_12 GENMASK(27, 20)
1938#define HAL_WBM_RELEASE_TX_INFO3_LOOPING_COUNT GENMASK(31, 28)
1939
1940struct hal_wbm_release_ring_tx {
1941 struct ath12k_buffer_addr buf_addr_info;
1942 __le32 info0;
1943 __le32 info1;
1944 __le32 info2;
1945 struct hal_tx_rate_stats rate_stats;
1946 __le32 info3;
1947} __packed;
1948
1949#define HAL_WBM_RELEASE_RX_INFO0_REL_SRC_MODULE GENMASK(2, 0)
1950#define HAL_WBM_RELEASE_RX_INFO0_BM_ACTION GENMASK(5, 3)
1951#define HAL_WBM_RELEASE_RX_INFO0_DESC_TYPE GENMASK(8, 6)
1952#define HAL_WBM_RELEASE_RX_INFO0_FIRST_MSDU_IDX GENMASK(12, 9)
1953#define HAL_WBM_RELEASE_RX_INFO0_CC_STATUS BIT(16)
1954#define HAL_WBM_RELEASE_RX_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17)
1955#define HAL_WBM_RELEASE_RX_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19)
1956#define HAL_WBM_RELEASE_RX_INFO0_REO_PUSH_REASON GENMASK(25, 24)
1957#define HAL_WBM_RELEASE_RX_INFO0_REO_ERROR_CODE GENMASK(30, 26)
1958#define HAL_WBM_RELEASE_RX_INFO0_WBM_INTERNAL_ERROR BIT(31)
1959
1960#define HAL_WBM_RELEASE_RX_INFO2_RING_ID GENMASK(27, 20)
1961#define HAL_WBM_RELEASE_RX_INFO2_LOOPING_COUNT GENMASK(31, 28)
1962
1963struct hal_wbm_release_ring_rx {
1964 struct ath12k_buffer_addr buf_addr_info;
1965 __le32 info0;
1966 struct rx_mpdu_desc rx_mpdu_info;
1967 struct rx_msdu_desc rx_msdu_info;
1968 __le32 info1;
1969 __le32 info2;
1970} __packed;
1971
1972#define HAL_WBM_RELEASE_RX_CC_INFO0_RBM GENMASK(12, 9)
1973#define HAL_WBM_RELEASE_RX_CC_INFO1_COOKIE GENMASK(27, 8)
1974/* Used when hw cc is success */
1975struct hal_wbm_release_ring_cc_rx {
1976 __le32 buf_va_lo;
1977 __le32 buf_va_hi;
1978 __le32 info0;
1979 struct rx_mpdu_desc rx_mpdu_info;
1980 struct rx_msdu_desc rx_msdu_info;
1981 __le32 buf_pa_lo;
1982 __le32 info1;
1983} __packed;
1984
1985#define HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE GENMASK(2, 0)
1986#define HAL_WBM_RELEASE_INFO0_BM_ACTION GENMASK(5, 3)
1987#define HAL_WBM_RELEASE_INFO0_DESC_TYPE GENMASK(8, 6)
1988#define HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17)
1989#define HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19)
1990#define HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON GENMASK(25, 24)
1991#define HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE GENMASK(30, 26)
1992#define HAL_WBM_RELEASE_INFO0_WBM_INTERNAL_ERROR BIT(31)
1993
1994#define HAL_WBM_RELEASE_INFO3_FIRST_MSDU BIT(0)
1995#define HAL_WBM_RELEASE_INFO3_LAST_MSDU BIT(1)
1996#define HAL_WBM_RELEASE_INFO3_CONTINUATION BIT(2)
1997
1998#define HAL_WBM_RELEASE_INFO5_LOOPING_COUNT GENMASK(31, 28)
1999
2000struct hal_wbm_release_ring {
2001 struct ath12k_buffer_addr buf_addr_info;
2002 __le32 info0;
2003 __le32 info1;
2004 __le32 info2;
2005 __le32 info3;
2006 __le32 info4;
2007 __le32 info5;
2008} __packed;
2009
2010/* hal_wbm_release_ring
2011 *
2012 * Producer: SW/TQM/RXDMA/REO/SWITCH
2013 * Consumer: WBM/SW/FW
2014 *
2015 * HTT tx status is overlaid on wbm_release ring on 4-byte words 2, 3, 4 and 5
2016 * for software based completions.
2017 *
2018 * buf_addr_info
2019 * Details of the physical address of the buffer or link descriptor.
2020 *
2021 * release_source_module
2022 * Indicates which module initiated the release of this buffer/descriptor.
2023 * Values are defined in enum %HAL_WBM_REL_SRC_MODULE_.
2024 *
2025 * buffer_or_desc_type
2026 * Field only valid when WBM is marked as the return_buffer_manager in
2027 * the Released_Buffer_address_info. Indicates that type of buffer or
2028 * descriptor is being released. Values are in enum %HAL_WBM_REL_DESC_TYPE.
2029 *
2030 * wbm_internal_error
2031 * Is set when WBM got a buffer pointer but the action was to push it to
2032 * the idle link descriptor ring or do link related activity OR
2033 * Is set when WBM got a link buffer pointer but the action was to push it
2034 * to the buffer descriptor ring.
2035 *
2036 * looping_count
2037 * A count value that indicates the number of times the
2038 * producer of entries into the Buffer Manager Ring has looped
2039 * around the ring.
2040 *
2041 * At initialization time, this value is set to 0. On the
2042 * first loop, this value is set to 1. After the max value is
2043 * reached allowed by the number of bits for this field, the
2044 * count value continues with 0 again.
2045 *
2046 * In case SW is the consumer of the ring entries, it can
2047 * use this field to figure out up to where the producer of
2048 * entries has created new entries. This eliminates the need to
2049 * check where the head pointer' of the ring is located once
2050 * the SW starts processing an interrupt indicating that new
2051 * entries have been put into this ring...
2052 *
2053 * Also note that SW if it wants only needs to look at the
2054 * LSB bit of this count value.
2055 */
2056
2057/**
2058 * enum hal_wbm_tqm_rel_reason - TQM release reason code
2059 * @HAL_WBM_TQM_REL_REASON_FRAME_ACKED: ACK or BACK received for the frame
2060 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU: Command remove_mpdus initiated by SW
2061 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX: Command remove transmitted_mpdus
2062 * initiated by sw.
2063 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX: Command remove untransmitted_mpdus
2064 * initiated by sw.
2065 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES: Command remove aged msdus or
2066 * mpdus.
2067 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1: Remove command initiated by
2068 * fw with fw_reason1.
2069 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2: Remove command initiated by
2070 * fw with fw_reason2.
2071 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3: Remove command initiated by
2072 * fw with fw_reason3.
2073 * @HAL_WBM_TQM_REL_REASON_CMD_DISABLE_QUEUE: Remove command initiated by
2074 * fw with disable queue.
2075 * @HAL_WBM_TQM_REL_REASON_CMD_TILL_NONMATCHING: Remove command initiated by
2076 * fw to remove all mpdu until 1st non-match.
2077 * @HAL_WBM_TQM_REL_REASON_DROP_THRESHOLD: Dropped due to drop threshold
2078 * criteria
2079 * @HAL_WBM_TQM_REL_REASON_DROP_LINK_DESC_UNAVAIL: Dropped due to link desc
2080 * not available
2081 * @HAL_WBM_TQM_REL_REASON_DROP_OR_INVALID_MSDU: Dropped due drop bit set or
2082 * null flow
2083 * @HAL_WBM_TQM_REL_REASON_MULTICAST_DROP: Dropped due mcast drop set for VDEV
2084 * @HAL_WBM_TQM_REL_REASON_VDEV_MISMATCH_DROP: Dropped due to being set with
2085 * 'TCL_drop_reason'
2086 */
2087enum hal_wbm_tqm_rel_reason {
2088 HAL_WBM_TQM_REL_REASON_FRAME_ACKED,
2089 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU,
2090 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX,
2091 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX,
2092 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES,
2093 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1,
2094 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2,
2095 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3,
2096 HAL_WBM_TQM_REL_REASON_CMD_DISABLE_QUEUE,
2097 HAL_WBM_TQM_REL_REASON_CMD_TILL_NONMATCHING,
2098 HAL_WBM_TQM_REL_REASON_DROP_THRESHOLD,
2099 HAL_WBM_TQM_REL_REASON_DROP_LINK_DESC_UNAVAIL,
2100 HAL_WBM_TQM_REL_REASON_DROP_OR_INVALID_MSDU,
2101 HAL_WBM_TQM_REL_REASON_MULTICAST_DROP,
2102 HAL_WBM_TQM_REL_REASON_VDEV_MISMATCH_DROP,
2103};
2104
2105struct hal_wbm_buffer_ring {
2106 struct ath12k_buffer_addr buf_addr_info;
2107};
2108
2109enum hal_mon_end_reason {
2110 HAL_MON_STATUS_BUFFER_FULL,
2111 HAL_MON_FLUSH_DETECTED,
2112 HAL_MON_END_OF_PPDU,
2113 HAL_MON_PPDU_TRUNCATED,
2114};
2115
2116#define HAL_SW_MONITOR_RING_INFO0_RXDMA_PUSH_REASON GENMASK(1, 0)
2117#define HAL_SW_MONITOR_RING_INFO0_RXDMA_ERROR_CODE GENMASK(6, 2)
2118#define HAL_SW_MONITOR_RING_INFO0_MPDU_FRAGMENT_NUMBER GENMASK(10, 7)
2119#define HAL_SW_MONITOR_RING_INFO0_FRAMELESS_BAR BIT(11)
2120#define HAL_SW_MONITOR_RING_INFO0_STATUS_BUF_COUNT GENMASK(15, 12)
2121#define HAL_SW_MONITOR_RING_INFO0_END_OF_PPDU BIT(16)
2122
2123#define HAL_SW_MONITOR_RING_INFO1_PHY_PPDU_ID GENMASK(15, 0)
2124#define HAL_SW_MONITOR_RING_INFO1_RING_ID GENMASK(27, 20)
2125#define HAL_SW_MONITOR_RING_INFO1_LOOPING_COUNT GENMASK(31, 28)
2126
2127struct hal_sw_monitor_ring {
2128 struct ath12k_buffer_addr buf_addr_info;
2129 struct rx_mpdu_desc rx_mpdu_info;
2130 struct ath12k_buffer_addr status_buff_addr_info;
2131 __le32 info0; /* %HAL_SW_MONITOR_RING_INFO0 */
2132 __le32 info1; /* %HAL_SW_MONITOR_RING_INFO1 */
2133} __packed;
2134
2135/* hal_sw_monitor_ring
2136 *
2137 * Producer: RXDMA
2138 * Consumer: REO/SW/FW
2139 * buf_addr_info
2140 * Details of the physical address of a buffer or MSDU
2141 * link descriptor.
2142 *
2143 * rx_mpdu_info
2144 * Details related to the MPDU being pushed to SW, valid
2145 * only if end_of_ppdu is set to 0.
2146 *
2147 * status_buff_addr_info
2148 * Details of the physical address of the first status
2149 * buffer used for the PPDU (either the PPDU that included the
2150 * MPDU being pushed to SW if end_of_ppdu = 0, or the PPDU
2151 * whose end is indicated through end_of_ppdu = 1)
2152 *
2153 * rxdma_push_reason
2154 * Indicates why RXDMA pushed the frame to this ring
2155 *
2156 * <enum 0 rxdma_error_detected> RXDMA detected an error an
2157 * pushed this frame to this queue
2158 *
2159 * <enum 1 rxdma_routing_instruction> RXDMA pushed the
2160 * frame to this queue per received routing instructions. No
2161 * error within RXDMA was detected
2162 *
2163 * <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a
2164 * result the MSDU link descriptor might not have the
2165 * last_msdu_in_mpdu_flag set, but instead WBM might just see a
2166 * NULL pointer in the MSDU link descriptor. This is to be
2167 * considered a normal condition for this scenario.
2168 *
2169 * rxdma_error_code
2170 * Field only valid when rxdma_push_reason is set to
2171 * 'rxdma_error_detected.'
2172 *
2173 * <enum 0 rxdma_overflow_err>MPDU frame is not complete
2174 * due to a FIFO overflow error in RXPCU.
2175 *
2176 * <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
2177 * due to receiving incomplete MPDU from the PHY
2178 *
2179 * <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
2180 * error or CRYPTO received an encrypted frame, but did not get
2181 * a valid corresponding key id in the peer entry.
2182 *
2183 * <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
2184 * error
2185 *
2186 * <enum 5 rxdma_unecrypted_err>CRYPTO reported an
2187 * unencrypted frame error when encrypted was expected
2188 *
2189 * <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
2190 * length error
2191 *
2192 * <enum 7 rxdma_msdu_limit_err>RX OLE reported that max
2193 * number of MSDUs allowed in an MPDU got exceeded
2194 *
2195 * <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
2196 * error
2197 *
2198 * <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
2199 * parsing error
2200 *
2201 * <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
2202 * during SA search
2203 *
2204 * <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
2205 * during DA search
2206 *
2207 * <enum 12 rxdma_flow_timeout_err>RX OLE reported a
2208 * timeout during flow search
2209 *
2210 * <enum 13 rxdma_flush_request>RXDMA received a flush
2211 * request
2212 *
2213 * <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU
2214 * present as well as a fragmented MPDU.
2215 *
2216 * mpdu_fragment_number
2217 * Field only valid when Reo_level_mpdu_frame_info.
2218 * Rx_mpdu_desc_info_details.Fragment_flag is set and
2219 * end_of_ppdu is set to 0.
2220 *
2221 * The fragment number from the 802.11 header.
2222 *
2223 * Note that the sequence number is embedded in the field:
2224 * Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details.
2225 * Mpdu_sequence_number
2226 *
2227 * frameless_bar
2228 * When set, this SW monitor ring struct contains BAR info
2229 * from a multi TID BAR frame. The original multi TID BAR frame
2230 * itself contained all the REO info for the first TID, but all
2231 * the subsequent TID info and their linkage to the REO
2232 * descriptors is passed down as 'frameless' BAR info.
2233 *
2234 * The only fields valid in this descriptor when this bit
2235 * is within the
2236 *
2237 * Reo_level_mpdu_frame_info:
2238 * Within Rx_mpdu_desc_info_details:
2239 * Mpdu_Sequence_number
2240 * BAR_frame
2241 * Peer_meta_data
2242 * All other fields shall be set to 0.
2243 *
2244 * status_buf_count
2245 * A count of status buffers used so far for the PPDU
2246 * (either the PPDU that included the MPDU being pushed to SW
2247 * if end_of_ppdu = 0, or the PPDU whose end is indicated
2248 * through end_of_ppdu = 1)
2249 *
2250 * end_of_ppdu
2251 * Some hw RXDMA can be configured to generate a separate
2252 * 'SW_MONITOR_RING' descriptor at the end of a PPDU (either
2253 * through an 'RX_PPDU_END' TLV or through an 'RX_FLUSH') to
2254 * demarcate PPDUs.
2255 *
2256 * For such a descriptor, this bit is set to 1 and fields
2257 * Reo_level_mpdu_frame_info, mpdu_fragment_number and
2258 * Frameless_bar are all set to 0.
2259 *
2260 * Otherwise this bit is set to 0.
2261 *
2262 * phy_ppdu_id
2263 * A PPDU counter value that PHY increments for every PPDU
2264 * received
2265 *
2266 * The counter value wraps around. Some hw RXDMA can be
2267 * configured to copy this from the RX_PPDU_START TLV for every
2268 * output descriptor.
2269 *
2270 * ring_id
2271 * For debugging.
2272 * This field is filled in by the SRNG module.
2273 * It help to identify the ring that is being looked
2274 *
2275 * looping_count
2276 * For debugging.
2277 * This field is filled in by the SRNG module.
2278 *
2279 * A count value that indicates the number of times the
2280 * producer of entries into this Ring has looped around the
2281 * ring.
2282 * At initialization time, this value is set to 0. On the
2283 * first loop, this value is set to 1. After the max value is
2284 * reached allowed by the number of bits for this field, the
2285 * count value continues with 0 again.
2286 *
2287 * In case SW is the consumer of the ring entries, it can
2288 * use this field to figure out up to where the producer of
2289 * entries has created new entries. This eliminates the need to
2290 * check where the head pointer' of the ring is located once
2291 * the SW starts processing an interrupt indicating that new
2292 * entries have been put into this ring...
2293 */
2294
2295enum hal_desc_owner {
2296 HAL_DESC_OWNER_WBM,
2297 HAL_DESC_OWNER_SW,
2298 HAL_DESC_OWNER_TQM,
2299 HAL_DESC_OWNER_RXDMA,
2300 HAL_DESC_OWNER_REO,
2301 HAL_DESC_OWNER_SWITCH,
2302};
2303
2304enum hal_desc_buf_type {
2305 HAL_DESC_BUF_TYPE_TX_MSDU_LINK,
2306 HAL_DESC_BUF_TYPE_TX_MPDU_LINK,
2307 HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_HEAD,
2308 HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_EXT,
2309 HAL_DESC_BUF_TYPE_TX_FLOW,
2310 HAL_DESC_BUF_TYPE_TX_BUFFER,
2311 HAL_DESC_BUF_TYPE_RX_MSDU_LINK,
2312 HAL_DESC_BUF_TYPE_RX_MPDU_LINK,
2313 HAL_DESC_BUF_TYPE_RX_REO_QUEUE,
2314 HAL_DESC_BUF_TYPE_RX_REO_QUEUE_EXT,
2315 HAL_DESC_BUF_TYPE_RX_BUFFER,
2316 HAL_DESC_BUF_TYPE_IDLE_LINK,
2317};
2318
2319#define HAL_DESC_REO_OWNED 4
2320#define HAL_DESC_REO_QUEUE_DESC 8
2321#define HAL_DESC_REO_QUEUE_EXT_DESC 9
2322#define HAL_DESC_REO_NON_QOS_TID 16
2323
2324#define HAL_DESC_HDR_INFO0_OWNER GENMASK(3, 0)
2325#define HAL_DESC_HDR_INFO0_BUF_TYPE GENMASK(7, 4)
2326#define HAL_DESC_HDR_INFO0_DBG_RESERVED GENMASK(31, 8)
2327
2328struct hal_desc_header {
2329 __le32 info0;
2330} __packed;
2331
2332struct hal_rx_mpdu_link_ptr {
2333 struct ath12k_buffer_addr addr_info;
2334} __packed;
2335
2336struct hal_rx_msdu_details {
2337 struct ath12k_buffer_addr buf_addr_info;
2338 struct rx_msdu_desc rx_msdu_info;
2339 struct rx_msdu_ext_desc rx_msdu_ext_info;
2340} __packed;
2341
2342#define HAL_RX_MSDU_LNK_INFO0_RX_QUEUE_NUMBER GENMASK(15, 0)
2343#define HAL_RX_MSDU_LNK_INFO0_FIRST_MSDU_LNK BIT(16)
2344
2345struct hal_rx_msdu_link {
2346 struct hal_desc_header desc_hdr;
2347 struct ath12k_buffer_addr buf_addr_info;
2348 __le32 info0;
2349 __le32 pn[4];
2350 struct hal_rx_msdu_details msdu_link[6];
2351} __packed;
2352
2353struct hal_rx_reo_queue_ext {
2354 struct hal_desc_header desc_hdr;
2355 __le32 rsvd;
2356 struct hal_rx_mpdu_link_ptr mpdu_link[15];
2357} __packed;
2358
2359/* hal_rx_reo_queue_ext
2360 * Consumer: REO
2361 * Producer: REO
2362 *
2363 * descriptor_header
2364 * Details about which module owns this struct.
2365 *
2366 * mpdu_link
2367 * Pointer to the next MPDU_link descriptor in the MPDU queue.
2368 */
2369
2370enum hal_rx_reo_queue_pn_size {
2371 HAL_RX_REO_QUEUE_PN_SIZE_24,
2372 HAL_RX_REO_QUEUE_PN_SIZE_48,
2373 HAL_RX_REO_QUEUE_PN_SIZE_128,
2374};
2375
2376#define HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER GENMASK(15, 0)
2377
2378#define HAL_RX_REO_QUEUE_INFO0_VLD BIT(0)
2379#define HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER GENMASK(2, 1)
2380#define HAL_RX_REO_QUEUE_INFO0_DIS_DUP_DETECTION BIT(3)
2381#define HAL_RX_REO_QUEUE_INFO0_SOFT_REORDER_EN BIT(4)
2382#define HAL_RX_REO_QUEUE_INFO0_AC GENMASK(6, 5)
2383#define HAL_RX_REO_QUEUE_INFO0_BAR BIT(7)
2384#define HAL_RX_REO_QUEUE_INFO0_RETRY BIT(8)
2385#define HAL_RX_REO_QUEUE_INFO0_CHECK_2K_MODE BIT(9)
2386#define HAL_RX_REO_QUEUE_INFO0_OOR_MODE BIT(10)
2387#define HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE GENMASK(20, 11)
2388#define HAL_RX_REO_QUEUE_INFO0_PN_CHECK BIT(21)
2389#define HAL_RX_REO_QUEUE_INFO0_EVEN_PN BIT(22)
2390#define HAL_RX_REO_QUEUE_INFO0_UNEVEN_PN BIT(23)
2391#define HAL_RX_REO_QUEUE_INFO0_PN_HANDLE_ENABLE BIT(24)
2392#define HAL_RX_REO_QUEUE_INFO0_PN_SIZE GENMASK(26, 25)
2393#define HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG BIT(27)
2394
2395#define HAL_RX_REO_QUEUE_INFO1_SVLD BIT(0)
2396#define HAL_RX_REO_QUEUE_INFO1_SSN GENMASK(12, 1)
2397#define HAL_RX_REO_QUEUE_INFO1_CURRENT_IDX GENMASK(22, 13)
2398#define HAL_RX_REO_QUEUE_INFO1_SEQ_2K_ERR BIT(23)
2399#define HAL_RX_REO_QUEUE_INFO1_PN_ERR BIT(24)
2400#define HAL_RX_REO_QUEUE_INFO1_PN_VALID BIT(31)
2401
2402#define HAL_RX_REO_QUEUE_INFO2_MPDU_COUNT GENMASK(6, 0)
2403#define HAL_RX_REO_QUEUE_INFO2_MSDU_COUNT (31, 7)
2404
2405#define HAL_RX_REO_QUEUE_INFO3_TIMEOUT_COUNT GENMASK(9, 4)
2406#define HAL_RX_REO_QUEUE_INFO3_FWD_DUE_TO_BAR_CNT GENMASK(15, 10)
2407#define HAL_RX_REO_QUEUE_INFO3_DUPLICATE_COUNT GENMASK(31, 16)
2408
2409#define HAL_RX_REO_QUEUE_INFO4_FRAME_IN_ORD_COUNT GENMASK(23, 0)
2410#define HAL_RX_REO_QUEUE_INFO4_BAR_RECVD_COUNT GENMASK(31, 24)
2411
2412#define HAL_RX_REO_QUEUE_INFO5_LATE_RX_MPDU_COUNT GENMASK(11, 0)
2413#define HAL_RX_REO_QUEUE_INFO5_WINDOW_JUMP_2K GENMASK(15, 12)
2414#define HAL_RX_REO_QUEUE_INFO5_HOLE_COUNT GENMASK(31, 16)
2415
2416struct hal_rx_reo_queue {
2417 struct hal_desc_header desc_hdr;
2418 __le32 rx_queue_num;
2419 __le32 info0;
2420 __le32 info1;
2421 __le32 pn[4];
2422 __le32 last_rx_enqueue_timestamp;
2423 __le32 last_rx_dequeue_timestamp;
2424 __le32 next_aging_queue[2];
2425 __le32 prev_aging_queue[2];
2426 __le32 rx_bitmap[9];
2427 __le32 info2;
2428 __le32 info3;
2429 __le32 info4;
2430 __le32 processed_mpdus;
2431 __le32 processed_msdus;
2432 __le32 processed_total_bytes;
2433 __le32 info5;
2434 __le32 rsvd[2];
2435 struct hal_rx_reo_queue_ext ext_desc[];
2436} __packed;
2437
2438/* hal_rx_reo_queue
2439 *
2440 * descriptor_header
2441 * Details about which module owns this struct. Note that sub field
2442 * Buffer_type shall be set to receive_reo_queue_descriptor.
2443 *
2444 * receive_queue_number
2445 * Indicates the MPDU queue ID to which this MPDU link descriptor belongs.
2446 *
2447 * vld
2448 * Valid bit indicating a session is established and the queue descriptor
2449 * is valid.
2450 * associated_link_descriptor_counter
2451 * Indicates which of the 3 link descriptor counters shall be incremented
2452 * or decremented when link descriptors are added or removed from this
2453 * flow queue.
2454 * disable_duplicate_detection
2455 * When set, do not perform any duplicate detection.
2456 * soft_reorder_enable
2457 * When set, REO has been instructed to not perform the actual re-ordering
2458 * of frames for this queue, but just to insert the reorder opcodes.
2459 * ac
2460 * Indicates the access category of the queue descriptor.
2461 * bar
2462 * Indicates if BAR has been received.
2463 * retry
2464 * Retry bit is checked if this bit is set.
2465 * chk_2k_mode
2466 * Indicates what type of operation is expected from Reo when the received
2467 * frame SN falls within the 2K window.
2468 * oor_mode
2469 * Indicates what type of operation is expected when the received frame
2470 * falls within the OOR window.
2471 * ba_window_size
2472 * Indicates the negotiated (window size + 1). Max of 256 bits.
2473 *
2474 * A value 255 means 256 bitmap, 63 means 64 bitmap, 0 (means non-BA
2475 * session, with window size of 0). The 3 values here are the main values
2476 * validated, but other values should work as well.
2477 *
2478 * A BA window size of 0 (=> one frame entry bitmat), means that there is
2479 * no additional rx_reo_queue_ext desc. following rx_reo_queue in memory.
2480 * A BA window size of 1 - 105, means that there is 1 rx_reo_queue_ext.
2481 * A BA window size of 106 - 210, means that there are 2 rx_reo_queue_ext.
2482 * A BA window size of 211 - 256, means that there are 3 rx_reo_queue_ext.
2483 * pn_check_needed, pn_shall_be_even, pn_shall_be_uneven, pn_handling_enable,
2484 * pn_size
2485 * REO shall perform the PN increment check, even number check, uneven
2486 * number check, PN error check and size of the PN field check.
2487 * ignore_ampdu_flag
2488 * REO shall ignore the ampdu_flag on entrance descriptor for this queue.
2489 *
2490 * svld
2491 * Sequence number in next field is valid one.
2492 * ssn
2493 * Starting Sequence number of the session.
2494 * current_index
2495 * Points to last forwarded packet
2496 * seq_2k_error_detected_flag
2497 * REO has detected a 2k error jump in the sequence number and from that
2498 * moment forward, all new frames are forwarded directly to FW, without
2499 * duplicate detect, reordering, etc.
2500 * pn_error_detected_flag
2501 * REO has detected a PN error.
2502 */
2503
2504#define HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
2505#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM BIT(8)
2506#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD BIT(9)
2507#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT BIT(10)
2508#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION BIT(11)
2509#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN BIT(12)
2510#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC BIT(13)
2511#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR BIT(14)
2512#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY BIT(15)
2513#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE BIT(16)
2514#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE BIT(17)
2515#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE BIT(18)
2516#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK BIT(19)
2517#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN BIT(20)
2518#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN BIT(21)
2519#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE BIT(22)
2520#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE BIT(23)
2521#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG BIT(24)
2522#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD BIT(25)
2523#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN BIT(26)
2524#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR BIT(27)
2525#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_ERR BIT(28)
2526#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID BIT(29)
2527#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN BIT(30)
2528
2529#define HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER GENMASK(15, 0)
2530#define HAL_REO_UPD_RX_QUEUE_INFO1_VLD BIT(16)
2531#define HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER GENMASK(18, 17)
2532#define HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION BIT(19)
2533#define HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN BIT(20)
2534#define HAL_REO_UPD_RX_QUEUE_INFO1_AC GENMASK(22, 21)
2535#define HAL_REO_UPD_RX_QUEUE_INFO1_BAR BIT(23)
2536#define HAL_REO_UPD_RX_QUEUE_INFO1_RETRY BIT(24)
2537#define HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE BIT(25)
2538#define HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE BIT(26)
2539#define HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK BIT(27)
2540#define HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN BIT(28)
2541#define HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN BIT(29)
2542#define HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE BIT(30)
2543#define HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG BIT(31)
2544
2545#define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE GENMASK(9, 0)
2546#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE GENMASK(11, 10)
2547#define HAL_REO_UPD_RX_QUEUE_INFO2_SVLD BIT(12)
2548#define HAL_REO_UPD_RX_QUEUE_INFO2_SSN GENMASK(24, 13)
2549#define HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR BIT(25)
2550#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR BIT(26)
2551#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_VALID BIT(27)
2552
2553struct hal_reo_update_rx_queue {
2554 struct hal_reo_cmd_hdr cmd;
2555 __le32 queue_addr_lo;
2556 __le32 info0;
2557 __le32 info1;
2558 __le32 info2;
2559 __le32 pn[4];
2560} __packed;
2561
2562struct hal_rx_reo_queue_1k {
2563 struct hal_desc_header desc_hdr;
2564 __le32 rx_bitmap_1023_288[23];
2565 __le32 reserved[8];
2566} __packed;
2567
2568#define HAL_REO_UNBLOCK_CACHE_INFO0_UNBLK_CACHE BIT(0)
2569#define HAL_REO_UNBLOCK_CACHE_INFO0_RESOURCE_IDX GENMASK(2, 1)
2570
2571struct hal_reo_unblock_cache {
2572 struct hal_reo_cmd_hdr cmd;
2573 __le32 info0;
2574 __le32 rsvd[7];
2575} __packed;
2576
2577enum hal_reo_exec_status {
2578 HAL_REO_EXEC_STATUS_SUCCESS,
2579 HAL_REO_EXEC_STATUS_BLOCKED,
2580 HAL_REO_EXEC_STATUS_FAILED,
2581 HAL_REO_EXEC_STATUS_RESOURCE_BLOCKED,
2582};
2583
2584#define HAL_REO_STATUS_HDR_INFO0_STATUS_NUM GENMASK(15, 0)
2585#define HAL_REO_STATUS_HDR_INFO0_EXEC_TIME GENMASK(25, 16)
2586#define HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS GENMASK(27, 26)
2587
2588struct hal_reo_status_hdr {
2589 __le32 info0;
2590 __le32 timestamp;
2591} __packed;
2592
2593/* hal_reo_status_hdr
2594 * Producer: REO
2595 * Consumer: SW
2596 *
2597 * status_num
2598 * The value in this field is equal to value of the reo command
2599 * number. This field helps to correlate the statuses with the REO
2600 * commands.
2601 *
2602 * execution_time (in us)
2603 * The amount of time REO took to execute the command. Note that
2604 * this time does not include the duration of the command waiting
2605 * in the command ring, before the execution started.
2606 *
2607 * execution_status
2608 * Execution status of the command. Values are defined in
2609 * enum %HAL_REO_EXEC_STATUS_.
2610 */
2611#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN GENMASK(11, 0)
2612#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX GENMASK(21, 12)
2613
2614#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT GENMASK(6, 0)
2615#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT GENMASK(31, 7)
2616
2617#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_WINDOW_JMP2K GENMASK(3, 0)
2618#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT GENMASK(9, 4)
2619#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT GENMASK(15, 10)
2620#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT GENMASK(31, 16)
2621
2622#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT GENMASK(23, 0)
2623#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT GENMASK(31, 24)
2624
2625#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU GENMASK(11, 0)
2626#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT GENMASK(27, 12)
2627
2628#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT GENMASK(31, 28)
2629
2630struct hal_reo_get_queue_stats_status {
2631 struct hal_reo_status_hdr hdr;
2632 __le32 info0;
2633 __le32 pn[4];
2634 __le32 last_rx_enqueue_timestamp;
2635 __le32 last_rx_dequeue_timestamp;
2636 __le32 rx_bitmap[9];
2637 __le32 info1;
2638 __le32 info2;
2639 __le32 info3;
2640 __le32 num_mpdu_frames;
2641 __le32 num_msdu_frames;
2642 __le32 total_bytes;
2643 __le32 info4;
2644 __le32 info5;
2645} __packed;
2646
2647/* hal_reo_get_queue_stats_status
2648 * Producer: REO
2649 * Consumer: SW
2650 *
2651 * status_hdr
2652 * Details that can link this status with the original command. It
2653 * also contains info on how long REO took to execute this command.
2654 *
2655 * ssn
2656 * Starting Sequence number of the session, this changes whenever
2657 * window moves (can be filled by SW then maintained by REO).
2658 *
2659 * current_index
2660 * Points to last forwarded packet.
2661 *
2662 * pn
2663 * Bits of the PN number.
2664 *
2665 * last_rx_enqueue_timestamp
2666 * last_rx_dequeue_timestamp
2667 * Timestamp of arrival of the last MPDU for this queue and
2668 * Timestamp of forwarding an MPDU accordingly.
2669 *
2670 * rx_bitmap
2671 * When a bit is set, the corresponding frame is currently held
2672 * in the re-order queue. The bitmap is Fully managed by HW.
2673 *
2674 * current_mpdu_count
2675 * current_msdu_count
2676 * The number of MPDUs and MSDUs in the queue.
2677 *
2678 * timeout_count
2679 * The number of times REO started forwarding frames even though
2680 * there is a hole in the bitmap. Forwarding reason is timeout.
2681 *
2682 * forward_due_to_bar_count
2683 * The number of times REO started forwarding frames even though
2684 * there is a hole in the bitmap. Fwd reason is reception of BAR.
2685 *
2686 * duplicate_count
2687 * The number of duplicate frames that have been detected.
2688 *
2689 * frames_in_order_count
2690 * The number of frames that have been received in order (without
2691 * a hole that prevented them from being forwarded immediately).
2692 *
2693 * bar_received_count
2694 * The number of times a BAR frame is received.
2695 *
2696 * mpdu_frames_processed_count
2697 * msdu_frames_processed_count
2698 * The total number of MPDU/MSDU frames that have been processed.
2699 *
2700 * total_bytes
2701 * An approximation of the number of bytes received for this queue.
2702 *
2703 * late_receive_mpdu_count
2704 * The number of MPDUs received after the window had already moved
2705 * on. The 'late' sequence window is defined as
2706 * (Window SSN - 256) - (Window SSN - 1).
2707 *
2708 * window_jump_2k
2709 * The number of times the window moved more than 2K
2710 *
2711 * hole_count
2712 * The number of times a hole was created in the receive bitmap.
2713 *
2714 * looping_count
2715 * A count value that indicates the number of times the producer of
2716 * entries into this Ring has looped around the ring.
2717 */
2718
2719#define HAL_REO_STATUS_LOOP_CNT GENMASK(31, 28)
2720
2721#define HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED BIT(0)
2722#define HAL_REO_FLUSH_QUEUE_INFO0_RSVD GENMASK(31, 1)
2723#define HAL_REO_FLUSH_QUEUE_INFO1_RSVD GENMASK(27, 0)
2724
2725struct hal_reo_flush_queue_status {
2726 struct hal_reo_status_hdr hdr;
2727 __le32 info0;
2728 __le32 rsvd0[21];
2729 __le32 info1;
2730} __packed;
2731
2732/* hal_reo_flush_queue_status
2733 * Producer: REO
2734 * Consumer: SW
2735 *
2736 * status_hdr
2737 * Details that can link this status with the original command. It
2738 * also contains info on how long REO took to execute this command.
2739 *
2740 * error_detected
2741 * Status of blocking resource
2742 *
2743 * 0 - No error has been detected while executing this command
2744 * 1 - Error detected. The resource to be used for blocking was
2745 * already in use.
2746 *
2747 * looping_count
2748 * A count value that indicates the number of times the producer of
2749 * entries into this Ring has looped around the ring.
2750 */
2751
2752#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR BIT(0)
2753#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE GENMASK(2, 1)
2754#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT BIT(8)
2755#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE GENMASK(11, 9)
2756#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID GENMASK(15, 12)
2757#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR GENMASK(17, 16)
2758#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT GENMASK(25, 18)
2759
2760struct hal_reo_flush_cache_status {
2761 struct hal_reo_status_hdr hdr;
2762 __le32 info0;
2763 __le32 rsvd0[21];
2764 __le32 info1;
2765} __packed;
2766
2767/* hal_reo_flush_cache_status
2768 * Producer: REO
2769 * Consumer: SW
2770 *
2771 * status_hdr
2772 * Details that can link this status with the original command. It
2773 * also contains info on how long REO took to execute this command.
2774 *
2775 * error_detected
2776 * Status for blocking resource handling
2777 *
2778 * 0 - No error has been detected while executing this command
2779 * 1 - An error in the blocking resource management was detected
2780 *
2781 * block_error_details
2782 * only valid when error_detected is set
2783 *
2784 * 0 - No blocking related errors found
2785 * 1 - Blocking resource is already in use
2786 * 2 - Resource requested to be unblocked, was not blocked
2787 *
2788 * cache_controller_flush_status_hit
2789 * The status that the cache controller returned on executing the
2790 * flush command.
2791 *
2792 * 0 - miss; 1 - hit
2793 *
2794 * cache_controller_flush_status_desc_type
2795 * Flush descriptor type
2796 *
2797 * cache_controller_flush_status_client_id
2798 * Module who made the flush request
2799 *
2800 * In REO, this is always 0
2801 *
2802 * cache_controller_flush_status_error
2803 * Error condition
2804 *
2805 * 0 - No error found
2806 * 1 - HW interface is still busy
2807 * 2 - Line currently locked. Used for one line flush command
2808 * 3 - At least one line is still locked.
2809 * Used for cache flush command.
2810 *
2811 * cache_controller_flush_count
2812 * The number of lines that were actually flushed out
2813 *
2814 * looping_count
2815 * A count value that indicates the number of times the producer of
2816 * entries into this Ring has looped around the ring.
2817 */
2818
2819#define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR BIT(0)
2820#define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE BIT(1)
2821
2822struct hal_reo_unblock_cache_status {
2823 struct hal_reo_status_hdr hdr;
2824 __le32 info0;
2825 __le32 rsvd0[21];
2826 __le32 info1;
2827} __packed;
2828
2829/* hal_reo_unblock_cache_status
2830 * Producer: REO
2831 * Consumer: SW
2832 *
2833 * status_hdr
2834 * Details that can link this status with the original command. It
2835 * also contains info on how long REO took to execute this command.
2836 *
2837 * error_detected
2838 * 0 - No error has been detected while executing this command
2839 * 1 - The blocking resource was not in use, and therefore it could
2840 * not be unblocked.
2841 *
2842 * unblock_type
2843 * Reference to the type of unblock command
2844 * 0 - Unblock a blocking resource
2845 * 1 - The entire cache usage is unblock
2846 *
2847 * looping_count
2848 * A count value that indicates the number of times the producer of
2849 * entries into this Ring has looped around the ring.
2850 */
2851
2852#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR BIT(0)
2853#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY BIT(1)
2854
2855#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT GENMASK(15, 0)
2856#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT GENMASK(31, 16)
2857
2858struct hal_reo_flush_timeout_list_status {
2859 struct hal_reo_status_hdr hdr;
2860 __le32 info0;
2861 __le32 info1;
2862 __le32 rsvd0[20];
2863 __le32 info2;
2864} __packed;
2865
2866/* hal_reo_flush_timeout_list_status
2867 * Producer: REO
2868 * Consumer: SW
2869 *
2870 * status_hdr
2871 * Details that can link this status with the original command. It
2872 * also contains info on how long REO took to execute this command.
2873 *
2874 * error_detected
2875 * 0 - No error has been detected while executing this command
2876 * 1 - Command not properly executed and returned with error
2877 *
2878 * timeout_list_empty
2879 * When set, REO has depleted the timeout list and all entries are
2880 * gone.
2881 *
2882 * release_desc_count
2883 * Producer: SW; Consumer: REO
2884 * The number of link descriptor released
2885 *
2886 * forward_buf_count
2887 * Producer: SW; Consumer: REO
2888 * The number of buffers forwarded to the REO destination rings
2889 *
2890 * looping_count
2891 * A count value that indicates the number of times the producer of
2892 * entries into this Ring has looped around the ring.
2893 */
2894
2895#define HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX GENMASK(1, 0)
2896#define HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0 GENMASK(23, 0)
2897#define HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1 GENMASK(23, 0)
2898#define HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2 GENMASK(23, 0)
2899#define HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM GENMASK(25, 0)
2900
2901struct hal_reo_desc_thresh_reached_status {
2902 struct hal_reo_status_hdr hdr;
2903 __le32 info0;
2904 __le32 info1;
2905 __le32 info2;
2906 __le32 info3;
2907 __le32 info4;
2908 __le32 rsvd0[17];
2909 __le32 info5;
2910} __packed;
2911
2912/* hal_reo_desc_thresh_reached_status
2913 * Producer: REO
2914 * Consumer: SW
2915 *
2916 * status_hdr
2917 * Details that can link this status with the original command. It
2918 * also contains info on how long REO took to execute this command.
2919 *
2920 * threshold_index
2921 * The index of the threshold register whose value got reached
2922 *
2923 * link_descriptor_counter0
2924 * link_descriptor_counter1
2925 * link_descriptor_counter2
2926 * link_descriptor_counter_sum
2927 * Value of the respective counters at generation of this message
2928 *
2929 * looping_count
2930 * A count value that indicates the number of times the producer of
2931 * entries into this Ring has looped around the ring.
2932 */
2933
2934#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_DATA_LENGTH GENMASK(13, 0)
2935#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_L4_CSUM_STATUS BIT(14)
2936#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_L3_CSUM_STATUS BIT(15)
2937#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_PID GENMASK(27, 24)
2938#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_QDISC BIT(28)
2939#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_MULTICAST BIT(29)
2940#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_MORE BIT(30)
2941#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_VALID_TOGGLE BIT(31)
2942
2943struct hal_tcl_entrance_from_ppe_ring {
2944 __le32 buffer_addr;
2945 __le32 info0;
2946} __packed;
2947
2948struct hal_mon_buf_ring {
2949 __le32 paddr_lo;
2950 __le32 paddr_hi;
2951 __le64 cookie;
2952};
2953
2954/* hal_mon_buf_ring
2955 * Producer : SW
2956 * Consumer : Monitor
2957 *
2958 * paddr_lo
2959 * Lower 32-bit physical address of the buffer pointer from the source ring.
2960 * paddr_hi
2961 * bit range 7-0 : upper 8 bit of the physical address.
2962 * bit range 31-8 : reserved.
2963 * cookie
2964 * Consumer: RxMon/TxMon 64 bit cookie of the buffers.
2965 */
2966
2967#define HAL_MON_DEST_COOKIE_BUF_ID GENMASK(17, 0)
2968
2969#define HAL_MON_DEST_INFO0_END_OFFSET GENMASK(15, 0)
2970#define HAL_MON_DEST_INFO0_FLUSH_DETECTED BIT(16)
2971#define HAL_MON_DEST_INFO0_END_OF_PPDU BIT(17)
2972#define HAL_MON_DEST_INFO0_INITIATOR BIT(18)
2973#define HAL_MON_DEST_INFO0_EMPTY_DESC BIT(19)
2974#define HAL_MON_DEST_INFO0_RING_ID GENMASK(27, 20)
2975#define HAL_MON_DEST_INFO0_LOOPING_COUNT GENMASK(31, 28)
2976
2977struct hal_mon_dest_desc {
2978 __le32 cookie;
2979 __le32 reserved;
2980 __le32 ppdu_id;
2981 __le32 info0;
2982};
2983
2984/* hal_mon_dest_ring
2985 * Producer : TxMon/RxMon
2986 * Consumer : SW
2987 * cookie
2988 * bit 0 -17 buf_id to track the skb's vaddr.
2989 * ppdu_id
2990 * Phy ppdu_id
2991 * end_offset
2992 * The offset into status buffer where DMA ended, ie., offset to the last
2993 * TLV + last TLV size.
2994 * flush_detected
2995 * Indicates whether 'tx_flush' or 'rx_flush' occurred.
2996 * end_of_ppdu
2997 * Indicates end of ppdu.
2998 * pmac_id
2999 * Indicates PMAC that received from frame.
3000 * empty_descriptor
3001 * This descriptor is written on flush or end of ppdu or end of status
3002 * buffer.
3003 * ring_id
3004 * updated by SRNG.
3005 * looping_count
3006 * updated by SRNG.
3007 */
3008
3009#define HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_FLAG BIT(8)
3010#define HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_TYPE GENMASK(16, 15)
3011#define HAL_TX_MSDU_METADATA_INFO0_HOST_TX_DESC_POOL BIT(31)
3012
3013struct hal_tx_msdu_metadata {
3014 __le32 info0;
3015 __le32 rsvd0[6];
3016} __packed;
3017
3018/* hal_tx_msdu_metadata
3019 * valid_encrypt_type
3020 * if set, encrypt type is valid
3021 * encrypt_type
3022 * 0 = NO_ENCRYPT,
3023 * 1 = ENCRYPT,
3024 * 2 ~ 3 - Reserved
3025 * host_tx_desc_pool
3026 * If set, Firmware allocates tx_descriptors
3027 * in WAL_BUFFERID_TX_HOST_DATA_EXP,instead
3028 * of WAL_BUFFERID_TX_TCL_DATA_EXP.
3029 * Use cases:
3030 * Any time firmware uses TQM-BYPASS for Data
3031 * TID, firmware expect host to set this bit.
3032 */
3033
3034#endif /* ATH12K_HAL_DESC_H */