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1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
2/*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7#ifndef DEBUG_HTT_STATS_H
8#define DEBUG_HTT_STATS_H
9
10#define ATH12K_HTT_STATS_BUF_SIZE (1024 * 512)
11#define ATH12K_HTT_STATS_COOKIE_LSB GENMASK_ULL(31, 0)
12#define ATH12K_HTT_STATS_COOKIE_MSB GENMASK_ULL(63, 32)
13#define ATH12K_HTT_STATS_MAGIC_VALUE 0xF0F0F0F0
14#define ATH12K_HTT_STATS_SUBTYPE_MAX 16
15#define ATH12K_HTT_MAX_STRING_LEN 256
16
17#define ATH12K_HTT_STATS_RESET_BITMAP32_OFFSET(_idx) ((_idx) & 0x1f)
18#define ATH12K_HTT_STATS_RESET_BITMAP64_OFFSET(_idx) ((_idx) & 0x3f)
19#define ATH12K_HTT_STATS_RESET_BITMAP32_BIT(_idx) (1 << \
20 ATH12K_HTT_STATS_RESET_BITMAP32_OFFSET(_idx))
21#define ATH12K_HTT_STATS_RESET_BITMAP64_BIT(_idx) (1 << \
22 ATH12K_HTT_STATS_RESET_BITMAP64_OFFSET(_idx))
23
24void ath12k_debugfs_htt_stats_register(struct ath12k *ar);
25
26#ifdef CONFIG_ATH12K_DEBUGFS
27void ath12k_debugfs_htt_ext_stats_handler(struct ath12k_base *ab,
28 struct sk_buff *skb);
29#else /* CONFIG_ATH12K_DEBUGFS */
30static inline void ath12k_debugfs_htt_ext_stats_handler(struct ath12k_base *ab,
31 struct sk_buff *skb)
32{
33}
34#endif
35
36/**
37 * DOC: target -> host extended statistics upload
38 *
39 * The following field definitions describe the format of the HTT
40 * target to host stats upload confirmation message.
41 * The message contains a cookie echoed from the HTT host->target stats
42 * upload request, which identifies which request the confirmation is
43 * for, and a single stats can span over multiple HTT stats indication
44 * due to the HTT message size limitation so every HTT ext stats
45 * indication will have tag-length-value stats information elements.
46 * The tag-length header for each HTT stats IND message also includes a
47 * status field, to indicate whether the request for the stat type in
48 * question was fully met, partially met, unable to be met, or invalid
49 * (if the stat type in question is disabled in the target).
50 * A Done bit 1's indicate the end of the of stats info elements.
51 *
52 *
53 * |31 16|15 12|11|10 8|7 5|4 0|
54 * |--------------------------------------------------------------|
55 * | reserved | msg type |
56 * |--------------------------------------------------------------|
57 * | cookie LSBs |
58 * |--------------------------------------------------------------|
59 * | cookie MSBs |
60 * |--------------------------------------------------------------|
61 * | stats entry length | rsvd | D| S | stat type |
62 * |--------------------------------------------------------------|
63 * | type-specific stats info |
64 * | (see debugfs_htt_stats.h) |
65 * |--------------------------------------------------------------|
66 * Header fields:
67 * - MSG_TYPE
68 * Bits 7:0
69 * Purpose: Identifies this is a extended statistics upload confirmation
70 * message.
71 * Value: 0x1c
72 * - COOKIE_LSBS
73 * Bits 31:0
74 * Purpose: Provide a mechanism to match a target->host stats confirmation
75 * message with its preceding host->target stats request message.
76 * Value: MSBs of the opaque cookie specified by the host-side requestor
77 * - COOKIE_MSBS
78 * Bits 31:0
79 * Purpose: Provide a mechanism to match a target->host stats confirmation
80 * message with its preceding host->target stats request message.
81 * Value: MSBs of the opaque cookie specified by the host-side requestor
82 *
83 * Stats Information Element tag-length header fields:
84 * - STAT_TYPE
85 * Bits 7:0
86 * Purpose: identifies the type of statistics info held in the
87 * following information element
88 * Value: ath12k_dbg_htt_ext_stats_type
89 * - STATUS
90 * Bits 10:8
91 * Purpose: indicate whether the requested stats are present
92 * Value:
93 * 0 -> The requested stats have been delivered in full
94 * 1 -> The requested stats have been delivered in part
95 * 2 -> The requested stats could not be delivered (error case)
96 * 3 -> The requested stat type is either not recognized (invalid)
97 * - DONE
98 * Bits 11
99 * Purpose:
100 * Indicates the completion of the stats entry, this will be the last
101 * stats conf HTT segment for the requested stats type.
102 * Value:
103 * 0 -> the stats retrieval is ongoing
104 * 1 -> the stats retrieval is complete
105 * - LENGTH
106 * Bits 31:16
107 * Purpose: indicate the stats information size
108 * Value: This field specifies the number of bytes of stats information
109 * that follows the element tag-length header.
110 * It is expected but not required that this length is a multiple of
111 * 4 bytes.
112 */
113
114#define ATH12K_HTT_T2H_EXT_STATS_INFO1_DONE BIT(11)
115#define ATH12K_HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16)
116
117struct ath12k_htt_extd_stats_msg {
118 __le32 info0;
119 __le64 cookie;
120 __le32 info1;
121 u8 data[];
122} __packed;
123
124/* htt_dbg_ext_stats_type */
125enum ath12k_dbg_htt_ext_stats_type {
126 ATH12K_DBG_HTT_EXT_STATS_RESET = 0,
127 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX = 1,
128 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_SCHED = 4,
129 ATH12K_DBG_HTT_EXT_STATS_PDEV_ERROR = 5,
130 ATH12K_DBG_HTT_EXT_STATS_PDEV_TQM = 6,
131 ATH12K_DBG_HTT_EXT_STATS_TX_DE_INFO = 8,
132 ATH12K_DBG_HTT_EXT_STATS_TX_SELFGEN_INFO = 12,
133 ATH12K_DBG_HTT_EXT_STATS_SRNG_INFO = 15,
134 ATH12K_DBG_HTT_EXT_STATS_SFM_INFO = 16,
135 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_MU = 17,
136 ATH12K_DBG_HTT_EXT_STATS_PDEV_CCA_STATS = 19,
137 ATH12K_DBG_HTT_EXT_STATS_PDEV_OBSS_PD_STATS = 23,
138 ATH12K_DBG_HTT_EXT_STATS_SOC_ERROR = 45,
139 ATH12K_DBG_HTT_EXT_STATS_PDEV_SCHED_ALGO = 49,
140 ATH12K_DBG_HTT_EXT_STATS_MANDATORY_MUOFDMA = 51,
141
142 /* keep this last */
143 ATH12K_DBG_HTT_NUM_EXT_STATS,
144};
145
146enum ath12k_dbg_htt_tlv_tag {
147 HTT_STATS_TX_PDEV_CMN_TAG = 0,
148 HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1,
149 HTT_STATS_TX_PDEV_SIFS_TAG = 2,
150 HTT_STATS_TX_PDEV_FLUSH_TAG = 3,
151 HTT_STATS_STRING_TAG = 5,
152 HTT_STATS_TX_TQM_GEN_MPDU_TAG = 11,
153 HTT_STATS_TX_TQM_LIST_MPDU_TAG = 12,
154 HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG = 13,
155 HTT_STATS_TX_TQM_CMN_TAG = 14,
156 HTT_STATS_TX_TQM_PDEV_TAG = 15,
157 HTT_STATS_TX_DE_EAPOL_PACKETS_TAG = 17,
158 HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG = 18,
159 HTT_STATS_TX_DE_CLASSIFY_STATS_TAG = 19,
160 HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG = 20,
161 HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG = 21,
162 HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG = 22,
163 HTT_STATS_TX_DE_CMN_TAG = 23,
164 HTT_STATS_TX_PDEV_MU_MIMO_STATS_TAG = 25,
165 HTT_STATS_SFM_CMN_TAG = 26,
166 HTT_STATS_SRING_STATS_TAG = 27,
167 HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG = 36,
168 HTT_STATS_TX_SCHED_CMN_TAG = 37,
169 HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG = 39,
170 HTT_STATS_SFM_CLIENT_USER_TAG = 41,
171 HTT_STATS_SFM_CLIENT_TAG = 42,
172 HTT_STATS_TX_TQM_ERROR_STATS_TAG = 43,
173 HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG = 44,
174 HTT_STATS_TX_SELFGEN_AC_ERR_STATS_TAG = 46,
175 HTT_STATS_TX_SELFGEN_CMN_STATS_TAG = 47,
176 HTT_STATS_TX_SELFGEN_AC_STATS_TAG = 48,
177 HTT_STATS_TX_SELFGEN_AX_STATS_TAG = 49,
178 HTT_STATS_TX_SELFGEN_AX_ERR_STATS_TAG = 50,
179 HTT_STATS_HW_INTR_MISC_TAG = 54,
180 HTT_STATS_HW_PDEV_ERRS_TAG = 56,
181 HTT_STATS_TX_DE_COMPL_STATS_TAG = 65,
182 HTT_STATS_WHAL_TX_TAG = 66,
183 HTT_STATS_TX_PDEV_SIFS_HIST_TAG = 67,
184 HTT_STATS_PDEV_CCA_1SEC_HIST_TAG = 70,
185 HTT_STATS_PDEV_CCA_100MSEC_HIST_TAG = 71,
186 HTT_STATS_PDEV_CCA_STAT_CUMULATIVE_TAG = 72,
187 HTT_STATS_PDEV_CCA_COUNTERS_TAG = 73,
188 HTT_STATS_TX_PDEV_MPDU_STATS_TAG = 74,
189 HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG = 86,
190 HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG = 87,
191 HTT_STATS_PDEV_OBSS_PD_TAG = 88,
192 HTT_STATS_HW_WAR_TAG = 89,
193 HTT_STATS_SCHED_TXQ_SUPERCYCLE_TRIGGER_TAG = 100,
194 HTT_STATS_PDEV_CTRL_PATH_TX_STATS_TAG = 102,
195 HTT_STATS_TX_SELFGEN_AC_SCHED_STATUS_STATS_TAG = 111,
196 HTT_STATS_TX_SELFGEN_AX_SCHED_STATUS_STATS_TAG = 112,
197 HTT_STATS_MU_PPDU_DIST_TAG = 129,
198 HTT_STATS_TX_PDEV_MUMIMO_GRP_STATS_TAG = 130,
199 HTT_STATS_TX_PDEV_RATE_STATS_BE_OFDMA_TAG = 135,
200 HTT_STATS_TX_SELFGEN_BE_ERR_STATS_TAG = 137,
201 HTT_STATS_TX_SELFGEN_BE_STATS_TAG = 138,
202 HTT_STATS_TX_SELFGEN_BE_SCHED_STATUS_STATS_TAG = 139,
203 HTT_STATS_DMAC_RESET_STATS_TAG = 155,
204 HTT_STATS_PDEV_SCHED_ALGO_OFDMA_STATS_TAG = 165,
205
206 HTT_STATS_MAX_TAG,
207};
208
209#define ATH12K_HTT_STATS_MAC_ID GENMASK(7, 0)
210
211#define ATH12K_HTT_TX_PDEV_MAX_SIFS_BURST_STATS 9
212#define ATH12K_HTT_TX_PDEV_MAX_FLUSH_REASON_STATS 150
213
214/* MU MIMO distribution stats is a 2-dimensional array
215 * with dimension one denoting stats for nr4[0] or nr8[1]
216 */
217#define ATH12K_HTT_STATS_NUM_NR_BINS 2
218#define ATH12K_HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST 10
219#define ATH12K_HTT_TX_PDEV_MAX_SIFS_BURST_HIST_STATS 10
220#define ATH12K_HTT_STATS_MAX_NUM_SCHED_STATUS 9
221#define ATH12K_HTT_STATS_NUM_SCHED_STATUS_WORDS \
222 (ATH12K_HTT_STATS_NUM_NR_BINS * ATH12K_HTT_STATS_MAX_NUM_SCHED_STATUS)
223#define ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS \
224 (ATH12K_HTT_STATS_NUM_NR_BINS * ATH12K_HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST)
225
226enum ath12k_htt_tx_pdev_underrun_enum {
227 HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0,
228 HTT_STATS_TX_PDEV_DATA_UNDERRUN_BETWEEN_MPDU = 1,
229 HTT_STATS_TX_PDEV_DATA_UNDERRUN_WITHIN_MPDU = 2,
230 HTT_TX_PDEV_MAX_URRN_STATS = 3,
231};
232
233enum ath12k_htt_stats_reset_cfg_param_alloc_pos {
234 ATH12K_HTT_STATS_RESET_PARAM_CFG_32_BYTES = 1,
235 ATH12K_HTT_STATS_RESET_PARAM_CFG_64_BYTES,
236 ATH12K_HTT_STATS_RESET_PARAM_CFG_128_BYTES,
237};
238
239struct debug_htt_stats_req {
240 bool done;
241 bool override_cfg_param;
242 u8 pdev_id;
243 enum ath12k_dbg_htt_ext_stats_type type;
244 u32 cfg_param[4];
245 u8 peer_addr[ETH_ALEN];
246 struct completion htt_stats_rcvd;
247 u32 buf_len;
248 u8 buf[];
249};
250
251struct ath12k_htt_tx_pdev_stats_cmn_tlv {
252 __le32 mac_id__word;
253 __le32 hw_queued;
254 __le32 hw_reaped;
255 __le32 underrun;
256 __le32 hw_paused;
257 __le32 hw_flush;
258 __le32 hw_filt;
259 __le32 tx_abort;
260 __le32 mpdu_requed;
261 __le32 tx_xretry;
262 __le32 data_rc;
263 __le32 mpdu_dropped_xretry;
264 __le32 illgl_rate_phy_err;
265 __le32 cont_xretry;
266 __le32 tx_timeout;
267 __le32 pdev_resets;
268 __le32 phy_underrun;
269 __le32 txop_ovf;
270 __le32 seq_posted;
271 __le32 seq_failed_queueing;
272 __le32 seq_completed;
273 __le32 seq_restarted;
274 __le32 mu_seq_posted;
275 __le32 seq_switch_hw_paused;
276 __le32 next_seq_posted_dsr;
277 __le32 seq_posted_isr;
278 __le32 seq_ctrl_cached;
279 __le32 mpdu_count_tqm;
280 __le32 msdu_count_tqm;
281 __le32 mpdu_removed_tqm;
282 __le32 msdu_removed_tqm;
283 __le32 mpdus_sw_flush;
284 __le32 mpdus_hw_filter;
285 __le32 mpdus_truncated;
286 __le32 mpdus_ack_failed;
287 __le32 mpdus_expired;
288 __le32 mpdus_seq_hw_retry;
289 __le32 ack_tlv_proc;
290 __le32 coex_abort_mpdu_cnt_valid;
291 __le32 coex_abort_mpdu_cnt;
292 __le32 num_total_ppdus_tried_ota;
293 __le32 num_data_ppdus_tried_ota;
294 __le32 local_ctrl_mgmt_enqued;
295 __le32 local_ctrl_mgmt_freed;
296 __le32 local_data_enqued;
297 __le32 local_data_freed;
298 __le32 mpdu_tried;
299 __le32 isr_wait_seq_posted;
300
301 __le32 tx_active_dur_us_low;
302 __le32 tx_active_dur_us_high;
303 __le32 remove_mpdus_max_retries;
304 __le32 comp_delivered;
305 __le32 ppdu_ok;
306 __le32 self_triggers;
307 __le32 tx_time_dur_data;
308 __le32 seq_qdepth_repost_stop;
309 __le32 mu_seq_min_msdu_repost_stop;
310 __le32 seq_min_msdu_repost_stop;
311 __le32 seq_txop_repost_stop;
312 __le32 next_seq_cancel;
313 __le32 fes_offsets_err_cnt;
314 __le32 num_mu_peer_blacklisted;
315 __le32 mu_ofdma_seq_posted;
316 __le32 ul_mumimo_seq_posted;
317 __le32 ul_ofdma_seq_posted;
318
319 __le32 thermal_suspend_cnt;
320 __le32 dfs_suspend_cnt;
321 __le32 tx_abort_suspend_cnt;
322 __le32 tgt_specific_opaque_txq_suspend_info;
323 __le32 last_suspend_reason;
324} __packed;
325
326struct ath12k_htt_tx_pdev_stats_urrn_tlv {
327 DECLARE_FLEX_ARRAY(__le32, urrn_stats);
328} __packed;
329
330struct ath12k_htt_tx_pdev_stats_flush_tlv {
331 DECLARE_FLEX_ARRAY(__le32, flush_errs);
332} __packed;
333
334struct ath12k_htt_tx_pdev_stats_phy_err_tlv {
335 DECLARE_FLEX_ARRAY(__le32, phy_errs);
336} __packed;
337
338struct ath12k_htt_tx_pdev_stats_sifs_tlv {
339 DECLARE_FLEX_ARRAY(__le32, sifs_status);
340} __packed;
341
342struct ath12k_htt_pdev_ctrl_path_tx_stats_tlv {
343 __le32 fw_tx_mgmt_subtype[ATH12K_HTT_STATS_SUBTYPE_MAX];
344} __packed;
345
346struct ath12k_htt_tx_pdev_stats_sifs_hist_tlv {
347 DECLARE_FLEX_ARRAY(__le32, sifs_hist_status);
348} __packed;
349
350enum ath12k_htt_stats_hw_mode {
351 ATH12K_HTT_STATS_HWMODE_AC = 0,
352 ATH12K_HTT_STATS_HWMODE_AX = 1,
353 ATH12K_HTT_STATS_HWMODE_BE = 2,
354};
355
356struct ath12k_htt_tx_pdev_mu_ppdu_dist_stats_tlv {
357 __le32 hw_mode;
358 __le32 num_seq_term_status[ATH12K_HTT_STATS_NUM_SCHED_STATUS_WORDS];
359 __le32 num_ppdu_cmpl_per_burst[ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS];
360 __le32 num_seq_posted[ATH12K_HTT_STATS_NUM_NR_BINS];
361 __le32 num_ppdu_posted_per_burst[ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS];
362} __packed;
363
364#define ATH12K_HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID GENMASK(7, 0)
365#define ATH12K_HTT_TX_PDEV_STATS_SCHED_PER_TXQ_ID GENMASK(15, 8)
366
367#define ATH12K_HTT_TX_PDEV_NUM_SCHED_ORDER_LOG 20
368
369struct ath12k_htt_stats_tx_sched_cmn_tlv {
370 __le32 mac_id__word;
371 __le32 current_timestamp;
372} __packed;
373
374struct ath12k_htt_tx_pdev_stats_sched_per_txq_tlv {
375 __le32 mac_id__word;
376 __le32 sched_policy;
377 __le32 last_sched_cmd_posted_timestamp;
378 __le32 last_sched_cmd_compl_timestamp;
379 __le32 sched_2_tac_lwm_count;
380 __le32 sched_2_tac_ring_full;
381 __le32 sched_cmd_post_failure;
382 __le32 num_active_tids;
383 __le32 num_ps_schedules;
384 __le32 sched_cmds_pending;
385 __le32 num_tid_register;
386 __le32 num_tid_unregister;
387 __le32 num_qstats_queried;
388 __le32 qstats_update_pending;
389 __le32 last_qstats_query_timestamp;
390 __le32 num_tqm_cmdq_full;
391 __le32 num_de_sched_algo_trigger;
392 __le32 num_rt_sched_algo_trigger;
393 __le32 num_tqm_sched_algo_trigger;
394 __le32 notify_sched;
395 __le32 dur_based_sendn_term;
396 __le32 su_notify2_sched;
397 __le32 su_optimal_queued_msdus_sched;
398 __le32 su_delay_timeout_sched;
399 __le32 su_min_txtime_sched_delay;
400 __le32 su_no_delay;
401 __le32 num_supercycles;
402 __le32 num_subcycles_with_sort;
403 __le32 num_subcycles_no_sort;
404} __packed;
405
406struct ath12k_htt_sched_txq_cmd_posted_tlv {
407 DECLARE_FLEX_ARRAY(__le32, sched_cmd_posted);
408} __packed;
409
410struct ath12k_htt_sched_txq_cmd_reaped_tlv {
411 DECLARE_FLEX_ARRAY(__le32, sched_cmd_reaped);
412} __packed;
413
414struct ath12k_htt_sched_txq_sched_order_su_tlv {
415 DECLARE_FLEX_ARRAY(__le32, sched_order_su);
416} __packed;
417
418struct ath12k_htt_sched_txq_sched_ineligibility_tlv {
419 DECLARE_FLEX_ARRAY(__le32, sched_ineligibility);
420} __packed;
421
422enum ath12k_htt_sched_txq_supercycle_triggers_tlv_enum {
423 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_NONE = 0,
424 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_FORCED,
425 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_TIDQ_ENTRIES,
426 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_ACTIVE_TIDS,
427 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_MAX_ITR_REACHED,
428 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_DUR_THRESHOLD_REACHED,
429 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_TWT_TRIGGER,
430 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_MAX,
431};
432
433struct ath12k_htt_sched_txq_supercycle_triggers_tlv {
434 DECLARE_FLEX_ARRAY(__le32, supercycle_triggers);
435} __packed;
436
437struct ath12k_htt_hw_stats_pdev_errs_tlv {
438 __le32 mac_id__word;
439 __le32 tx_abort;
440 __le32 tx_abort_fail_count;
441 __le32 rx_abort;
442 __le32 rx_abort_fail_count;
443 __le32 warm_reset;
444 __le32 cold_reset;
445 __le32 tx_flush;
446 __le32 tx_glb_reset;
447 __le32 tx_txq_reset;
448 __le32 rx_timeout_reset;
449 __le32 mac_cold_reset_restore_cal;
450 __le32 mac_cold_reset;
451 __le32 mac_warm_reset;
452 __le32 mac_only_reset;
453 __le32 phy_warm_reset;
454 __le32 phy_warm_reset_ucode_trig;
455 __le32 mac_warm_reset_restore_cal;
456 __le32 mac_sfm_reset;
457 __le32 phy_warm_reset_m3_ssr;
458 __le32 phy_warm_reset_reason_phy_m3;
459 __le32 phy_warm_reset_reason_tx_hw_stuck;
460 __le32 phy_warm_reset_reason_num_rx_frame_stuck;
461 __le32 phy_warm_reset_reason_wal_rx_rec_rx_busy;
462 __le32 phy_warm_reset_reason_wal_rx_rec_mac_hng;
463 __le32 phy_warm_reset_reason_mac_conv_phy_reset;
464 __le32 wal_rx_recovery_rst_mac_hang_cnt;
465 __le32 wal_rx_recovery_rst_known_sig_cnt;
466 __le32 wal_rx_recovery_rst_no_rx_cnt;
467 __le32 wal_rx_recovery_rst_no_rx_consec_cnt;
468 __le32 wal_rx_recovery_rst_rx_busy_cnt;
469 __le32 wal_rx_recovery_rst_phy_mac_hang_cnt;
470 __le32 rx_flush_cnt;
471 __le32 phy_warm_reset_reason_tx_exp_cca_stuck;
472 __le32 phy_warm_reset_reason_tx_consec_flsh_war;
473 __le32 phy_warm_reset_reason_tx_hwsch_reset_war;
474 __le32 phy_warm_reset_reason_hwsch_cca_wdog_war;
475 __le32 fw_rx_rings_reset;
476 __le32 rx_dest_drain_rx_descs_leak_prevented;
477 __le32 rx_dest_drain_rx_descs_saved_cnt;
478 __le32 rx_dest_drain_rxdma2reo_leak_detected;
479 __le32 rx_dest_drain_rxdma2fw_leak_detected;
480 __le32 rx_dest_drain_rxdma2wbm_leak_detected;
481 __le32 rx_dest_drain_rxdma1_2sw_leak_detected;
482 __le32 rx_dest_drain_rx_drain_ok_mac_idle;
483 __le32 rx_dest_drain_ok_mac_not_idle;
484 __le32 rx_dest_drain_prerequisite_invld;
485 __le32 rx_dest_drain_skip_non_lmac_reset;
486 __le32 rx_dest_drain_hw_fifo_notempty_post_wait;
487} __packed;
488
489#define ATH12K_HTT_STATS_MAX_HW_INTR_NAME_LEN 8
490struct ath12k_htt_hw_stats_intr_misc_tlv {
491 u8 hw_intr_name[ATH12K_HTT_STATS_MAX_HW_INTR_NAME_LEN];
492 __le32 mask;
493 __le32 count;
494} __packed;
495
496struct ath12k_htt_hw_stats_whal_tx_tlv {
497 __le32 mac_id__word;
498 __le32 last_unpause_ppdu_id;
499 __le32 hwsch_unpause_wait_tqm_write;
500 __le32 hwsch_dummy_tlv_skipped;
501 __le32 hwsch_misaligned_offset_received;
502 __le32 hwsch_reset_count;
503 __le32 hwsch_dev_reset_war;
504 __le32 hwsch_delayed_pause;
505 __le32 hwsch_long_delayed_pause;
506 __le32 sch_rx_ppdu_no_response;
507 __le32 sch_selfgen_response;
508 __le32 sch_rx_sifs_resp_trigger;
509} __packed;
510
511struct ath12k_htt_hw_war_stats_tlv {
512 __le32 mac_id__word;
513 DECLARE_FLEX_ARRAY(__le32, hw_wars);
514} __packed;
515
516struct ath12k_htt_tx_tqm_cmn_stats_tlv {
517 __le32 mac_id__word;
518 __le32 max_cmdq_id;
519 __le32 list_mpdu_cnt_hist_intvl;
520 __le32 add_msdu;
521 __le32 q_empty;
522 __le32 q_not_empty;
523 __le32 drop_notification;
524 __le32 desc_threshold;
525 __le32 hwsch_tqm_invalid_status;
526 __le32 missed_tqm_gen_mpdus;
527 __le32 tqm_active_tids;
528 __le32 tqm_inactive_tids;
529 __le32 tqm_active_msduq_flows;
530 __le32 msduq_timestamp_updates;
531 __le32 msduq_updates_mpdu_head_info_cmd;
532 __le32 msduq_updates_emp_to_nonemp_status;
533 __le32 get_mpdu_head_info_cmds_by_query;
534 __le32 get_mpdu_head_info_cmds_by_tac;
535 __le32 gen_mpdu_cmds_by_query;
536 __le32 high_prio_q_not_empty;
537} __packed;
538
539struct ath12k_htt_tx_tqm_error_stats_tlv {
540 __le32 q_empty_failure;
541 __le32 q_not_empty_failure;
542 __le32 add_msdu_failure;
543 __le32 tqm_cache_ctl_err;
544 __le32 tqm_soft_reset;
545 __le32 tqm_reset_num_in_use_link_descs;
546 __le32 tqm_reset_num_lost_link_descs;
547 __le32 tqm_reset_num_lost_host_tx_buf_cnt;
548 __le32 tqm_reset_num_in_use_internal_tqm;
549 __le32 tqm_reset_num_in_use_idle_link_rng;
550 __le32 tqm_reset_time_to_tqm_hang_delta_ms;
551 __le32 tqm_reset_recovery_time_ms;
552 __le32 tqm_reset_num_peers_hdl;
553 __le32 tqm_reset_cumm_dirty_hw_mpduq_cnt;
554 __le32 tqm_reset_cumm_dirty_hw_msduq_proc;
555 __le32 tqm_reset_flush_cache_cmd_su_cnt;
556 __le32 tqm_reset_flush_cache_cmd_other_cnt;
557 __le32 tqm_reset_flush_cache_cmd_trig_type;
558 __le32 tqm_reset_flush_cache_cmd_trig_cfg;
559 __le32 tqm_reset_flush_cmd_skp_status_null;
560} __packed;
561
562struct ath12k_htt_tx_tqm_gen_mpdu_stats_tlv {
563 DECLARE_FLEX_ARRAY(__le32, gen_mpdu_end_reason);
564} __packed;
565
566#define ATH12K_HTT_TX_TQM_MAX_LIST_MPDU_END_REASON 16
567#define ATH12K_HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS 16
568
569struct ath12k_htt_tx_tqm_list_mpdu_stats_tlv {
570 DECLARE_FLEX_ARRAY(__le32, list_mpdu_end_reason);
571} __packed;
572
573struct ath12k_htt_tx_tqm_list_mpdu_cnt_tlv {
574 DECLARE_FLEX_ARRAY(__le32, list_mpdu_cnt_hist);
575} __packed;
576
577struct ath12k_htt_tx_tqm_pdev_stats_tlv {
578 __le32 msdu_count;
579 __le32 mpdu_count;
580 __le32 remove_msdu;
581 __le32 remove_mpdu;
582 __le32 remove_msdu_ttl;
583 __le32 send_bar;
584 __le32 bar_sync;
585 __le32 notify_mpdu;
586 __le32 sync_cmd;
587 __le32 write_cmd;
588 __le32 hwsch_trigger;
589 __le32 ack_tlv_proc;
590 __le32 gen_mpdu_cmd;
591 __le32 gen_list_cmd;
592 __le32 remove_mpdu_cmd;
593 __le32 remove_mpdu_tried_cmd;
594 __le32 mpdu_queue_stats_cmd;
595 __le32 mpdu_head_info_cmd;
596 __le32 msdu_flow_stats_cmd;
597 __le32 remove_msdu_cmd;
598 __le32 remove_msdu_ttl_cmd;
599 __le32 flush_cache_cmd;
600 __le32 update_mpduq_cmd;
601 __le32 enqueue;
602 __le32 enqueue_notify;
603 __le32 notify_mpdu_at_head;
604 __le32 notify_mpdu_state_valid;
605 __le32 sched_udp_notify1;
606 __le32 sched_udp_notify2;
607 __le32 sched_nonudp_notify1;
608 __le32 sched_nonudp_notify2;
609} __packed;
610
611struct ath12k_htt_tx_de_cmn_stats_tlv {
612 __le32 mac_id__word;
613 __le32 tcl2fw_entry_count;
614 __le32 not_to_fw;
615 __le32 invalid_pdev_vdev_peer;
616 __le32 tcl_res_invalid_addrx;
617 __le32 wbm2fw_entry_count;
618 __le32 invalid_pdev;
619 __le32 tcl_res_addrx_timeout;
620 __le32 invalid_vdev;
621 __le32 invalid_tcl_exp_frame_desc;
622 __le32 vdev_id_mismatch_cnt;
623} __packed;
624
625struct ath12k_htt_tx_de_eapol_packets_stats_tlv {
626 __le32 m1_packets;
627 __le32 m2_packets;
628 __le32 m3_packets;
629 __le32 m4_packets;
630 __le32 g1_packets;
631 __le32 g2_packets;
632 __le32 rc4_packets;
633 __le32 eap_packets;
634 __le32 eapol_start_packets;
635 __le32 eapol_logoff_packets;
636 __le32 eapol_encap_asf_packets;
637} __packed;
638
639struct ath12k_htt_tx_de_classify_stats_tlv {
640 __le32 arp_packets;
641 __le32 igmp_packets;
642 __le32 dhcp_packets;
643 __le32 host_inspected;
644 __le32 htt_included;
645 __le32 htt_valid_mcs;
646 __le32 htt_valid_nss;
647 __le32 htt_valid_preamble_type;
648 __le32 htt_valid_chainmask;
649 __le32 htt_valid_guard_interval;
650 __le32 htt_valid_retries;
651 __le32 htt_valid_bw_info;
652 __le32 htt_valid_power;
653 __le32 htt_valid_key_flags;
654 __le32 htt_valid_no_encryption;
655 __le32 fse_entry_count;
656 __le32 fse_priority_be;
657 __le32 fse_priority_high;
658 __le32 fse_priority_low;
659 __le32 fse_traffic_ptrn_be;
660 __le32 fse_traffic_ptrn_over_sub;
661 __le32 fse_traffic_ptrn_bursty;
662 __le32 fse_traffic_ptrn_interactive;
663 __le32 fse_traffic_ptrn_periodic;
664 __le32 fse_hwqueue_alloc;
665 __le32 fse_hwqueue_created;
666 __le32 fse_hwqueue_send_to_host;
667 __le32 mcast_entry;
668 __le32 bcast_entry;
669 __le32 htt_update_peer_cache;
670 __le32 htt_learning_frame;
671 __le32 fse_invalid_peer;
672 __le32 mec_notify;
673} __packed;
674
675struct ath12k_htt_tx_de_classify_failed_stats_tlv {
676 __le32 ap_bss_peer_not_found;
677 __le32 ap_bcast_mcast_no_peer;
678 __le32 sta_delete_in_progress;
679 __le32 ibss_no_bss_peer;
680 __le32 invalid_vdev_type;
681 __le32 invalid_ast_peer_entry;
682 __le32 peer_entry_invalid;
683 __le32 ethertype_not_ip;
684 __le32 eapol_lookup_failed;
685 __le32 qpeer_not_allow_data;
686 __le32 fse_tid_override;
687 __le32 ipv6_jumbogram_zero_length;
688 __le32 qos_to_non_qos_in_prog;
689 __le32 ap_bcast_mcast_eapol;
690 __le32 unicast_on_ap_bss_peer;
691 __le32 ap_vdev_invalid;
692 __le32 incomplete_llc;
693 __le32 eapol_duplicate_m3;
694 __le32 eapol_duplicate_m4;
695} __packed;
696
697struct ath12k_htt_tx_de_classify_status_stats_tlv {
698 __le32 eok;
699 __le32 classify_done;
700 __le32 lookup_failed;
701 __le32 send_host_dhcp;
702 __le32 send_host_mcast;
703 __le32 send_host_unknown_dest;
704 __le32 send_host;
705 __le32 status_invalid;
706} __packed;
707
708struct ath12k_htt_tx_de_enqueue_packets_stats_tlv {
709 __le32 enqueued_pkts;
710 __le32 to_tqm;
711 __le32 to_tqm_bypass;
712} __packed;
713
714struct ath12k_htt_tx_de_enqueue_discard_stats_tlv {
715 __le32 discarded_pkts;
716 __le32 local_frames;
717 __le32 is_ext_msdu;
718} __packed;
719
720struct ath12k_htt_tx_de_compl_stats_tlv {
721 __le32 tcl_dummy_frame;
722 __le32 tqm_dummy_frame;
723 __le32 tqm_notify_frame;
724 __le32 fw2wbm_enq;
725 __le32 tqm_bypass_frame;
726} __packed;
727
728enum ath12k_htt_tx_mumimo_grp_invalid_reason_code_stats {
729 ATH12K_HTT_TX_MUMIMO_GRP_VALID,
730 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_NUM_MU_USERS_EXCEEDED_MU_MAX_USERS,
731 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_SCHED_ALGO_NOT_MU_COMPATIBLE_GID,
732 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_NON_PRIMARY_GRP,
733 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_ZERO_CANDIDATES,
734 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_MORE_CANDIDATES,
735 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_GROUP_SIZE_EXCEED_NSS,
736 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_GROUP_INELIGIBLE,
737 ATH12K_HTT_TX_MUMIMO_GRP_INVALID,
738 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_GROUP_EFF_MU_TPUT_OMBPS,
739 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_MAX_REASON_CODE,
740};
741
742#define ATH12K_HTT_NUM_AC_WMM 0x4
743#define ATH12K_HTT_MAX_NUM_SBT_INTR 4
744#define ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS 4
745#define ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS 8
746#define ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS 8
747#define ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS 7
748#define ATH12K_HTT_TX_NUM_OFDMA_USER_STATS 74
749#define ATH12K_HTT_TX_NUM_UL_MUMIMO_USER_STATS 8
750#define ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ 8
751#define ATH12K_HTT_STATS_MUMIMO_TPUT_NUM_BINS 10
752
753#define ATH12K_HTT_STATS_MAX_INVALID_REASON_CODE \
754 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_MAX_REASON_CODE
755#define ATH12K_HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS \
756 (ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ * ATH12K_HTT_STATS_MAX_INVALID_REASON_CODE)
757
758struct ath12k_htt_tx_selfgen_cmn_stats_tlv {
759 __le32 mac_id__word;
760 __le32 su_bar;
761 __le32 rts;
762 __le32 cts2self;
763 __le32 qos_null;
764 __le32 delayed_bar_1;
765 __le32 delayed_bar_2;
766 __le32 delayed_bar_3;
767 __le32 delayed_bar_4;
768 __le32 delayed_bar_5;
769 __le32 delayed_bar_6;
770 __le32 delayed_bar_7;
771} __packed;
772
773struct ath12k_htt_tx_selfgen_ac_stats_tlv {
774 __le32 ac_su_ndpa;
775 __le32 ac_su_ndp;
776 __le32 ac_mu_mimo_ndpa;
777 __le32 ac_mu_mimo_ndp;
778 __le32 ac_mu_mimo_brpoll[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS - 1];
779} __packed;
780
781struct ath12k_htt_tx_selfgen_ax_stats_tlv {
782 __le32 ax_su_ndpa;
783 __le32 ax_su_ndp;
784 __le32 ax_mu_mimo_ndpa;
785 __le32 ax_mu_mimo_ndp;
786 __le32 ax_mu_mimo_brpoll[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS - 1];
787 __le32 ax_basic_trigger;
788 __le32 ax_bsr_trigger;
789 __le32 ax_mu_bar_trigger;
790 __le32 ax_mu_rts_trigger;
791 __le32 ax_ulmumimo_trigger;
792} __packed;
793
794struct ath12k_htt_tx_selfgen_be_stats_tlv {
795 __le32 be_su_ndpa;
796 __le32 be_su_ndp;
797 __le32 be_mu_mimo_ndpa;
798 __le32 be_mu_mimo_ndp;
799 __le32 be_mu_mimo_brpoll[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1];
800 __le32 be_basic_trigger;
801 __le32 be_bsr_trigger;
802 __le32 be_mu_bar_trigger;
803 __le32 be_mu_rts_trigger;
804 __le32 be_ulmumimo_trigger;
805 __le32 be_su_ndpa_queued;
806 __le32 be_su_ndp_queued;
807 __le32 be_mu_mimo_ndpa_queued;
808 __le32 be_mu_mimo_ndp_queued;
809 __le32 be_mu_mimo_brpoll_queued[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1];
810 __le32 be_ul_mumimo_trigger[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS];
811} __packed;
812
813struct ath12k_htt_tx_selfgen_ac_err_stats_tlv {
814 __le32 ac_su_ndp_err;
815 __le32 ac_su_ndpa_err;
816 __le32 ac_mu_mimo_ndpa_err;
817 __le32 ac_mu_mimo_ndp_err;
818 __le32 ac_mu_mimo_brp1_err;
819 __le32 ac_mu_mimo_brp2_err;
820 __le32 ac_mu_mimo_brp3_err;
821} __packed;
822
823struct ath12k_htt_tx_selfgen_ax_err_stats_tlv {
824 __le32 ax_su_ndp_err;
825 __le32 ax_su_ndpa_err;
826 __le32 ax_mu_mimo_ndpa_err;
827 __le32 ax_mu_mimo_ndp_err;
828 __le32 ax_mu_mimo_brp_err[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS - 1];
829 __le32 ax_basic_trigger_err;
830 __le32 ax_bsr_trigger_err;
831 __le32 ax_mu_bar_trigger_err;
832 __le32 ax_mu_rts_trigger_err;
833 __le32 ax_ulmumimo_trigger_err;
834} __packed;
835
836struct ath12k_htt_tx_selfgen_be_err_stats_tlv {
837 __le32 be_su_ndp_err;
838 __le32 be_su_ndpa_err;
839 __le32 be_mu_mimo_ndpa_err;
840 __le32 be_mu_mimo_ndp_err;
841 __le32 be_mu_mimo_brp_err[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1];
842 __le32 be_basic_trigger_err;
843 __le32 be_bsr_trigger_err;
844 __le32 be_mu_bar_trigger_err;
845 __le32 be_mu_rts_trigger_err;
846 __le32 be_ulmumimo_trigger_err;
847 __le32 be_mu_mimo_brp_err_num_cbf_rxd[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS];
848 __le32 be_su_ndpa_flushed;
849 __le32 be_su_ndp_flushed;
850 __le32 be_mu_mimo_ndpa_flushed;
851 __le32 be_mu_mimo_ndp_flushed;
852 __le32 be_mu_mimo_brpoll_flushed[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1];
853 __le32 be_ul_mumimo_trigger_err[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS];
854} __packed;
855
856enum ath12k_htt_tx_selfgen_sch_tsflag_error_stats {
857 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_FLUSH_RCVD_ERR,
858 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_FILT_SCHED_CMD_ERR,
859 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_MISMATCH_ERR,
860 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_MIMO_CTRL_MISMATCH_ERR,
861 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_BW_MISMATCH_ERR,
862 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RETRY_COUNT_FAIL_ERR,
863 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_TOO_LATE_RECEIVED_ERR,
864 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_SIFS_STALL_NO_NEXT_CMD_ERR,
865
866 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS
867};
868
869struct ath12k_htt_tx_selfgen_ac_sched_status_stats_tlv {
870 __le32 ac_su_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
871 __le32 ac_su_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
872 __le32 ac_su_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
873 __le32 ac_mu_mimo_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
874 __le32 ac_mu_mimo_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
875 __le32 ac_mu_mimo_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
876 __le32 ac_mu_mimo_brp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
877 __le32 ac_mu_mimo_brp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
878} __packed;
879
880struct ath12k_htt_tx_selfgen_ax_sched_status_stats_tlv {
881 __le32 ax_su_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
882 __le32 ax_su_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
883 __le32 ax_su_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
884 __le32 ax_mu_mimo_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
885 __le32 ax_mu_mimo_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
886 __le32 ax_mu_mimo_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
887 __le32 ax_mu_brp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
888 __le32 ax_mu_brp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
889 __le32 ax_mu_bar_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
890 __le32 ax_mu_bar_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
891 __le32 ax_basic_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
892 __le32 ax_basic_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
893 __le32 ax_ulmumimo_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
894 __le32 ax_ulmumimo_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
895} __packed;
896
897struct ath12k_htt_tx_selfgen_be_sched_status_stats_tlv {
898 __le32 be_su_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
899 __le32 be_su_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
900 __le32 be_su_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
901 __le32 be_mu_mimo_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
902 __le32 be_mu_mimo_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
903 __le32 be_mu_mimo_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
904 __le32 be_mu_brp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
905 __le32 be_mu_brp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
906 __le32 be_mu_bar_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
907 __le32 be_mu_bar_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
908 __le32 be_basic_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
909 __le32 be_basic_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
910 __le32 be_ulmumimo_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
911 __le32 be_ulmumimo_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS];
912} __packed;
913
914struct ath12k_htt_stats_string_tlv {
915 DECLARE_FLEX_ARRAY(__le32, data);
916} __packed;
917
918#define ATH12K_HTT_SRING_STATS_MAC_ID GENMASK(7, 0)
919#define ATH12K_HTT_SRING_STATS_RING_ID GENMASK(15, 8)
920#define ATH12K_HTT_SRING_STATS_ARENA GENMASK(23, 16)
921#define ATH12K_HTT_SRING_STATS_EP BIT(24)
922#define ATH12K_HTT_SRING_STATS_NUM_AVAIL_WORDS GENMASK(15, 0)
923#define ATH12K_HTT_SRING_STATS_NUM_VALID_WORDS GENMASK(31, 16)
924#define ATH12K_HTT_SRING_STATS_HEAD_PTR GENMASK(15, 0)
925#define ATH12K_HTT_SRING_STATS_TAIL_PTR GENMASK(31, 16)
926#define ATH12K_HTT_SRING_STATS_CONSUMER_EMPTY GENMASK(15, 0)
927#define ATH12K_HTT_SRING_STATS_PRODUCER_FULL GENMASK(31, 16)
928#define ATH12K_HTT_SRING_STATS_PREFETCH_COUNT GENMASK(15, 0)
929#define ATH12K_HTT_SRING_STATS_INTERNAL_TAIL_PTR GENMASK(31, 16)
930
931struct ath12k_htt_sring_stats_tlv {
932 __le32 mac_id__ring_id__arena__ep;
933 __le32 base_addr_lsb;
934 __le32 base_addr_msb;
935 __le32 ring_size;
936 __le32 elem_size;
937 __le32 num_avail_words__num_valid_words;
938 __le32 head_ptr__tail_ptr;
939 __le32 consumer_empty__producer_full;
940 __le32 prefetch_count__internal_tail_ptr;
941} __packed;
942
943struct ath12k_htt_sfm_cmn_tlv {
944 __le32 mac_id__word;
945 __le32 buf_total;
946 __le32 mem_empty;
947 __le32 deallocate_bufs;
948 __le32 num_records;
949} __packed;
950
951struct ath12k_htt_sfm_client_tlv {
952 __le32 client_id;
953 __le32 buf_min;
954 __le32 buf_max;
955 __le32 buf_busy;
956 __le32 buf_alloc;
957 __le32 buf_avail;
958 __le32 num_users;
959} __packed;
960
961struct ath12k_htt_sfm_client_user_tlv {
962 DECLARE_FLEX_ARRAY(__le32, dwords_used_by_user_n);
963} __packed;
964
965struct ath12k_htt_tx_pdev_mu_mimo_sch_stats_tlv {
966 __le32 mu_mimo_sch_posted;
967 __le32 mu_mimo_sch_failed;
968 __le32 mu_mimo_ppdu_posted;
969 __le32 ac_mu_mimo_sch_nusers[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS];
970 __le32 ax_mu_mimo_sch_nusers[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS];
971 __le32 ax_ofdma_sch_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS];
972 __le32 ax_ul_ofdma_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS];
973 __le32 ax_ul_ofdma_bsr_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS];
974 __le32 ax_ul_ofdma_bar_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS];
975 __le32 ax_ul_ofdma_brp_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS];
976 __le32 ax_ul_mumimo_nusers[ATH12K_HTT_TX_NUM_UL_MUMIMO_USER_STATS];
977 __le32 ax_ul_mumimo_brp_nusers[ATH12K_HTT_TX_NUM_UL_MUMIMO_USER_STATS];
978 __le32 ac_mu_mimo_per_grp_sz[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS];
979 __le32 ax_mu_mimo_per_grp_sz[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS];
980 __le32 be_mu_mimo_sch_nusers[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS];
981 __le32 be_mu_mimo_per_grp_sz[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS];
982 __le32 ac_mu_mimo_grp_sz_ext[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS];
983} __packed;
984
985struct ath12k_htt_tx_pdev_mumimo_grp_stats_tlv {
986 __le32 dl_mumimo_grp_best_grp_size[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ];
987 __le32 dl_mumimo_grp_best_num_usrs[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS];
988 __le32 dl_mumimo_grp_eligible[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ];
989 __le32 dl_mumimo_grp_ineligible[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ];
990 __le32 dl_mumimo_grp_invalid[ATH12K_HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS];
991 __le32 dl_mumimo_grp_tputs[ATH12K_HTT_STATS_MUMIMO_TPUT_NUM_BINS];
992 __le32 ul_mumimo_grp_best_grp_size[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ];
993 __le32 ul_mumimo_grp_best_usrs[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS];
994 __le32 ul_mumimo_grp_tputs[ATH12K_HTT_STATS_MUMIMO_TPUT_NUM_BINS];
995} __packed;
996
997enum ath12k_htt_stats_tx_sched_modes {
998 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_MIMO_AC = 0,
999 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_MIMO_AX,
1000 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_OFDMA_AX,
1001 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_OFDMA_BE,
1002 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_MIMO_BE
1003};
1004
1005struct ath12k_htt_tx_pdev_mpdu_stats_tlv {
1006 __le32 mpdus_queued_usr;
1007 __le32 mpdus_tried_usr;
1008 __le32 mpdus_failed_usr;
1009 __le32 mpdus_requeued_usr;
1010 __le32 err_no_ba_usr;
1011 __le32 mpdu_underrun_usr;
1012 __le32 ampdu_underrun_usr;
1013 __le32 user_index;
1014 __le32 tx_sched_mode;
1015} __packed;
1016
1017struct ath12k_htt_pdev_stats_cca_counters_tlv {
1018 __le32 tx_frame_usec;
1019 __le32 rx_frame_usec;
1020 __le32 rx_clear_usec;
1021 __le32 my_rx_frame_usec;
1022 __le32 usec_cnt;
1023 __le32 med_rx_idle_usec;
1024 __le32 med_tx_idle_global_usec;
1025 __le32 cca_obss_usec;
1026} __packed;
1027
1028struct ath12k_htt_pdev_cca_stats_hist_v1_tlv {
1029 __le32 chan_num;
1030 __le32 num_records;
1031 __le32 valid_cca_counters_bitmap;
1032 __le32 collection_interval;
1033} __packed;
1034
1035struct ath12k_htt_pdev_obss_pd_stats_tlv {
1036 __le32 num_obss_tx_ppdu_success;
1037 __le32 num_obss_tx_ppdu_failure;
1038 __le32 num_sr_tx_transmissions;
1039 __le32 num_spatial_reuse_opportunities;
1040 __le32 num_non_srg_opportunities;
1041 __le32 num_non_srg_ppdu_tried;
1042 __le32 num_non_srg_ppdu_success;
1043 __le32 num_srg_opportunities;
1044 __le32 num_srg_ppdu_tried;
1045 __le32 num_srg_ppdu_success;
1046 __le32 num_psr_opportunities;
1047 __le32 num_psr_ppdu_tried;
1048 __le32 num_psr_ppdu_success;
1049 __le32 num_non_srg_tried_per_ac[ATH12K_HTT_NUM_AC_WMM];
1050 __le32 num_non_srg_success_ac[ATH12K_HTT_NUM_AC_WMM];
1051 __le32 num_srg_tried_per_ac[ATH12K_HTT_NUM_AC_WMM];
1052 __le32 num_srg_success_per_ac[ATH12K_HTT_NUM_AC_WMM];
1053 __le32 num_obss_min_dur_check_flush_cnt;
1054 __le32 num_sr_ppdu_abort_flush_cnt;
1055} __packed;
1056
1057struct ath12k_htt_dmac_reset_stats_tlv {
1058 __le32 reset_count;
1059 __le32 reset_time_lo_ms;
1060 __le32 reset_time_hi_ms;
1061 __le32 disengage_time_lo_ms;
1062 __le32 disengage_time_hi_ms;
1063 __le32 engage_time_lo_ms;
1064 __le32 engage_time_hi_ms;
1065 __le32 disengage_count;
1066 __le32 engage_count;
1067 __le32 drain_dest_ring_mask;
1068} __packed;
1069
1070struct ath12k_htt_pdev_sched_algo_ofdma_stats_tlv {
1071 __le32 mac_id__word;
1072 __le32 rate_based_dlofdma_enabled_cnt[ATH12K_HTT_NUM_AC_WMM];
1073 __le32 rate_based_dlofdma_disabled_cnt[ATH12K_HTT_NUM_AC_WMM];
1074 __le32 rate_based_dlofdma_probing_cnt[ATH12K_HTT_NUM_AC_WMM];
1075 __le32 rate_based_dlofdma_monitor_cnt[ATH12K_HTT_NUM_AC_WMM];
1076 __le32 chan_acc_lat_based_dlofdma_enabled_cnt[ATH12K_HTT_NUM_AC_WMM];
1077 __le32 chan_acc_lat_based_dlofdma_disabled_cnt[ATH12K_HTT_NUM_AC_WMM];
1078 __le32 chan_acc_lat_based_dlofdma_monitor_cnt[ATH12K_HTT_NUM_AC_WMM];
1079 __le32 downgrade_to_dl_su_ru_alloc_fail[ATH12K_HTT_NUM_AC_WMM];
1080 __le32 candidate_list_single_user_disable_ofdma[ATH12K_HTT_NUM_AC_WMM];
1081 __le32 dl_cand_list_dropped_high_ul_qos_weight[ATH12K_HTT_NUM_AC_WMM];
1082 __le32 ax_dlofdma_disabled_due_to_pipelining[ATH12K_HTT_NUM_AC_WMM];
1083 __le32 dlofdma_disabled_su_only_eligible[ATH12K_HTT_NUM_AC_WMM];
1084 __le32 dlofdma_disabled_consec_no_mpdus_tried[ATH12K_HTT_NUM_AC_WMM];
1085 __le32 dlofdma_disabled_consec_no_mpdus_success[ATH12K_HTT_NUM_AC_WMM];
1086} __packed;
1087
1088enum ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE {
1089 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_26,
1090 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_52,
1091 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_52_26,
1092 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_106,
1093 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_106_26,
1094 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_242,
1095 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_484,
1096 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_484_242,
1097 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996,
1098 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996_484,
1099 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996_484_242,
1100 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x2,
1101 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x2_484,
1102 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x3,
1103 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x3_484,
1104 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x4,
1105 ATH12K_HTT_TX_RX_PDEV_NUM_BE_RU_SIZE_CNTRS,
1106};
1107
1108#define ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8
1109#define ATH12K_HTT_TX_PDEV_NUM_BE_MCS_CNTRS 16
1110#define ATH12K_HTT_TX_PDEV_NUM_BE_BW_CNTRS 5
1111#define ATH12K_HTT_TX_PDEV_NUM_EHT_SIG_MCS_CNTRS 4
1112#define ATH12K_HTT_TX_PDEV_NUM_GI_CNTRS 4
1113
1114struct ath12k_htt_tx_pdev_rate_stats_be_ofdma_tlv {
1115 __le32 mac_id__word;
1116 __le32 be_ofdma_tx_ldpc;
1117 __le32 be_ofdma_tx_mcs[ATH12K_HTT_TX_PDEV_NUM_BE_MCS_CNTRS];
1118 __le32 be_ofdma_tx_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1119 __le32 be_ofdma_tx_bw[ATH12K_HTT_TX_PDEV_NUM_BE_BW_CNTRS];
1120 __le32 gi[ATH12K_HTT_TX_PDEV_NUM_GI_CNTRS][ATH12K_HTT_TX_PDEV_NUM_BE_MCS_CNTRS];
1121 __le32 be_ofdma_tx_ru_size[ATH12K_HTT_TX_RX_PDEV_NUM_BE_RU_SIZE_CNTRS];
1122 __le32 be_ofdma_eht_sig_mcs[ATH12K_HTT_TX_PDEV_NUM_EHT_SIG_MCS_CNTRS];
1123} __packed;
1124
1125#endif