1// SPDX-License-Identifier: GPL-2.0
  2
  3/* Copyright (C) 2022 Linaro Ltd. */
  4
 
 
  5#include <linux/types.h>
  6
  7#include "../ipa.h"
  8#include "../ipa_reg.h"
 
  9
 10static const u32 reg_comp_cfg_fmask[] = {
 11	[COMP_CFG_ENABLE]				= BIT(0),
 12	[GSI_SNOC_BYPASS_DIS]				= BIT(1),
 13	[GEN_QMB_0_SNOC_BYPASS_DIS]			= BIT(2),
 14	[GEN_QMB_1_SNOC_BYPASS_DIS]			= BIT(3),
 15	[IPA_DCMP_FAST_CLK_EN]				= BIT(4),
 16						/* Bits 5-31 reserved */
 17};
 18
 19REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
 20
 21static const u32 reg_clkon_cfg_fmask[] = {
 22	[CLKON_RX]					= BIT(0),
 23	[CLKON_PROC]					= BIT(1),
 24	[TX_WRAPPER]					= BIT(2),
 25	[CLKON_MISC]					= BIT(3),
 26	[RAM_ARB]					= BIT(4),
 27	[FTCH_HPS]					= BIT(5),
 28	[FTCH_DPS]					= BIT(6),
 29	[CLKON_HPS]					= BIT(7),
 30	[CLKON_DPS]					= BIT(8),
 31	[RX_HPS_CMDQS]					= BIT(9),
 32	[HPS_DPS_CMDQS]					= BIT(10),
 33	[DPS_TX_CMDQS]					= BIT(11),
 34	[RSRC_MNGR]					= BIT(12),
 35	[CTX_HANDLER]					= BIT(13),
 36	[ACK_MNGR]					= BIT(14),
 37	[D_DCPH]					= BIT(15),
 38	[H_DCPH]					= BIT(16),
 39						/* Bit 17 reserved */
 40	[NTF_TX_CMDQS]					= BIT(18),
 41	[CLKON_TX_0]					= BIT(19),
 42	[CLKON_TX_1]					= BIT(20),
 43	[CLKON_FNR]					= BIT(21),
 44						/* Bits 22-31 reserved */
 45};
 46
 47REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
 48
 49static const u32 reg_route_fmask[] = {
 50	[ROUTE_DIS]					= BIT(0),
 51	[ROUTE_DEF_PIPE]				= GENMASK(5, 1),
 52	[ROUTE_DEF_HDR_TABLE]				= BIT(6),
 53	[ROUTE_DEF_HDR_OFST]				= GENMASK(16, 7),
 54	[ROUTE_FRAG_DEF_PIPE]				= GENMASK(21, 17),
 55						/* Bits 22-23 reserved */
 56	[ROUTE_DEF_RETAIN_HDR]				= BIT(24),
 57						/* Bits 25-31 reserved */
 58};
 59
 60REG_FIELDS(ROUTE, route, 0x00000048);
 61
 62static const u32 reg_shared_mem_size_fmask[] = {
 63	[MEM_SIZE]					= GENMASK(15, 0),
 64	[MEM_BADDR]					= GENMASK(31, 16),
 65};
 66
 67REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
 68
 69static const u32 reg_qsb_max_writes_fmask[] = {
 70	[GEN_QMB_0_MAX_WRITES]				= GENMASK(3, 0),
 71	[GEN_QMB_1_MAX_WRITES]				= GENMASK(7, 4),
 72						/* Bits 8-31 reserved */
 73};
 74
 75REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
 76
 77static const u32 reg_qsb_max_reads_fmask[] = {
 78	[GEN_QMB_0_MAX_READS]				= GENMASK(3, 0),
 79	[GEN_QMB_1_MAX_READS]				= GENMASK(7, 4),
 80};
 81
 82REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
 83
 84static const u32 reg_filt_rout_hash_en_fmask[] = {
 85	[IPV6_ROUTER_HASH]				= BIT(0),
 86						/* Bits 1-3 reserved */
 87	[IPV6_FILTER_HASH]				= BIT(4),
 88						/* Bits 5-7 reserved */
 89	[IPV4_ROUTER_HASH]				= BIT(8),
 90						/* Bits 9-11 reserved */
 91	[IPV4_FILTER_HASH]				= BIT(12),
 92						/* Bits 13-31 reserved */
 93};
 94
 95REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x000008c);
 96
 97static const u32 reg_filt_rout_hash_flush_fmask[] = {
 98	[IPV6_ROUTER_HASH]				= BIT(0),
 99						/* Bits 1-3 reserved */
100	[IPV6_FILTER_HASH]				= BIT(4),
101						/* Bits 5-7 reserved */
102	[IPV4_ROUTER_HASH]				= BIT(8),
103						/* Bits 9-11 reserved */
104	[IPV4_FILTER_HASH]				= BIT(12),
105						/* Bits 13-31 reserved */
106};
107
108REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090);
109
110/* Valid bits defined by ipa->available */
111REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c, 0x0004);
112
113REG(IPA_BCR, ipa_bcr, 0x000001d0);
114
115static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
116	[IPA_BASE_ADDR]					= GENMASK(16, 0),
117						/* Bits 17-31 reserved */
118};
119
120/* Offset must be a multiple of 8 */
121REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
122
123/* Valid bits defined by ipa->available */
124REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
125
126static const u32 reg_counter_cfg_fmask[] = {
127						/* Bits 0-3 reserved */
128	[AGGR_GRANULARITY]				= GENMASK(8, 4),
129						/* Bits 5-31 reserved */
130};
131
132REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);
133
134static const u32 reg_ipa_tx_cfg_fmask[] = {
135	[TX0_PREFETCH_DISABLE]				= BIT(0),
136	[TX1_PREFETCH_DISABLE]				= BIT(1),
137	[PREFETCH_ALMOST_EMPTY_SIZE]			= GENMASK(4, 2),
138						/* Bits 5-31 reserved */
139};
140
141REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
142
143static const u32 reg_flavor_0_fmask[] = {
144	[MAX_PIPES]					= GENMASK(3, 0),
145						/* Bits 4-7 reserved */
146	[MAX_CONS_PIPES]				= GENMASK(12, 8),
147						/* Bits 13-15 reserved */
148	[MAX_PROD_PIPES]				= GENMASK(20, 16),
149						/* Bits 21-23 reserved */
150	[PROD_LOWEST]					= GENMASK(27, 24),
151						/* Bits 28-31 reserved */
152};
153
154REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
155
156static const u32 reg_idle_indication_cfg_fmask[] = {
157	[ENTER_IDLE_DEBOUNCE_THRESH]			= GENMASK(15, 0),
158	[CONST_NON_IDLE_ENABLE]				= BIT(16),
159						/* Bits 17-31 reserved */
160};
161
162REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000220);
163
164static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
165	[X_MIN_LIM]					= GENMASK(5, 0),
166						/* Bits 6-7 reserved */
167	[X_MAX_LIM]					= GENMASK(13, 8),
168						/* Bits 14-15 reserved */
169	[Y_MIN_LIM]					= GENMASK(21, 16),
170						/* Bits 22-23 reserved */
171	[Y_MAX_LIM]					= GENMASK(29, 24),
172						/* Bits 30-31 reserved */
173};
174
175REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
176		  0x00000400, 0x0020);
177
178static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
179	[X_MIN_LIM]					= GENMASK(5, 0),
180						/* Bits 6-7 reserved */
181	[X_MAX_LIM]					= GENMASK(13, 8),
182						/* Bits 14-15 reserved */
183	[Y_MIN_LIM]					= GENMASK(21, 16),
184						/* Bits 22-23 reserved */
185	[Y_MAX_LIM]					= GENMASK(29, 24),
186						/* Bits 30-31 reserved */
187};
188
189REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
190		  0x00000404, 0x0020);
191
192static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
193	[X_MIN_LIM]					= GENMASK(5, 0),
194						/* Bits 6-7 reserved */
195	[X_MAX_LIM]					= GENMASK(13, 8),
196						/* Bits 14-15 reserved */
197	[Y_MIN_LIM]					= GENMASK(21, 16),
198						/* Bits 22-23 reserved */
199	[Y_MAX_LIM]					= GENMASK(29, 24),
200						/* Bits 30-31 reserved */
201};
202
203REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
204		  0x00000500, 0x0020);
205
206static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
207	[X_MIN_LIM]					= GENMASK(5, 0),
208						/* Bits 6-7 reserved */
209	[X_MAX_LIM]					= GENMASK(13, 8),
210						/* Bits 14-15 reserved */
211	[Y_MIN_LIM]					= GENMASK(21, 16),
212						/* Bits 22-23 reserved */
213	[Y_MAX_LIM]					= GENMASK(29, 24),
214						/* Bits 30-31 reserved */
215};
216
217REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
218		  0x00000504, 0x0020);
219
220static const u32 reg_endp_init_ctrl_fmask[] = {
221	[ENDP_SUSPEND]					= BIT(0),
222	[ENDP_DELAY]					= BIT(1),
223						/* Bits 2-31 reserved */
224};
225
226REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070);
227
228static const u32 reg_endp_init_cfg_fmask[] = {
229	[FRAG_OFFLOAD_EN]				= BIT(0),
230	[CS_OFFLOAD_EN]					= GENMASK(2, 1),
231	[CS_METADATA_HDR_OFFSET]			= GENMASK(6, 3),
232						/* Bit 7 reserved */
233	[CS_GEN_QMB_MASTER_SEL]				= BIT(8),
234						/* Bits 9-31 reserved */
235};
236
237REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
238
239static const u32 reg_endp_init_nat_fmask[] = {
240	[NAT_EN]					= GENMASK(1, 0),
241						/* Bits 2-31 reserved */
242};
243
244REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
245
246static const u32 reg_endp_init_hdr_fmask[] = {
247	[HDR_LEN]					= GENMASK(5, 0),
248	[HDR_OFST_METADATA_VALID]			= BIT(6),
249	[HDR_OFST_METADATA]				= GENMASK(12, 7),
250	[HDR_ADDITIONAL_CONST_LEN]			= GENMASK(18, 13),
251	[HDR_OFST_PKT_SIZE_VALID]			= BIT(19),
252	[HDR_OFST_PKT_SIZE]				= GENMASK(25, 20),
253	[HDR_A5_MUX]					= BIT(26),
254	[HDR_LEN_INC_DEAGG_HDR]				= BIT(27),
255	[HDR_METADATA_REG_VALID]			= BIT(28),
256						/* Bits 29-31 reserved */
257};
258
259REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
260
261static const u32 reg_endp_init_hdr_ext_fmask[] = {
262	[HDR_ENDIANNESS]				= BIT(0),
263	[HDR_TOTAL_LEN_OR_PAD_VALID]			= BIT(1),
264	[HDR_TOTAL_LEN_OR_PAD]				= BIT(2),
265	[HDR_PAYLOAD_LEN_INC_PADDING]			= BIT(3),
266	[HDR_TOTAL_LEN_OR_PAD_OFFSET]			= GENMASK(9, 4),
267	[HDR_PAD_TO_ALIGNMENT]				= GENMASK(13, 10),
268						/* Bits 14-31 reserved */
269};
270
271REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
272
273REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
274	   0x00000818, 0x0070);
275
276static const u32 reg_endp_init_mode_fmask[] = {
277	[ENDP_MODE]					= GENMASK(2, 0),
278						/* Bit 3 reserved */
279	[DEST_PIPE_INDEX]				= GENMASK(8, 4),
280						/* Bits 9-11 reserved */
281	[BYTE_THRESHOLD]				= GENMASK(27, 12),
282	[PIPE_REPLICATION_EN]				= BIT(28),
283	[PAD_EN]					= BIT(29),
284	[HDR_FTCH_DISABLE]				= BIT(30),
285						/* Bit 31 reserved */
286};
287
288REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
289
290static const u32 reg_endp_init_aggr_fmask[] = {
291	[AGGR_EN]					= GENMASK(1, 0),
292	[AGGR_TYPE]					= GENMASK(4, 2),
293	[BYTE_LIMIT]					= GENMASK(9, 5),
294	[TIME_LIMIT]					= GENMASK(14, 10),
295	[PKT_LIMIT]					= GENMASK(20, 15),
296	[SW_EOF_ACTIVE]					= BIT(21),
297	[FORCE_CLOSE]					= BIT(22),
298						/* Bit 23 reserved */
299	[HARD_BYTE_LIMIT_EN]				= BIT(24),
300						/* Bits 25-31 reserved */
301};
302
303REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
304
305static const u32 reg_endp_init_hol_block_en_fmask[] = {
306	[HOL_BLOCK_EN]					= BIT(0),
307						/* Bits 1-31 reserved */
308};
309
310REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
311		  0x0000082c, 0x0070);
312
313/* Entire register is a tick count */
314static const u32 reg_endp_init_hol_block_timer_fmask[] = {
315	[TIMER_BASE_VALUE]				= GENMASK(31, 0),
316};
317
318REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
319		  0x00000830, 0x0070);
320
321static const u32 reg_endp_init_deaggr_fmask[] = {
322	[DEAGGR_HDR_LEN]				= GENMASK(5, 0),
323	[SYSPIPE_ERR_DETECTION]				= BIT(6),
324	[PACKET_OFFSET_VALID]				= BIT(7),
325	[PACKET_OFFSET_LOCATION]			= GENMASK(13, 8),
326	[IGNORE_MIN_PKT_ERR]				= BIT(14),
327						/* Bit 15 reserved */
328	[MAX_PACKET_LEN]				= GENMASK(31, 16),
329};
330
331REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
332
333static const u32 reg_endp_init_rsrc_grp_fmask[] = {
334	[ENDP_RSRC_GRP]					= GENMASK(1, 0),
335						/* Bits 2-31 reserved */
336};
337
338REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
339
340static const u32 reg_endp_init_seq_fmask[] = {
341	[SEQ_TYPE]					= GENMASK(7, 0),
342	[SEQ_REP_TYPE]					= GENMASK(15, 8),
343						/* Bits 16-31 reserved */
344};
345
346REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
347
348static const u32 reg_endp_status_fmask[] = {
349	[STATUS_EN]					= BIT(0),
350	[STATUS_ENDP]					= GENMASK(5, 1),
351						/* Bits 6-7 reserved */
352	[STATUS_LOCATION]				= BIT(8),
353						/* Bits 9-31 reserved */
354};
355
356REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
357
358static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = {
359	[FILTER_HASH_MSK_SRC_ID]			= BIT(0),
360	[FILTER_HASH_MSK_SRC_IP]			= BIT(1),
361	[FILTER_HASH_MSK_DST_IP]			= BIT(2),
362	[FILTER_HASH_MSK_SRC_PORT]			= BIT(3),
363	[FILTER_HASH_MSK_DST_PORT]			= BIT(4),
364	[FILTER_HASH_MSK_PROTOCOL]			= BIT(5),
365	[FILTER_HASH_MSK_METADATA]			= BIT(6),
366	[FILTER_HASH_MSK_ALL]				= GENMASK(6, 0),
367						/* Bits 7-15 reserved */
368	[ROUTER_HASH_MSK_SRC_ID]			= BIT(16),
369	[ROUTER_HASH_MSK_SRC_IP]			= BIT(17),
370	[ROUTER_HASH_MSK_DST_IP]			= BIT(18),
371	[ROUTER_HASH_MSK_SRC_PORT]			= BIT(19),
372	[ROUTER_HASH_MSK_DST_PORT]			= BIT(20),
373	[ROUTER_HASH_MSK_PROTOCOL]			= BIT(21),
374	[ROUTER_HASH_MSK_METADATA]			= BIT(22),
375	[ROUTER_HASH_MSK_ALL]				= GENMASK(22, 16),
376						/* Bits 23-31 reserved */
377};
378
379REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
380		  0x0000085c, 0x0070);
381
382/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
383REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
384
385/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
386REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
387
388/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
389REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
390
391static const u32 reg_ipa_irq_uc_fmask[] = {
392	[UC_INTR]					= BIT(0),
393						/* Bits 1-31 reserved */
394};
395
396REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
397
398/* Valid bits defined by ipa->available */
399REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
400	   0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
401
402/* Valid bits defined by ipa->available */
403REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
404	   0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
405
406/* Valid bits defined by ipa->available */
407REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
408	   0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);
409
410static const struct reg *reg_array[] = {
411	[COMP_CFG]			= &reg_comp_cfg,
412	[CLKON_CFG]			= &reg_clkon_cfg,
413	[ROUTE]				= &reg_route,
414	[SHARED_MEM_SIZE]		= &reg_shared_mem_size,
415	[QSB_MAX_WRITES]		= &reg_qsb_max_writes,
416	[QSB_MAX_READS]			= &reg_qsb_max_reads,
417	[FILT_ROUT_HASH_EN]		= &reg_filt_rout_hash_en,
418	[FILT_ROUT_HASH_FLUSH]		= &reg_filt_rout_hash_flush,
419	[STATE_AGGR_ACTIVE]		= &reg_state_aggr_active,
420	[IPA_BCR]			= &reg_ipa_bcr,
421	[LOCAL_PKT_PROC_CNTXT]		= &reg_local_pkt_proc_cntxt,
422	[AGGR_FORCE_CLOSE]		= &reg_aggr_force_close,
423	[COUNTER_CFG]			= &reg_counter_cfg,
424	[IPA_TX_CFG]			= &reg_ipa_tx_cfg,
425	[FLAVOR_0]			= &reg_flavor_0,
426	[IDLE_INDICATION_CFG]		= &reg_idle_indication_cfg,
427	[SRC_RSRC_GRP_01_RSRC_TYPE]	= &reg_src_rsrc_grp_01_rsrc_type,
428	[SRC_RSRC_GRP_23_RSRC_TYPE]	= &reg_src_rsrc_grp_23_rsrc_type,
429	[DST_RSRC_GRP_01_RSRC_TYPE]	= &reg_dst_rsrc_grp_01_rsrc_type,
430	[DST_RSRC_GRP_23_RSRC_TYPE]	= &reg_dst_rsrc_grp_23_rsrc_type,
431	[ENDP_INIT_CTRL]		= &reg_endp_init_ctrl,
432	[ENDP_INIT_CFG]			= &reg_endp_init_cfg,
433	[ENDP_INIT_NAT]			= &reg_endp_init_nat,
434	[ENDP_INIT_HDR]			= &reg_endp_init_hdr,
435	[ENDP_INIT_HDR_EXT]		= &reg_endp_init_hdr_ext,
436	[ENDP_INIT_HDR_METADATA_MASK]	= &reg_endp_init_hdr_metadata_mask,
437	[ENDP_INIT_MODE]		= &reg_endp_init_mode,
438	[ENDP_INIT_AGGR]		= &reg_endp_init_aggr,
439	[ENDP_INIT_HOL_BLOCK_EN]	= &reg_endp_init_hol_block_en,
440	[ENDP_INIT_HOL_BLOCK_TIMER]	= &reg_endp_init_hol_block_timer,
441	[ENDP_INIT_DEAGGR]		= &reg_endp_init_deaggr,
442	[ENDP_INIT_RSRC_GRP]		= &reg_endp_init_rsrc_grp,
443	[ENDP_INIT_SEQ]			= &reg_endp_init_seq,
444	[ENDP_STATUS]			= &reg_endp_status,
445	[ENDP_FILTER_ROUTER_HSH_CFG]	= &reg_endp_filter_router_hsh_cfg,
446	[IPA_IRQ_STTS]			= &reg_ipa_irq_stts,
447	[IPA_IRQ_EN]			= &reg_ipa_irq_en,
448	[IPA_IRQ_CLR]			= &reg_ipa_irq_clr,
449	[IPA_IRQ_UC]			= &reg_ipa_irq_uc,
450	[IRQ_SUSPEND_INFO]		= &reg_irq_suspend_info,
451	[IRQ_SUSPEND_EN]		= &reg_irq_suspend_en,
452	[IRQ_SUSPEND_CLR]		= &reg_irq_suspend_clr,
453};
454
455const struct regs ipa_regs_v3_5_1 = {
456	.reg_count	= ARRAY_SIZE(reg_array),
457	.reg		= reg_array,
458};

  1// SPDX-License-Identifier: GPL-2.0
  2
  3/* Copyright (C) 2022-2024 Linaro Ltd. */
  4
  5#include <linux/array_size.h>
  6#include <linux/bits.h>
  7#include <linux/types.h>
  8
 
  9#include "../ipa_reg.h"
 10#include "../ipa_version.h"
 11
 12static const u32 reg_comp_cfg_fmask[] = {
 13	[COMP_CFG_ENABLE]				= BIT(0),
 14	[GSI_SNOC_BYPASS_DIS]				= BIT(1),
 15	[GEN_QMB_0_SNOC_BYPASS_DIS]			= BIT(2),
 16	[GEN_QMB_1_SNOC_BYPASS_DIS]			= BIT(3),
 17	[IPA_DCMP_FAST_CLK_EN]				= BIT(4),
 18						/* Bits 5-31 reserved */
 19};
 20
 21REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
 22
 23static const u32 reg_clkon_cfg_fmask[] = {
 24	[CLKON_RX]					= BIT(0),
 25	[CLKON_PROC]					= BIT(1),
 26	[TX_WRAPPER]					= BIT(2),
 27	[CLKON_MISC]					= BIT(3),
 28	[RAM_ARB]					= BIT(4),
 29	[FTCH_HPS]					= BIT(5),
 30	[FTCH_DPS]					= BIT(6),
 31	[CLKON_HPS]					= BIT(7),
 32	[CLKON_DPS]					= BIT(8),
 33	[RX_HPS_CMDQS]					= BIT(9),
 34	[HPS_DPS_CMDQS]					= BIT(10),
 35	[DPS_TX_CMDQS]					= BIT(11),
 36	[RSRC_MNGR]					= BIT(12),
 37	[CTX_HANDLER]					= BIT(13),
 38	[ACK_MNGR]					= BIT(14),
 39	[D_DCPH]					= BIT(15),
 40	[H_DCPH]					= BIT(16),
 41						/* Bit 17 reserved */
 42	[NTF_TX_CMDQS]					= BIT(18),
 43	[CLKON_TX_0]					= BIT(19),
 44	[CLKON_TX_1]					= BIT(20),
 45	[CLKON_FNR]					= BIT(21),
 46						/* Bits 22-31 reserved */
 47};
 48
 49REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
 50
 51static const u32 reg_route_fmask[] = {
 52	[ROUTE_DIS]					= BIT(0),
 53	[ROUTE_DEF_PIPE]				= GENMASK(5, 1),
 54	[ROUTE_DEF_HDR_TABLE]				= BIT(6),
 55	[ROUTE_DEF_HDR_OFST]				= GENMASK(16, 7),
 56	[ROUTE_FRAG_DEF_PIPE]				= GENMASK(21, 17),
 57						/* Bits 22-23 reserved */
 58	[ROUTE_DEF_RETAIN_HDR]				= BIT(24),
 59						/* Bits 25-31 reserved */
 60};
 61
 62REG_FIELDS(ROUTE, route, 0x00000048);
 63
 64static const u32 reg_shared_mem_size_fmask[] = {
 65	[MEM_SIZE]					= GENMASK(15, 0),
 66	[MEM_BADDR]					= GENMASK(31, 16),
 67};
 68
 69REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
 70
 71static const u32 reg_qsb_max_writes_fmask[] = {
 72	[GEN_QMB_0_MAX_WRITES]				= GENMASK(3, 0),
 73	[GEN_QMB_1_MAX_WRITES]				= GENMASK(7, 4),
 74						/* Bits 8-31 reserved */
 75};
 76
 77REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
 78
 79static const u32 reg_qsb_max_reads_fmask[] = {
 80	[GEN_QMB_0_MAX_READS]				= GENMASK(3, 0),
 81	[GEN_QMB_1_MAX_READS]				= GENMASK(7, 4),
 82};
 83
 84REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
 85
 
 
 
 
 
 
 
 
 
 
 
 
 
 86static const u32 reg_filt_rout_hash_flush_fmask[] = {
 87	[IPV6_ROUTER_HASH]				= BIT(0),
 88						/* Bits 1-3 reserved */
 89	[IPV6_FILTER_HASH]				= BIT(4),
 90						/* Bits 5-7 reserved */
 91	[IPV4_ROUTER_HASH]				= BIT(8),
 92						/* Bits 9-11 reserved */
 93	[IPV4_FILTER_HASH]				= BIT(12),
 94						/* Bits 13-31 reserved */
 95};
 96
 97REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090);
 98
 99/* Valid bits defined by ipa->available */
100REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c, 0x0004);
101
102REG(IPA_BCR, ipa_bcr, 0x000001d0);
103
104static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
105	[IPA_BASE_ADDR]					= GENMASK(16, 0),
106						/* Bits 17-31 reserved */
107};
108
109/* Offset must be a multiple of 8 */
110REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
111
112/* Valid bits defined by ipa->available */
113REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
114
115static const u32 reg_counter_cfg_fmask[] = {
116						/* Bits 0-3 reserved */
117	[AGGR_GRANULARITY]				= GENMASK(8, 4),
118						/* Bits 5-31 reserved */
119};
120
121REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);
122
123static const u32 reg_ipa_tx_cfg_fmask[] = {
124	[TX0_PREFETCH_DISABLE]				= BIT(0),
125	[TX1_PREFETCH_DISABLE]				= BIT(1),
126	[PREFETCH_ALMOST_EMPTY_SIZE]			= GENMASK(4, 2),
127						/* Bits 5-31 reserved */
128};
129
130REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
131
132static const u32 reg_flavor_0_fmask[] = {
133	[MAX_PIPES]					= GENMASK(3, 0),
134						/* Bits 4-7 reserved */
135	[MAX_CONS_PIPES]				= GENMASK(12, 8),
136						/* Bits 13-15 reserved */
137	[MAX_PROD_PIPES]				= GENMASK(20, 16),
138						/* Bits 21-23 reserved */
139	[PROD_LOWEST]					= GENMASK(27, 24),
140						/* Bits 28-31 reserved */
141};
142
143REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
144
145static const u32 reg_idle_indication_cfg_fmask[] = {
146	[ENTER_IDLE_DEBOUNCE_THRESH]			= GENMASK(15, 0),
147	[CONST_NON_IDLE_ENABLE]				= BIT(16),
148						/* Bits 17-31 reserved */
149};
150
151REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000220);
152
153static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
154	[X_MIN_LIM]					= GENMASK(5, 0),
155						/* Bits 6-7 reserved */
156	[X_MAX_LIM]					= GENMASK(13, 8),
157						/* Bits 14-15 reserved */
158	[Y_MIN_LIM]					= GENMASK(21, 16),
159						/* Bits 22-23 reserved */
160	[Y_MAX_LIM]					= GENMASK(29, 24),
161						/* Bits 30-31 reserved */
162};
163
164REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
165		  0x00000400, 0x0020);
166
167static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
168	[X_MIN_LIM]					= GENMASK(5, 0),
169						/* Bits 6-7 reserved */
170	[X_MAX_LIM]					= GENMASK(13, 8),
171						/* Bits 14-15 reserved */
172	[Y_MIN_LIM]					= GENMASK(21, 16),
173						/* Bits 22-23 reserved */
174	[Y_MAX_LIM]					= GENMASK(29, 24),
175						/* Bits 30-31 reserved */
176};
177
178REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
179		  0x00000404, 0x0020);
180
181static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
182	[X_MIN_LIM]					= GENMASK(5, 0),
183						/* Bits 6-7 reserved */
184	[X_MAX_LIM]					= GENMASK(13, 8),
185						/* Bits 14-15 reserved */
186	[Y_MIN_LIM]					= GENMASK(21, 16),
187						/* Bits 22-23 reserved */
188	[Y_MAX_LIM]					= GENMASK(29, 24),
189						/* Bits 30-31 reserved */
190};
191
192REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
193		  0x00000500, 0x0020);
194
195static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
196	[X_MIN_LIM]					= GENMASK(5, 0),
197						/* Bits 6-7 reserved */
198	[X_MAX_LIM]					= GENMASK(13, 8),
199						/* Bits 14-15 reserved */
200	[Y_MIN_LIM]					= GENMASK(21, 16),
201						/* Bits 22-23 reserved */
202	[Y_MAX_LIM]					= GENMASK(29, 24),
203						/* Bits 30-31 reserved */
204};
205
206REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
207		  0x00000504, 0x0020);
208
209static const u32 reg_endp_init_ctrl_fmask[] = {
210	[ENDP_SUSPEND]					= BIT(0),
211	[ENDP_DELAY]					= BIT(1),
212						/* Bits 2-31 reserved */
213};
214
215REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070);
216
217static const u32 reg_endp_init_cfg_fmask[] = {
218	[FRAG_OFFLOAD_EN]				= BIT(0),
219	[CS_OFFLOAD_EN]					= GENMASK(2, 1),
220	[CS_METADATA_HDR_OFFSET]			= GENMASK(6, 3),
221						/* Bit 7 reserved */
222	[CS_GEN_QMB_MASTER_SEL]				= BIT(8),
223						/* Bits 9-31 reserved */
224};
225
226REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
227
228static const u32 reg_endp_init_nat_fmask[] = {
229	[NAT_EN]					= GENMASK(1, 0),
230						/* Bits 2-31 reserved */
231};
232
233REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
234
235static const u32 reg_endp_init_hdr_fmask[] = {
236	[HDR_LEN]					= GENMASK(5, 0),
237	[HDR_OFST_METADATA_VALID]			= BIT(6),
238	[HDR_OFST_METADATA]				= GENMASK(12, 7),
239	[HDR_ADDITIONAL_CONST_LEN]			= GENMASK(18, 13),
240	[HDR_OFST_PKT_SIZE_VALID]			= BIT(19),
241	[HDR_OFST_PKT_SIZE]				= GENMASK(25, 20),
242	[HDR_A5_MUX]					= BIT(26),
243	[HDR_LEN_INC_DEAGG_HDR]				= BIT(27),
244	[HDR_METADATA_REG_VALID]			= BIT(28),
245						/* Bits 29-31 reserved */
246};
247
248REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
249
250static const u32 reg_endp_init_hdr_ext_fmask[] = {
251	[HDR_ENDIANNESS]				= BIT(0),
252	[HDR_TOTAL_LEN_OR_PAD_VALID]			= BIT(1),
253	[HDR_TOTAL_LEN_OR_PAD]				= BIT(2),
254	[HDR_PAYLOAD_LEN_INC_PADDING]			= BIT(3),
255	[HDR_TOTAL_LEN_OR_PAD_OFFSET]			= GENMASK(9, 4),
256	[HDR_PAD_TO_ALIGNMENT]				= GENMASK(13, 10),
257						/* Bits 14-31 reserved */
258};
259
260REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
261
262REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
263	   0x00000818, 0x0070);
264
265static const u32 reg_endp_init_mode_fmask[] = {
266	[ENDP_MODE]					= GENMASK(2, 0),
267						/* Bit 3 reserved */
268	[DEST_PIPE_INDEX]				= GENMASK(8, 4),
269						/* Bits 9-11 reserved */
270	[BYTE_THRESHOLD]				= GENMASK(27, 12),
271	[PIPE_REPLICATION_EN]				= BIT(28),
272	[PAD_EN]					= BIT(29),
273	[HDR_FTCH_DISABLE]				= BIT(30),
274						/* Bit 31 reserved */
275};
276
277REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
278
279static const u32 reg_endp_init_aggr_fmask[] = {
280	[AGGR_EN]					= GENMASK(1, 0),
281	[AGGR_TYPE]					= GENMASK(4, 2),
282	[BYTE_LIMIT]					= GENMASK(9, 5),
283	[TIME_LIMIT]					= GENMASK(14, 10),
284	[PKT_LIMIT]					= GENMASK(20, 15),
285	[SW_EOF_ACTIVE]					= BIT(21),
286	[FORCE_CLOSE]					= BIT(22),
287						/* Bit 23 reserved */
288	[HARD_BYTE_LIMIT_EN]				= BIT(24),
289						/* Bits 25-31 reserved */
290};
291
292REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
293
294static const u32 reg_endp_init_hol_block_en_fmask[] = {
295	[HOL_BLOCK_EN]					= BIT(0),
296						/* Bits 1-31 reserved */
297};
298
299REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
300		  0x0000082c, 0x0070);
301
302/* Entire register is a tick count */
303static const u32 reg_endp_init_hol_block_timer_fmask[] = {
304	[TIMER_BASE_VALUE]				= GENMASK(31, 0),
305};
306
307REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
308		  0x00000830, 0x0070);
309
310static const u32 reg_endp_init_deaggr_fmask[] = {
311	[DEAGGR_HDR_LEN]				= GENMASK(5, 0),
312	[SYSPIPE_ERR_DETECTION]				= BIT(6),
313	[PACKET_OFFSET_VALID]				= BIT(7),
314	[PACKET_OFFSET_LOCATION]			= GENMASK(13, 8),
315	[IGNORE_MIN_PKT_ERR]				= BIT(14),
316						/* Bit 15 reserved */
317	[MAX_PACKET_LEN]				= GENMASK(31, 16),
318};
319
320REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
321
322static const u32 reg_endp_init_rsrc_grp_fmask[] = {
323	[ENDP_RSRC_GRP]					= GENMASK(1, 0),
324						/* Bits 2-31 reserved */
325};
326
327REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
328
329static const u32 reg_endp_init_seq_fmask[] = {
330	[SEQ_TYPE]					= GENMASK(7, 0),
331	[SEQ_REP_TYPE]					= GENMASK(15, 8),
332						/* Bits 16-31 reserved */
333};
334
335REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
336
337static const u32 reg_endp_status_fmask[] = {
338	[STATUS_EN]					= BIT(0),
339	[STATUS_ENDP]					= GENMASK(5, 1),
340						/* Bits 6-7 reserved */
341	[STATUS_LOCATION]				= BIT(8),
342						/* Bits 9-31 reserved */
343};
344
345REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
346
347static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = {
348	[FILTER_HASH_MSK_SRC_ID]			= BIT(0),
349	[FILTER_HASH_MSK_SRC_IP]			= BIT(1),
350	[FILTER_HASH_MSK_DST_IP]			= BIT(2),
351	[FILTER_HASH_MSK_SRC_PORT]			= BIT(3),
352	[FILTER_HASH_MSK_DST_PORT]			= BIT(4),
353	[FILTER_HASH_MSK_PROTOCOL]			= BIT(5),
354	[FILTER_HASH_MSK_METADATA]			= BIT(6),
355	[FILTER_HASH_MSK_ALL]				= GENMASK(6, 0),
356						/* Bits 7-15 reserved */
357	[ROUTER_HASH_MSK_SRC_ID]			= BIT(16),
358	[ROUTER_HASH_MSK_SRC_IP]			= BIT(17),
359	[ROUTER_HASH_MSK_DST_IP]			= BIT(18),
360	[ROUTER_HASH_MSK_SRC_PORT]			= BIT(19),
361	[ROUTER_HASH_MSK_DST_PORT]			= BIT(20),
362	[ROUTER_HASH_MSK_PROTOCOL]			= BIT(21),
363	[ROUTER_HASH_MSK_METADATA]			= BIT(22),
364	[ROUTER_HASH_MSK_ALL]				= GENMASK(22, 16),
365						/* Bits 23-31 reserved */
366};
367
368REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
369		  0x0000085c, 0x0070);
370
371/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
372REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
373
374/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
375REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
376
377/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
378REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
379
380static const u32 reg_ipa_irq_uc_fmask[] = {
381	[UC_INTR]					= BIT(0),
382						/* Bits 1-31 reserved */
383};
384
385REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
386
387/* Valid bits defined by ipa->available */
388REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
389	   0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
390
391/* Valid bits defined by ipa->available */
392REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
393	   0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
394
395/* Valid bits defined by ipa->available */
396REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
397	   0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);
398
399static const struct reg *reg_array[] = {
400	[COMP_CFG]			= &reg_comp_cfg,
401	[CLKON_CFG]			= &reg_clkon_cfg,
402	[ROUTE]				= &reg_route,
403	[SHARED_MEM_SIZE]		= &reg_shared_mem_size,
404	[QSB_MAX_WRITES]		= &reg_qsb_max_writes,
405	[QSB_MAX_READS]			= &reg_qsb_max_reads,
 
406	[FILT_ROUT_HASH_FLUSH]		= &reg_filt_rout_hash_flush,
407	[STATE_AGGR_ACTIVE]		= &reg_state_aggr_active,
408	[IPA_BCR]			= &reg_ipa_bcr,
409	[LOCAL_PKT_PROC_CNTXT]		= &reg_local_pkt_proc_cntxt,
410	[AGGR_FORCE_CLOSE]		= &reg_aggr_force_close,
411	[COUNTER_CFG]			= &reg_counter_cfg,
412	[IPA_TX_CFG]			= &reg_ipa_tx_cfg,
413	[FLAVOR_0]			= &reg_flavor_0,
414	[IDLE_INDICATION_CFG]		= &reg_idle_indication_cfg,
415	[SRC_RSRC_GRP_01_RSRC_TYPE]	= &reg_src_rsrc_grp_01_rsrc_type,
416	[SRC_RSRC_GRP_23_RSRC_TYPE]	= &reg_src_rsrc_grp_23_rsrc_type,
417	[DST_RSRC_GRP_01_RSRC_TYPE]	= &reg_dst_rsrc_grp_01_rsrc_type,
418	[DST_RSRC_GRP_23_RSRC_TYPE]	= &reg_dst_rsrc_grp_23_rsrc_type,
419	[ENDP_INIT_CTRL]		= &reg_endp_init_ctrl,
420	[ENDP_INIT_CFG]			= &reg_endp_init_cfg,
421	[ENDP_INIT_NAT]			= &reg_endp_init_nat,
422	[ENDP_INIT_HDR]			= &reg_endp_init_hdr,
423	[ENDP_INIT_HDR_EXT]		= &reg_endp_init_hdr_ext,
424	[ENDP_INIT_HDR_METADATA_MASK]	= &reg_endp_init_hdr_metadata_mask,
425	[ENDP_INIT_MODE]		= &reg_endp_init_mode,
426	[ENDP_INIT_AGGR]		= &reg_endp_init_aggr,
427	[ENDP_INIT_HOL_BLOCK_EN]	= &reg_endp_init_hol_block_en,
428	[ENDP_INIT_HOL_BLOCK_TIMER]	= &reg_endp_init_hol_block_timer,
429	[ENDP_INIT_DEAGGR]		= &reg_endp_init_deaggr,
430	[ENDP_INIT_RSRC_GRP]		= &reg_endp_init_rsrc_grp,
431	[ENDP_INIT_SEQ]			= &reg_endp_init_seq,
432	[ENDP_STATUS]			= &reg_endp_status,
433	[ENDP_FILTER_ROUTER_HSH_CFG]	= &reg_endp_filter_router_hsh_cfg,
434	[IPA_IRQ_STTS]			= &reg_ipa_irq_stts,
435	[IPA_IRQ_EN]			= &reg_ipa_irq_en,
436	[IPA_IRQ_CLR]			= &reg_ipa_irq_clr,
437	[IPA_IRQ_UC]			= &reg_ipa_irq_uc,
438	[IRQ_SUSPEND_INFO]		= &reg_irq_suspend_info,
439	[IRQ_SUSPEND_EN]		= &reg_irq_suspend_en,
440	[IRQ_SUSPEND_CLR]		= &reg_irq_suspend_clr,
441};
442
443const struct regs ipa_regs_v3_5_1 = {
444	.reg_count	= ARRAY_SIZE(reg_array),
445	.reg		= reg_array,
446};