1/* SPDX-License-Identifier: GPL-2.0+ */
  2/* Copyright (c) Tehuti Networks Ltd. */
  3
  4#ifndef _TN40_H_
  5#define _TN40_H_
  6
  7#include "tn40_regs.h"
  8
  9#define TN40_DRV_NAME "tn40xx"
 10
 11#define TN40_MDIO_SPEED_1MHZ (1)
 12#define TN40_MDIO_SPEED_6MHZ (6)
 13
 14/* netdev tx queue len for Luxor. The default value is 1000.
 15 * ifconfig eth1 txqueuelen 3000 - to change it at runtime.
 16 */
 17#define TN40_NDEV_TXQ_LEN 1000
 18
 19#define TN40_FIFO_SIZE 4096
 20#define TN40_FIFO_EXTRA_SPACE 1024
 21
 22#define TN40_TXF_DESC_SZ 16
 23#define TN40_MAX_TX_LEVEL (priv->txd_fifo0.m.memsz - 16)
 24#define TN40_MIN_TX_LEVEL 256
 25#define TN40_NO_UPD_PACKETS 40
 26#define TN40_MAX_MTU BIT(14)
 27
 28#define TN40_PCK_TH_MULT 128
 29#define TN40_INT_COAL_MULT 2
 30
 31#define TN40_INT_REG_VAL(coal, coal_rc, rxf_th, pck_th) (	\
 32	FIELD_PREP(GENMASK(14, 0), (coal)) |		\
 33	FIELD_PREP(BIT(15), (coal_rc)) |		\
 34	FIELD_PREP(GENMASK(19, 16), (rxf_th)) |		\
 35	FIELD_PREP(GENMASK(31, 20), (pck_th))		\
 36	)
 37
 38struct tn40_fifo {
 39	dma_addr_t da; /* Physical address of fifo (used by HW) */
 40	char *va; /* Virtual address of fifo (used by SW) */
 41	u32 rptr, wptr;
 42	 /* Cached values of RPTR and WPTR registers,
 43	  * they're 32 bits on both 32 and 64 archs.
 44	  */
 45	u16 reg_cfg0;
 46	u16 reg_cfg1;
 47	u16 reg_rptr;
 48	u16 reg_wptr;
 49	u16 memsz; /* Memory size allocated for fifo */
 50	u16 size_mask;
 51	u16 pktsz; /* Skb packet size to allocate */
 52	u16 rcvno; /* Number of buffers that come from this RXF */
 53};
 54
 55struct tn40_txf_fifo {
 56	struct tn40_fifo m; /* The minimal set of variables used by all fifos */
 57};
 58
 59struct tn40_txd_fifo {
 60	struct tn40_fifo m; /* The minimal set of variables used by all fifos */
 61};
 62
 63struct tn40_rxf_fifo {
 64	struct tn40_fifo m; /* The minimal set of variables used by all fifos */
 65};
 66
 67struct tn40_rxd_fifo {
 68	struct tn40_fifo m; /* The minimal set of variables used by all fifos */
 69};
 70
 71struct tn40_rx_map {
 72	struct page *page;
 73};
 74
 75struct tn40_rxdb {
 76	unsigned int *stack;
 77	struct tn40_rx_map *elems;
 78	unsigned int nelem;
 79	unsigned int top;
 80};
 81
 82union tn40_tx_dma_addr {
 83	dma_addr_t dma;
 84	struct sk_buff *skb;
 85};
 86
 87/* Entry in the db.
 88 * if len == 0 addr is dma
 89 * if len != 0 addr is skb
 90 */
 91struct tn40_tx_map {
 92	union tn40_tx_dma_addr addr;
 93	int len;
 94};
 95
 96/* tx database - implemented as circular fifo buffer */
 97struct tn40_txdb {
 98	struct tn40_tx_map *start; /* Points to the first element */
 99	struct tn40_tx_map *end; /* Points just AFTER the last element */
100	struct tn40_tx_map *rptr; /* Points to the next element to read */
101	struct tn40_tx_map *wptr; /* Points to the next element to write */
102	int size; /* Number of elements in the db */
103};
104
105struct tn40_priv {
106	struct net_device *ndev;
107	struct pci_dev *pdev;
108
109	struct napi_struct napi;
110	/* RX FIFOs: 1 for data (full) descs, and 2 for free descs */
111	struct tn40_rxd_fifo rxd_fifo0;
112	struct tn40_rxf_fifo rxf_fifo0;
113	struct tn40_rxdb *rxdb0; /* Rx dbs to store skb pointers */
114	struct page_pool *page_pool;
115
116	/* Tx FIFOs: 1 for data desc, 1 for empty (acks) desc */
117	struct tn40_txd_fifo txd_fifo0;
118	struct tn40_txf_fifo txf_fifo0;
119	struct tn40_txdb txdb;
120	int tx_level;
121	int tx_update_mark;
122	int tx_noupd;
123
124	int stats_flag;
125	struct rtnl_link_stats64 stats;
126	u64 alloc_fail;
127	struct u64_stats_sync syncp;
128
129	u8 txd_size;
130	u8 txf_size;
131	u8 rxd_size;
132	u8 rxf_size;
133	u32 rdintcm;
134	u32 tdintcm;
135
136	u32 isr_mask;
137
138	void __iomem *regs;
139
140	/* SHORT_PKT_FIX */
141	u32 b0_len;
142	dma_addr_t b0_dma; /* Physical address of buffer */
143	char *b0_va; /* Virtual address of buffer */
144
145	struct mii_bus *mdio;
146	struct phy_device *phydev;
147	struct phylink *phylink;
148	struct phylink_config phylink_config;
149};
150
151/* RX FREE descriptor - 64bit */
152struct tn40_rxf_desc {
153	__le32 info; /* Buffer Count + Info - described below */
154	__le32 va_lo; /* VAdr[31:0] */
155	__le32 va_hi; /* VAdr[63:32] */
156	__le32 pa_lo; /* PAdr[31:0] */
157	__le32 pa_hi; /* PAdr[63:32] */
158	__le32 len; /* Buffer Length */
159};
160
161#define TN40_GET_RXD_BC(x) FIELD_GET(GENMASK(4, 0), (x))
162#define TN40_GET_RXD_ERR(x) FIELD_GET(GENMASK(26, 21), (x))
163#define TN40_GET_RXD_PKT_ID(x) FIELD_GET(GENMASK(30, 28), (x))
164#define TN40_GET_RXD_VTAG(x) FIELD_GET(BIT(31), (x))
165#define TN40_GET_RXD_VLAN_TCI(x) FIELD_GET(GENMASK(15, 0), (x))
166
167struct tn40_rxd_desc {
168	__le32 rxd_val1;
169	__le16 len;
170	__le16 rxd_vlan;
171	__le32 va_lo;
172	__le32 va_hi;
173	__le32 rss_lo;
174	__le32 rss_hash;
175};
176
177#define TN40_MAX_PBL (19)
178/* PBL describes each virtual buffer to be transmitted from the host. */
179struct tn40_pbl {
180	__le32 pa_lo;
181	__le32 pa_hi;
182	__le32 len;
183};
184
185/* First word for TXD descriptor. It means: type = 3 for regular Tx packet,
186 * hw_csum = 7 for IP+UDP+TCP HW checksums.
187 */
188#define TN40_TXD_W1_VAL(bc, checksum, vtag, lgsnd, vlan_id) (		\
189	GENMASK(17, 16) |						\
190	FIELD_PREP(GENMASK(4, 0), (bc)) |				\
191	FIELD_PREP(GENMASK(7, 5), (checksum)) |				\
192	FIELD_PREP(BIT(8), (vtag)) |					\
193	FIELD_PREP(GENMASK(12, 9), (lgsnd)) |				\
194	FIELD_PREP(GENMASK(15, 13),					\
195		   FIELD_GET(GENMASK(15, 13), (vlan_id))) |		\
196	FIELD_PREP(GENMASK(31, 20),					\
197		   FIELD_GET(GENMASK(11, 0), (vlan_id)))		\
198	)
199
200struct tn40_txd_desc {
201	__le32 txd_val1;
202	__le16 mss;
203	__le16 length;
204	__le32 va_lo;
205	__le32 va_hi;
206	struct tn40_pbl pbl[]; /* Fragments */
207};
208
209struct tn40_txf_desc {
210	u32 status;
211	u32 va_lo; /* VAdr[31:0] */
212	u32 va_hi; /* VAdr[63:32] */
213	u32 pad;
214};
215
216static inline u32 tn40_read_reg(struct tn40_priv *priv, u32 reg)
217{
218	return readl(priv->regs + reg);
219}
220
221static inline void tn40_write_reg(struct tn40_priv *priv, u32 reg, u32 val)
222{
223	writel(val, priv->regs + reg);
224}
225
226int tn40_set_link_speed(struct tn40_priv *priv, u32 speed);
227
228int tn40_mdiobus_init(struct tn40_priv *priv);
229
230int tn40_phy_register(struct tn40_priv *priv);
231void tn40_phy_unregister(struct tn40_priv *priv);
232
233#endif /* _TN40XX_H */