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1/* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2018 Broadcom Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
11#ifndef BNXT_H
12#define BNXT_H
13
14#define DRV_MODULE_NAME "bnxt_en"
15
16/* DO NOT CHANGE DRV_VER_* defines
17 * FIXME: Delete them
18 */
19#define DRV_VER_MAJ 1
20#define DRV_VER_MIN 10
21#define DRV_VER_UPD 3
22
23#include <linux/ethtool.h>
24#include <linux/interrupt.h>
25#include <linux/rhashtable.h>
26#include <linux/crash_dump.h>
27#include <linux/auxiliary_bus.h>
28#include <net/devlink.h>
29#include <net/dst_metadata.h>
30#include <net/xdp.h>
31#include <linux/dim.h>
32#include <linux/io-64-nonatomic-lo-hi.h>
33#ifdef CONFIG_TEE_BNXT_FW
34#include <linux/firmware/broadcom/tee_bnxt_fw.h>
35#endif
36
37extern struct list_head bnxt_block_cb_list;
38
39struct page_pool;
40
41struct tx_bd {
42 __le32 tx_bd_len_flags_type;
43 #define TX_BD_TYPE (0x3f << 0)
44 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)
45 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)
46 #define TX_BD_FLAGS_PACKET_END (1 << 6)
47 #define TX_BD_FLAGS_NO_CMPL (1 << 7)
48 #define TX_BD_FLAGS_BD_CNT (0x1f << 8)
49 #define TX_BD_FLAGS_BD_CNT_SHIFT 8
50 #define TX_BD_FLAGS_LHINT (3 << 13)
51 #define TX_BD_FLAGS_LHINT_SHIFT 13
52 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)
53 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13)
54 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13)
55 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13)
56 #define TX_BD_FLAGS_COAL_NOW (1 << 15)
57 #define TX_BD_LEN (0xffff << 16)
58 #define TX_BD_LEN_SHIFT 16
59
60 u32 tx_bd_opaque;
61 __le64 tx_bd_haddr;
62} __packed;
63
64#define TX_OPAQUE_IDX_MASK 0x0000ffff
65#define TX_OPAQUE_BDS_MASK 0x00ff0000
66#define TX_OPAQUE_BDS_SHIFT 16
67#define TX_OPAQUE_RING_MASK 0xff000000
68#define TX_OPAQUE_RING_SHIFT 24
69
70#define SET_TX_OPAQUE(bp, txr, idx, bds) \
71 (((txr)->tx_napi_idx << TX_OPAQUE_RING_SHIFT) | \
72 ((bds) << TX_OPAQUE_BDS_SHIFT) | ((idx) & (bp)->tx_ring_mask))
73
74#define TX_OPAQUE_IDX(opq) ((opq) & TX_OPAQUE_IDX_MASK)
75#define TX_OPAQUE_RING(opq) (((opq) & TX_OPAQUE_RING_MASK) >> \
76 TX_OPAQUE_RING_SHIFT)
77#define TX_OPAQUE_BDS(opq) (((opq) & TX_OPAQUE_BDS_MASK) >> \
78 TX_OPAQUE_BDS_SHIFT)
79#define TX_OPAQUE_PROD(bp, opq) ((TX_OPAQUE_IDX(opq) + TX_OPAQUE_BDS(opq)) &\
80 (bp)->tx_ring_mask)
81
82struct tx_bd_ext {
83 __le32 tx_bd_hsize_lflags;
84 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)
85 #define TX_BD_FLAGS_IP_CKSUM (1 << 1)
86 #define TX_BD_FLAGS_NO_CRC (1 << 2)
87 #define TX_BD_FLAGS_STAMP (1 << 3)
88 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4)
89 #define TX_BD_FLAGS_LSO (1 << 5)
90 #define TX_BD_FLAGS_IPID_FMT (1 << 6)
91 #define TX_BD_FLAGS_T_IPID (1 << 7)
92 #define TX_BD_HSIZE (0xff << 16)
93 #define TX_BD_HSIZE_SHIFT 16
94
95 __le32 tx_bd_mss;
96 __le32 tx_bd_cfa_action;
97 #define TX_BD_CFA_ACTION (0xffff << 16)
98 #define TX_BD_CFA_ACTION_SHIFT 16
99
100 __le32 tx_bd_cfa_meta;
101 #define TX_BD_CFA_META_MASK 0xfffffff
102 #define TX_BD_CFA_META_VID_MASK 0xfff
103 #define TX_BD_CFA_META_PRI_MASK (0xf << 12)
104 #define TX_BD_CFA_META_PRI_SHIFT 12
105 #define TX_BD_CFA_META_TPID_MASK (3 << 16)
106 #define TX_BD_CFA_META_TPID_SHIFT 16
107 #define TX_BD_CFA_META_KEY (0xf << 28)
108 #define TX_BD_CFA_META_KEY_SHIFT 28
109 #define TX_BD_CFA_META_KEY_VLAN (1 << 28)
110};
111
112#define BNXT_TX_PTP_IS_SET(lflags) ((lflags) & cpu_to_le32(TX_BD_FLAGS_STAMP))
113
114struct rx_bd {
115 __le32 rx_bd_len_flags_type;
116 #define RX_BD_TYPE (0x3f << 0)
117 #define RX_BD_TYPE_RX_PACKET_BD 0x4
118 #define RX_BD_TYPE_RX_BUFFER_BD 0x5
119 #define RX_BD_TYPE_RX_AGG_BD 0x6
120 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4)
121 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4)
122 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4)
123 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4)
124 #define RX_BD_FLAGS_SOP (1 << 6)
125 #define RX_BD_FLAGS_EOP (1 << 7)
126 #define RX_BD_FLAGS_BUFFERS (3 << 8)
127 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)
128 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8)
129 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8)
130 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8)
131 #define RX_BD_LEN (0xffff << 16)
132 #define RX_BD_LEN_SHIFT 16
133
134 u32 rx_bd_opaque;
135 __le64 rx_bd_haddr;
136};
137
138struct tx_cmp {
139 __le32 tx_cmp_flags_type;
140 #define CMP_TYPE (0x3f << 0)
141 #define CMP_TYPE_TX_L2_CMP 0
142 #define CMP_TYPE_TX_L2_COAL_CMP 2
143 #define CMP_TYPE_TX_L2_PKT_TS_CMP 4
144 #define CMP_TYPE_RX_L2_CMP 17
145 #define CMP_TYPE_RX_AGG_CMP 18
146 #define CMP_TYPE_RX_L2_TPA_START_CMP 19
147 #define CMP_TYPE_RX_L2_TPA_END_CMP 21
148 #define CMP_TYPE_RX_TPA_AGG_CMP 22
149 #define CMP_TYPE_RX_L2_V3_CMP 23
150 #define CMP_TYPE_RX_L2_TPA_START_V3_CMP 25
151 #define CMP_TYPE_STATUS_CMP 32
152 #define CMP_TYPE_REMOTE_DRIVER_REQ 34
153 #define CMP_TYPE_REMOTE_DRIVER_RESP 36
154 #define CMP_TYPE_ERROR_STATUS 48
155 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
156 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL
157 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL
158 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL
159 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
160
161 #define TX_CMP_FLAGS_ERROR (1 << 6)
162 #define TX_CMP_FLAGS_PUSH (1 << 7)
163
164 u32 tx_cmp_opaque;
165 __le32 tx_cmp_errors_v;
166 #define TX_CMP_V (1 << 0)
167 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1)
168 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0
169 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2
170 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4
171 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5
172 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4)
173 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5)
174 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6)
175 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7)
176
177 __le32 sq_cons_idx;
178 #define TX_CMP_SQ_CONS_IDX_MASK 0x00ffffff
179};
180
181#define TX_CMP_SQ_CONS_IDX(txcmp) \
182 (le32_to_cpu((txcmp)->sq_cons_idx) & TX_CMP_SQ_CONS_IDX_MASK)
183
184struct rx_cmp {
185 __le32 rx_cmp_len_flags_type;
186 #define RX_CMP_CMP_TYPE (0x3f << 0)
187 #define RX_CMP_FLAGS_ERROR (1 << 6)
188 #define RX_CMP_FLAGS_PLACEMENT (7 << 7)
189 #define RX_CMP_FLAGS_RSS_VALID (1 << 10)
190 #define RX_CMP_FLAGS_PKT_METADATA_PRESENT (1 << 11)
191 #define RX_CMP_FLAGS_ITYPES_SHIFT 12
192 #define RX_CMP_FLAGS_ITYPES_MASK 0xf000
193 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
194 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12)
195 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)
196 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12)
197 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12)
198 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12)
199 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12)
200 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12)
201 #define RX_CMP_LEN (0xffff << 16)
202 #define RX_CMP_LEN_SHIFT 16
203
204 u32 rx_cmp_opaque;
205 __le32 rx_cmp_misc_v1;
206 #define RX_CMP_V1 (1 << 0)
207 #define RX_CMP_AGG_BUFS (0x1f << 1)
208 #define RX_CMP_AGG_BUFS_SHIFT 1
209 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9)
210 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9
211 #define RX_CMP_V3_RSS_EXT_OP_LEGACY (0xf << 12)
212 #define RX_CMP_V3_RSS_EXT_OP_LEGACY_SHIFT 12
213 #define RX_CMP_V3_RSS_EXT_OP_NEW (0xf << 8)
214 #define RX_CMP_V3_RSS_EXT_OP_NEW_SHIFT 8
215 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16)
216 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16
217 #define RX_CMP_SUB_NS_TS (0xf << 16)
218 #define RX_CMP_SUB_NS_TS_SHIFT 16
219 #define RX_CMP_METADATA1 (0xf << 28)
220 #define RX_CMP_METADATA1_SHIFT 28
221 #define RX_CMP_METADATA1_TPID_SEL (0x7 << 28)
222 #define RX_CMP_METADATA1_TPID_8021Q (0x1 << 28)
223 #define RX_CMP_METADATA1_TPID_8021AD (0x0 << 28)
224 #define RX_CMP_METADATA1_VALID (0x8 << 28)
225
226 __le32 rx_cmp_rss_hash;
227};
228
229#define BNXT_PTP_RX_TS_VALID(flags) \
230 (((flags) & RX_CMP_FLAGS_ITYPES_MASK) == RX_CMP_FLAGS_ITYPE_PTP_W_TS)
231
232#define BNXT_ALL_RX_TS_VALID(flags) \
233 !((flags) & RX_CMP_FLAGS_PKT_METADATA_PRESENT)
234
235#define RX_CMP_HASH_VALID(rxcmp) \
236 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
237
238#define RSS_PROFILE_ID_MASK 0x1f
239
240#define RX_CMP_HASH_TYPE(rxcmp) \
241 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
242 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
243
244#define RX_CMP_V3_HASH_TYPE_LEGACY(rxcmp) \
245 ((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_V3_RSS_EXT_OP_LEGACY) >>\
246 RX_CMP_V3_RSS_EXT_OP_LEGACY_SHIFT)
247
248#define RX_CMP_V3_HASH_TYPE_NEW(rxcmp) \
249 ((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_V3_RSS_EXT_OP_NEW) >>\
250 RX_CMP_V3_RSS_EXT_OP_NEW_SHIFT)
251
252#define RX_CMP_V3_HASH_TYPE(bp, rxcmp) \
253 (((bp)->rss_cap & BNXT_RSS_CAP_RSS_TCAM) ? \
254 RX_CMP_V3_HASH_TYPE_NEW(rxcmp) : \
255 RX_CMP_V3_HASH_TYPE_LEGACY(rxcmp))
256
257#define EXT_OP_INNER_4 0x0
258#define EXT_OP_OUTER_4 0x2
259#define EXT_OP_INNFL_3 0x8
260#define EXT_OP_OUTFL_3 0xa
261
262#define RX_CMP_VLAN_VALID(rxcmp) \
263 ((rxcmp)->rx_cmp_misc_v1 & cpu_to_le32(RX_CMP_METADATA1_VALID))
264
265#define RX_CMP_VLAN_TPID_SEL(rxcmp) \
266 (le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_METADATA1_TPID_SEL)
267
268struct rx_cmp_ext {
269 __le32 rx_cmp_flags2;
270 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1
271 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
272 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
273 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
274 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)
275 __le32 rx_cmp_meta_data;
276 #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff
277 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff
278 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000
279 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16
280 __le32 rx_cmp_cfa_code_errors_v2;
281 #define RX_CMP_V (1 << 0)
282 #define RX_CMPL_ERRORS_MASK (0x7fff << 1)
283 #define RX_CMPL_ERRORS_SFT 1
284 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
285 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
286 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)
287 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
288 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
289 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)
290 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)
291 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)
292 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)
293 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)
294 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)
295 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)
296 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)
297 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)
298 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)
299 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)
300 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)
301 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)
302 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)
303 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)
304 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)
305 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)
306 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)
307 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)
308 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)
309 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)
310 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
311 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)
312
313 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
314 #define RX_CMPL_CFA_CODE_SFT 16
315 #define RX_CMPL_METADATA0_TCI_MASK (0xffff << 16)
316 #define RX_CMPL_METADATA0_VID_MASK (0x0fff << 16)
317 #define RX_CMPL_METADATA0_SFT 16
318
319 __le32 rx_cmp_timestamp;
320};
321
322#define RX_CMP_L2_ERRORS \
323 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
324
325#define RX_CMP_L4_CS_BITS \
326 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
327
328#define RX_CMP_L4_CS_ERR_BITS \
329 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
330
331#define RX_CMP_L4_CS_OK(rxcmp1) \
332 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \
333 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
334
335#define RX_CMP_ENCAP(rxcmp1) \
336 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \
337 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
338
339#define RX_CMP_CFA_CODE(rxcmpl1) \
340 ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \
341 RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
342
343#define RX_CMP_METADATA0_TCI(rxcmp1) \
344 ((le32_to_cpu((rxcmp1)->rx_cmp_cfa_code_errors_v2) & \
345 RX_CMPL_METADATA0_TCI_MASK) >> RX_CMPL_METADATA0_SFT)
346
347struct rx_agg_cmp {
348 __le32 rx_agg_cmp_len_flags_type;
349 #define RX_AGG_CMP_TYPE (0x3f << 0)
350 #define RX_AGG_CMP_LEN (0xffff << 16)
351 #define RX_AGG_CMP_LEN_SHIFT 16
352 u32 rx_agg_cmp_opaque;
353 __le32 rx_agg_cmp_v;
354 #define RX_AGG_CMP_V (1 << 0)
355 #define RX_AGG_CMP_AGG_ID (0xffff << 16)
356 #define RX_AGG_CMP_AGG_ID_SHIFT 16
357 __le32 rx_agg_cmp_unused;
358};
359
360#define TPA_AGG_AGG_ID(rx_agg) \
361 ((le32_to_cpu((rx_agg)->rx_agg_cmp_v) & \
362 RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)
363
364struct rx_tpa_start_cmp {
365 __le32 rx_tpa_start_cmp_len_flags_type;
366 #define RX_TPA_START_CMP_TYPE (0x3f << 0)
367 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6)
368 #define RX_TPA_START_CMP_FLAGS_SHIFT 6
369 #define RX_TPA_START_CMP_FLAGS_ERROR (0x1 << 6)
370 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)
371 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7
372 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
373 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
374 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
375 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
376 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)
377 #define RX_TPA_START_CMP_FLAGS_TIMESTAMP (0x1 << 11)
378 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)
379 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12
380 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
381 #define RX_TPA_START_CMP_LEN (0xffff << 16)
382 #define RX_TPA_START_CMP_LEN_SHIFT 16
383
384 u32 rx_tpa_start_cmp_opaque;
385 __le32 rx_tpa_start_cmp_misc_v1;
386 #define RX_TPA_START_CMP_V1 (0x1 << 0)
387 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9)
388 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9
389 #define RX_TPA_START_CMP_V3_RSS_HASH_TYPE (0x1ff << 7)
390 #define RX_TPA_START_CMP_V3_RSS_HASH_TYPE_SHIFT 7
391 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25)
392 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25
393 #define RX_TPA_START_CMP_AGG_ID_P5 (0xffff << 16)
394 #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5 16
395 #define RX_TPA_START_CMP_METADATA1 (0xf << 28)
396 #define RX_TPA_START_CMP_METADATA1_SHIFT 28
397 #define RX_TPA_START_METADATA1_TPID_SEL (0x7 << 28)
398 #define RX_TPA_START_METADATA1_TPID_8021Q (0x1 << 28)
399 #define RX_TPA_START_METADATA1_TPID_8021AD (0x0 << 28)
400 #define RX_TPA_START_METADATA1_VALID (0x8 << 28)
401
402 __le32 rx_tpa_start_cmp_rss_hash;
403};
404
405#define TPA_START_HASH_VALID(rx_tpa_start) \
406 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
407 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
408
409#define TPA_START_HASH_TYPE(rx_tpa_start) \
410 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
411 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \
412 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
413
414#define TPA_START_V3_HASH_TYPE(rx_tpa_start) \
415 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
416 RX_TPA_START_CMP_V3_RSS_HASH_TYPE) >> \
417 RX_TPA_START_CMP_V3_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
418
419#define TPA_START_AGG_ID(rx_tpa_start) \
420 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
421 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
422
423#define TPA_START_AGG_ID_P5(rx_tpa_start) \
424 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
425 RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)
426
427#define TPA_START_ERROR(rx_tpa_start) \
428 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
429 cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))
430
431#define TPA_START_VLAN_VALID(rx_tpa_start) \
432 ((rx_tpa_start)->rx_tpa_start_cmp_misc_v1 & \
433 cpu_to_le32(RX_TPA_START_METADATA1_VALID))
434
435#define TPA_START_VLAN_TPID_SEL(rx_tpa_start) \
436 (le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
437 RX_TPA_START_METADATA1_TPID_SEL)
438
439struct rx_tpa_start_cmp_ext {
440 __le32 rx_tpa_start_cmp_flags2;
441 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)
442 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
443 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
444 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
445 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8)
446 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID (0x1 << 9)
447 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT (0x3 << 10)
448 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT 10
449 #define RX_TPA_START_CMP_V3_FLAGS2_T_IP_TYPE (0x1 << 10)
450 #define RX_TPA_START_CMP_V3_FLAGS2_AGG_GRO (0x1 << 11)
451 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL (0xffff << 16)
452 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT 16
453
454 __le32 rx_tpa_start_cmp_metadata;
455 __le32 rx_tpa_start_cmp_cfa_code_v2;
456 #define RX_TPA_START_CMP_V2 (0x1 << 0)
457 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
458 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT 1
459 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
460 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
461 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
462 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)
463 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16
464 #define RX_TPA_START_CMP_METADATA0_TCI_MASK (0xffff << 16)
465 #define RX_TPA_START_CMP_METADATA0_VID_MASK (0x0fff << 16)
466 #define RX_TPA_START_CMP_METADATA0_SFT 16
467 __le32 rx_tpa_start_cmp_hdr_info;
468};
469
470#define TPA_START_CFA_CODE(rx_tpa_start) \
471 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
472 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
473
474#define TPA_START_IS_IPV6(rx_tpa_start) \
475 (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 & \
476 cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
477
478#define TPA_START_ERROR_CODE(rx_tpa_start) \
479 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
480 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >> \
481 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)
482
483#define TPA_START_METADATA0_TCI(rx_tpa_start) \
484 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
485 RX_TPA_START_CMP_METADATA0_TCI_MASK) >> \
486 RX_TPA_START_CMP_METADATA0_SFT)
487
488struct rx_tpa_end_cmp {
489 __le32 rx_tpa_end_cmp_len_flags_type;
490 #define RX_TPA_END_CMP_TYPE (0x3f << 0)
491 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6)
492 #define RX_TPA_END_CMP_FLAGS_SHIFT 6
493 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7)
494 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7
495 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
496 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
497 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
498 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
499 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10)
500 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12)
501 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12
502 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
503 #define RX_TPA_END_CMP_LEN (0xffff << 16)
504 #define RX_TPA_END_CMP_LEN_SHIFT 16
505
506 u32 rx_tpa_end_cmp_opaque;
507 __le32 rx_tpa_end_cmp_misc_v1;
508 #define RX_TPA_END_CMP_V1 (0x1 << 0)
509 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1)
510 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1
511 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8)
512 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8
513 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16)
514 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16
515 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25)
516 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25
517 #define RX_TPA_END_CMP_AGG_ID_P5 (0xffff << 16)
518 #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5 16
519
520 __le32 rx_tpa_end_cmp_tsdelta;
521 #define RX_TPA_END_GRO_TS (0x1 << 31)
522};
523
524#define TPA_END_AGG_ID(rx_tpa_end) \
525 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
526 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
527
528#define TPA_END_AGG_ID_P5(rx_tpa_end) \
529 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
530 RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)
531
532#define TPA_END_PAYLOAD_OFF(rx_tpa_end) \
533 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
534 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)
535
536#define TPA_END_AGG_BUFS(rx_tpa_end) \
537 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
538 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)
539
540#define TPA_END_TPA_SEGS(rx_tpa_end) \
541 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
542 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
543
544#define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \
545 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \
546 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
547
548#define TPA_END_GRO(rx_tpa_end) \
549 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \
550 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
551
552#define TPA_END_GRO_TS(rx_tpa_end) \
553 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \
554 cpu_to_le32(RX_TPA_END_GRO_TS)))
555
556struct rx_tpa_end_cmp_ext {
557 __le32 rx_tpa_end_cmp_dup_acks;
558 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)
559 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5 (0xff << 16)
560 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5 16
561 #define RX_TPA_END_CMP_AGG_BUFS_P5 (0xff << 24)
562 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5 24
563
564 __le32 rx_tpa_end_cmp_seg_len;
565 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)
566
567 __le32 rx_tpa_end_cmp_errors_v2;
568 #define RX_TPA_END_CMP_V2 (0x1 << 0)
569 #define RX_TPA_END_CMP_ERRORS (0x3 << 1)
570 #define RX_TPA_END_CMP_ERRORS_P5 (0x7 << 1)
571 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1
572 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
573 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
574 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
575 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR (0x4 << 1)
576 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
577
578 u32 rx_tpa_end_cmp_start_opaque;
579};
580
581#define TPA_END_ERRORS(rx_tpa_end_ext) \
582 ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \
583 cpu_to_le32(RX_TPA_END_CMP_ERRORS))
584
585#define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext) \
586 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
587 RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >> \
588 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)
589
590#define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext) \
591 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
592 RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)
593
594#define EVENT_DATA1_RESET_NOTIFY_FATAL(data1) \
595 (((data1) & \
596 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
597 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)
598
599#define EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1) \
600 (((data1) & \
601 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
602 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION)
603
604#define EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2) \
605 ((data2) & \
606 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK)
607
608#define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1) \
609 !!((data1) & \
610 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
611
612#define EVENT_DATA1_RECOVERY_ENABLED(data1) \
613 !!((data1) & \
614 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
615
616#define BNXT_EVENT_ERROR_REPORT_TYPE(data1) \
617 (((data1) & \
618 ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >>\
619 ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT)
620
621#define BNXT_EVENT_INVALID_SIGNAL_DATA(data2) \
622 (((data2) & \
623 ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK) >>\
624 ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT)
625
626struct nqe_cn {
627 __le16 type;
628 #define NQ_CN_TYPE_MASK 0x3fUL
629 #define NQ_CN_TYPE_SFT 0
630 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
631 #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
632 #define NQ_CN_TOGGLE_MASK 0xc0UL
633 #define NQ_CN_TOGGLE_SFT 6
634 __le16 reserved16;
635 __le32 cq_handle_low;
636 __le32 v;
637 #define NQ_CN_V 0x1UL
638 __le32 cq_handle_high;
639};
640
641#define BNXT_NQ_HDL_IDX_MASK 0x00ffffff
642#define BNXT_NQ_HDL_TYPE_MASK 0xff000000
643#define BNXT_NQ_HDL_TYPE_SHIFT 24
644#define BNXT_NQ_HDL_TYPE_RX 0x00
645#define BNXT_NQ_HDL_TYPE_TX 0x01
646
647#define BNXT_NQ_HDL_IDX(hdl) ((hdl) & BNXT_NQ_HDL_IDX_MASK)
648#define BNXT_NQ_HDL_TYPE(hdl) (((hdl) & BNXT_NQ_HDL_TYPE_MASK) >> \
649 BNXT_NQ_HDL_TYPE_SHIFT)
650
651#define BNXT_SET_NQ_HDL(cpr) \
652 (((cpr)->cp_ring_type << BNXT_NQ_HDL_TYPE_SHIFT) | (cpr)->cp_idx)
653
654#define NQE_CN_TYPE(type) ((type) & NQ_CN_TYPE_MASK)
655#define NQE_CN_TOGGLE(type) (((type) & NQ_CN_TOGGLE_MASK) >> \
656 NQ_CN_TOGGLE_SFT)
657
658#define DB_IDX_MASK 0xffffff
659#define DB_IDX_VALID (0x1 << 26)
660#define DB_IRQ_DIS (0x1 << 27)
661#define DB_KEY_TX (0x0 << 28)
662#define DB_KEY_RX (0x1 << 28)
663#define DB_KEY_CP (0x2 << 28)
664#define DB_KEY_ST (0x3 << 28)
665#define DB_KEY_TX_PUSH (0x4 << 28)
666#define DB_LONG_TX_PUSH (0x2 << 24)
667
668#define BNXT_MIN_ROCE_CP_RINGS 2
669#define BNXT_MIN_ROCE_STAT_CTXS 1
670
671/* 64-bit doorbell */
672#define DBR_INDEX_MASK 0x0000000000ffffffULL
673#define DBR_EPOCH_MASK 0x01000000UL
674#define DBR_EPOCH_SFT 24
675#define DBR_TOGGLE_MASK 0x06000000UL
676#define DBR_TOGGLE_SFT 25
677#define DBR_XID_MASK 0x000fffff00000000ULL
678#define DBR_XID_SFT 32
679#define DBR_PATH_L2 (0x1ULL << 56)
680#define DBR_VALID (0x1ULL << 58)
681#define DBR_TYPE_SQ (0x0ULL << 60)
682#define DBR_TYPE_RQ (0x1ULL << 60)
683#define DBR_TYPE_SRQ (0x2ULL << 60)
684#define DBR_TYPE_SRQ_ARM (0x3ULL << 60)
685#define DBR_TYPE_CQ (0x4ULL << 60)
686#define DBR_TYPE_CQ_ARMSE (0x5ULL << 60)
687#define DBR_TYPE_CQ_ARMALL (0x6ULL << 60)
688#define DBR_TYPE_CQ_ARMENA (0x7ULL << 60)
689#define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60)
690#define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60)
691#define DBR_TYPE_NQ (0xaULL << 60)
692#define DBR_TYPE_NQ_ARM (0xbULL << 60)
693#define DBR_TYPE_NQ_MASK (0xeULL << 60)
694#define DBR_TYPE_NULL (0xfULL << 60)
695
696#define DB_PF_OFFSET_P5 0x10000
697#define DB_VF_OFFSET_P5 0x4000
698
699#define INVALID_HW_RING_ID ((u16)-1)
700
701/* The hardware supports certain page sizes. Use the supported page sizes
702 * to allocate the rings.
703 */
704#if (PAGE_SHIFT < 12)
705#define BNXT_PAGE_SHIFT 12
706#elif (PAGE_SHIFT <= 13)
707#define BNXT_PAGE_SHIFT PAGE_SHIFT
708#elif (PAGE_SHIFT < 16)
709#define BNXT_PAGE_SHIFT 13
710#else
711#define BNXT_PAGE_SHIFT 16
712#endif
713
714#define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)
715
716/* The RXBD length is 16-bit so we can only support page sizes < 64K */
717#if (PAGE_SHIFT > 15)
718#define BNXT_RX_PAGE_SHIFT 15
719#else
720#define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
721#endif
722
723#define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
724
725#define BNXT_MAX_MTU 9500
726
727/* First RX buffer page in XDP multi-buf mode
728 *
729 * +-------------------------------------------------------------------------+
730 * | XDP_PACKET_HEADROOM | bp->rx_buf_use_size | skb_shared_info|
731 * | (bp->rx_dma_offset) | | |
732 * +-------------------------------------------------------------------------+
733 */
734#define BNXT_MAX_PAGE_MODE_MTU_SBUF \
735 ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \
736 XDP_PACKET_HEADROOM)
737#define BNXT_MAX_PAGE_MODE_MTU \
738 (BNXT_MAX_PAGE_MODE_MTU_SBUF - \
739 SKB_DATA_ALIGN((unsigned int)sizeof(struct skb_shared_info)))
740
741#define BNXT_MIN_PKT_SIZE 52
742
743#define BNXT_DEFAULT_RX_RING_SIZE 511
744#define BNXT_DEFAULT_TX_RING_SIZE 511
745
746#define MAX_TPA 64
747#define MAX_TPA_P5 256
748#define MAX_TPA_P5_MASK (MAX_TPA_P5 - 1)
749#define MAX_TPA_SEGS_P5 0x3f
750
751#if (BNXT_PAGE_SHIFT == 16)
752#define MAX_RX_PAGES_AGG_ENA 1
753#define MAX_RX_PAGES 4
754#define MAX_RX_AGG_PAGES 4
755#define MAX_TX_PAGES 1
756#define MAX_CP_PAGES 16
757#else
758#define MAX_RX_PAGES_AGG_ENA 8
759#define MAX_RX_PAGES 32
760#define MAX_RX_AGG_PAGES 32
761#define MAX_TX_PAGES 8
762#define MAX_CP_PAGES 128
763#endif
764
765#define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
766#define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
767#define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
768
769#define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
770#define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
771
772#define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
773
774#define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
775#define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
776
777#define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
778
779#define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1)
780#define BNXT_MAX_RX_DESC_CNT_JUM_ENA (RX_DESC_CNT * MAX_RX_PAGES_AGG_ENA - 1)
781#define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
782#define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)
783
784/* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1. We need one extra
785 * BD because the first TX BD is always a long BD.
786 */
787#define BNXT_MIN_TX_DESC_CNT (MAX_SKB_FRAGS + 2)
788
789#define RX_RING(bp, x) (((x) & (bp)->rx_ring_mask) >> (BNXT_PAGE_SHIFT - 4))
790#define RX_AGG_RING(bp, x) (((x) & (bp)->rx_agg_ring_mask) >> \
791 (BNXT_PAGE_SHIFT - 4))
792#define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
793
794#define TX_RING(bp, x) (((x) & (bp)->tx_ring_mask) >> (BNXT_PAGE_SHIFT - 4))
795#define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))
796
797#define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
798#define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))
799
800#define TX_CMP_VALID(txcmp, raw_cons) \
801 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \
802 !((raw_cons) & bp->cp_bit))
803
804#define RX_CMP_VALID(rxcmp1, raw_cons) \
805 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
806 !((raw_cons) & bp->cp_bit))
807
808#define RX_AGG_CMP_VALID(agg, raw_cons) \
809 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
810 !((raw_cons) & bp->cp_bit))
811
812#define NQ_CMP_VALID(nqcmp, raw_cons) \
813 (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
814
815#define TX_CMP_TYPE(txcmp) \
816 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
817
818#define RX_CMP_TYPE(rxcmp) \
819 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
820
821#define RING_RX(bp, idx) ((idx) & (bp)->rx_ring_mask)
822#define NEXT_RX(idx) ((idx) + 1)
823
824#define RING_RX_AGG(bp, idx) ((idx) & (bp)->rx_agg_ring_mask)
825#define NEXT_RX_AGG(idx) ((idx) + 1)
826
827#define RING_TX(bp, idx) ((idx) & (bp)->tx_ring_mask)
828#define NEXT_TX(idx) ((idx) + 1)
829
830#define ADV_RAW_CMP(idx, n) ((idx) + (n))
831#define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1)
832#define RING_CMP(idx) ((idx) & bp->cp_ring_mask)
833#define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1))
834
835#define DFLT_HWRM_CMD_TIMEOUT 500
836
837#define BNXT_RX_EVENT 1
838#define BNXT_AGG_EVENT 2
839#define BNXT_TX_EVENT 4
840#define BNXT_REDIRECT_EVENT 8
841#define BNXT_TX_CMP_EVENT 0x10
842
843struct bnxt_sw_tx_bd {
844 union {
845 struct sk_buff *skb;
846 struct xdp_frame *xdpf;
847 };
848 DEFINE_DMA_UNMAP_ADDR(mapping);
849 DEFINE_DMA_UNMAP_LEN(len);
850 struct page *page;
851 u8 is_gso;
852 u8 is_push;
853 u8 action;
854 unsigned short nr_frags;
855 u16 rx_prod;
856};
857
858struct bnxt_sw_rx_bd {
859 void *data;
860 u8 *data_ptr;
861 dma_addr_t mapping;
862};
863
864struct bnxt_sw_rx_agg_bd {
865 struct page *page;
866 unsigned int offset;
867 dma_addr_t mapping;
868};
869
870struct bnxt_ring_mem_info {
871 int nr_pages;
872 int page_size;
873 u16 flags;
874#define BNXT_RMEM_VALID_PTE_FLAG 1
875#define BNXT_RMEM_RING_PTE_FLAG 2
876#define BNXT_RMEM_USE_FULL_PAGE_FLAG 4
877
878 u16 depth;
879 struct bnxt_ctx_mem_type *ctx_mem;
880
881 void **pg_arr;
882 dma_addr_t *dma_arr;
883
884 __le64 *pg_tbl;
885 dma_addr_t pg_tbl_map;
886
887 int vmem_size;
888 void **vmem;
889};
890
891struct bnxt_ring_struct {
892 struct bnxt_ring_mem_info ring_mem;
893
894 u16 fw_ring_id; /* Ring id filled by Chimp FW */
895 union {
896 u16 grp_idx;
897 u16 map_idx; /* Used by cmpl rings */
898 };
899 u32 handle;
900 u8 queue_id;
901};
902
903struct tx_push_bd {
904 __le32 doorbell;
905 __le32 tx_bd_len_flags_type;
906 u32 tx_bd_opaque;
907 struct tx_bd_ext txbd2;
908};
909
910struct tx_push_buffer {
911 struct tx_push_bd push_bd;
912 u32 data[25];
913};
914
915struct bnxt_db_info {
916 void __iomem *doorbell;
917 union {
918 u64 db_key64;
919 u32 db_key32;
920 };
921 u32 db_ring_mask;
922 u32 db_epoch_mask;
923 u8 db_epoch_shift;
924};
925
926#define DB_EPOCH(db, idx) (((idx) & (db)->db_epoch_mask) << \
927 ((db)->db_epoch_shift))
928
929#define DB_TOGGLE(tgl) ((tgl) << DBR_TOGGLE_SFT)
930
931#define DB_RING_IDX(db, idx) (((idx) & (db)->db_ring_mask) | \
932 DB_EPOCH(db, idx))
933
934struct bnxt_tx_ring_info {
935 struct bnxt_napi *bnapi;
936 struct bnxt_cp_ring_info *tx_cpr;
937 u16 tx_prod;
938 u16 tx_cons;
939 u16 tx_hw_cons;
940 u16 txq_index;
941 u8 tx_napi_idx;
942 u8 kick_pending;
943 struct bnxt_db_info tx_db;
944
945 struct tx_bd *tx_desc_ring[MAX_TX_PAGES];
946 struct bnxt_sw_tx_bd *tx_buf_ring;
947
948 dma_addr_t tx_desc_mapping[MAX_TX_PAGES];
949
950 struct tx_push_buffer *tx_push;
951 dma_addr_t tx_push_mapping;
952 __le64 data_mapping;
953
954#define BNXT_DEV_STATE_CLOSING 0x1
955 u32 dev_state;
956
957 struct bnxt_ring_struct tx_ring_struct;
958 /* Synchronize simultaneous xdp_xmit on same ring */
959 spinlock_t xdp_tx_lock;
960};
961
962#define BNXT_LEGACY_COAL_CMPL_PARAMS \
963 (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN | \
964 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX | \
965 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET | \
966 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE | \
967 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR | \
968 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
969 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR | \
970 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
971 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
972
973#define BNXT_COAL_CMPL_ENABLES \
974 (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
975 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
976 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
977 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
978
979#define BNXT_COAL_CMPL_MIN_TMR_ENABLE \
980 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
981
982#define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE \
983 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
984
985struct bnxt_coal_cap {
986 u32 cmpl_params;
987 u32 nq_params;
988 u16 num_cmpl_dma_aggr_max;
989 u16 num_cmpl_dma_aggr_during_int_max;
990 u16 cmpl_aggr_dma_tmr_max;
991 u16 cmpl_aggr_dma_tmr_during_int_max;
992 u16 int_lat_tmr_min_max;
993 u16 int_lat_tmr_max_max;
994 u16 num_cmpl_aggr_int_max;
995 u16 timer_units;
996};
997
998struct bnxt_coal {
999 u16 coal_ticks;
1000 u16 coal_ticks_irq;
1001 u16 coal_bufs;
1002 u16 coal_bufs_irq;
1003 /* RING_IDLE enabled when coal ticks < idle_thresh */
1004 u16 idle_thresh;
1005 u8 bufs_per_record;
1006 u8 budget;
1007 u16 flags;
1008};
1009
1010struct bnxt_tpa_info {
1011 void *data;
1012 u8 *data_ptr;
1013 dma_addr_t mapping;
1014 u16 len;
1015 unsigned short gso_type;
1016 u32 flags2;
1017 u32 metadata;
1018 enum pkt_hash_types hash_type;
1019 u32 rss_hash;
1020 u32 hdr_info;
1021
1022#define BNXT_TPA_L4_SIZE(hdr_info) \
1023 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
1024
1025#define BNXT_TPA_INNER_L3_OFF(hdr_info) \
1026 (((hdr_info) >> 18) & 0x1ff)
1027
1028#define BNXT_TPA_INNER_L2_OFF(hdr_info) \
1029 (((hdr_info) >> 9) & 0x1ff)
1030
1031#define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
1032 ((hdr_info) & 0x1ff)
1033
1034 u16 cfa_code; /* cfa_code in TPA start compl */
1035 u8 agg_count;
1036 u8 vlan_valid:1;
1037 u8 cfa_code_valid:1;
1038 struct rx_agg_cmp *agg_arr;
1039};
1040
1041#define BNXT_AGG_IDX_BMAP_SIZE (MAX_TPA_P5 / BITS_PER_LONG)
1042
1043struct bnxt_tpa_idx_map {
1044 u16 agg_id_tbl[1024];
1045 unsigned long agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];
1046};
1047
1048struct bnxt_rx_ring_info {
1049 struct bnxt_napi *bnapi;
1050 struct bnxt_cp_ring_info *rx_cpr;
1051 u16 rx_prod;
1052 u16 rx_agg_prod;
1053 u16 rx_sw_agg_prod;
1054 u16 rx_next_cons;
1055 struct bnxt_db_info rx_db;
1056 struct bnxt_db_info rx_agg_db;
1057
1058 struct bpf_prog *xdp_prog;
1059
1060 struct rx_bd *rx_desc_ring[MAX_RX_PAGES];
1061 struct bnxt_sw_rx_bd *rx_buf_ring;
1062
1063 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
1064 struct bnxt_sw_rx_agg_bd *rx_agg_ring;
1065
1066 unsigned long *rx_agg_bmap;
1067 u16 rx_agg_bmap_size;
1068
1069 dma_addr_t rx_desc_mapping[MAX_RX_PAGES];
1070 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
1071
1072 struct bnxt_tpa_info *rx_tpa;
1073 struct bnxt_tpa_idx_map *rx_tpa_idx_map;
1074
1075 struct bnxt_ring_struct rx_ring_struct;
1076 struct bnxt_ring_struct rx_agg_ring_struct;
1077 struct xdp_rxq_info xdp_rxq;
1078 struct page_pool *page_pool;
1079};
1080
1081struct bnxt_rx_sw_stats {
1082 u64 rx_l4_csum_errors;
1083 u64 rx_resets;
1084 u64 rx_buf_errors;
1085 u64 rx_oom_discards;
1086 u64 rx_netpoll_discards;
1087};
1088
1089struct bnxt_tx_sw_stats {
1090 u64 tx_resets;
1091};
1092
1093struct bnxt_cmn_sw_stats {
1094 u64 missed_irqs;
1095};
1096
1097struct bnxt_sw_stats {
1098 struct bnxt_rx_sw_stats rx;
1099 struct bnxt_tx_sw_stats tx;
1100 struct bnxt_cmn_sw_stats cmn;
1101};
1102
1103struct bnxt_total_ring_err_stats {
1104 u64 rx_total_l4_csum_errors;
1105 u64 rx_total_resets;
1106 u64 rx_total_buf_errors;
1107 u64 rx_total_oom_discards;
1108 u64 rx_total_netpoll_discards;
1109 u64 rx_total_ring_discards;
1110 u64 tx_total_resets;
1111 u64 tx_total_ring_discards;
1112 u64 total_missed_irqs;
1113};
1114
1115struct bnxt_stats_mem {
1116 u64 *sw_stats;
1117 u64 *hw_masks;
1118 void *hw_stats;
1119 dma_addr_t hw_stats_map;
1120 int len;
1121};
1122
1123struct bnxt_cp_ring_info {
1124 struct bnxt_napi *bnapi;
1125 u32 cp_raw_cons;
1126 struct bnxt_db_info cp_db;
1127
1128 u8 had_work_done:1;
1129 u8 has_more_work:1;
1130 u8 had_nqe_notify:1;
1131 u8 toggle;
1132
1133 u8 cp_ring_type;
1134 u8 cp_idx;
1135
1136 u32 last_cp_raw_cons;
1137
1138 struct bnxt_coal rx_ring_coal;
1139 u64 rx_packets;
1140 u64 rx_bytes;
1141 u64 event_ctr;
1142
1143 struct dim dim;
1144
1145 union {
1146 struct tx_cmp **cp_desc_ring;
1147 struct nqe_cn **nq_desc_ring;
1148 };
1149
1150 dma_addr_t *cp_desc_mapping;
1151
1152 struct bnxt_stats_mem stats;
1153 u32 hw_stats_ctx_id;
1154
1155 struct bnxt_sw_stats sw_stats;
1156
1157 struct bnxt_ring_struct cp_ring_struct;
1158
1159 int cp_ring_count;
1160 struct bnxt_cp_ring_info *cp_ring_arr;
1161};
1162
1163#define BNXT_MAX_QUEUE 8
1164#define BNXT_MAX_TXR_PER_NAPI BNXT_MAX_QUEUE
1165
1166#define bnxt_for_each_napi_tx(iter, bnapi, txr) \
1167 for (iter = 0, txr = (bnapi)->tx_ring[0]; txr; \
1168 txr = (iter < BNXT_MAX_TXR_PER_NAPI - 1) ? \
1169 (bnapi)->tx_ring[++iter] : NULL)
1170
1171struct bnxt_napi {
1172 struct napi_struct napi;
1173 struct bnxt *bp;
1174
1175 int index;
1176 struct bnxt_cp_ring_info cp_ring;
1177 struct bnxt_rx_ring_info *rx_ring;
1178 struct bnxt_tx_ring_info *tx_ring[BNXT_MAX_TXR_PER_NAPI];
1179
1180 void (*tx_int)(struct bnxt *, struct bnxt_napi *,
1181 int budget);
1182 u8 events;
1183 u8 tx_fault:1;
1184
1185 u32 flags;
1186#define BNXT_NAPI_FLAG_XDP 0x1
1187
1188 bool in_reset;
1189};
1190
1191struct bnxt_irq {
1192 irq_handler_t handler;
1193 unsigned int vector;
1194 u8 requested:1;
1195 u8 have_cpumask:1;
1196 char name[IFNAMSIZ + 2];
1197 cpumask_var_t cpu_mask;
1198};
1199
1200#define HWRM_RING_ALLOC_TX 0x1
1201#define HWRM_RING_ALLOC_RX 0x2
1202#define HWRM_RING_ALLOC_AGG 0x4
1203#define HWRM_RING_ALLOC_CMPL 0x8
1204#define HWRM_RING_ALLOC_NQ 0x10
1205
1206#define INVALID_STATS_CTX_ID -1
1207
1208struct bnxt_ring_grp_info {
1209 u16 fw_stats_ctx;
1210 u16 fw_grp_id;
1211 u16 rx_fw_ring_id;
1212 u16 agg_fw_ring_id;
1213 u16 cp_fw_ring_id;
1214};
1215
1216struct bnxt_vnic_info {
1217 u16 fw_vnic_id; /* returned by Chimp during alloc */
1218#define BNXT_MAX_CTX_PER_VNIC 8
1219 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
1220 u16 fw_l2_ctx_id;
1221#define BNXT_MAX_UC_ADDRS 4
1222 struct bnxt_l2_filter *l2_filters[BNXT_MAX_UC_ADDRS];
1223 /* index 0 always dev_addr */
1224 u16 uc_filter_count;
1225 u8 *uc_list;
1226
1227 u16 *fw_grp_ids;
1228 dma_addr_t rss_table_dma_addr;
1229 __le16 *rss_table;
1230 dma_addr_t rss_hash_key_dma_addr;
1231 u64 *rss_hash_key;
1232 int rss_table_size;
1233#define BNXT_RSS_TABLE_ENTRIES_P5 64
1234#define BNXT_RSS_TABLE_SIZE_P5 (BNXT_RSS_TABLE_ENTRIES_P5 * 4)
1235#define BNXT_RSS_TABLE_MAX_TBL_P5 8
1236#define BNXT_MAX_RSS_TABLE_SIZE_P5 \
1237 (BNXT_RSS_TABLE_SIZE_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1238#define BNXT_MAX_RSS_TABLE_ENTRIES_P5 \
1239 (BNXT_RSS_TABLE_ENTRIES_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1240
1241 u32 rx_mask;
1242
1243 u8 *mc_list;
1244 int mc_list_size;
1245 int mc_list_count;
1246 dma_addr_t mc_list_mapping;
1247#define BNXT_MAX_MC_ADDRS 16
1248
1249 u32 flags;
1250#define BNXT_VNIC_RSS_FLAG 1
1251#define BNXT_VNIC_RFS_FLAG 2
1252#define BNXT_VNIC_MCAST_FLAG 4
1253#define BNXT_VNIC_UCAST_FLAG 8
1254#define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10
1255};
1256
1257struct bnxt_hw_resc {
1258 u16 min_rsscos_ctxs;
1259 u16 max_rsscos_ctxs;
1260 u16 min_cp_rings;
1261 u16 max_cp_rings;
1262 u16 resv_cp_rings;
1263 u16 min_tx_rings;
1264 u16 max_tx_rings;
1265 u16 resv_tx_rings;
1266 u16 max_tx_sch_inputs;
1267 u16 min_rx_rings;
1268 u16 max_rx_rings;
1269 u16 resv_rx_rings;
1270 u16 min_hw_ring_grps;
1271 u16 max_hw_ring_grps;
1272 u16 resv_hw_ring_grps;
1273 u16 min_l2_ctxs;
1274 u16 max_l2_ctxs;
1275 u16 min_vnics;
1276 u16 max_vnics;
1277 u16 resv_vnics;
1278 u16 min_stat_ctxs;
1279 u16 max_stat_ctxs;
1280 u16 resv_stat_ctxs;
1281 u16 max_nqs;
1282 u16 max_irqs;
1283 u16 resv_irqs;
1284};
1285
1286#if defined(CONFIG_BNXT_SRIOV)
1287struct bnxt_vf_info {
1288 u16 fw_fid;
1289 u8 mac_addr[ETH_ALEN]; /* PF assigned MAC Address */
1290 u8 vf_mac_addr[ETH_ALEN]; /* VF assigned MAC address, only
1291 * stored by PF.
1292 */
1293 u16 vlan;
1294 u16 func_qcfg_flags;
1295 u32 flags;
1296#define BNXT_VF_QOS 0x1
1297#define BNXT_VF_SPOOFCHK 0x2
1298#define BNXT_VF_LINK_FORCED 0x4
1299#define BNXT_VF_LINK_UP 0x8
1300#define BNXT_VF_TRUST 0x10
1301 u32 min_tx_rate;
1302 u32 max_tx_rate;
1303 void *hwrm_cmd_req_addr;
1304 dma_addr_t hwrm_cmd_req_dma_addr;
1305};
1306#endif
1307
1308struct bnxt_pf_info {
1309#define BNXT_FIRST_PF_FID 1
1310#define BNXT_FIRST_VF_FID 128
1311 u16 fw_fid;
1312 u16 port_id;
1313 u8 mac_addr[ETH_ALEN];
1314 u32 first_vf_id;
1315 u16 active_vfs;
1316 u16 registered_vfs;
1317 u16 max_vfs;
1318 u32 max_encap_records;
1319 u32 max_decap_records;
1320 u32 max_tx_em_flows;
1321 u32 max_tx_wm_flows;
1322 u32 max_rx_em_flows;
1323 u32 max_rx_wm_flows;
1324 unsigned long *vf_event_bmap;
1325 u16 hwrm_cmd_req_pages;
1326 u8 vf_resv_strategy;
1327#define BNXT_VF_RESV_STRATEGY_MAXIMAL 0
1328#define BNXT_VF_RESV_STRATEGY_MINIMAL 1
1329#define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC 2
1330 void *hwrm_cmd_req_addr[4];
1331 dma_addr_t hwrm_cmd_req_dma_addr[4];
1332 struct bnxt_vf_info *vf;
1333};
1334
1335struct bnxt_filter_base {
1336 struct hlist_node hash;
1337 __le64 filter_id;
1338 u8 type;
1339#define BNXT_FLTR_TYPE_NTUPLE 1
1340#define BNXT_FLTR_TYPE_L2 2
1341 u8 flags;
1342#define BNXT_ACT_DROP 1
1343#define BNXT_ACT_RING_DST 2
1344#define BNXT_ACT_FUNC_DST 4
1345#define BNXT_ACT_NO_AGING 8
1346 u16 sw_id;
1347 u16 rxq;
1348 u16 fw_vnic_id;
1349 u16 vf_idx;
1350 unsigned long state;
1351#define BNXT_FLTR_VALID 0
1352#define BNXT_FLTR_INSERTED 1
1353#define BNXT_FLTR_FW_DELETED 2
1354
1355 struct rcu_head rcu;
1356};
1357
1358struct bnxt_ntuple_filter {
1359 struct bnxt_filter_base base;
1360 struct flow_keys fkeys;
1361 struct bnxt_l2_filter *l2_fltr;
1362 u32 ntuple_flags;
1363#define BNXT_NTUPLE_MATCH_SRC_IP 1
1364#define BNXT_NTUPLE_MATCH_DST_IP 2
1365#define BNXT_NTUPLE_MATCH_SRC_PORT 4
1366#define BNXT_NTUPLE_MATCH_DST_PORT 8
1367#define BNXT_NTUPLE_MATCH_ALL (BNXT_NTUPLE_MATCH_SRC_IP | \
1368 BNXT_NTUPLE_MATCH_DST_IP | \
1369 BNXT_NTUPLE_MATCH_SRC_PORT | \
1370 BNXT_NTUPLE_MATCH_DST_PORT)
1371 u32 flow_id;
1372};
1373
1374struct bnxt_l2_key {
1375 union {
1376 struct {
1377 u8 dst_mac_addr[ETH_ALEN];
1378 u16 vlan;
1379 };
1380 u32 filter_key;
1381 };
1382};
1383
1384struct bnxt_ipv4_tuple {
1385 struct flow_dissector_key_ipv4_addrs v4addrs;
1386 struct flow_dissector_key_ports ports;
1387};
1388
1389struct bnxt_ipv6_tuple {
1390 struct flow_dissector_key_ipv6_addrs v6addrs;
1391 struct flow_dissector_key_ports ports;
1392};
1393
1394#define BNXT_L2_KEY_SIZE (sizeof(struct bnxt_l2_key) / 4)
1395
1396struct bnxt_l2_filter {
1397 struct bnxt_filter_base base;
1398 struct bnxt_l2_key l2_key;
1399 atomic_t refcnt;
1400};
1401
1402struct bnxt_link_info {
1403 u8 phy_type;
1404 u8 media_type;
1405 u8 transceiver;
1406 u8 phy_addr;
1407 u8 phy_link_status;
1408#define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK
1409#define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL
1410#define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK
1411 u8 wire_speed;
1412 u8 phy_state;
1413#define BNXT_PHY_STATE_ENABLED 0
1414#define BNXT_PHY_STATE_DISABLED 1
1415
1416 u8 link_state;
1417#define BNXT_LINK_STATE_UNKNOWN 0
1418#define BNXT_LINK_STATE_DOWN 1
1419#define BNXT_LINK_STATE_UP 2
1420#define BNXT_LINK_IS_UP(bp) ((bp)->link_info.link_state == BNXT_LINK_STATE_UP)
1421 u8 active_lanes;
1422 u8 duplex;
1423#define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1424#define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1425 u8 pause;
1426#define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX
1427#define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX
1428#define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \
1429 PORT_PHY_QCFG_RESP_PAUSE_TX)
1430 u8 lp_pause;
1431 u8 auto_pause_setting;
1432 u8 force_pause_setting;
1433 u8 duplex_setting;
1434 u8 auto_mode;
1435#define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \
1436 (mode) <= BNXT_LINK_AUTO_MSK)
1437#define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1438#define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1439#define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1440#define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1441#define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1442#define PHY_VER_LEN 3
1443 u8 phy_ver[PHY_VER_LEN];
1444 u16 link_speed;
1445#define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1446#define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1447#define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1448#define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1449#define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1450#define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1451#define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1452#define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1453#define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1454#define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1455#define BNXT_LINK_SPEED_200GB PORT_PHY_QCFG_RESP_LINK_SPEED_200GB
1456#define BNXT_LINK_SPEED_400GB PORT_PHY_QCFG_RESP_LINK_SPEED_400GB
1457 u16 support_speeds;
1458 u16 support_pam4_speeds;
1459 u16 support_speeds2;
1460
1461 u16 auto_link_speeds; /* fw adv setting */
1462#define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1463#define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1464#define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1465#define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1466#define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1467#define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1468#define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1469#define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1470#define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1471#define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1472 u16 auto_pam4_link_speeds;
1473#define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G
1474#define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G
1475#define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G
1476 u16 auto_link_speeds2;
1477#define BNXT_LINK_SPEEDS2_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB
1478#define BNXT_LINK_SPEEDS2_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB
1479#define BNXT_LINK_SPEEDS2_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_25GB
1480#define BNXT_LINK_SPEEDS2_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_40GB
1481#define BNXT_LINK_SPEEDS2_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB
1482#define BNXT_LINK_SPEEDS2_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB
1483#define BNXT_LINK_SPEEDS2_MSK_50GB_PAM4 \
1484 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB_PAM4_56
1485#define BNXT_LINK_SPEEDS2_MSK_100GB_PAM4 \
1486 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_56
1487#define BNXT_LINK_SPEEDS2_MSK_200GB_PAM4 \
1488 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_56
1489#define BNXT_LINK_SPEEDS2_MSK_400GB_PAM4 \
1490 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_56
1491#define BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112 \
1492 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_112
1493#define BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112 \
1494 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_112
1495#define BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112 \
1496 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_112
1497
1498 u16 support_auto_speeds;
1499 u16 support_pam4_auto_speeds;
1500 u16 support_auto_speeds2;
1501
1502 u16 lp_auto_link_speeds;
1503 u16 lp_auto_pam4_link_speeds;
1504 u16 force_link_speed;
1505 u16 force_pam4_link_speed;
1506 u16 force_link_speed2;
1507#define BNXT_LINK_SPEED_50GB_PAM4 \
1508 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56
1509#define BNXT_LINK_SPEED_100GB_PAM4 \
1510 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56
1511#define BNXT_LINK_SPEED_200GB_PAM4 \
1512 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56
1513#define BNXT_LINK_SPEED_400GB_PAM4 \
1514 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56
1515#define BNXT_LINK_SPEED_100GB_PAM4_112 \
1516 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112
1517#define BNXT_LINK_SPEED_200GB_PAM4_112 \
1518 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112
1519#define BNXT_LINK_SPEED_400GB_PAM4_112 \
1520 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112
1521
1522 u32 preemphasis;
1523 u8 module_status;
1524 u8 active_fec_sig_mode;
1525 u16 fec_cfg;
1526#define BNXT_FEC_NONE PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
1527#define BNXT_FEC_AUTONEG_CAP PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED
1528#define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1529#define BNXT_FEC_ENC_BASE_R_CAP \
1530 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED
1531#define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1532#define BNXT_FEC_ENC_RS_CAP \
1533 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED
1534#define BNXT_FEC_ENC_LLRS_CAP \
1535 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED | \
1536 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED)
1537#define BNXT_FEC_ENC_RS \
1538 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED | \
1539 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED | \
1540 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED)
1541#define BNXT_FEC_ENC_LLRS \
1542 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED | \
1543 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED)
1544
1545 /* copy of requested setting from ethtool cmd */
1546 u8 autoneg;
1547#define BNXT_AUTONEG_SPEED 1
1548#define BNXT_AUTONEG_FLOW_CTRL 2
1549 u8 req_signal_mode;
1550#define BNXT_SIG_MODE_NRZ PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ
1551#define BNXT_SIG_MODE_PAM4 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
1552#define BNXT_SIG_MODE_PAM4_112 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112
1553#define BNXT_SIG_MODE_MAX (PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST + 1)
1554 u8 req_duplex;
1555 u8 req_flow_ctrl;
1556 u16 req_link_speed;
1557 u16 advertising; /* user adv setting */
1558 u16 advertising_pam4;
1559 bool force_link_chng;
1560
1561 bool phy_retry;
1562 unsigned long phy_retry_expires;
1563
1564 /* a copy of phy_qcfg output used to report link
1565 * info to VF
1566 */
1567 struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1568};
1569
1570#define BNXT_FEC_RS544_ON \
1571 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE | \
1572 PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE)
1573
1574#define BNXT_FEC_RS544_OFF \
1575 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE | \
1576 PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE)
1577
1578#define BNXT_FEC_RS272_ON \
1579 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE | \
1580 PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE)
1581
1582#define BNXT_FEC_RS272_OFF \
1583 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE | \
1584 PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE)
1585
1586#define BNXT_PAM4_SUPPORTED(link_info) \
1587 ((link_info)->support_pam4_speeds)
1588
1589#define BNXT_FEC_RS_ON(link_info) \
1590 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \
1591 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1592 (BNXT_PAM4_SUPPORTED(link_info) ? \
1593 (BNXT_FEC_RS544_ON | BNXT_FEC_RS272_OFF) : 0))
1594
1595#define BNXT_FEC_LLRS_ON \
1596 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \
1597 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1598 BNXT_FEC_RS272_ON | BNXT_FEC_RS544_OFF)
1599
1600#define BNXT_FEC_RS_OFF(link_info) \
1601 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE | \
1602 (BNXT_PAM4_SUPPORTED(link_info) ? \
1603 (BNXT_FEC_RS544_OFF | BNXT_FEC_RS272_OFF) : 0))
1604
1605#define BNXT_FEC_BASE_R_ON(link_info) \
1606 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE | \
1607 BNXT_FEC_RS_OFF(link_info))
1608
1609#define BNXT_FEC_ALL_OFF(link_info) \
1610 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1611 BNXT_FEC_RS_OFF(link_info))
1612
1613struct bnxt_queue_info {
1614 u8 queue_id;
1615 u8 queue_profile;
1616};
1617
1618#define BNXT_MAX_LED 4
1619
1620struct bnxt_led_info {
1621 u8 led_id;
1622 u8 led_type;
1623 u8 led_group_id;
1624 u8 unused;
1625 __le16 led_state_caps;
1626#define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
1627 cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1628
1629 __le16 led_color_caps;
1630};
1631
1632#define BNXT_MAX_TEST 8
1633
1634struct bnxt_test_info {
1635 u8 offline_mask;
1636 u16 timeout;
1637 char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1638};
1639
1640#define CHIMP_REG_VIEW_ADDR \
1641 ((bp->flags & BNXT_FLAG_CHIP_P5_PLUS) ? 0x80000000 : 0xb1000000)
1642
1643#define BNXT_GRCPF_REG_CHIMP_COMM 0x0
1644#define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
1645#define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
1646#define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014
1647#define BNXT_CAG_REG_BASE 0x300000
1648
1649#define BNXT_GRC_REG_STATUS_P5 0x520
1650
1651#define BNXT_GRCPF_REG_KONG_COMM 0xA00
1652#define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00
1653
1654#define BNXT_GRC_REG_CHIP_NUM 0x48
1655#define BNXT_GRC_REG_BASE 0x260000
1656
1657#define BNXT_TS_REG_TIMESYNC_TS0_LOWER 0x640180c
1658#define BNXT_TS_REG_TIMESYNC_TS0_UPPER 0x6401810
1659
1660#define BNXT_GRC_BASE_MASK 0xfffff000
1661#define BNXT_GRC_OFFSET_MASK 0x00000ffc
1662
1663struct bnxt_tc_flow_stats {
1664 u64 packets;
1665 u64 bytes;
1666};
1667
1668#ifdef CONFIG_BNXT_FLOWER_OFFLOAD
1669struct bnxt_flower_indr_block_cb_priv {
1670 struct net_device *tunnel_netdev;
1671 struct bnxt *bp;
1672 struct list_head list;
1673};
1674#endif
1675
1676struct bnxt_tc_info {
1677 bool enabled;
1678
1679 /* hash table to store TC offloaded flows */
1680 struct rhashtable flow_table;
1681 struct rhashtable_params flow_ht_params;
1682
1683 /* hash table to store L2 keys of TC flows */
1684 struct rhashtable l2_table;
1685 struct rhashtable_params l2_ht_params;
1686 /* hash table to store L2 keys for TC tunnel decap */
1687 struct rhashtable decap_l2_table;
1688 struct rhashtable_params decap_l2_ht_params;
1689 /* hash table to store tunnel decap entries */
1690 struct rhashtable decap_table;
1691 struct rhashtable_params decap_ht_params;
1692 /* hash table to store tunnel encap entries */
1693 struct rhashtable encap_table;
1694 struct rhashtable_params encap_ht_params;
1695
1696 /* lock to atomically add/del an l2 node when a flow is
1697 * added or deleted.
1698 */
1699 struct mutex lock;
1700
1701 /* Fields used for batching stats query */
1702 struct rhashtable_iter iter;
1703#define BNXT_FLOW_STATS_BATCH_MAX 10
1704 struct bnxt_tc_stats_batch {
1705 void *flow_node;
1706 struct bnxt_tc_flow_stats hw_stats;
1707 } stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1708
1709 /* Stat counter mask (width) */
1710 u64 bytes_mask;
1711 u64 packets_mask;
1712};
1713
1714struct bnxt_vf_rep_stats {
1715 u64 packets;
1716 u64 bytes;
1717 u64 dropped;
1718};
1719
1720struct bnxt_vf_rep {
1721 struct bnxt *bp;
1722 struct net_device *dev;
1723 struct metadata_dst *dst;
1724 u16 vf_idx;
1725 u16 tx_cfa_action;
1726 u16 rx_cfa_code;
1727
1728 struct bnxt_vf_rep_stats rx_stats;
1729 struct bnxt_vf_rep_stats tx_stats;
1730};
1731
1732#define PTU_PTE_VALID 0x1UL
1733#define PTU_PTE_LAST 0x2UL
1734#define PTU_PTE_NEXT_TO_LAST 0x4UL
1735
1736#define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
1737#define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES)
1738
1739struct bnxt_ctx_pg_info {
1740 u32 entries;
1741 u32 nr_pages;
1742 void *ctx_pg_arr[MAX_CTX_PAGES];
1743 dma_addr_t ctx_dma_arr[MAX_CTX_PAGES];
1744 struct bnxt_ring_mem_info ring_mem;
1745 struct bnxt_ctx_pg_info **ctx_pg_tbl;
1746};
1747
1748#define BNXT_MAX_TQM_SP_RINGS 1
1749#define BNXT_MAX_TQM_FP_RINGS 8
1750#define BNXT_MAX_TQM_RINGS \
1751 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
1752
1753#define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256
1754
1755#define BNXT_SET_CTX_PAGE_ATTR(attr) \
1756do { \
1757 if (BNXT_PAGE_SIZE == 0x2000) \
1758 attr = FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K; \
1759 else if (BNXT_PAGE_SIZE == 0x10000) \
1760 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K; \
1761 else \
1762 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K; \
1763} while (0)
1764
1765struct bnxt_ctx_mem_type {
1766 u16 type;
1767 u16 entry_size;
1768 u32 flags;
1769#define BNXT_CTX_MEM_TYPE_VALID FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID
1770 u32 instance_bmap;
1771 u8 init_value;
1772 u8 entry_multiple;
1773 u16 init_offset;
1774#define BNXT_CTX_INIT_INVALID_OFFSET 0xffff
1775 u32 max_entries;
1776 u32 min_entries;
1777 u8 last:1;
1778 u8 split_entry_cnt;
1779#define BNXT_MAX_SPLIT_ENTRY 4
1780 union {
1781 struct {
1782 u32 qp_l2_entries;
1783 u32 qp_qp1_entries;
1784 u32 qp_fast_qpmd_entries;
1785 };
1786 u32 srq_l2_entries;
1787 u32 cq_l2_entries;
1788 u32 vnic_entries;
1789 struct {
1790 u32 mrav_av_entries;
1791 u32 mrav_num_entries_units;
1792 };
1793 u32 split[BNXT_MAX_SPLIT_ENTRY];
1794 };
1795 struct bnxt_ctx_pg_info *pg_info;
1796};
1797
1798#define BNXT_CTX_MRAV_AV_SPLIT_ENTRY 0
1799
1800#define BNXT_CTX_QP FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP
1801#define BNXT_CTX_SRQ FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ
1802#define BNXT_CTX_CQ FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ
1803#define BNXT_CTX_VNIC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC
1804#define BNXT_CTX_STAT FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT
1805#define BNXT_CTX_STQM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING
1806#define BNXT_CTX_FTQM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING
1807#define BNXT_CTX_MRAV FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV
1808#define BNXT_CTX_TIM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM
1809#define BNXT_CTX_TKC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TKC
1810#define BNXT_CTX_RKC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RKC
1811#define BNXT_CTX_MTQM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING
1812#define BNXT_CTX_SQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW
1813#define BNXT_CTX_RQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW
1814#define BNXT_CTX_SRQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW
1815#define BNXT_CTX_CQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW
1816#define BNXT_CTX_QTKC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_TKC
1817#define BNXT_CTX_QRKC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_RKC
1818#define BNXT_CTX_TBLSC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TBL_SCOPE
1819#define BNXT_CTX_XPAR FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_XID_PARTITION
1820
1821#define BNXT_CTX_MAX (BNXT_CTX_TIM + 1)
1822#define BNXT_CTX_L2_MAX (BNXT_CTX_FTQM + 1)
1823#define BNXT_CTX_V2_MAX (BNXT_CTX_XPAR + 1)
1824#define BNXT_CTX_INV ((u16)-1)
1825
1826struct bnxt_ctx_mem_info {
1827 u8 tqm_fp_rings_count;
1828
1829 u32 flags;
1830 #define BNXT_CTX_FLAG_INITED 0x01
1831 struct bnxt_ctx_mem_type ctx_arr[BNXT_CTX_V2_MAX];
1832};
1833
1834enum bnxt_health_severity {
1835 SEVERITY_NORMAL = 0,
1836 SEVERITY_WARNING,
1837 SEVERITY_RECOVERABLE,
1838 SEVERITY_FATAL,
1839};
1840
1841enum bnxt_health_remedy {
1842 REMEDY_DEVLINK_RECOVER,
1843 REMEDY_POWER_CYCLE_DEVICE,
1844 REMEDY_POWER_CYCLE_HOST,
1845 REMEDY_FW_UPDATE,
1846 REMEDY_HW_REPLACE,
1847};
1848
1849struct bnxt_fw_health {
1850 u32 flags;
1851 u32 polling_dsecs;
1852 u32 master_func_wait_dsecs;
1853 u32 normal_func_wait_dsecs;
1854 u32 post_reset_wait_dsecs;
1855 u32 post_reset_max_wait_dsecs;
1856 u32 regs[4];
1857 u32 mapped_regs[4];
1858#define BNXT_FW_HEALTH_REG 0
1859#define BNXT_FW_HEARTBEAT_REG 1
1860#define BNXT_FW_RESET_CNT_REG 2
1861#define BNXT_FW_RESET_INPROG_REG 3
1862 u32 fw_reset_inprog_reg_mask;
1863 u32 last_fw_heartbeat;
1864 u32 last_fw_reset_cnt;
1865 u8 enabled:1;
1866 u8 primary:1;
1867 u8 status_reliable:1;
1868 u8 resets_reliable:1;
1869 u8 tmr_multiplier;
1870 u8 tmr_counter;
1871 u8 fw_reset_seq_cnt;
1872 u32 fw_reset_seq_regs[16];
1873 u32 fw_reset_seq_vals[16];
1874 u32 fw_reset_seq_delay_msec[16];
1875 u32 echo_req_data1;
1876 u32 echo_req_data2;
1877 struct devlink_health_reporter *fw_reporter;
1878 /* Protects severity and remedy */
1879 struct mutex lock;
1880 enum bnxt_health_severity severity;
1881 enum bnxt_health_remedy remedy;
1882 u32 arrests;
1883 u32 discoveries;
1884 u32 survivals;
1885 u32 fatalities;
1886 u32 diagnoses;
1887};
1888
1889#define BNXT_FW_HEALTH_REG_TYPE_MASK 3
1890#define BNXT_FW_HEALTH_REG_TYPE_CFG 0
1891#define BNXT_FW_HEALTH_REG_TYPE_GRC 1
1892#define BNXT_FW_HEALTH_REG_TYPE_BAR0 2
1893#define BNXT_FW_HEALTH_REG_TYPE_BAR1 3
1894
1895#define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
1896#define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
1897
1898#define BNXT_FW_HEALTH_WIN_BASE 0x3000
1899#define BNXT_FW_HEALTH_WIN_MAP_OFF 8
1900
1901#define BNXT_FW_HEALTH_WIN_OFF(reg) (BNXT_FW_HEALTH_WIN_BASE + \
1902 ((reg) & BNXT_GRC_OFFSET_MASK))
1903
1904#define BNXT_FW_STATUS_HEALTH_MSK 0xffff
1905#define BNXT_FW_STATUS_HEALTHY 0x8000
1906#define BNXT_FW_STATUS_SHUTDOWN 0x100000
1907#define BNXT_FW_STATUS_RECOVERING 0x400000
1908
1909#define BNXT_FW_IS_HEALTHY(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\
1910 BNXT_FW_STATUS_HEALTHY)
1911
1912#define BNXT_FW_IS_BOOTING(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \
1913 BNXT_FW_STATUS_HEALTHY)
1914
1915#define BNXT_FW_IS_ERR(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \
1916 BNXT_FW_STATUS_HEALTHY)
1917
1918#define BNXT_FW_IS_RECOVERING(sts) (BNXT_FW_IS_ERR(sts) && \
1919 ((sts) & BNXT_FW_STATUS_RECOVERING))
1920
1921#define BNXT_FW_RETRY 5
1922#define BNXT_FW_IF_RETRY 10
1923#define BNXT_FW_SLOT_RESET_RETRY 4
1924
1925struct bnxt_aux_priv {
1926 struct auxiliary_device aux_dev;
1927 struct bnxt_en_dev *edev;
1928 int id;
1929};
1930
1931enum board_idx {
1932 BCM57301,
1933 BCM57302,
1934 BCM57304,
1935 BCM57417_NPAR,
1936 BCM58700,
1937 BCM57311,
1938 BCM57312,
1939 BCM57402,
1940 BCM57404,
1941 BCM57406,
1942 BCM57402_NPAR,
1943 BCM57407,
1944 BCM57412,
1945 BCM57414,
1946 BCM57416,
1947 BCM57417,
1948 BCM57412_NPAR,
1949 BCM57314,
1950 BCM57417_SFP,
1951 BCM57416_SFP,
1952 BCM57404_NPAR,
1953 BCM57406_NPAR,
1954 BCM57407_SFP,
1955 BCM57407_NPAR,
1956 BCM57414_NPAR,
1957 BCM57416_NPAR,
1958 BCM57452,
1959 BCM57454,
1960 BCM5745x_NPAR,
1961 BCM57508,
1962 BCM57504,
1963 BCM57502,
1964 BCM57508_NPAR,
1965 BCM57504_NPAR,
1966 BCM57502_NPAR,
1967 BCM57608,
1968 BCM57604,
1969 BCM57602,
1970 BCM57601,
1971 BCM58802,
1972 BCM58804,
1973 BCM58808,
1974 NETXTREME_E_VF,
1975 NETXTREME_C_VF,
1976 NETXTREME_S_VF,
1977 NETXTREME_C_VF_HV,
1978 NETXTREME_E_VF_HV,
1979 NETXTREME_E_P5_VF,
1980 NETXTREME_E_P5_VF_HV,
1981};
1982
1983struct bnxt {
1984 void __iomem *bar0;
1985 void __iomem *bar1;
1986 void __iomem *bar2;
1987
1988 u32 reg_base;
1989 u16 chip_num;
1990#define CHIP_NUM_57301 0x16c8
1991#define CHIP_NUM_57302 0x16c9
1992#define CHIP_NUM_57304 0x16ca
1993#define CHIP_NUM_58700 0x16cd
1994#define CHIP_NUM_57402 0x16d0
1995#define CHIP_NUM_57404 0x16d1
1996#define CHIP_NUM_57406 0x16d2
1997#define CHIP_NUM_57407 0x16d5
1998
1999#define CHIP_NUM_57311 0x16ce
2000#define CHIP_NUM_57312 0x16cf
2001#define CHIP_NUM_57314 0x16df
2002#define CHIP_NUM_57317 0x16e0
2003#define CHIP_NUM_57412 0x16d6
2004#define CHIP_NUM_57414 0x16d7
2005#define CHIP_NUM_57416 0x16d8
2006#define CHIP_NUM_57417 0x16d9
2007#define CHIP_NUM_57412L 0x16da
2008#define CHIP_NUM_57414L 0x16db
2009
2010#define CHIP_NUM_5745X 0xd730
2011#define CHIP_NUM_57452 0xc452
2012#define CHIP_NUM_57454 0xc454
2013
2014#define CHIP_NUM_57508 0x1750
2015#define CHIP_NUM_57504 0x1751
2016#define CHIP_NUM_57502 0x1752
2017
2018#define CHIP_NUM_57608 0x1760
2019
2020#define CHIP_NUM_58802 0xd802
2021#define CHIP_NUM_58804 0xd804
2022#define CHIP_NUM_58808 0xd808
2023
2024 u8 chip_rev;
2025
2026#define BNXT_CHIP_NUM_5730X(chip_num) \
2027 ((chip_num) >= CHIP_NUM_57301 && \
2028 (chip_num) <= CHIP_NUM_57304)
2029
2030#define BNXT_CHIP_NUM_5740X(chip_num) \
2031 (((chip_num) >= CHIP_NUM_57402 && \
2032 (chip_num) <= CHIP_NUM_57406) || \
2033 (chip_num) == CHIP_NUM_57407)
2034
2035#define BNXT_CHIP_NUM_5731X(chip_num) \
2036 ((chip_num) == CHIP_NUM_57311 || \
2037 (chip_num) == CHIP_NUM_57312 || \
2038 (chip_num) == CHIP_NUM_57314 || \
2039 (chip_num) == CHIP_NUM_57317)
2040
2041#define BNXT_CHIP_NUM_5741X(chip_num) \
2042 ((chip_num) >= CHIP_NUM_57412 && \
2043 (chip_num) <= CHIP_NUM_57414L)
2044
2045#define BNXT_CHIP_NUM_58700(chip_num) \
2046 ((chip_num) == CHIP_NUM_58700)
2047
2048#define BNXT_CHIP_NUM_5745X(chip_num) \
2049 ((chip_num) == CHIP_NUM_5745X || \
2050 (chip_num) == CHIP_NUM_57452 || \
2051 (chip_num) == CHIP_NUM_57454)
2052
2053
2054#define BNXT_CHIP_NUM_57X0X(chip_num) \
2055 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
2056
2057#define BNXT_CHIP_NUM_57X1X(chip_num) \
2058 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
2059
2060#define BNXT_CHIP_NUM_588XX(chip_num) \
2061 ((chip_num) == CHIP_NUM_58802 || \
2062 (chip_num) == CHIP_NUM_58804 || \
2063 (chip_num) == CHIP_NUM_58808)
2064
2065#define BNXT_VPD_FLD_LEN 32
2066 char board_partno[BNXT_VPD_FLD_LEN];
2067 char board_serialno[BNXT_VPD_FLD_LEN];
2068
2069 struct net_device *dev;
2070 struct pci_dev *pdev;
2071
2072 atomic_t intr_sem;
2073
2074 u32 flags;
2075 #define BNXT_FLAG_CHIP_P5_PLUS 0x1
2076 #define BNXT_FLAG_VF 0x2
2077 #define BNXT_FLAG_LRO 0x4
2078#ifdef CONFIG_INET
2079 #define BNXT_FLAG_GRO 0x8
2080#else
2081 /* Cannot support hardware GRO if CONFIG_INET is not set */
2082 #define BNXT_FLAG_GRO 0x0
2083#endif
2084 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
2085 #define BNXT_FLAG_JUMBO 0x10
2086 #define BNXT_FLAG_STRIP_VLAN 0x20
2087 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
2088 BNXT_FLAG_LRO)
2089 #define BNXT_FLAG_USING_MSIX 0x40
2090 #define BNXT_FLAG_MSIX_CAP 0x80
2091 #define BNXT_FLAG_RFS 0x100
2092 #define BNXT_FLAG_SHARED_RINGS 0x200
2093 #define BNXT_FLAG_PORT_STATS 0x400
2094 #define BNXT_FLAG_WOL_CAP 0x4000
2095 #define BNXT_FLAG_ROCEV1_CAP 0x8000
2096 #define BNXT_FLAG_ROCEV2_CAP 0x10000
2097 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \
2098 BNXT_FLAG_ROCEV2_CAP)
2099 #define BNXT_FLAG_NO_AGG_RINGS 0x20000
2100 #define BNXT_FLAG_RX_PAGE_MODE 0x40000
2101 #define BNXT_FLAG_CHIP_P7 0x80000
2102 #define BNXT_FLAG_MULTI_HOST 0x100000
2103 #define BNXT_FLAG_DSN_VALID 0x200000
2104 #define BNXT_FLAG_DOUBLE_DB 0x400000
2105 #define BNXT_FLAG_UDP_GSO_CAP 0x800000
2106 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
2107 #define BNXT_FLAG_DIM 0x2000000
2108 #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000
2109 #define BNXT_FLAG_TX_COAL_CMPL 0x8000000
2110 #define BNXT_FLAG_PORT_STATS_EXT 0x10000000
2111
2112 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \
2113 BNXT_FLAG_RFS | \
2114 BNXT_FLAG_STRIP_VLAN)
2115
2116#define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
2117#define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
2118#define BNXT_NPAR(bp) ((bp)->port_partition_type)
2119#define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
2120#define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
2121#define BNXT_SH_PORT_CFG_OK(bp) (BNXT_PF(bp) && \
2122 ((bp)->phy_flags & BNXT_PHY_FL_SHARED_PORT_CFG))
2123#define BNXT_PHY_CFG_ABLE(bp) ((BNXT_SINGLE_PF(bp) || \
2124 BNXT_SH_PORT_CFG_OK(bp)) && \
2125 (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED)
2126#define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
2127#define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
2128#define BNXT_SUPPORTS_TPA(bp) (!BNXT_CHIP_TYPE_NITRO_A0(bp) && \
2129 (!((bp)->flags & BNXT_FLAG_CHIP_P5_PLUS) ||\
2130 (bp)->max_tpa_v2) && !is_kdump_kernel())
2131#define BNXT_RX_JUMBO_MODE(bp) ((bp)->flags & BNXT_FLAG_JUMBO)
2132
2133#define BNXT_CHIP_P7(bp) \
2134 ((bp)->chip_num == CHIP_NUM_57608)
2135
2136#define BNXT_CHIP_P5(bp) \
2137 ((bp)->chip_num == CHIP_NUM_57508 || \
2138 (bp)->chip_num == CHIP_NUM_57504 || \
2139 (bp)->chip_num == CHIP_NUM_57502)
2140
2141/* Chip class phase 5 */
2142#define BNXT_CHIP_P5_PLUS(bp) \
2143 (BNXT_CHIP_P5(bp) || BNXT_CHIP_P7(bp))
2144
2145/* Chip class phase 4.x */
2146#define BNXT_CHIP_P4(bp) \
2147 (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
2148 BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
2149 BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
2150 (BNXT_CHIP_NUM_58700((bp)->chip_num) && \
2151 !BNXT_CHIP_TYPE_NITRO_A0(bp)))
2152
2153#define BNXT_CHIP_P4_PLUS(bp) \
2154 (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5_PLUS(bp))
2155
2156 struct bnxt_aux_priv *aux_priv;
2157 struct bnxt_en_dev *edev;
2158
2159 struct bnxt_napi **bnapi;
2160
2161 struct bnxt_rx_ring_info *rx_ring;
2162 struct bnxt_tx_ring_info *tx_ring;
2163 u16 *tx_ring_map;
2164
2165 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int,
2166 struct sk_buff *);
2167
2168 struct sk_buff * (*rx_skb_func)(struct bnxt *,
2169 struct bnxt_rx_ring_info *,
2170 u16, void *, u8 *, dma_addr_t,
2171 unsigned int);
2172
2173 u16 max_tpa_v2;
2174 u16 max_tpa;
2175 u32 rx_buf_size;
2176 u32 rx_buf_use_size; /* useable size */
2177 u16 rx_offset;
2178 u16 rx_dma_offset;
2179 enum dma_data_direction rx_dir;
2180 u32 rx_ring_size;
2181 u32 rx_agg_ring_size;
2182 u32 rx_copy_thresh;
2183 u32 rx_ring_mask;
2184 u32 rx_agg_ring_mask;
2185 int rx_nr_pages;
2186 int rx_agg_nr_pages;
2187 int rx_nr_rings;
2188 int rsscos_nr_ctxs;
2189
2190 u32 tx_ring_size;
2191 u32 tx_ring_mask;
2192 int tx_nr_pages;
2193 int tx_nr_rings;
2194 int tx_nr_rings_per_tc;
2195 int tx_nr_rings_xdp;
2196
2197 int tx_wake_thresh;
2198 int tx_push_thresh;
2199 int tx_push_size;
2200
2201 u32 cp_ring_size;
2202 u32 cp_ring_mask;
2203 u32 cp_bit;
2204 int cp_nr_pages;
2205 int cp_nr_rings;
2206
2207 /* grp_info indexed by completion ring index */
2208 struct bnxt_ring_grp_info *grp_info;
2209 struct bnxt_vnic_info *vnic_info;
2210 int nr_vnics;
2211 u16 *rss_indir_tbl;
2212 u16 rss_indir_tbl_entries;
2213 u32 rss_hash_cfg;
2214 u32 rss_hash_delta;
2215 u32 rss_cap;
2216#define BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA BIT(0)
2217#define BNXT_RSS_CAP_UDP_RSS_CAP BIT(1)
2218#define BNXT_RSS_CAP_NEW_RSS_CAP BIT(2)
2219#define BNXT_RSS_CAP_RSS_TCAM BIT(3)
2220
2221 u16 max_mtu;
2222 u8 max_tc;
2223 u8 max_lltc; /* lossless TCs */
2224 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE];
2225 u8 tc_to_qidx[BNXT_MAX_QUEUE];
2226 u8 q_ids[BNXT_MAX_QUEUE];
2227 u8 max_q;
2228 u8 num_tc;
2229
2230 unsigned int current_interval;
2231#define BNXT_TIMER_INTERVAL HZ
2232
2233 struct timer_list timer;
2234
2235 unsigned long state;
2236#define BNXT_STATE_OPEN 0
2237#define BNXT_STATE_IN_SP_TASK 1
2238#define BNXT_STATE_READ_STATS 2
2239#define BNXT_STATE_FW_RESET_DET 3
2240#define BNXT_STATE_IN_FW_RESET 4
2241#define BNXT_STATE_ABORT_ERR 5
2242#define BNXT_STATE_FW_FATAL_COND 6
2243#define BNXT_STATE_DRV_REGISTERED 7
2244#define BNXT_STATE_PCI_CHANNEL_IO_FROZEN 8
2245#define BNXT_STATE_NAPI_DISABLED 9
2246#define BNXT_STATE_L2_FILTER_RETRY 10
2247#define BNXT_STATE_FW_ACTIVATE 11
2248#define BNXT_STATE_RECOVER 12
2249#define BNXT_STATE_FW_NON_FATAL_COND 13
2250#define BNXT_STATE_FW_ACTIVATE_RESET 14
2251#define BNXT_STATE_HALF_OPEN 15 /* For offline ethtool tests */
2252
2253#define BNXT_NO_FW_ACCESS(bp) \
2254 (test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) || \
2255 pci_channel_offline((bp)->pdev))
2256
2257 struct bnxt_irq *irq_tbl;
2258 int total_irqs;
2259 u8 mac_addr[ETH_ALEN];
2260
2261#ifdef CONFIG_BNXT_DCB
2262 struct ieee_pfc *ieee_pfc;
2263 struct ieee_ets *ieee_ets;
2264 u8 dcbx_cap;
2265 u8 default_pri;
2266 u8 max_dscp_value;
2267#endif /* CONFIG_BNXT_DCB */
2268
2269 u32 msg_enable;
2270
2271 u64 fw_cap;
2272 #define BNXT_FW_CAP_SHORT_CMD BIT_ULL(0)
2273 #define BNXT_FW_CAP_LLDP_AGENT BIT_ULL(1)
2274 #define BNXT_FW_CAP_DCBX_AGENT BIT_ULL(2)
2275 #define BNXT_FW_CAP_NEW_RM BIT_ULL(3)
2276 #define BNXT_FW_CAP_IF_CHANGE BIT_ULL(4)
2277 #define BNXT_FW_CAP_KONG_MB_CHNL BIT_ULL(7)
2278 #define BNXT_FW_CAP_OVS_64BIT_HANDLE BIT_ULL(10)
2279 #define BNXT_FW_CAP_TRUSTED_VF BIT_ULL(11)
2280 #define BNXT_FW_CAP_ERROR_RECOVERY BIT_ULL(13)
2281 #define BNXT_FW_CAP_PKG_VER BIT_ULL(14)
2282 #define BNXT_FW_CAP_CFA_ADV_FLOW BIT_ULL(15)
2283 #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 BIT_ULL(16)
2284 #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED BIT_ULL(17)
2285 #define BNXT_FW_CAP_EXT_STATS_SUPPORTED BIT_ULL(18)
2286 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT_ULL(20)
2287 #define BNXT_FW_CAP_HOT_RESET BIT_ULL(21)
2288 #define BNXT_FW_CAP_PTP_RTC BIT_ULL(22)
2289 #define BNXT_FW_CAP_RX_ALL_PKT_TS BIT_ULL(23)
2290 #define BNXT_FW_CAP_VLAN_RX_STRIP BIT_ULL(24)
2291 #define BNXT_FW_CAP_VLAN_TX_INSERT BIT_ULL(25)
2292 #define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED BIT_ULL(26)
2293 #define BNXT_FW_CAP_LIVEPATCH BIT_ULL(27)
2294 #define BNXT_FW_CAP_PTP_PPS BIT_ULL(28)
2295 #define BNXT_FW_CAP_HOT_RESET_IF BIT_ULL(29)
2296 #define BNXT_FW_CAP_RING_MONITOR BIT_ULL(30)
2297 #define BNXT_FW_CAP_DBG_QCAPS BIT_ULL(31)
2298 #define BNXT_FW_CAP_PTP BIT_ULL(32)
2299 #define BNXT_FW_CAP_THRESHOLD_TEMP_SUPPORTED BIT_ULL(33)
2300 #define BNXT_FW_CAP_DFLT_VLAN_TPID_PCP BIT_ULL(34)
2301 #define BNXT_FW_CAP_PRE_RESV_VNICS BIT_ULL(35)
2302 #define BNXT_FW_CAP_BACKING_STORE_V2 BIT_ULL(36)
2303 #define BNXT_FW_CAP_VNIC_TUNNEL_TPA BIT_ULL(37)
2304
2305 u32 fw_dbg_cap;
2306
2307#define BNXT_NEW_RM(bp) ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
2308#define BNXT_PTP_USE_RTC(bp) (!BNXT_MH(bp) && \
2309 ((bp)->fw_cap & BNXT_FW_CAP_PTP_RTC))
2310 u32 hwrm_spec_code;
2311 u16 hwrm_cmd_seq;
2312 u16 hwrm_cmd_kong_seq;
2313 struct dma_pool *hwrm_dma_pool;
2314 struct hlist_head hwrm_pending_list;
2315
2316 struct rtnl_link_stats64 net_stats_prev;
2317 struct bnxt_stats_mem port_stats;
2318 struct bnxt_stats_mem rx_port_stats_ext;
2319 struct bnxt_stats_mem tx_port_stats_ext;
2320 u16 fw_rx_stats_ext_size;
2321 u16 fw_tx_stats_ext_size;
2322 u16 hw_ring_stats_size;
2323 u8 pri2cos_idx[8];
2324 u8 pri2cos_valid;
2325
2326 struct bnxt_total_ring_err_stats ring_err_stats_prev;
2327
2328 u16 hwrm_max_req_len;
2329 u16 hwrm_max_ext_req_len;
2330 unsigned int hwrm_cmd_timeout;
2331 unsigned int hwrm_cmd_max_timeout;
2332 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */
2333 struct hwrm_ver_get_output ver_resp;
2334#define FW_VER_STR_LEN 32
2335#define BC_HWRM_STR_LEN 21
2336#define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
2337 char fw_ver_str[FW_VER_STR_LEN];
2338 char hwrm_ver_supp[FW_VER_STR_LEN];
2339 char nvm_cfg_ver[FW_VER_STR_LEN];
2340 u64 fw_ver_code;
2341#define BNXT_FW_VER_CODE(maj, min, bld, rsv) \
2342 ((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv))
2343#define BNXT_FW_MAJ(bp) ((bp)->fw_ver_code >> 48)
2344#define BNXT_FW_BLD(bp) (((bp)->fw_ver_code >> 16) & 0xffff)
2345
2346 u16 vxlan_fw_dst_port_id;
2347 u16 nge_fw_dst_port_id;
2348 u16 vxlan_gpe_fw_dst_port_id;
2349 __be16 vxlan_port;
2350 __be16 nge_port;
2351 __be16 vxlan_gpe_port;
2352 u8 port_partition_type;
2353 u8 port_count;
2354 u16 br_mode;
2355
2356 struct bnxt_coal_cap coal_cap;
2357 struct bnxt_coal rx_coal;
2358 struct bnxt_coal tx_coal;
2359
2360 u32 stats_coal_ticks;
2361#define BNXT_DEF_STATS_COAL_TICKS 1000000
2362#define BNXT_MIN_STATS_COAL_TICKS 250000
2363#define BNXT_MAX_STATS_COAL_TICKS 1000000
2364
2365 struct work_struct sp_task;
2366 unsigned long sp_event;
2367#define BNXT_RX_MASK_SP_EVENT 0
2368#define BNXT_RX_NTP_FLTR_SP_EVENT 1
2369#define BNXT_LINK_CHNG_SP_EVENT 2
2370#define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
2371#define BNXT_RESET_TASK_SP_EVENT 6
2372#define BNXT_RST_RING_SP_EVENT 7
2373#define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8
2374#define BNXT_PERIODIC_STATS_SP_EVENT 9
2375#define BNXT_HWRM_PORT_MODULE_SP_EVENT 10
2376#define BNXT_RESET_TASK_SILENT_SP_EVENT 11
2377#define BNXT_LINK_SPEED_CHNG_SP_EVENT 14
2378#define BNXT_FLOW_STATS_SP_EVENT 15
2379#define BNXT_UPDATE_PHY_SP_EVENT 16
2380#define BNXT_RING_COAL_NOW_SP_EVENT 17
2381#define BNXT_FW_RESET_NOTIFY_SP_EVENT 18
2382#define BNXT_FW_EXCEPTION_SP_EVENT 19
2383#define BNXT_LINK_CFG_CHANGE_SP_EVENT 21
2384#define BNXT_THERMAL_THRESHOLD_SP_EVENT 22
2385#define BNXT_FW_ECHO_REQUEST_SP_EVENT 23
2386
2387 struct delayed_work fw_reset_task;
2388 int fw_reset_state;
2389#define BNXT_FW_RESET_STATE_POLL_VF 1
2390#define BNXT_FW_RESET_STATE_RESET_FW 2
2391#define BNXT_FW_RESET_STATE_ENABLE_DEV 3
2392#define BNXT_FW_RESET_STATE_POLL_FW 4
2393#define BNXT_FW_RESET_STATE_OPENING 5
2394#define BNXT_FW_RESET_STATE_POLL_FW_DOWN 6
2395
2396 u16 fw_reset_min_dsecs;
2397#define BNXT_DFLT_FW_RST_MIN_DSECS 20
2398 u16 fw_reset_max_dsecs;
2399#define BNXT_DFLT_FW_RST_MAX_DSECS 60
2400 unsigned long fw_reset_timestamp;
2401
2402 struct bnxt_fw_health *fw_health;
2403
2404 struct bnxt_hw_resc hw_resc;
2405 struct bnxt_pf_info pf;
2406 struct bnxt_ctx_mem_info *ctx;
2407#ifdef CONFIG_BNXT_SRIOV
2408 int nr_vfs;
2409 struct bnxt_vf_info vf;
2410 wait_queue_head_t sriov_cfg_wait;
2411 bool sriov_cfg;
2412#define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
2413#endif
2414
2415#if BITS_PER_LONG == 32
2416 /* ensure atomic 64-bit doorbell writes on 32-bit systems. */
2417 spinlock_t db_lock;
2418#endif
2419 int db_offset; /* db_offset within db_size */
2420 int db_size;
2421
2422#define BNXT_NTP_FLTR_MAX_FLTR 4096
2423#define BNXT_MAX_FLTR (BNXT_NTP_FLTR_MAX_FLTR + BNXT_L2_FLTR_MAX_FLTR)
2424#define BNXT_NTP_FLTR_HASH_SIZE 512
2425#define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
2426 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
2427 spinlock_t ntp_fltr_lock; /* for hash table add, del */
2428
2429 unsigned long *ntp_fltr_bmap;
2430 int ntp_fltr_count;
2431
2432#define BNXT_L2_FLTR_MAX_FLTR 1024
2433#define BNXT_L2_FLTR_HASH_SIZE 32
2434#define BNXT_L2_FLTR_HASH_MASK (BNXT_L2_FLTR_HASH_SIZE - 1)
2435 struct hlist_head l2_fltr_hash_tbl[BNXT_L2_FLTR_HASH_SIZE];
2436
2437 u32 hash_seed;
2438 u64 toeplitz_prefix;
2439
2440 /* To protect link related settings during link changes and
2441 * ethtool settings changes.
2442 */
2443 struct mutex link_lock;
2444 struct bnxt_link_info link_info;
2445 struct ethtool_eee eee;
2446 u32 lpi_tmr_lo;
2447 u32 lpi_tmr_hi;
2448
2449 /* copied from flags and flags2 in hwrm_port_phy_qcaps_output */
2450 u32 phy_flags;
2451#define BNXT_PHY_FL_EEE_CAP PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED
2452#define BNXT_PHY_FL_EXT_LPBK PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED
2453#define BNXT_PHY_FL_AN_PHY_LPBK PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED
2454#define BNXT_PHY_FL_SHARED_PORT_CFG PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED
2455#define BNXT_PHY_FL_PORT_STATS_NO_RESET PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET
2456#define BNXT_PHY_FL_NO_PHY_LPBK PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED
2457#define BNXT_PHY_FL_FW_MANAGED_LKDN PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN
2458#define BNXT_PHY_FL_NO_FCS PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS
2459#define BNXT_PHY_FL_NO_PAUSE (PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED << 8)
2460#define BNXT_PHY_FL_NO_PFC (PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED << 8)
2461#define BNXT_PHY_FL_BANK_SEL (PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED << 8)
2462#define BNXT_PHY_FL_SPEEDS2 (PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED << 8)
2463
2464 u8 num_tests;
2465 struct bnxt_test_info *test_info;
2466
2467 u8 wol_filter_id;
2468 u8 wol;
2469
2470 u8 num_leds;
2471 struct bnxt_led_info leds[BNXT_MAX_LED];
2472 u16 dump_flag;
2473#define BNXT_DUMP_LIVE 0
2474#define BNXT_DUMP_CRASH 1
2475
2476 struct bpf_prog *xdp_prog;
2477
2478 struct bnxt_ptp_cfg *ptp_cfg;
2479 u8 ptp_all_rx_tstamp;
2480
2481 /* devlink interface and vf-rep structs */
2482 struct devlink *dl;
2483 struct devlink_port dl_port;
2484 enum devlink_eswitch_mode eswitch_mode;
2485 struct bnxt_vf_rep **vf_reps; /* array of vf-rep ptrs */
2486 u16 *cfa_code_map; /* cfa_code -> vf_idx map */
2487 u8 dsn[8];
2488 struct bnxt_tc_info *tc_info;
2489 struct list_head tc_indr_block_list;
2490 struct dentry *debugfs_pdev;
2491#ifdef CONFIG_BNXT_HWMON
2492 struct device *hwmon_dev;
2493 u8 warn_thresh_temp;
2494 u8 crit_thresh_temp;
2495 u8 fatal_thresh_temp;
2496 u8 shutdown_thresh_temp;
2497#endif
2498 u32 thermal_threshold_type;
2499 enum board_idx board_idx;
2500};
2501
2502#define BNXT_NUM_RX_RING_STATS 8
2503#define BNXT_NUM_TX_RING_STATS 8
2504#define BNXT_NUM_TPA_RING_STATS 4
2505#define BNXT_NUM_TPA_RING_STATS_P5 5
2506#define BNXT_NUM_TPA_RING_STATS_P7 6
2507
2508#define BNXT_RING_STATS_SIZE_P5 \
2509 ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \
2510 BNXT_NUM_TPA_RING_STATS_P5) * 8)
2511
2512#define BNXT_RING_STATS_SIZE_P7 \
2513 ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \
2514 BNXT_NUM_TPA_RING_STATS_P7) * 8)
2515
2516#define BNXT_GET_RING_STATS64(sw, counter) \
2517 (*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))
2518
2519#define BNXT_GET_RX_PORT_STATS64(sw, counter) \
2520 (*((sw) + offsetof(struct rx_port_stats, counter) / 8))
2521
2522#define BNXT_GET_TX_PORT_STATS64(sw, counter) \
2523 (*((sw) + offsetof(struct tx_port_stats, counter) / 8))
2524
2525#define BNXT_PORT_STATS_SIZE \
2526 (sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024)
2527
2528#define BNXT_TX_PORT_STATS_BYTE_OFFSET \
2529 (sizeof(struct rx_port_stats) + 512)
2530
2531#define BNXT_RX_STATS_OFFSET(counter) \
2532 (offsetof(struct rx_port_stats, counter) / 8)
2533
2534#define BNXT_TX_STATS_OFFSET(counter) \
2535 ((offsetof(struct tx_port_stats, counter) + \
2536 BNXT_TX_PORT_STATS_BYTE_OFFSET) / 8)
2537
2538#define BNXT_RX_STATS_EXT_OFFSET(counter) \
2539 (offsetof(struct rx_port_stats_ext, counter) / 8)
2540
2541#define BNXT_RX_STATS_EXT_NUM_LEGACY \
2542 BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)
2543
2544#define BNXT_TX_STATS_EXT_OFFSET(counter) \
2545 (offsetof(struct tx_port_stats_ext, counter) / 8)
2546
2547#define BNXT_HW_FEATURE_VLAN_ALL_RX \
2548 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)
2549#define BNXT_HW_FEATURE_VLAN_ALL_TX \
2550 (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX)
2551
2552#define I2C_DEV_ADDR_A0 0xa0
2553#define I2C_DEV_ADDR_A2 0xa2
2554#define SFF_DIAG_SUPPORT_OFFSET 0x5c
2555#define SFF_MODULE_ID_SFP 0x3
2556#define SFF_MODULE_ID_QSFP 0xc
2557#define SFF_MODULE_ID_QSFP_PLUS 0xd
2558#define SFF_MODULE_ID_QSFP28 0x11
2559#define BNXT_MAX_PHY_I2C_RESP_SIZE 64
2560
2561static inline u32 bnxt_tx_avail(struct bnxt *bp,
2562 const struct bnxt_tx_ring_info *txr)
2563{
2564 u32 used = READ_ONCE(txr->tx_prod) - READ_ONCE(txr->tx_cons);
2565
2566 return bp->tx_ring_size - (used & bp->tx_ring_mask);
2567}
2568
2569static inline void bnxt_writeq(struct bnxt *bp, u64 val,
2570 volatile void __iomem *addr)
2571{
2572#if BITS_PER_LONG == 32
2573 spin_lock(&bp->db_lock);
2574 lo_hi_writeq(val, addr);
2575 spin_unlock(&bp->db_lock);
2576#else
2577 writeq(val, addr);
2578#endif
2579}
2580
2581static inline void bnxt_writeq_relaxed(struct bnxt *bp, u64 val,
2582 volatile void __iomem *addr)
2583{
2584#if BITS_PER_LONG == 32
2585 spin_lock(&bp->db_lock);
2586 lo_hi_writeq_relaxed(val, addr);
2587 spin_unlock(&bp->db_lock);
2588#else
2589 writeq_relaxed(val, addr);
2590#endif
2591}
2592
2593/* For TX and RX ring doorbells with no ordering guarantee*/
2594static inline void bnxt_db_write_relaxed(struct bnxt *bp,
2595 struct bnxt_db_info *db, u32 idx)
2596{
2597 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
2598 bnxt_writeq_relaxed(bp, db->db_key64 | DB_RING_IDX(db, idx),
2599 db->doorbell);
2600 } else {
2601 u32 db_val = db->db_key32 | DB_RING_IDX(db, idx);
2602
2603 writel_relaxed(db_val, db->doorbell);
2604 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2605 writel_relaxed(db_val, db->doorbell);
2606 }
2607}
2608
2609/* For TX and RX ring doorbells */
2610static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
2611 u32 idx)
2612{
2613 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
2614 bnxt_writeq(bp, db->db_key64 | DB_RING_IDX(db, idx),
2615 db->doorbell);
2616 } else {
2617 u32 db_val = db->db_key32 | DB_RING_IDX(db, idx);
2618
2619 writel(db_val, db->doorbell);
2620 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2621 writel(db_val, db->doorbell);
2622 }
2623}
2624
2625/* Must hold rtnl_lock */
2626static inline bool bnxt_sriov_cfg(struct bnxt *bp)
2627{
2628#if defined(CONFIG_BNXT_SRIOV)
2629 return BNXT_PF(bp) && (bp->pf.active_vfs || bp->sriov_cfg);
2630#else
2631 return false;
2632#endif
2633}
2634
2635extern const u16 bnxt_lhint_arr[];
2636
2637int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
2638 u16 prod, gfp_t gfp);
2639void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
2640u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);
2641void bnxt_set_tpa_flags(struct bnxt *bp);
2642void bnxt_set_ring_params(struct bnxt *);
2643int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
2644int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap,
2645 int bmap_size, bool async_only);
2646int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp);
2647void bnxt_del_l2_filter(struct bnxt *bp, struct bnxt_l2_filter *fltr);
2648int bnxt_hwrm_l2_filter_free(struct bnxt *bp, struct bnxt_l2_filter *fltr);
2649int bnxt_hwrm_l2_filter_alloc(struct bnxt *bp, struct bnxt_l2_filter *fltr);
2650int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
2651 struct bnxt_ntuple_filter *fltr);
2652int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
2653 struct bnxt_ntuple_filter *fltr);
2654void bnxt_fill_ipv6_mask(__be32 mask[4]);
2655int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings);
2656int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
2657int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
2658int bnxt_nq_rings_in_use(struct bnxt *bp);
2659int bnxt_hwrm_set_coal(struct bnxt *);
2660void bnxt_free_ctx_mem(struct bnxt *bp);
2661int bnxt_num_tx_to_cp(struct bnxt *bp, int tx);
2662unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
2663unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
2664unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
2665unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
2666int bnxt_get_avail_msix(struct bnxt *bp, int num);
2667int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
2668void bnxt_tx_disable(struct bnxt *bp);
2669void bnxt_tx_enable(struct bnxt *bp);
2670void bnxt_sched_reset_txr(struct bnxt *bp, struct bnxt_tx_ring_info *txr,
2671 u16 curr);
2672void bnxt_report_link(struct bnxt *bp);
2673int bnxt_update_link(struct bnxt *bp, bool chng_link_state);
2674int bnxt_hwrm_set_pause(struct bnxt *);
2675int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
2676int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset);
2677int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
2678int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
2679int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
2680int bnxt_hwrm_func_qcaps(struct bnxt *bp);
2681int bnxt_hwrm_fw_set_time(struct bnxt *);
2682int bnxt_open_nic(struct bnxt *, bool, bool);
2683int bnxt_half_open_nic(struct bnxt *bp);
2684void bnxt_half_close_nic(struct bnxt *bp);
2685void bnxt_reenable_sriov(struct bnxt *bp);
2686void bnxt_close_nic(struct bnxt *, bool, bool);
2687void bnxt_get_ring_err_stats(struct bnxt *bp,
2688 struct bnxt_total_ring_err_stats *stats);
2689int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
2690 u32 *reg_buf);
2691void bnxt_fw_exception(struct bnxt *bp);
2692void bnxt_fw_reset(struct bnxt *bp);
2693int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
2694 int tx_xdp);
2695int bnxt_fw_init_one(struct bnxt *bp);
2696bool bnxt_hwrm_reset_permitted(struct bnxt *bp);
2697int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
2698struct bnxt_ntuple_filter *bnxt_lookup_ntp_filter_from_idx(struct bnxt *bp,
2699 struct bnxt_ntuple_filter *fltr, u32 idx);
2700u32 bnxt_get_ntp_filter_idx(struct bnxt *bp, struct flow_keys *fkeys,
2701 const struct sk_buff *skb);
2702int bnxt_insert_ntp_filter(struct bnxt *bp, struct bnxt_ntuple_filter *fltr,
2703 u32 idx);
2704void bnxt_del_ntp_filter(struct bnxt *bp, struct bnxt_ntuple_filter *fltr);
2705int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
2706int bnxt_restore_pf_fw_resources(struct bnxt *bp);
2707int bnxt_get_port_parent_id(struct net_device *dev,
2708 struct netdev_phys_item_id *ppid);
2709void bnxt_dim_work(struct work_struct *work);
2710int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);
2711void bnxt_print_device_info(struct bnxt *bp);
2712#endif
1/* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2018 Broadcom Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
11#ifndef BNXT_H
12#define BNXT_H
13
14#define DRV_MODULE_NAME "bnxt_en"
15
16/* DO NOT CHANGE DRV_VER_* defines
17 * FIXME: Delete them
18 */
19#define DRV_VER_MAJ 1
20#define DRV_VER_MIN 10
21#define DRV_VER_UPD 3
22
23#include <linux/ethtool.h>
24#include <linux/interrupt.h>
25#include <linux/rhashtable.h>
26#include <linux/crash_dump.h>
27#include <linux/auxiliary_bus.h>
28#include <net/devlink.h>
29#include <net/dst_metadata.h>
30#include <net/xdp.h>
31#include <linux/dim.h>
32#include <linux/io-64-nonatomic-lo-hi.h>
33#ifdef CONFIG_TEE_BNXT_FW
34#include <linux/firmware/broadcom/tee_bnxt_fw.h>
35#endif
36
37extern struct list_head bnxt_block_cb_list;
38
39struct page_pool;
40
41struct tx_bd {
42 __le32 tx_bd_len_flags_type;
43 #define TX_BD_TYPE (0x3f << 0)
44 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)
45 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)
46 #define TX_BD_FLAGS_PACKET_END (1 << 6)
47 #define TX_BD_FLAGS_NO_CMPL (1 << 7)
48 #define TX_BD_FLAGS_BD_CNT (0x1f << 8)
49 #define TX_BD_FLAGS_BD_CNT_SHIFT 8
50 #define TX_BD_FLAGS_LHINT (3 << 13)
51 #define TX_BD_FLAGS_LHINT_SHIFT 13
52 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)
53 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13)
54 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13)
55 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13)
56 #define TX_BD_FLAGS_COAL_NOW (1 << 15)
57 #define TX_BD_LEN (0xffff << 16)
58 #define TX_BD_LEN_SHIFT 16
59
60 u32 tx_bd_opaque;
61 __le64 tx_bd_haddr;
62} __packed;
63
64#define TX_OPAQUE_IDX_MASK 0x0000ffff
65#define TX_OPAQUE_BDS_MASK 0x00ff0000
66#define TX_OPAQUE_BDS_SHIFT 16
67#define TX_OPAQUE_RING_MASK 0xff000000
68#define TX_OPAQUE_RING_SHIFT 24
69
70#define SET_TX_OPAQUE(bp, txr, idx, bds) \
71 (((txr)->tx_napi_idx << TX_OPAQUE_RING_SHIFT) | \
72 ((bds) << TX_OPAQUE_BDS_SHIFT) | ((idx) & (bp)->tx_ring_mask))
73
74#define TX_OPAQUE_IDX(opq) ((opq) & TX_OPAQUE_IDX_MASK)
75#define TX_OPAQUE_RING(opq) (((opq) & TX_OPAQUE_RING_MASK) >> \
76 TX_OPAQUE_RING_SHIFT)
77#define TX_OPAQUE_BDS(opq) (((opq) & TX_OPAQUE_BDS_MASK) >> \
78 TX_OPAQUE_BDS_SHIFT)
79#define TX_OPAQUE_PROD(bp, opq) ((TX_OPAQUE_IDX(opq) + TX_OPAQUE_BDS(opq)) &\
80 (bp)->tx_ring_mask)
81
82struct tx_bd_ext {
83 __le32 tx_bd_hsize_lflags;
84 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)
85 #define TX_BD_FLAGS_IP_CKSUM (1 << 1)
86 #define TX_BD_FLAGS_NO_CRC (1 << 2)
87 #define TX_BD_FLAGS_STAMP (1 << 3)
88 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4)
89 #define TX_BD_FLAGS_LSO (1 << 5)
90 #define TX_BD_FLAGS_IPID_FMT (1 << 6)
91 #define TX_BD_FLAGS_T_IPID (1 << 7)
92 #define TX_BD_HSIZE (0xff << 16)
93 #define TX_BD_HSIZE_SHIFT 16
94
95 __le32 tx_bd_mss;
96 __le32 tx_bd_cfa_action;
97 #define TX_BD_CFA_ACTION (0xffff << 16)
98 #define TX_BD_CFA_ACTION_SHIFT 16
99
100 __le32 tx_bd_cfa_meta;
101 #define TX_BD_CFA_META_MASK 0xfffffff
102 #define TX_BD_CFA_META_VID_MASK 0xfff
103 #define TX_BD_CFA_META_PRI_MASK (0xf << 12)
104 #define TX_BD_CFA_META_PRI_SHIFT 12
105 #define TX_BD_CFA_META_TPID_MASK (3 << 16)
106 #define TX_BD_CFA_META_TPID_SHIFT 16
107 #define TX_BD_CFA_META_KEY (0xf << 28)
108 #define TX_BD_CFA_META_KEY_SHIFT 28
109 #define TX_BD_CFA_META_KEY_VLAN (1 << 28)
110};
111
112#define BNXT_TX_PTP_IS_SET(lflags) ((lflags) & cpu_to_le32(TX_BD_FLAGS_STAMP))
113
114struct rx_bd {
115 __le32 rx_bd_len_flags_type;
116 #define RX_BD_TYPE (0x3f << 0)
117 #define RX_BD_TYPE_RX_PACKET_BD 0x4
118 #define RX_BD_TYPE_RX_BUFFER_BD 0x5
119 #define RX_BD_TYPE_RX_AGG_BD 0x6
120 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4)
121 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4)
122 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4)
123 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4)
124 #define RX_BD_FLAGS_SOP (1 << 6)
125 #define RX_BD_FLAGS_EOP (1 << 7)
126 #define RX_BD_FLAGS_BUFFERS (3 << 8)
127 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)
128 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8)
129 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8)
130 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8)
131 #define RX_BD_LEN (0xffff << 16)
132 #define RX_BD_LEN_SHIFT 16
133
134 u32 rx_bd_opaque;
135 __le64 rx_bd_haddr;
136};
137
138struct tx_cmp {
139 __le32 tx_cmp_flags_type;
140 #define CMP_TYPE (0x3f << 0)
141 #define CMP_TYPE_TX_L2_CMP 0
142 #define CMP_TYPE_TX_L2_COAL_CMP 2
143 #define CMP_TYPE_TX_L2_PKT_TS_CMP 4
144 #define CMP_TYPE_RX_L2_CMP 17
145 #define CMP_TYPE_RX_AGG_CMP 18
146 #define CMP_TYPE_RX_L2_TPA_START_CMP 19
147 #define CMP_TYPE_RX_L2_TPA_END_CMP 21
148 #define CMP_TYPE_RX_TPA_AGG_CMP 22
149 #define CMP_TYPE_RX_L2_V3_CMP 23
150 #define CMP_TYPE_RX_L2_TPA_START_V3_CMP 25
151 #define CMP_TYPE_STATUS_CMP 32
152 #define CMP_TYPE_REMOTE_DRIVER_REQ 34
153 #define CMP_TYPE_REMOTE_DRIVER_RESP 36
154 #define CMP_TYPE_ERROR_STATUS 48
155 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
156 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL
157 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL
158 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL
159 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
160
161 #define TX_CMP_FLAGS_ERROR (1 << 6)
162 #define TX_CMP_FLAGS_PUSH (1 << 7)
163
164 u32 tx_cmp_opaque;
165 __le32 tx_cmp_errors_v;
166 #define TX_CMP_V (1 << 0)
167 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1)
168 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0
169 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2
170 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4
171 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5
172 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4)
173 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5)
174 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6)
175 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7)
176
177 __le32 sq_cons_idx;
178 #define TX_CMP_SQ_CONS_IDX_MASK 0x00ffffff
179};
180
181#define TX_CMP_SQ_CONS_IDX(txcmp) \
182 (le32_to_cpu((txcmp)->sq_cons_idx) & TX_CMP_SQ_CONS_IDX_MASK)
183
184struct tx_ts_cmp {
185 __le32 tx_ts_cmp_flags_type;
186 #define TX_TS_CMP_FLAGS_ERROR (1 << 6)
187 #define TX_TS_CMP_FLAGS_TS_TYPE (1 << 7)
188 #define TX_TS_CMP_FLAGS_TS_TYPE_PM (0 << 7)
189 #define TX_TS_CMP_FLAGS_TS_TYPE_PA (1 << 7)
190 #define TX_TS_CMP_FLAGS_TS_FALLBACK (1 << 8)
191 #define TX_TS_CMP_TS_SUB_NS (0xf << 12)
192 #define TX_TS_CMP_TS_NS_MID (0xffff << 16)
193 #define TX_TS_CMP_TS_NS_MID_SFT 16
194 u32 tx_ts_cmp_opaque;
195 __le32 tx_ts_cmp_errors_v;
196 #define TX_TS_CMP_V (1 << 0)
197 #define TX_TS_CMP_TS_INVALID_ERR (1 << 10)
198 __le32 tx_ts_cmp_ts_ns_lo;
199};
200
201#define BNXT_GET_TX_TS_48B_NS(tscmp) \
202 (le32_to_cpu((tscmp)->tx_ts_cmp_ts_ns_lo) | \
203 ((u64)(le32_to_cpu((tscmp)->tx_ts_cmp_flags_type) & \
204 TX_TS_CMP_TS_NS_MID) << TX_TS_CMP_TS_NS_MID_SFT))
205
206#define BNXT_TX_TS_ERR(tscmp) \
207 (((tscmp)->tx_ts_cmp_flags_type & cpu_to_le32(TX_TS_CMP_FLAGS_ERROR)) &&\
208 ((tscmp)->tx_ts_cmp_errors_v & cpu_to_le32(TX_TS_CMP_TS_INVALID_ERR)))
209
210struct rx_cmp {
211 __le32 rx_cmp_len_flags_type;
212 #define RX_CMP_CMP_TYPE (0x3f << 0)
213 #define RX_CMP_FLAGS_ERROR (1 << 6)
214 #define RX_CMP_FLAGS_PLACEMENT (7 << 7)
215 #define RX_CMP_FLAGS_RSS_VALID (1 << 10)
216 #define RX_CMP_FLAGS_PKT_METADATA_PRESENT (1 << 11)
217 #define RX_CMP_FLAGS_ITYPES_SHIFT 12
218 #define RX_CMP_FLAGS_ITYPES_MASK 0xf000
219 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
220 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12)
221 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)
222 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12)
223 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12)
224 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12)
225 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12)
226 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12)
227 #define RX_CMP_LEN (0xffff << 16)
228 #define RX_CMP_LEN_SHIFT 16
229
230 u32 rx_cmp_opaque;
231 __le32 rx_cmp_misc_v1;
232 #define RX_CMP_V1 (1 << 0)
233 #define RX_CMP_AGG_BUFS (0x1f << 1)
234 #define RX_CMP_AGG_BUFS_SHIFT 1
235 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9)
236 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9
237 #define RX_CMP_V3_RSS_EXT_OP_LEGACY (0xf << 12)
238 #define RX_CMP_V3_RSS_EXT_OP_LEGACY_SHIFT 12
239 #define RX_CMP_V3_RSS_EXT_OP_NEW (0xf << 8)
240 #define RX_CMP_V3_RSS_EXT_OP_NEW_SHIFT 8
241 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16)
242 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16
243 #define RX_CMP_SUB_NS_TS (0xf << 16)
244 #define RX_CMP_SUB_NS_TS_SHIFT 16
245 #define RX_CMP_METADATA1 (0xf << 28)
246 #define RX_CMP_METADATA1_SHIFT 28
247 #define RX_CMP_METADATA1_TPID_SEL (0x7 << 28)
248 #define RX_CMP_METADATA1_TPID_8021Q (0x1 << 28)
249 #define RX_CMP_METADATA1_TPID_8021AD (0x0 << 28)
250 #define RX_CMP_METADATA1_VALID (0x8 << 28)
251
252 __le32 rx_cmp_rss_hash;
253};
254
255#define BNXT_PTP_RX_TS_VALID(flags) \
256 (((flags) & RX_CMP_FLAGS_ITYPES_MASK) == RX_CMP_FLAGS_ITYPE_PTP_W_TS)
257
258#define BNXT_ALL_RX_TS_VALID(flags) \
259 !((flags) & RX_CMP_FLAGS_PKT_METADATA_PRESENT)
260
261#define RX_CMP_HASH_VALID(rxcmp) \
262 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
263
264#define RSS_PROFILE_ID_MASK 0x1f
265
266#define RX_CMP_HASH_TYPE(rxcmp) \
267 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
268 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
269
270#define RX_CMP_ITYPES(rxcmp) \
271 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_FLAGS_ITYPES_MASK)
272
273#define RX_CMP_V3_HASH_TYPE_LEGACY(rxcmp) \
274 ((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_V3_RSS_EXT_OP_LEGACY) >>\
275 RX_CMP_V3_RSS_EXT_OP_LEGACY_SHIFT)
276
277#define RX_CMP_V3_HASH_TYPE_NEW(rxcmp) \
278 ((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_V3_RSS_EXT_OP_NEW) >>\
279 RX_CMP_V3_RSS_EXT_OP_NEW_SHIFT)
280
281#define RX_CMP_V3_HASH_TYPE(bp, rxcmp) \
282 (((bp)->rss_cap & BNXT_RSS_CAP_RSS_TCAM) ? \
283 RX_CMP_V3_HASH_TYPE_NEW(rxcmp) : \
284 RX_CMP_V3_HASH_TYPE_LEGACY(rxcmp))
285
286#define EXT_OP_INNER_4 0x0
287#define EXT_OP_OUTER_4 0x2
288#define EXT_OP_INNFL_3 0x8
289#define EXT_OP_OUTFL_3 0xa
290
291#define RX_CMP_VLAN_VALID(rxcmp) \
292 ((rxcmp)->rx_cmp_misc_v1 & cpu_to_le32(RX_CMP_METADATA1_VALID))
293
294#define RX_CMP_VLAN_TPID_SEL(rxcmp) \
295 (le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_METADATA1_TPID_SEL)
296
297struct rx_cmp_ext {
298 __le32 rx_cmp_flags2;
299 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1
300 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
301 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
302 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
303 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)
304 __le32 rx_cmp_meta_data;
305 #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff
306 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff
307 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000
308 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16
309 __le32 rx_cmp_cfa_code_errors_v2;
310 #define RX_CMP_V (1 << 0)
311 #define RX_CMPL_ERRORS_MASK (0x7fff << 1)
312 #define RX_CMPL_ERRORS_SFT 1
313 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
314 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
315 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)
316 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
317 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
318 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)
319 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)
320 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)
321 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)
322 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)
323 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)
324 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)
325 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)
326 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)
327 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)
328 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)
329 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)
330 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)
331 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)
332 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)
333 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)
334 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)
335 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)
336 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)
337 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)
338 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)
339 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
340 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)
341
342 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
343 #define RX_CMPL_CFA_CODE_SFT 16
344 #define RX_CMPL_METADATA0_TCI_MASK (0xffff << 16)
345 #define RX_CMPL_METADATA0_VID_MASK (0x0fff << 16)
346 #define RX_CMPL_METADATA0_SFT 16
347
348 __le32 rx_cmp_timestamp;
349};
350
351#define RX_CMP_L2_ERRORS \
352 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
353
354#define RX_CMP_L4_CS_BITS \
355 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
356
357#define RX_CMP_L4_CS_ERR_BITS \
358 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
359
360#define RX_CMP_L4_CS_OK(rxcmp1) \
361 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \
362 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
363
364#define RX_CMP_ENCAP(rxcmp1) \
365 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \
366 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
367
368#define RX_CMP_CFA_CODE(rxcmpl1) \
369 ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \
370 RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
371
372#define RX_CMP_METADATA0_TCI(rxcmp1) \
373 ((le32_to_cpu((rxcmp1)->rx_cmp_cfa_code_errors_v2) & \
374 RX_CMPL_METADATA0_TCI_MASK) >> RX_CMPL_METADATA0_SFT)
375
376struct rx_agg_cmp {
377 __le32 rx_agg_cmp_len_flags_type;
378 #define RX_AGG_CMP_TYPE (0x3f << 0)
379 #define RX_AGG_CMP_LEN (0xffff << 16)
380 #define RX_AGG_CMP_LEN_SHIFT 16
381 u32 rx_agg_cmp_opaque;
382 __le32 rx_agg_cmp_v;
383 #define RX_AGG_CMP_V (1 << 0)
384 #define RX_AGG_CMP_AGG_ID (0x0fff << 16)
385 #define RX_AGG_CMP_AGG_ID_SHIFT 16
386 __le32 rx_agg_cmp_unused;
387};
388
389#define TPA_AGG_AGG_ID(rx_agg) \
390 ((le32_to_cpu((rx_agg)->rx_agg_cmp_v) & \
391 RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)
392
393struct rx_tpa_start_cmp {
394 __le32 rx_tpa_start_cmp_len_flags_type;
395 #define RX_TPA_START_CMP_TYPE (0x3f << 0)
396 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6)
397 #define RX_TPA_START_CMP_FLAGS_SHIFT 6
398 #define RX_TPA_START_CMP_FLAGS_ERROR (0x1 << 6)
399 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)
400 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7
401 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
402 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
403 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
404 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
405 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)
406 #define RX_TPA_START_CMP_FLAGS_TIMESTAMP (0x1 << 11)
407 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)
408 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12
409 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
410 #define RX_TPA_START_CMP_LEN (0xffff << 16)
411 #define RX_TPA_START_CMP_LEN_SHIFT 16
412
413 u32 rx_tpa_start_cmp_opaque;
414 __le32 rx_tpa_start_cmp_misc_v1;
415 #define RX_TPA_START_CMP_V1 (0x1 << 0)
416 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9)
417 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9
418 #define RX_TPA_START_CMP_V3_RSS_HASH_TYPE (0x1ff << 7)
419 #define RX_TPA_START_CMP_V3_RSS_HASH_TYPE_SHIFT 7
420 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25)
421 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25
422 #define RX_TPA_START_CMP_AGG_ID_P5 (0x0fff << 16)
423 #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5 16
424 #define RX_TPA_START_CMP_METADATA1 (0xf << 28)
425 #define RX_TPA_START_CMP_METADATA1_SHIFT 28
426 #define RX_TPA_START_METADATA1_TPID_SEL (0x7 << 28)
427 #define RX_TPA_START_METADATA1_TPID_8021Q (0x1 << 28)
428 #define RX_TPA_START_METADATA1_TPID_8021AD (0x0 << 28)
429 #define RX_TPA_START_METADATA1_VALID (0x8 << 28)
430
431 __le32 rx_tpa_start_cmp_rss_hash;
432};
433
434#define TPA_START_HASH_VALID(rx_tpa_start) \
435 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
436 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
437
438#define TPA_START_HASH_TYPE(rx_tpa_start) \
439 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
440 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \
441 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
442
443#define TPA_START_V3_HASH_TYPE(rx_tpa_start) \
444 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
445 RX_TPA_START_CMP_V3_RSS_HASH_TYPE) >> \
446 RX_TPA_START_CMP_V3_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
447
448#define TPA_START_AGG_ID(rx_tpa_start) \
449 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
450 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
451
452#define TPA_START_AGG_ID_P5(rx_tpa_start) \
453 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
454 RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)
455
456#define TPA_START_ERROR(rx_tpa_start) \
457 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
458 cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))
459
460#define TPA_START_VLAN_VALID(rx_tpa_start) \
461 ((rx_tpa_start)->rx_tpa_start_cmp_misc_v1 & \
462 cpu_to_le32(RX_TPA_START_METADATA1_VALID))
463
464#define TPA_START_VLAN_TPID_SEL(rx_tpa_start) \
465 (le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
466 RX_TPA_START_METADATA1_TPID_SEL)
467
468struct rx_tpa_start_cmp_ext {
469 __le32 rx_tpa_start_cmp_flags2;
470 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)
471 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
472 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
473 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
474 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8)
475 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID (0x1 << 9)
476 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT (0x3 << 10)
477 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT 10
478 #define RX_TPA_START_CMP_V3_FLAGS2_T_IP_TYPE (0x1 << 10)
479 #define RX_TPA_START_CMP_V3_FLAGS2_AGG_GRO (0x1 << 11)
480 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL (0xffff << 16)
481 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT 16
482
483 __le32 rx_tpa_start_cmp_metadata;
484 __le32 rx_tpa_start_cmp_cfa_code_v2;
485 #define RX_TPA_START_CMP_V2 (0x1 << 0)
486 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
487 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT 1
488 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
489 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
490 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
491 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)
492 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16
493 #define RX_TPA_START_CMP_METADATA0_TCI_MASK (0xffff << 16)
494 #define RX_TPA_START_CMP_METADATA0_VID_MASK (0x0fff << 16)
495 #define RX_TPA_START_CMP_METADATA0_SFT 16
496 __le32 rx_tpa_start_cmp_hdr_info;
497};
498
499#define TPA_START_CFA_CODE(rx_tpa_start) \
500 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
501 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
502
503#define TPA_START_IS_IPV6(rx_tpa_start) \
504 (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 & \
505 cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
506
507#define TPA_START_ERROR_CODE(rx_tpa_start) \
508 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
509 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >> \
510 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)
511
512#define TPA_START_METADATA0_TCI(rx_tpa_start) \
513 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
514 RX_TPA_START_CMP_METADATA0_TCI_MASK) >> \
515 RX_TPA_START_CMP_METADATA0_SFT)
516
517struct rx_tpa_end_cmp {
518 __le32 rx_tpa_end_cmp_len_flags_type;
519 #define RX_TPA_END_CMP_TYPE (0x3f << 0)
520 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6)
521 #define RX_TPA_END_CMP_FLAGS_SHIFT 6
522 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7)
523 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7
524 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
525 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
526 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
527 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
528 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10)
529 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12)
530 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12
531 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
532 #define RX_TPA_END_CMP_LEN (0xffff << 16)
533 #define RX_TPA_END_CMP_LEN_SHIFT 16
534
535 u32 rx_tpa_end_cmp_opaque;
536 __le32 rx_tpa_end_cmp_misc_v1;
537 #define RX_TPA_END_CMP_V1 (0x1 << 0)
538 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1)
539 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1
540 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8)
541 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8
542 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16)
543 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16
544 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25)
545 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25
546 #define RX_TPA_END_CMP_AGG_ID_P5 (0x0fff << 16)
547 #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5 16
548
549 __le32 rx_tpa_end_cmp_tsdelta;
550 #define RX_TPA_END_GRO_TS (0x1 << 31)
551};
552
553#define TPA_END_AGG_ID(rx_tpa_end) \
554 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
555 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
556
557#define TPA_END_AGG_ID_P5(rx_tpa_end) \
558 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
559 RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)
560
561#define TPA_END_PAYLOAD_OFF(rx_tpa_end) \
562 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
563 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)
564
565#define TPA_END_AGG_BUFS(rx_tpa_end) \
566 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
567 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)
568
569#define TPA_END_TPA_SEGS(rx_tpa_end) \
570 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
571 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
572
573#define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \
574 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \
575 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
576
577#define TPA_END_GRO(rx_tpa_end) \
578 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \
579 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
580
581#define TPA_END_GRO_TS(rx_tpa_end) \
582 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \
583 cpu_to_le32(RX_TPA_END_GRO_TS)))
584
585struct rx_tpa_end_cmp_ext {
586 __le32 rx_tpa_end_cmp_dup_acks;
587 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)
588 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5 (0xff << 16)
589 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5 16
590 #define RX_TPA_END_CMP_AGG_BUFS_P5 (0xff << 24)
591 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5 24
592
593 __le32 rx_tpa_end_cmp_seg_len;
594 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)
595
596 __le32 rx_tpa_end_cmp_errors_v2;
597 #define RX_TPA_END_CMP_V2 (0x1 << 0)
598 #define RX_TPA_END_CMP_ERRORS (0x3 << 1)
599 #define RX_TPA_END_CMP_ERRORS_P5 (0x7 << 1)
600 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1
601 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
602 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
603 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
604 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR (0x4 << 1)
605 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
606
607 u32 rx_tpa_end_cmp_start_opaque;
608};
609
610#define TPA_END_ERRORS(rx_tpa_end_ext) \
611 ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \
612 cpu_to_le32(RX_TPA_END_CMP_ERRORS))
613
614#define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext) \
615 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
616 RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >> \
617 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)
618
619#define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext) \
620 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
621 RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)
622
623#define EVENT_DATA1_RESET_NOTIFY_FATAL(data1) \
624 (((data1) & \
625 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
626 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)
627
628#define EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1) \
629 (((data1) & \
630 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
631 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION)
632
633#define EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2) \
634 ((data2) & \
635 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK)
636
637#define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1) \
638 !!((data1) & \
639 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
640
641#define EVENT_DATA1_RECOVERY_ENABLED(data1) \
642 !!((data1) & \
643 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
644
645#define BNXT_EVENT_ERROR_REPORT_TYPE(data1) \
646 (((data1) & \
647 ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >>\
648 ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT)
649
650#define BNXT_EVENT_INVALID_SIGNAL_DATA(data2) \
651 (((data2) & \
652 ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK) >>\
653 ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT)
654
655struct nqe_cn {
656 __le16 type;
657 #define NQ_CN_TYPE_MASK 0x3fUL
658 #define NQ_CN_TYPE_SFT 0
659 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
660 #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
661 #define NQ_CN_TOGGLE_MASK 0xc0UL
662 #define NQ_CN_TOGGLE_SFT 6
663 __le16 reserved16;
664 __le32 cq_handle_low;
665 __le32 v;
666 #define NQ_CN_V 0x1UL
667 __le32 cq_handle_high;
668};
669
670#define BNXT_NQ_HDL_IDX_MASK 0x00ffffff
671#define BNXT_NQ_HDL_TYPE_MASK 0xff000000
672#define BNXT_NQ_HDL_TYPE_SHIFT 24
673#define BNXT_NQ_HDL_TYPE_RX 0x00
674#define BNXT_NQ_HDL_TYPE_TX 0x01
675
676#define BNXT_NQ_HDL_IDX(hdl) ((hdl) & BNXT_NQ_HDL_IDX_MASK)
677#define BNXT_NQ_HDL_TYPE(hdl) (((hdl) & BNXT_NQ_HDL_TYPE_MASK) >> \
678 BNXT_NQ_HDL_TYPE_SHIFT)
679
680#define BNXT_SET_NQ_HDL(cpr) \
681 (((cpr)->cp_ring_type << BNXT_NQ_HDL_TYPE_SHIFT) | (cpr)->cp_idx)
682
683#define NQE_CN_TYPE(type) ((type) & NQ_CN_TYPE_MASK)
684#define NQE_CN_TOGGLE(type) (((type) & NQ_CN_TOGGLE_MASK) >> \
685 NQ_CN_TOGGLE_SFT)
686
687#define DB_IDX_MASK 0xffffff
688#define DB_IDX_VALID (0x1 << 26)
689#define DB_IRQ_DIS (0x1 << 27)
690#define DB_KEY_TX (0x0 << 28)
691#define DB_KEY_RX (0x1 << 28)
692#define DB_KEY_CP (0x2 << 28)
693#define DB_KEY_ST (0x3 << 28)
694#define DB_KEY_TX_PUSH (0x4 << 28)
695#define DB_LONG_TX_PUSH (0x2 << 24)
696
697#define BNXT_MIN_ROCE_CP_RINGS 2
698#define BNXT_MIN_ROCE_STAT_CTXS 1
699
700/* 64-bit doorbell */
701#define DBR_INDEX_MASK 0x0000000000ffffffULL
702#define DBR_EPOCH_MASK 0x01000000UL
703#define DBR_EPOCH_SFT 24
704#define DBR_TOGGLE_MASK 0x06000000UL
705#define DBR_TOGGLE_SFT 25
706#define DBR_XID_MASK 0x000fffff00000000ULL
707#define DBR_XID_SFT 32
708#define DBR_PATH_L2 (0x1ULL << 56)
709#define DBR_VALID (0x1ULL << 58)
710#define DBR_TYPE_SQ (0x0ULL << 60)
711#define DBR_TYPE_RQ (0x1ULL << 60)
712#define DBR_TYPE_SRQ (0x2ULL << 60)
713#define DBR_TYPE_SRQ_ARM (0x3ULL << 60)
714#define DBR_TYPE_CQ (0x4ULL << 60)
715#define DBR_TYPE_CQ_ARMSE (0x5ULL << 60)
716#define DBR_TYPE_CQ_ARMALL (0x6ULL << 60)
717#define DBR_TYPE_CQ_ARMENA (0x7ULL << 60)
718#define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60)
719#define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60)
720#define DBR_TYPE_NQ (0xaULL << 60)
721#define DBR_TYPE_NQ_ARM (0xbULL << 60)
722#define DBR_TYPE_NQ_MASK (0xeULL << 60)
723#define DBR_TYPE_NULL (0xfULL << 60)
724
725#define DB_PF_OFFSET_P5 0x10000
726#define DB_VF_OFFSET_P5 0x4000
727
728#define INVALID_HW_RING_ID ((u16)-1)
729
730/* The hardware supports certain page sizes. Use the supported page sizes
731 * to allocate the rings.
732 */
733#if (PAGE_SHIFT < 12)
734#define BNXT_PAGE_SHIFT 12
735#elif (PAGE_SHIFT <= 13)
736#define BNXT_PAGE_SHIFT PAGE_SHIFT
737#elif (PAGE_SHIFT < 16)
738#define BNXT_PAGE_SHIFT 13
739#else
740#define BNXT_PAGE_SHIFT 16
741#endif
742
743#define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)
744
745/* The RXBD length is 16-bit so we can only support page sizes < 64K */
746#if (PAGE_SHIFT > 15)
747#define BNXT_RX_PAGE_SHIFT 15
748#else
749#define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
750#endif
751
752#define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
753
754#define BNXT_MAX_MTU 9500
755
756/* First RX buffer page in XDP multi-buf mode
757 *
758 * +-------------------------------------------------------------------------+
759 * | XDP_PACKET_HEADROOM | bp->rx_buf_use_size | skb_shared_info|
760 * | (bp->rx_dma_offset) | | |
761 * +-------------------------------------------------------------------------+
762 */
763#define BNXT_MAX_PAGE_MODE_MTU_SBUF \
764 ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \
765 XDP_PACKET_HEADROOM)
766#define BNXT_MAX_PAGE_MODE_MTU \
767 (BNXT_MAX_PAGE_MODE_MTU_SBUF - \
768 SKB_DATA_ALIGN((unsigned int)sizeof(struct skb_shared_info)))
769
770#define BNXT_MIN_PKT_SIZE 52
771
772#define BNXT_DEFAULT_RX_RING_SIZE 511
773#define BNXT_DEFAULT_TX_RING_SIZE 511
774
775#define MAX_TPA 64
776#define MAX_TPA_P5 256
777#define MAX_TPA_P5_MASK (MAX_TPA_P5 - 1)
778#define MAX_TPA_SEGS_P5 0x3f
779
780#if (BNXT_PAGE_SHIFT == 16)
781#define MAX_RX_PAGES_AGG_ENA 1
782#define MAX_RX_PAGES 4
783#define MAX_RX_AGG_PAGES 4
784#define MAX_TX_PAGES 1
785#define MAX_CP_PAGES 16
786#else
787#define MAX_RX_PAGES_AGG_ENA 8
788#define MAX_RX_PAGES 32
789#define MAX_RX_AGG_PAGES 32
790#define MAX_TX_PAGES 8
791#define MAX_CP_PAGES 128
792#endif
793
794#define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
795#define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
796#define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
797
798#define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
799#define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
800
801#define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
802
803#define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
804#define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
805
806#define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
807
808#define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1)
809#define BNXT_MAX_RX_DESC_CNT_JUM_ENA (RX_DESC_CNT * MAX_RX_PAGES_AGG_ENA - 1)
810#define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
811#define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)
812
813/* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1. We need one extra
814 * BD because the first TX BD is always a long BD.
815 */
816#define BNXT_MIN_TX_DESC_CNT (MAX_SKB_FRAGS + 2)
817
818#define RX_RING(bp, x) (((x) & (bp)->rx_ring_mask) >> (BNXT_PAGE_SHIFT - 4))
819#define RX_AGG_RING(bp, x) (((x) & (bp)->rx_agg_ring_mask) >> \
820 (BNXT_PAGE_SHIFT - 4))
821#define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
822
823#define TX_RING(bp, x) (((x) & (bp)->tx_ring_mask) >> (BNXT_PAGE_SHIFT - 4))
824#define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))
825
826#define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
827#define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))
828
829#define TX_CMP_VALID(txcmp, raw_cons) \
830 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \
831 !((raw_cons) & bp->cp_bit))
832
833#define RX_CMP_VALID(rxcmp1, raw_cons) \
834 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
835 !((raw_cons) & bp->cp_bit))
836
837#define RX_AGG_CMP_VALID(agg, raw_cons) \
838 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
839 !((raw_cons) & bp->cp_bit))
840
841#define NQ_CMP_VALID(nqcmp, raw_cons) \
842 (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
843
844#define TX_CMP_TYPE(txcmp) \
845 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
846
847#define RX_CMP_TYPE(rxcmp) \
848 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
849
850#define RING_RX(bp, idx) ((idx) & (bp)->rx_ring_mask)
851#define NEXT_RX(idx) ((idx) + 1)
852
853#define RING_RX_AGG(bp, idx) ((idx) & (bp)->rx_agg_ring_mask)
854#define NEXT_RX_AGG(idx) ((idx) + 1)
855
856#define RING_TX(bp, idx) ((idx) & (bp)->tx_ring_mask)
857#define NEXT_TX(idx) ((idx) + 1)
858
859#define ADV_RAW_CMP(idx, n) ((idx) + (n))
860#define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1)
861#define RING_CMP(idx) ((idx) & bp->cp_ring_mask)
862#define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1))
863
864#define DFLT_HWRM_CMD_TIMEOUT 500
865
866#define BNXT_RX_EVENT 1
867#define BNXT_AGG_EVENT 2
868#define BNXT_TX_EVENT 4
869#define BNXT_REDIRECT_EVENT 8
870#define BNXT_TX_CMP_EVENT 0x10
871
872struct bnxt_sw_tx_bd {
873 union {
874 struct sk_buff *skb;
875 struct xdp_frame *xdpf;
876 };
877 DEFINE_DMA_UNMAP_ADDR(mapping);
878 DEFINE_DMA_UNMAP_LEN(len);
879 struct page *page;
880 u8 is_ts_pkt;
881 u8 is_push;
882 u8 action;
883 unsigned short nr_frags;
884 union {
885 u16 rx_prod;
886 u16 txts_prod;
887 };
888};
889
890struct bnxt_sw_rx_bd {
891 void *data;
892 u8 *data_ptr;
893 dma_addr_t mapping;
894};
895
896struct bnxt_sw_rx_agg_bd {
897 struct page *page;
898 unsigned int offset;
899 dma_addr_t mapping;
900};
901
902struct bnxt_ring_mem_info {
903 int nr_pages;
904 int page_size;
905 u16 flags;
906#define BNXT_RMEM_VALID_PTE_FLAG 1
907#define BNXT_RMEM_RING_PTE_FLAG 2
908#define BNXT_RMEM_USE_FULL_PAGE_FLAG 4
909
910 u16 depth;
911 struct bnxt_ctx_mem_type *ctx_mem;
912
913 void **pg_arr;
914 dma_addr_t *dma_arr;
915
916 __le64 *pg_tbl;
917 dma_addr_t pg_tbl_map;
918
919 int vmem_size;
920 void **vmem;
921};
922
923struct bnxt_ring_struct {
924 struct bnxt_ring_mem_info ring_mem;
925
926 u16 fw_ring_id; /* Ring id filled by Chimp FW */
927 union {
928 u16 grp_idx;
929 u16 map_idx; /* Used by cmpl rings */
930 };
931 u32 handle;
932 u8 queue_id;
933};
934
935struct tx_push_bd {
936 __le32 doorbell;
937 __le32 tx_bd_len_flags_type;
938 u32 tx_bd_opaque;
939 struct tx_bd_ext txbd2;
940};
941
942struct tx_push_buffer {
943 struct tx_push_bd push_bd;
944 u32 data[25];
945};
946
947struct bnxt_db_info {
948 void __iomem *doorbell;
949 union {
950 u64 db_key64;
951 u32 db_key32;
952 };
953 u32 db_ring_mask;
954 u32 db_epoch_mask;
955 u8 db_epoch_shift;
956};
957
958#define DB_EPOCH(db, idx) (((idx) & (db)->db_epoch_mask) << \
959 ((db)->db_epoch_shift))
960
961#define DB_TOGGLE(tgl) ((tgl) << DBR_TOGGLE_SFT)
962
963#define DB_RING_IDX(db, idx) (((idx) & (db)->db_ring_mask) | \
964 DB_EPOCH(db, idx))
965
966struct bnxt_tx_ring_info {
967 struct bnxt_napi *bnapi;
968 struct bnxt_cp_ring_info *tx_cpr;
969 u16 tx_prod;
970 u16 tx_cons;
971 u16 tx_hw_cons;
972 u16 txq_index;
973 u8 tx_napi_idx;
974 u8 kick_pending;
975 struct bnxt_db_info tx_db;
976
977 struct tx_bd *tx_desc_ring[MAX_TX_PAGES];
978 struct bnxt_sw_tx_bd *tx_buf_ring;
979
980 dma_addr_t tx_desc_mapping[MAX_TX_PAGES];
981
982 struct tx_push_buffer *tx_push;
983 dma_addr_t tx_push_mapping;
984 __le64 data_mapping;
985
986#define BNXT_DEV_STATE_CLOSING 0x1
987 u32 dev_state;
988
989 struct bnxt_ring_struct tx_ring_struct;
990 /* Synchronize simultaneous xdp_xmit on same ring */
991 spinlock_t xdp_tx_lock;
992};
993
994#define BNXT_LEGACY_COAL_CMPL_PARAMS \
995 (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN | \
996 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX | \
997 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET | \
998 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE | \
999 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR | \
1000 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
1001 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR | \
1002 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
1003 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
1004
1005#define BNXT_COAL_CMPL_ENABLES \
1006 (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
1007 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
1008 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
1009 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
1010
1011#define BNXT_COAL_CMPL_MIN_TMR_ENABLE \
1012 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
1013
1014#define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE \
1015 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
1016
1017struct bnxt_coal_cap {
1018 u32 cmpl_params;
1019 u32 nq_params;
1020 u16 num_cmpl_dma_aggr_max;
1021 u16 num_cmpl_dma_aggr_during_int_max;
1022 u16 cmpl_aggr_dma_tmr_max;
1023 u16 cmpl_aggr_dma_tmr_during_int_max;
1024 u16 int_lat_tmr_min_max;
1025 u16 int_lat_tmr_max_max;
1026 u16 num_cmpl_aggr_int_max;
1027 u16 timer_units;
1028};
1029
1030struct bnxt_coal {
1031 u16 coal_ticks;
1032 u16 coal_ticks_irq;
1033 u16 coal_bufs;
1034 u16 coal_bufs_irq;
1035 /* RING_IDLE enabled when coal ticks < idle_thresh */
1036 u16 idle_thresh;
1037 u8 bufs_per_record;
1038 u8 budget;
1039 u16 flags;
1040};
1041
1042struct bnxt_tpa_info {
1043 void *data;
1044 u8 *data_ptr;
1045 dma_addr_t mapping;
1046 u16 len;
1047 unsigned short gso_type;
1048 u32 flags2;
1049 u32 metadata;
1050 enum pkt_hash_types hash_type;
1051 u32 rss_hash;
1052 u32 hdr_info;
1053
1054#define BNXT_TPA_L4_SIZE(hdr_info) \
1055 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
1056
1057#define BNXT_TPA_INNER_L3_OFF(hdr_info) \
1058 (((hdr_info) >> 18) & 0x1ff)
1059
1060#define BNXT_TPA_INNER_L2_OFF(hdr_info) \
1061 (((hdr_info) >> 9) & 0x1ff)
1062
1063#define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
1064 ((hdr_info) & 0x1ff)
1065
1066 u16 cfa_code; /* cfa_code in TPA start compl */
1067 u8 agg_count;
1068 u8 vlan_valid:1;
1069 u8 cfa_code_valid:1;
1070 struct rx_agg_cmp *agg_arr;
1071};
1072
1073#define BNXT_AGG_IDX_BMAP_SIZE (MAX_TPA_P5 / BITS_PER_LONG)
1074
1075struct bnxt_tpa_idx_map {
1076 u16 agg_id_tbl[1024];
1077 unsigned long agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];
1078};
1079
1080struct bnxt_rx_ring_info {
1081 struct bnxt_napi *bnapi;
1082 struct bnxt_cp_ring_info *rx_cpr;
1083 u16 rx_prod;
1084 u16 rx_agg_prod;
1085 u16 rx_sw_agg_prod;
1086 u16 rx_next_cons;
1087 struct bnxt_db_info rx_db;
1088 struct bnxt_db_info rx_agg_db;
1089
1090 struct bpf_prog *xdp_prog;
1091
1092 struct rx_bd *rx_desc_ring[MAX_RX_PAGES];
1093 struct bnxt_sw_rx_bd *rx_buf_ring;
1094
1095 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
1096 struct bnxt_sw_rx_agg_bd *rx_agg_ring;
1097
1098 unsigned long *rx_agg_bmap;
1099 u16 rx_agg_bmap_size;
1100
1101 dma_addr_t rx_desc_mapping[MAX_RX_PAGES];
1102 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
1103
1104 struct bnxt_tpa_info *rx_tpa;
1105 struct bnxt_tpa_idx_map *rx_tpa_idx_map;
1106
1107 struct bnxt_ring_struct rx_ring_struct;
1108 struct bnxt_ring_struct rx_agg_ring_struct;
1109 struct xdp_rxq_info xdp_rxq;
1110 struct page_pool *page_pool;
1111 struct page_pool *head_pool;
1112};
1113
1114struct bnxt_rx_sw_stats {
1115 u64 rx_l4_csum_errors;
1116 u64 rx_resets;
1117 u64 rx_buf_errors;
1118 u64 rx_oom_discards;
1119 u64 rx_netpoll_discards;
1120};
1121
1122struct bnxt_tx_sw_stats {
1123 u64 tx_resets;
1124};
1125
1126struct bnxt_cmn_sw_stats {
1127 u64 missed_irqs;
1128};
1129
1130struct bnxt_sw_stats {
1131 struct bnxt_rx_sw_stats rx;
1132 struct bnxt_tx_sw_stats tx;
1133 struct bnxt_cmn_sw_stats cmn;
1134};
1135
1136struct bnxt_total_ring_err_stats {
1137 u64 rx_total_l4_csum_errors;
1138 u64 rx_total_resets;
1139 u64 rx_total_buf_errors;
1140 u64 rx_total_oom_discards;
1141 u64 rx_total_netpoll_discards;
1142 u64 rx_total_ring_discards;
1143 u64 tx_total_resets;
1144 u64 tx_total_ring_discards;
1145 u64 total_missed_irqs;
1146};
1147
1148struct bnxt_stats_mem {
1149 u64 *sw_stats;
1150 u64 *hw_masks;
1151 void *hw_stats;
1152 dma_addr_t hw_stats_map;
1153 int len;
1154};
1155
1156struct bnxt_cp_ring_info {
1157 struct bnxt_napi *bnapi;
1158 u32 cp_raw_cons;
1159 struct bnxt_db_info cp_db;
1160
1161 u8 had_work_done:1;
1162 u8 has_more_work:1;
1163 u8 had_nqe_notify:1;
1164 u8 toggle;
1165
1166 u8 cp_ring_type;
1167 u8 cp_idx;
1168
1169 u32 last_cp_raw_cons;
1170
1171 struct bnxt_coal rx_ring_coal;
1172 u64 rx_packets;
1173 u64 rx_bytes;
1174 u64 event_ctr;
1175
1176 struct dim dim;
1177
1178 union {
1179 struct tx_cmp **cp_desc_ring;
1180 struct nqe_cn **nq_desc_ring;
1181 };
1182
1183 dma_addr_t *cp_desc_mapping;
1184
1185 struct bnxt_stats_mem stats;
1186 u32 hw_stats_ctx_id;
1187
1188 struct bnxt_sw_stats *sw_stats;
1189
1190 struct bnxt_ring_struct cp_ring_struct;
1191
1192 int cp_ring_count;
1193 struct bnxt_cp_ring_info *cp_ring_arr;
1194};
1195
1196#define BNXT_MAX_QUEUE 8
1197#define BNXT_MAX_TXR_PER_NAPI BNXT_MAX_QUEUE
1198
1199#define bnxt_for_each_napi_tx(iter, bnapi, txr) \
1200 for (iter = 0, txr = (bnapi)->tx_ring[0]; txr; \
1201 txr = (iter < BNXT_MAX_TXR_PER_NAPI - 1) ? \
1202 (bnapi)->tx_ring[++iter] : NULL)
1203
1204struct bnxt_napi {
1205 struct napi_struct napi;
1206 struct bnxt *bp;
1207
1208 int index;
1209 struct bnxt_cp_ring_info cp_ring;
1210 struct bnxt_rx_ring_info *rx_ring;
1211 struct bnxt_tx_ring_info *tx_ring[BNXT_MAX_TXR_PER_NAPI];
1212
1213 void (*tx_int)(struct bnxt *, struct bnxt_napi *,
1214 int budget);
1215 u8 events;
1216 u8 tx_fault:1;
1217
1218 u32 flags;
1219#define BNXT_NAPI_FLAG_XDP 0x1
1220
1221 bool in_reset;
1222};
1223
1224/* "TxRx", 2 hypens, plus maximum integer */
1225#define BNXT_IRQ_NAME_EXTRA 17
1226
1227struct bnxt_irq {
1228 irq_handler_t handler;
1229 unsigned int vector;
1230 u8 requested:1;
1231 u8 have_cpumask:1;
1232 char name[IFNAMSIZ + BNXT_IRQ_NAME_EXTRA];
1233 cpumask_var_t cpu_mask;
1234};
1235
1236#define HWRM_RING_ALLOC_TX 0x1
1237#define HWRM_RING_ALLOC_RX 0x2
1238#define HWRM_RING_ALLOC_AGG 0x4
1239#define HWRM_RING_ALLOC_CMPL 0x8
1240#define HWRM_RING_ALLOC_NQ 0x10
1241
1242#define INVALID_STATS_CTX_ID -1
1243
1244struct bnxt_ring_grp_info {
1245 u16 fw_stats_ctx;
1246 u16 fw_grp_id;
1247 u16 rx_fw_ring_id;
1248 u16 agg_fw_ring_id;
1249 u16 cp_fw_ring_id;
1250};
1251
1252#define BNXT_VNIC_DEFAULT 0
1253#define BNXT_VNIC_NTUPLE 1
1254
1255struct bnxt_vnic_info {
1256 u16 fw_vnic_id; /* returned by Chimp during alloc */
1257#define BNXT_MAX_CTX_PER_VNIC 8
1258 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
1259 u16 fw_l2_ctx_id;
1260 u16 mru;
1261#define BNXT_MAX_UC_ADDRS 4
1262 struct bnxt_l2_filter *l2_filters[BNXT_MAX_UC_ADDRS];
1263 /* index 0 always dev_addr */
1264 u16 uc_filter_count;
1265 u8 *uc_list;
1266
1267 u16 *fw_grp_ids;
1268 dma_addr_t rss_table_dma_addr;
1269 __le16 *rss_table;
1270 dma_addr_t rss_hash_key_dma_addr;
1271 u64 *rss_hash_key;
1272 int rss_table_size;
1273#define BNXT_RSS_TABLE_ENTRIES_P5 64
1274#define BNXT_RSS_TABLE_SIZE_P5 (BNXT_RSS_TABLE_ENTRIES_P5 * 4)
1275#define BNXT_RSS_TABLE_MAX_TBL_P5 8
1276#define BNXT_MAX_RSS_TABLE_SIZE_P5 \
1277 (BNXT_RSS_TABLE_SIZE_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1278#define BNXT_MAX_RSS_TABLE_ENTRIES_P5 \
1279 (BNXT_RSS_TABLE_ENTRIES_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1280
1281 u32 rx_mask;
1282
1283 u8 *mc_list;
1284 int mc_list_size;
1285 int mc_list_count;
1286 dma_addr_t mc_list_mapping;
1287#define BNXT_MAX_MC_ADDRS 16
1288
1289 u32 flags;
1290#define BNXT_VNIC_RSS_FLAG 1
1291#define BNXT_VNIC_RFS_FLAG 2
1292#define BNXT_VNIC_MCAST_FLAG 4
1293#define BNXT_VNIC_UCAST_FLAG 8
1294#define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10
1295#define BNXT_VNIC_NTUPLE_FLAG 0x20
1296#define BNXT_VNIC_RSSCTX_FLAG 0x40
1297 struct ethtool_rxfh_context *rss_ctx;
1298 u32 vnic_id;
1299};
1300
1301struct bnxt_rss_ctx {
1302 struct bnxt_vnic_info vnic;
1303 u8 index;
1304};
1305
1306#define BNXT_MAX_ETH_RSS_CTX 32
1307#define BNXT_VNIC_ID_INVALID 0xffffffff
1308
1309struct bnxt_hw_rings {
1310 int tx;
1311 int rx;
1312 int grp;
1313 int cp;
1314 int cp_p5;
1315 int stat;
1316 int vnic;
1317 int rss_ctx;
1318};
1319
1320struct bnxt_hw_resc {
1321 u16 min_rsscos_ctxs;
1322 u16 max_rsscos_ctxs;
1323 u16 resv_rsscos_ctxs;
1324 u16 min_cp_rings;
1325 u16 max_cp_rings;
1326 u16 resv_cp_rings;
1327 u16 min_tx_rings;
1328 u16 max_tx_rings;
1329 u16 resv_tx_rings;
1330 u16 max_tx_sch_inputs;
1331 u16 min_rx_rings;
1332 u16 max_rx_rings;
1333 u16 resv_rx_rings;
1334 u16 min_hw_ring_grps;
1335 u16 max_hw_ring_grps;
1336 u16 resv_hw_ring_grps;
1337 u16 min_l2_ctxs;
1338 u16 max_l2_ctxs;
1339 u16 min_vnics;
1340 u16 max_vnics;
1341 u16 resv_vnics;
1342 u16 min_stat_ctxs;
1343 u16 max_stat_ctxs;
1344 u16 resv_stat_ctxs;
1345 u16 max_nqs;
1346 u16 max_irqs;
1347 u16 resv_irqs;
1348 u32 max_encap_records;
1349 u32 max_decap_records;
1350 u32 max_tx_em_flows;
1351 u32 max_tx_wm_flows;
1352 u32 max_rx_em_flows;
1353 u32 max_rx_wm_flows;
1354};
1355
1356#if defined(CONFIG_BNXT_SRIOV)
1357struct bnxt_vf_info {
1358 u16 fw_fid;
1359 u8 mac_addr[ETH_ALEN]; /* PF assigned MAC Address */
1360 u8 vf_mac_addr[ETH_ALEN]; /* VF assigned MAC address, only
1361 * stored by PF.
1362 */
1363 u16 vlan;
1364 u16 func_qcfg_flags;
1365 u32 flags;
1366#define BNXT_VF_SPOOFCHK 0x2
1367#define BNXT_VF_LINK_FORCED 0x4
1368#define BNXT_VF_LINK_UP 0x8
1369#define BNXT_VF_TRUST 0x10
1370 u32 min_tx_rate;
1371 u32 max_tx_rate;
1372 void *hwrm_cmd_req_addr;
1373 dma_addr_t hwrm_cmd_req_dma_addr;
1374};
1375#endif
1376
1377struct bnxt_pf_info {
1378#define BNXT_FIRST_PF_FID 1
1379#define BNXT_FIRST_VF_FID 128
1380 u16 fw_fid;
1381 u16 port_id;
1382 u8 mac_addr[ETH_ALEN];
1383 u32 first_vf_id;
1384 u16 active_vfs;
1385 u16 registered_vfs;
1386 u16 max_vfs;
1387 unsigned long *vf_event_bmap;
1388 u16 hwrm_cmd_req_pages;
1389 u8 vf_resv_strategy;
1390#define BNXT_VF_RESV_STRATEGY_MAXIMAL 0
1391#define BNXT_VF_RESV_STRATEGY_MINIMAL 1
1392#define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC 2
1393 void *hwrm_cmd_req_addr[4];
1394 dma_addr_t hwrm_cmd_req_dma_addr[4];
1395 struct bnxt_vf_info *vf;
1396};
1397
1398struct bnxt_filter_base {
1399 struct hlist_node hash;
1400 struct list_head list;
1401 __le64 filter_id;
1402 u8 type;
1403#define BNXT_FLTR_TYPE_NTUPLE 1
1404#define BNXT_FLTR_TYPE_L2 2
1405 u8 flags;
1406#define BNXT_ACT_DROP 1
1407#define BNXT_ACT_RING_DST 2
1408#define BNXT_ACT_FUNC_DST 4
1409#define BNXT_ACT_NO_AGING 8
1410#define BNXT_ACT_RSS_CTX 0x10
1411 u16 sw_id;
1412 u16 rxq;
1413 u16 fw_vnic_id;
1414 u16 vf_idx;
1415 unsigned long state;
1416#define BNXT_FLTR_VALID 0
1417#define BNXT_FLTR_INSERTED 1
1418#define BNXT_FLTR_FW_DELETED 2
1419
1420 struct rcu_head rcu;
1421};
1422
1423struct bnxt_flow_masks {
1424 struct flow_dissector_key_ports ports;
1425 struct flow_dissector_key_addrs addrs;
1426};
1427
1428extern const struct bnxt_flow_masks BNXT_FLOW_MASK_NONE;
1429extern const struct bnxt_flow_masks BNXT_FLOW_IPV6_MASK_ALL;
1430extern const struct bnxt_flow_masks BNXT_FLOW_IPV4_MASK_ALL;
1431
1432struct bnxt_ntuple_filter {
1433 /* base filter must be the first member */
1434 struct bnxt_filter_base base;
1435 struct flow_keys fkeys;
1436 struct bnxt_flow_masks fmasks;
1437 struct bnxt_l2_filter *l2_fltr;
1438 u32 flow_id;
1439};
1440
1441struct bnxt_l2_key {
1442 union {
1443 struct {
1444 u8 dst_mac_addr[ETH_ALEN];
1445 u16 vlan;
1446 };
1447 u32 filter_key;
1448 };
1449};
1450
1451struct bnxt_ipv4_tuple {
1452 struct flow_dissector_key_ipv4_addrs v4addrs;
1453 struct flow_dissector_key_ports ports;
1454};
1455
1456struct bnxt_ipv6_tuple {
1457 struct flow_dissector_key_ipv6_addrs v6addrs;
1458 struct flow_dissector_key_ports ports;
1459};
1460
1461#define BNXT_L2_KEY_SIZE (sizeof(struct bnxt_l2_key) / 4)
1462
1463struct bnxt_l2_filter {
1464 /* base filter must be the first member */
1465 struct bnxt_filter_base base;
1466 struct bnxt_l2_key l2_key;
1467 atomic_t refcnt;
1468};
1469
1470/* Compat version of hwrm_port_phy_qcfg_output capped at 96 bytes. The
1471 * first 95 bytes are identical to hwrm_port_phy_qcfg_output in bnxt_hsi.h.
1472 * The last valid byte in the compat version is different.
1473 */
1474struct hwrm_port_phy_qcfg_output_compat {
1475 __le16 error_code;
1476 __le16 req_type;
1477 __le16 seq_id;
1478 __le16 resp_len;
1479 u8 link;
1480 u8 active_fec_signal_mode;
1481 __le16 link_speed;
1482 u8 duplex_cfg;
1483 u8 pause;
1484 __le16 support_speeds;
1485 __le16 force_link_speed;
1486 u8 auto_mode;
1487 u8 auto_pause;
1488 __le16 auto_link_speed;
1489 __le16 auto_link_speed_mask;
1490 u8 wirespeed;
1491 u8 lpbk;
1492 u8 force_pause;
1493 u8 module_status;
1494 __le32 preemphasis;
1495 u8 phy_maj;
1496 u8 phy_min;
1497 u8 phy_bld;
1498 u8 phy_type;
1499 u8 media_type;
1500 u8 xcvr_pkg_type;
1501 u8 eee_config_phy_addr;
1502 u8 parallel_detect;
1503 __le16 link_partner_adv_speeds;
1504 u8 link_partner_adv_auto_mode;
1505 u8 link_partner_adv_pause;
1506 __le16 adv_eee_link_speed_mask;
1507 __le16 link_partner_adv_eee_link_speed_mask;
1508 __le32 xcvr_identifier_type_tx_lpi_timer;
1509 __le16 fec_cfg;
1510 u8 duplex_state;
1511 u8 option_flags;
1512 char phy_vendor_name[16];
1513 char phy_vendor_partnumber[16];
1514 __le16 support_pam4_speeds;
1515 __le16 force_pam4_link_speed;
1516 __le16 auto_pam4_link_speed_mask;
1517 u8 link_partner_pam4_adv_speeds;
1518 u8 valid;
1519};
1520
1521struct bnxt_link_info {
1522 u8 phy_type;
1523 u8 media_type;
1524 u8 transceiver;
1525 u8 phy_addr;
1526 u8 phy_link_status;
1527#define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK
1528#define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL
1529#define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK
1530 u8 wire_speed;
1531 u8 phy_state;
1532#define BNXT_PHY_STATE_ENABLED 0
1533#define BNXT_PHY_STATE_DISABLED 1
1534
1535 u8 link_state;
1536#define BNXT_LINK_STATE_UNKNOWN 0
1537#define BNXT_LINK_STATE_DOWN 1
1538#define BNXT_LINK_STATE_UP 2
1539#define BNXT_LINK_IS_UP(bp) ((bp)->link_info.link_state == BNXT_LINK_STATE_UP)
1540 u8 active_lanes;
1541 u8 duplex;
1542#define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1543#define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1544 u8 pause;
1545#define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX
1546#define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX
1547#define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \
1548 PORT_PHY_QCFG_RESP_PAUSE_TX)
1549 u8 lp_pause;
1550 u8 auto_pause_setting;
1551 u8 force_pause_setting;
1552 u8 duplex_setting;
1553 u8 auto_mode;
1554#define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \
1555 (mode) <= BNXT_LINK_AUTO_MSK)
1556#define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1557#define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1558#define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1559#define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1560#define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1561#define PHY_VER_LEN 3
1562 u8 phy_ver[PHY_VER_LEN];
1563 u16 link_speed;
1564#define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1565#define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1566#define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1567#define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1568#define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1569#define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1570#define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1571#define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1572#define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1573#define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1574#define BNXT_LINK_SPEED_200GB PORT_PHY_QCFG_RESP_LINK_SPEED_200GB
1575#define BNXT_LINK_SPEED_400GB PORT_PHY_QCFG_RESP_LINK_SPEED_400GB
1576 u16 support_speeds;
1577 u16 support_pam4_speeds;
1578 u16 support_speeds2;
1579
1580 u16 auto_link_speeds; /* fw adv setting */
1581#define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1582#define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1583#define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1584#define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1585#define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1586#define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1587#define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1588#define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1589#define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1590#define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1591 u16 auto_pam4_link_speeds;
1592#define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G
1593#define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G
1594#define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G
1595 u16 auto_link_speeds2;
1596#define BNXT_LINK_SPEEDS2_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB
1597#define BNXT_LINK_SPEEDS2_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB
1598#define BNXT_LINK_SPEEDS2_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_25GB
1599#define BNXT_LINK_SPEEDS2_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_40GB
1600#define BNXT_LINK_SPEEDS2_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB
1601#define BNXT_LINK_SPEEDS2_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB
1602#define BNXT_LINK_SPEEDS2_MSK_50GB_PAM4 \
1603 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB_PAM4_56
1604#define BNXT_LINK_SPEEDS2_MSK_100GB_PAM4 \
1605 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_56
1606#define BNXT_LINK_SPEEDS2_MSK_200GB_PAM4 \
1607 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_56
1608#define BNXT_LINK_SPEEDS2_MSK_400GB_PAM4 \
1609 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_56
1610#define BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112 \
1611 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_112
1612#define BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112 \
1613 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_112
1614#define BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112 \
1615 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_112
1616
1617 u16 support_auto_speeds;
1618 u16 support_pam4_auto_speeds;
1619 u16 support_auto_speeds2;
1620
1621 u16 lp_auto_link_speeds;
1622 u16 lp_auto_pam4_link_speeds;
1623 u16 force_link_speed;
1624 u16 force_pam4_link_speed;
1625 u16 force_link_speed2;
1626#define BNXT_LINK_SPEED_50GB_PAM4 \
1627 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56
1628#define BNXT_LINK_SPEED_100GB_PAM4 \
1629 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56
1630#define BNXT_LINK_SPEED_200GB_PAM4 \
1631 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56
1632#define BNXT_LINK_SPEED_400GB_PAM4 \
1633 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56
1634#define BNXT_LINK_SPEED_100GB_PAM4_112 \
1635 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112
1636#define BNXT_LINK_SPEED_200GB_PAM4_112 \
1637 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112
1638#define BNXT_LINK_SPEED_400GB_PAM4_112 \
1639 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112
1640
1641 u32 preemphasis;
1642 u8 module_status;
1643 u8 active_fec_sig_mode;
1644 u16 fec_cfg;
1645#define BNXT_FEC_NONE PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
1646#define BNXT_FEC_AUTONEG_CAP PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED
1647#define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1648#define BNXT_FEC_ENC_BASE_R_CAP \
1649 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED
1650#define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1651#define BNXT_FEC_ENC_RS_CAP \
1652 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED
1653#define BNXT_FEC_ENC_LLRS_CAP \
1654 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED | \
1655 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED)
1656#define BNXT_FEC_ENC_RS \
1657 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED | \
1658 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED | \
1659 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED)
1660#define BNXT_FEC_ENC_LLRS \
1661 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED | \
1662 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED)
1663
1664 /* copy of requested setting from ethtool cmd */
1665 u8 autoneg;
1666#define BNXT_AUTONEG_SPEED 1
1667#define BNXT_AUTONEG_FLOW_CTRL 2
1668 u8 req_signal_mode;
1669#define BNXT_SIG_MODE_NRZ PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ
1670#define BNXT_SIG_MODE_PAM4 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
1671#define BNXT_SIG_MODE_PAM4_112 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112
1672#define BNXT_SIG_MODE_MAX (PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST + 1)
1673 u8 req_duplex;
1674 u8 req_flow_ctrl;
1675 u16 req_link_speed;
1676 u16 advertising; /* user adv setting */
1677 u16 advertising_pam4;
1678 bool force_link_chng;
1679
1680 bool phy_retry;
1681 unsigned long phy_retry_expires;
1682
1683 /* a copy of phy_qcfg output used to report link
1684 * info to VF
1685 */
1686 struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1687};
1688
1689#define BNXT_FEC_RS544_ON \
1690 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE | \
1691 PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE)
1692
1693#define BNXT_FEC_RS544_OFF \
1694 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE | \
1695 PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE)
1696
1697#define BNXT_FEC_RS272_ON \
1698 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE | \
1699 PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE)
1700
1701#define BNXT_FEC_RS272_OFF \
1702 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE | \
1703 PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE)
1704
1705#define BNXT_PAM4_SUPPORTED(link_info) \
1706 ((link_info)->support_pam4_speeds)
1707
1708#define BNXT_FEC_RS_ON(link_info) \
1709 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \
1710 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1711 (BNXT_PAM4_SUPPORTED(link_info) ? \
1712 (BNXT_FEC_RS544_ON | BNXT_FEC_RS272_OFF) : 0))
1713
1714#define BNXT_FEC_LLRS_ON \
1715 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \
1716 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1717 BNXT_FEC_RS272_ON | BNXT_FEC_RS544_OFF)
1718
1719#define BNXT_FEC_RS_OFF(link_info) \
1720 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE | \
1721 (BNXT_PAM4_SUPPORTED(link_info) ? \
1722 (BNXT_FEC_RS544_OFF | BNXT_FEC_RS272_OFF) : 0))
1723
1724#define BNXT_FEC_BASE_R_ON(link_info) \
1725 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE | \
1726 BNXT_FEC_RS_OFF(link_info))
1727
1728#define BNXT_FEC_ALL_OFF(link_info) \
1729 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1730 BNXT_FEC_RS_OFF(link_info))
1731
1732struct bnxt_queue_info {
1733 u8 queue_id;
1734 u8 queue_profile;
1735};
1736
1737#define BNXT_MAX_LED 4
1738
1739struct bnxt_led_info {
1740 u8 led_id;
1741 u8 led_type;
1742 u8 led_group_id;
1743 u8 unused;
1744 __le16 led_state_caps;
1745#define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
1746 cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1747
1748 __le16 led_color_caps;
1749};
1750
1751#define BNXT_MAX_TEST 8
1752
1753struct bnxt_test_info {
1754 u8 offline_mask;
1755 u16 timeout;
1756 char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1757};
1758
1759#define CHIMP_REG_VIEW_ADDR \
1760 ((bp->flags & BNXT_FLAG_CHIP_P5_PLUS) ? 0x80000000 : 0xb1000000)
1761
1762#define BNXT_GRCPF_REG_CHIMP_COMM 0x0
1763#define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
1764#define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
1765
1766#define BNXT_GRC_REG_STATUS_P5 0x520
1767
1768#define BNXT_GRCPF_REG_KONG_COMM 0xA00
1769#define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00
1770
1771#define BNXT_GRC_REG_CHIP_NUM 0x48
1772#define BNXT_GRC_REG_BASE 0x260000
1773
1774#define BNXT_TS_REG_TIMESYNC_TS0_LOWER 0x640180c
1775#define BNXT_TS_REG_TIMESYNC_TS0_UPPER 0x6401810
1776
1777#define BNXT_GRC_BASE_MASK 0xfffff000
1778#define BNXT_GRC_OFFSET_MASK 0x00000ffc
1779
1780struct bnxt_tc_flow_stats {
1781 u64 packets;
1782 u64 bytes;
1783};
1784
1785#ifdef CONFIG_BNXT_FLOWER_OFFLOAD
1786struct bnxt_flower_indr_block_cb_priv {
1787 struct net_device *tunnel_netdev;
1788 struct bnxt *bp;
1789 struct list_head list;
1790};
1791#endif
1792
1793struct bnxt_tc_info {
1794 bool enabled;
1795
1796 /* hash table to store TC offloaded flows */
1797 struct rhashtable flow_table;
1798 struct rhashtable_params flow_ht_params;
1799
1800 /* hash table to store L2 keys of TC flows */
1801 struct rhashtable l2_table;
1802 struct rhashtable_params l2_ht_params;
1803 /* hash table to store L2 keys for TC tunnel decap */
1804 struct rhashtable decap_l2_table;
1805 struct rhashtable_params decap_l2_ht_params;
1806 /* hash table to store tunnel decap entries */
1807 struct rhashtable decap_table;
1808 struct rhashtable_params decap_ht_params;
1809 /* hash table to store tunnel encap entries */
1810 struct rhashtable encap_table;
1811 struct rhashtable_params encap_ht_params;
1812
1813 /* lock to atomically add/del an l2 node when a flow is
1814 * added or deleted.
1815 */
1816 struct mutex lock;
1817
1818 /* Fields used for batching stats query */
1819 struct rhashtable_iter iter;
1820#define BNXT_FLOW_STATS_BATCH_MAX 10
1821 struct bnxt_tc_stats_batch {
1822 void *flow_node;
1823 struct bnxt_tc_flow_stats hw_stats;
1824 } stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1825
1826 /* Stat counter mask (width) */
1827 u64 bytes_mask;
1828 u64 packets_mask;
1829};
1830
1831struct bnxt_vf_rep_stats {
1832 u64 packets;
1833 u64 bytes;
1834 u64 dropped;
1835};
1836
1837struct bnxt_vf_rep {
1838 struct bnxt *bp;
1839 struct net_device *dev;
1840 struct metadata_dst *dst;
1841 u16 vf_idx;
1842 u16 tx_cfa_action;
1843 u16 rx_cfa_code;
1844
1845 struct bnxt_vf_rep_stats rx_stats;
1846 struct bnxt_vf_rep_stats tx_stats;
1847};
1848
1849#define PTU_PTE_VALID 0x1UL
1850#define PTU_PTE_LAST 0x2UL
1851#define PTU_PTE_NEXT_TO_LAST 0x4UL
1852
1853#define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
1854#define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES)
1855#define MAX_CTX_BYTES ((size_t)MAX_CTX_TOTAL_PAGES * BNXT_PAGE_SIZE)
1856#define MAX_CTX_BYTES_MASK (MAX_CTX_BYTES - 1)
1857
1858struct bnxt_ctx_pg_info {
1859 u32 entries;
1860 u32 nr_pages;
1861 void *ctx_pg_arr[MAX_CTX_PAGES];
1862 dma_addr_t ctx_dma_arr[MAX_CTX_PAGES];
1863 struct bnxt_ring_mem_info ring_mem;
1864 struct bnxt_ctx_pg_info **ctx_pg_tbl;
1865};
1866
1867#define BNXT_MAX_TQM_SP_RINGS 1
1868#define BNXT_MAX_TQM_FP_RINGS 8
1869#define BNXT_MAX_TQM_RINGS \
1870 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
1871
1872#define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256
1873
1874#define BNXT_SET_CTX_PAGE_ATTR(attr) \
1875do { \
1876 if (BNXT_PAGE_SIZE == 0x2000) \
1877 attr = FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K; \
1878 else if (BNXT_PAGE_SIZE == 0x10000) \
1879 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K; \
1880 else \
1881 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K; \
1882} while (0)
1883
1884struct bnxt_ctx_mem_type {
1885 u16 type;
1886 u16 entry_size;
1887 u32 flags;
1888#define BNXT_CTX_MEM_TYPE_VALID FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID
1889#define BNXT_CTX_MEM_FW_TRACE \
1890 FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_FW_DBG_TRACE
1891#define BNXT_CTX_MEM_FW_BIN_TRACE \
1892 FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_FW_BIN_DBG_TRACE
1893#define BNXT_CTX_MEM_PERSIST \
1894 FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_NEXT_BS_OFFSET
1895
1896 u32 instance_bmap;
1897 u8 init_value;
1898 u8 entry_multiple;
1899 u16 init_offset;
1900#define BNXT_CTX_INIT_INVALID_OFFSET 0xffff
1901 u32 max_entries;
1902 u32 min_entries;
1903 u8 last:1;
1904 u8 mem_valid:1;
1905 u8 split_entry_cnt;
1906#define BNXT_MAX_SPLIT_ENTRY 4
1907 union {
1908 struct {
1909 u32 qp_l2_entries;
1910 u32 qp_qp1_entries;
1911 u32 qp_fast_qpmd_entries;
1912 };
1913 u32 srq_l2_entries;
1914 u32 cq_l2_entries;
1915 u32 vnic_entries;
1916 struct {
1917 u32 mrav_av_entries;
1918 u32 mrav_num_entries_units;
1919 };
1920 u32 split[BNXT_MAX_SPLIT_ENTRY];
1921 };
1922 struct bnxt_ctx_pg_info *pg_info;
1923};
1924
1925#define BNXT_CTX_MRAV_AV_SPLIT_ENTRY 0
1926
1927#define BNXT_CTX_QP FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP
1928#define BNXT_CTX_SRQ FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ
1929#define BNXT_CTX_CQ FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ
1930#define BNXT_CTX_VNIC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC
1931#define BNXT_CTX_STAT FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT
1932#define BNXT_CTX_STQM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING
1933#define BNXT_CTX_FTQM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING
1934#define BNXT_CTX_MRAV FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV
1935#define BNXT_CTX_TIM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM
1936#define BNXT_CTX_TCK FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TX_CK
1937#define BNXT_CTX_RCK FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RX_CK
1938#define BNXT_CTX_MTQM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING
1939#define BNXT_CTX_SQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW
1940#define BNXT_CTX_RQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW
1941#define BNXT_CTX_SRQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW
1942#define BNXT_CTX_CQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW
1943#define BNXT_CTX_TBLSC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TBL_SCOPE
1944#define BNXT_CTX_XPAR FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_XID_PARTITION
1945#define BNXT_CTX_SRT FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT_TRACE
1946#define BNXT_CTX_SRT2 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT2_TRACE
1947#define BNXT_CTX_CRT FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT_TRACE
1948#define BNXT_CTX_CRT2 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT2_TRACE
1949#define BNXT_CTX_RIGP0 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP0_TRACE
1950#define BNXT_CTX_L2HWRM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_L2_HWRM_TRACE
1951#define BNXT_CTX_REHWRM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ROCE_HWRM_TRACE
1952#define BNXT_CTX_CA0 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA0_TRACE
1953#define BNXT_CTX_CA1 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA1_TRACE
1954#define BNXT_CTX_CA2 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA2_TRACE
1955#define BNXT_CTX_RIGP1 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP1_TRACE
1956
1957#define BNXT_CTX_MAX (BNXT_CTX_TIM + 1)
1958#define BNXT_CTX_L2_MAX (BNXT_CTX_FTQM + 1)
1959#define BNXT_CTX_V2_MAX (BNXT_CTX_RIGP1 + 1)
1960#define BNXT_CTX_INV ((u16)-1)
1961
1962struct bnxt_ctx_mem_info {
1963 u8 tqm_fp_rings_count;
1964
1965 u32 flags;
1966 #define BNXT_CTX_FLAG_INITED 0x01
1967 struct bnxt_ctx_mem_type ctx_arr[BNXT_CTX_V2_MAX];
1968};
1969
1970enum bnxt_health_severity {
1971 SEVERITY_NORMAL = 0,
1972 SEVERITY_WARNING,
1973 SEVERITY_RECOVERABLE,
1974 SEVERITY_FATAL,
1975};
1976
1977enum bnxt_health_remedy {
1978 REMEDY_DEVLINK_RECOVER,
1979 REMEDY_POWER_CYCLE_DEVICE,
1980 REMEDY_POWER_CYCLE_HOST,
1981 REMEDY_FW_UPDATE,
1982 REMEDY_HW_REPLACE,
1983};
1984
1985struct bnxt_fw_health {
1986 u32 flags;
1987 u32 polling_dsecs;
1988 u32 master_func_wait_dsecs;
1989 u32 normal_func_wait_dsecs;
1990 u32 post_reset_wait_dsecs;
1991 u32 post_reset_max_wait_dsecs;
1992 u32 regs[4];
1993 u32 mapped_regs[4];
1994#define BNXT_FW_HEALTH_REG 0
1995#define BNXT_FW_HEARTBEAT_REG 1
1996#define BNXT_FW_RESET_CNT_REG 2
1997#define BNXT_FW_RESET_INPROG_REG 3
1998 u32 fw_reset_inprog_reg_mask;
1999 u32 last_fw_heartbeat;
2000 u32 last_fw_reset_cnt;
2001 u8 enabled:1;
2002 u8 primary:1;
2003 u8 status_reliable:1;
2004 u8 resets_reliable:1;
2005 u8 tmr_multiplier;
2006 u8 tmr_counter;
2007 u8 fw_reset_seq_cnt;
2008 u32 fw_reset_seq_regs[16];
2009 u32 fw_reset_seq_vals[16];
2010 u32 fw_reset_seq_delay_msec[16];
2011 u32 echo_req_data1;
2012 u32 echo_req_data2;
2013 struct devlink_health_reporter *fw_reporter;
2014 /* Protects severity and remedy */
2015 struct mutex lock;
2016 enum bnxt_health_severity severity;
2017 enum bnxt_health_remedy remedy;
2018 u32 arrests;
2019 u32 discoveries;
2020 u32 survivals;
2021 u32 fatalities;
2022 u32 diagnoses;
2023};
2024
2025#define BNXT_FW_HEALTH_REG_TYPE_MASK 3
2026#define BNXT_FW_HEALTH_REG_TYPE_CFG 0
2027#define BNXT_FW_HEALTH_REG_TYPE_GRC 1
2028#define BNXT_FW_HEALTH_REG_TYPE_BAR0 2
2029#define BNXT_FW_HEALTH_REG_TYPE_BAR1 3
2030
2031#define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
2032#define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
2033
2034#define BNXT_FW_HEALTH_WIN_BASE 0x3000
2035#define BNXT_FW_HEALTH_WIN_MAP_OFF 8
2036
2037#define BNXT_FW_HEALTH_WIN_OFF(reg) (BNXT_FW_HEALTH_WIN_BASE + \
2038 ((reg) & BNXT_GRC_OFFSET_MASK))
2039
2040#define BNXT_FW_STATUS_HEALTH_MSK 0xffff
2041#define BNXT_FW_STATUS_HEALTHY 0x8000
2042#define BNXT_FW_STATUS_SHUTDOWN 0x100000
2043#define BNXT_FW_STATUS_RECOVERING 0x400000
2044
2045#define BNXT_FW_IS_HEALTHY(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\
2046 BNXT_FW_STATUS_HEALTHY)
2047
2048#define BNXT_FW_IS_BOOTING(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \
2049 BNXT_FW_STATUS_HEALTHY)
2050
2051#define BNXT_FW_IS_ERR(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \
2052 BNXT_FW_STATUS_HEALTHY)
2053
2054#define BNXT_FW_IS_RECOVERING(sts) (BNXT_FW_IS_ERR(sts) && \
2055 ((sts) & BNXT_FW_STATUS_RECOVERING))
2056
2057#define BNXT_FW_RETRY 5
2058#define BNXT_FW_IF_RETRY 10
2059#define BNXT_FW_SLOT_RESET_RETRY 4
2060
2061struct bnxt_aux_priv {
2062 struct auxiliary_device aux_dev;
2063 struct bnxt_en_dev *edev;
2064 int id;
2065};
2066
2067enum board_idx {
2068 BCM57301,
2069 BCM57302,
2070 BCM57304,
2071 BCM57417_NPAR,
2072 BCM58700,
2073 BCM57311,
2074 BCM57312,
2075 BCM57402,
2076 BCM57404,
2077 BCM57406,
2078 BCM57402_NPAR,
2079 BCM57407,
2080 BCM57412,
2081 BCM57414,
2082 BCM57416,
2083 BCM57417,
2084 BCM57412_NPAR,
2085 BCM57314,
2086 BCM57417_SFP,
2087 BCM57416_SFP,
2088 BCM57404_NPAR,
2089 BCM57406_NPAR,
2090 BCM57407_SFP,
2091 BCM57407_NPAR,
2092 BCM57414_NPAR,
2093 BCM57416_NPAR,
2094 BCM57452,
2095 BCM57454,
2096 BCM5745x_NPAR,
2097 BCM57508,
2098 BCM57504,
2099 BCM57502,
2100 BCM57508_NPAR,
2101 BCM57504_NPAR,
2102 BCM57502_NPAR,
2103 BCM57608,
2104 BCM57604,
2105 BCM57602,
2106 BCM57601,
2107 BCM58802,
2108 BCM58804,
2109 BCM58808,
2110 NETXTREME_E_VF,
2111 NETXTREME_C_VF,
2112 NETXTREME_S_VF,
2113 NETXTREME_C_VF_HV,
2114 NETXTREME_E_VF_HV,
2115 NETXTREME_E_P5_VF,
2116 NETXTREME_E_P5_VF_HV,
2117 NETXTREME_E_P7_VF,
2118};
2119
2120#define BNXT_TRACE_BUF_MAGIC_BYTE ((u8)0xbc)
2121#define BNXT_TRACE_MAX 11
2122
2123struct bnxt_bs_trace_info {
2124 u8 *magic_byte;
2125 u32 last_offset;
2126 u8 wrapped:1;
2127 u16 ctx_type;
2128 u16 trace_type;
2129};
2130
2131static inline void bnxt_bs_trace_check_wrap(struct bnxt_bs_trace_info *bs_trace,
2132 u32 offset)
2133{
2134 if (!bs_trace->wrapped &&
2135 *bs_trace->magic_byte != BNXT_TRACE_BUF_MAGIC_BYTE)
2136 bs_trace->wrapped = 1;
2137 bs_trace->last_offset = offset;
2138}
2139
2140struct bnxt {
2141 void __iomem *bar0;
2142 void __iomem *bar1;
2143 void __iomem *bar2;
2144
2145 u32 reg_base;
2146 u16 chip_num;
2147#define CHIP_NUM_57301 0x16c8
2148#define CHIP_NUM_57302 0x16c9
2149#define CHIP_NUM_57304 0x16ca
2150#define CHIP_NUM_58700 0x16cd
2151#define CHIP_NUM_57402 0x16d0
2152#define CHIP_NUM_57404 0x16d1
2153#define CHIP_NUM_57406 0x16d2
2154#define CHIP_NUM_57407 0x16d5
2155
2156#define CHIP_NUM_57311 0x16ce
2157#define CHIP_NUM_57312 0x16cf
2158#define CHIP_NUM_57314 0x16df
2159#define CHIP_NUM_57317 0x16e0
2160#define CHIP_NUM_57412 0x16d6
2161#define CHIP_NUM_57414 0x16d7
2162#define CHIP_NUM_57416 0x16d8
2163#define CHIP_NUM_57417 0x16d9
2164#define CHIP_NUM_57412L 0x16da
2165#define CHIP_NUM_57414L 0x16db
2166
2167#define CHIP_NUM_5745X 0xd730
2168#define CHIP_NUM_57452 0xc452
2169#define CHIP_NUM_57454 0xc454
2170
2171#define CHIP_NUM_57508 0x1750
2172#define CHIP_NUM_57504 0x1751
2173#define CHIP_NUM_57502 0x1752
2174
2175#define CHIP_NUM_57608 0x1760
2176
2177#define CHIP_NUM_58802 0xd802
2178#define CHIP_NUM_58804 0xd804
2179#define CHIP_NUM_58808 0xd808
2180
2181 u8 chip_rev;
2182
2183#define BNXT_CHIP_NUM_5730X(chip_num) \
2184 ((chip_num) >= CHIP_NUM_57301 && \
2185 (chip_num) <= CHIP_NUM_57304)
2186
2187#define BNXT_CHIP_NUM_5740X(chip_num) \
2188 (((chip_num) >= CHIP_NUM_57402 && \
2189 (chip_num) <= CHIP_NUM_57406) || \
2190 (chip_num) == CHIP_NUM_57407)
2191
2192#define BNXT_CHIP_NUM_5731X(chip_num) \
2193 ((chip_num) == CHIP_NUM_57311 || \
2194 (chip_num) == CHIP_NUM_57312 || \
2195 (chip_num) == CHIP_NUM_57314 || \
2196 (chip_num) == CHIP_NUM_57317)
2197
2198#define BNXT_CHIP_NUM_5741X(chip_num) \
2199 ((chip_num) >= CHIP_NUM_57412 && \
2200 (chip_num) <= CHIP_NUM_57414L)
2201
2202#define BNXT_CHIP_NUM_58700(chip_num) \
2203 ((chip_num) == CHIP_NUM_58700)
2204
2205#define BNXT_CHIP_NUM_5745X(chip_num) \
2206 ((chip_num) == CHIP_NUM_5745X || \
2207 (chip_num) == CHIP_NUM_57452 || \
2208 (chip_num) == CHIP_NUM_57454)
2209
2210
2211#define BNXT_CHIP_NUM_57X0X(chip_num) \
2212 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
2213
2214#define BNXT_CHIP_NUM_57X1X(chip_num) \
2215 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
2216
2217#define BNXT_CHIP_NUM_588XX(chip_num) \
2218 ((chip_num) == CHIP_NUM_58802 || \
2219 (chip_num) == CHIP_NUM_58804 || \
2220 (chip_num) == CHIP_NUM_58808)
2221
2222#define BNXT_VPD_FLD_LEN 32
2223 char board_partno[BNXT_VPD_FLD_LEN];
2224 char board_serialno[BNXT_VPD_FLD_LEN];
2225
2226 struct net_device *dev;
2227 struct pci_dev *pdev;
2228
2229 atomic_t intr_sem;
2230
2231 u32 flags;
2232 #define BNXT_FLAG_CHIP_P5_PLUS 0x1
2233 #define BNXT_FLAG_VF 0x2
2234 #define BNXT_FLAG_LRO 0x4
2235#ifdef CONFIG_INET
2236 #define BNXT_FLAG_GRO 0x8
2237#else
2238 /* Cannot support hardware GRO if CONFIG_INET is not set */
2239 #define BNXT_FLAG_GRO 0x0
2240#endif
2241 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
2242 #define BNXT_FLAG_JUMBO 0x10
2243 #define BNXT_FLAG_STRIP_VLAN 0x20
2244 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
2245 BNXT_FLAG_LRO)
2246 #define BNXT_FLAG_RFS 0x100
2247 #define BNXT_FLAG_SHARED_RINGS 0x200
2248 #define BNXT_FLAG_PORT_STATS 0x400
2249 #define BNXT_FLAG_WOL_CAP 0x4000
2250 #define BNXT_FLAG_ROCEV1_CAP 0x8000
2251 #define BNXT_FLAG_ROCEV2_CAP 0x10000
2252 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \
2253 BNXT_FLAG_ROCEV2_CAP)
2254 #define BNXT_FLAG_NO_AGG_RINGS 0x20000
2255 #define BNXT_FLAG_RX_PAGE_MODE 0x40000
2256 #define BNXT_FLAG_CHIP_P7 0x80000
2257 #define BNXT_FLAG_MULTI_HOST 0x100000
2258 #define BNXT_FLAG_DSN_VALID 0x200000
2259 #define BNXT_FLAG_DOUBLE_DB 0x400000
2260 #define BNXT_FLAG_UDP_GSO_CAP 0x800000
2261 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
2262 #define BNXT_FLAG_DIM 0x2000000
2263 #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000
2264 #define BNXT_FLAG_TX_COAL_CMPL 0x8000000
2265 #define BNXT_FLAG_PORT_STATS_EXT 0x10000000
2266
2267 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \
2268 BNXT_FLAG_RFS | \
2269 BNXT_FLAG_STRIP_VLAN)
2270
2271#define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
2272#define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
2273#define BNXT_NPAR(bp) ((bp)->port_partition_type)
2274#define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
2275#define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
2276#define BNXT_SH_PORT_CFG_OK(bp) (BNXT_PF(bp) && \
2277 ((bp)->phy_flags & BNXT_PHY_FL_SHARED_PORT_CFG))
2278#define BNXT_PHY_CFG_ABLE(bp) ((BNXT_SINGLE_PF(bp) || \
2279 BNXT_SH_PORT_CFG_OK(bp)) && \
2280 (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED)
2281#define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
2282#define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
2283#define BNXT_SUPPORTS_TPA(bp) (!BNXT_CHIP_TYPE_NITRO_A0(bp) && \
2284 (!((bp)->flags & BNXT_FLAG_CHIP_P5_PLUS) ||\
2285 (bp)->max_tpa_v2) && !is_kdump_kernel())
2286#define BNXT_RX_JUMBO_MODE(bp) ((bp)->flags & BNXT_FLAG_JUMBO)
2287
2288#define BNXT_CHIP_P7(bp) \
2289 ((bp)->chip_num == CHIP_NUM_57608)
2290
2291#define BNXT_CHIP_P5(bp) \
2292 ((bp)->chip_num == CHIP_NUM_57508 || \
2293 (bp)->chip_num == CHIP_NUM_57504 || \
2294 (bp)->chip_num == CHIP_NUM_57502)
2295
2296/* Chip class phase 5 */
2297#define BNXT_CHIP_P5_PLUS(bp) \
2298 (BNXT_CHIP_P5(bp) || BNXT_CHIP_P7(bp))
2299
2300/* Chip class phase 4.x */
2301#define BNXT_CHIP_P4(bp) \
2302 (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
2303 BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
2304 BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
2305 (BNXT_CHIP_NUM_58700((bp)->chip_num) && \
2306 !BNXT_CHIP_TYPE_NITRO_A0(bp)))
2307
2308/* Chip class phase 3.x */
2309#define BNXT_CHIP_P3(bp) \
2310 (BNXT_CHIP_NUM_57X0X((bp)->chip_num) || \
2311 BNXT_CHIP_TYPE_NITRO_A0(bp))
2312
2313#define BNXT_CHIP_P4_PLUS(bp) \
2314 (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5_PLUS(bp))
2315
2316#define BNXT_CHIP_P5_AND_MINUS(bp) \
2317 (BNXT_CHIP_P3(bp) || BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
2318
2319 struct bnxt_aux_priv *aux_priv;
2320 struct bnxt_en_dev *edev;
2321
2322 struct bnxt_napi **bnapi;
2323
2324 struct bnxt_rx_ring_info *rx_ring;
2325 struct bnxt_tx_ring_info *tx_ring;
2326 u16 *tx_ring_map;
2327
2328 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int,
2329 struct sk_buff *);
2330
2331 struct sk_buff * (*rx_skb_func)(struct bnxt *,
2332 struct bnxt_rx_ring_info *,
2333 u16, void *, u8 *, dma_addr_t,
2334 unsigned int);
2335
2336 u16 max_tpa_v2;
2337 u16 max_tpa;
2338 u32 rx_buf_size;
2339 u32 rx_buf_use_size; /* useable size */
2340 u16 rx_offset;
2341 u16 rx_dma_offset;
2342 enum dma_data_direction rx_dir;
2343 u32 rx_ring_size;
2344 u32 rx_agg_ring_size;
2345 u32 rx_copy_thresh;
2346 u32 rx_ring_mask;
2347 u32 rx_agg_ring_mask;
2348 int rx_nr_pages;
2349 int rx_agg_nr_pages;
2350 int rx_nr_rings;
2351 int rsscos_nr_ctxs;
2352
2353 u32 tx_ring_size;
2354 u32 tx_ring_mask;
2355 int tx_nr_pages;
2356 int tx_nr_rings;
2357 int tx_nr_rings_per_tc;
2358 int tx_nr_rings_xdp;
2359
2360 int tx_wake_thresh;
2361 int tx_push_thresh;
2362 int tx_push_size;
2363
2364 u32 cp_ring_size;
2365 u32 cp_ring_mask;
2366 u32 cp_bit;
2367 int cp_nr_pages;
2368 int cp_nr_rings;
2369
2370 /* grp_info indexed by completion ring index */
2371 struct bnxt_ring_grp_info *grp_info;
2372 struct bnxt_vnic_info *vnic_info;
2373 u32 num_rss_ctx;
2374 int nr_vnics;
2375 u32 *rss_indir_tbl;
2376 u16 rss_indir_tbl_entries;
2377 u32 rss_hash_cfg;
2378 u32 rss_hash_delta;
2379 u32 rss_cap;
2380#define BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA BIT(0)
2381#define BNXT_RSS_CAP_UDP_RSS_CAP BIT(1)
2382#define BNXT_RSS_CAP_NEW_RSS_CAP BIT(2)
2383#define BNXT_RSS_CAP_RSS_TCAM BIT(3)
2384#define BNXT_RSS_CAP_AH_V4_RSS_CAP BIT(4)
2385#define BNXT_RSS_CAP_AH_V6_RSS_CAP BIT(5)
2386#define BNXT_RSS_CAP_ESP_V4_RSS_CAP BIT(6)
2387#define BNXT_RSS_CAP_ESP_V6_RSS_CAP BIT(7)
2388#define BNXT_RSS_CAP_MULTI_RSS_CTX BIT(8)
2389
2390 u8 rss_hash_key[HW_HASH_KEY_SIZE];
2391 u8 rss_hash_key_valid:1;
2392 u8 rss_hash_key_updated:1;
2393
2394 u16 max_mtu;
2395 u16 tso_max_segs;
2396 u8 max_tc;
2397 u8 max_lltc; /* lossless TCs */
2398 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE];
2399 u8 tc_to_qidx[BNXT_MAX_QUEUE];
2400 u8 q_ids[BNXT_MAX_QUEUE];
2401 u8 max_q;
2402 u8 num_tc;
2403
2404 unsigned int current_interval;
2405#define BNXT_TIMER_INTERVAL HZ
2406
2407 struct timer_list timer;
2408
2409 unsigned long state;
2410#define BNXT_STATE_OPEN 0
2411#define BNXT_STATE_IN_SP_TASK 1
2412#define BNXT_STATE_READ_STATS 2
2413#define BNXT_STATE_FW_RESET_DET 3
2414#define BNXT_STATE_IN_FW_RESET 4
2415#define BNXT_STATE_ABORT_ERR 5
2416#define BNXT_STATE_FW_FATAL_COND 6
2417#define BNXT_STATE_DRV_REGISTERED 7
2418#define BNXT_STATE_PCI_CHANNEL_IO_FROZEN 8
2419#define BNXT_STATE_NAPI_DISABLED 9
2420#define BNXT_STATE_L2_FILTER_RETRY 10
2421#define BNXT_STATE_FW_ACTIVATE 11
2422#define BNXT_STATE_RECOVER 12
2423#define BNXT_STATE_FW_NON_FATAL_COND 13
2424#define BNXT_STATE_FW_ACTIVATE_RESET 14
2425#define BNXT_STATE_HALF_OPEN 15 /* For offline ethtool tests */
2426
2427#define BNXT_NO_FW_ACCESS(bp) \
2428 (test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) || \
2429 pci_channel_offline((bp)->pdev))
2430
2431 struct bnxt_irq *irq_tbl;
2432 int total_irqs;
2433 int ulp_num_msix_want;
2434 u8 mac_addr[ETH_ALEN];
2435
2436#ifdef CONFIG_BNXT_DCB
2437 struct ieee_pfc *ieee_pfc;
2438 struct ieee_ets *ieee_ets;
2439 u8 dcbx_cap;
2440 u8 default_pri;
2441 u8 max_dscp_value;
2442#endif /* CONFIG_BNXT_DCB */
2443
2444 u32 msg_enable;
2445
2446 u64 fw_cap;
2447 #define BNXT_FW_CAP_SHORT_CMD BIT_ULL(0)
2448 #define BNXT_FW_CAP_LLDP_AGENT BIT_ULL(1)
2449 #define BNXT_FW_CAP_DCBX_AGENT BIT_ULL(2)
2450 #define BNXT_FW_CAP_NEW_RM BIT_ULL(3)
2451 #define BNXT_FW_CAP_IF_CHANGE BIT_ULL(4)
2452 #define BNXT_FW_CAP_ENABLE_RDMA_SRIOV BIT_ULL(5)
2453 #define BNXT_FW_CAP_ROCE_VF_RESC_MGMT_SUPPORTED BIT_ULL(6)
2454 #define BNXT_FW_CAP_KONG_MB_CHNL BIT_ULL(7)
2455 #define BNXT_FW_CAP_OVS_64BIT_HANDLE BIT_ULL(10)
2456 #define BNXT_FW_CAP_TRUSTED_VF BIT_ULL(11)
2457 #define BNXT_FW_CAP_ERROR_RECOVERY BIT_ULL(13)
2458 #define BNXT_FW_CAP_PKG_VER BIT_ULL(14)
2459 #define BNXT_FW_CAP_CFA_ADV_FLOW BIT_ULL(15)
2460 #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 BIT_ULL(16)
2461 #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED BIT_ULL(17)
2462 #define BNXT_FW_CAP_EXT_STATS_SUPPORTED BIT_ULL(18)
2463 #define BNXT_FW_CAP_TX_TS_CMP BIT_ULL(19)
2464 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT_ULL(20)
2465 #define BNXT_FW_CAP_HOT_RESET BIT_ULL(21)
2466 #define BNXT_FW_CAP_PTP_RTC BIT_ULL(22)
2467 #define BNXT_FW_CAP_RX_ALL_PKT_TS BIT_ULL(23)
2468 #define BNXT_FW_CAP_VLAN_RX_STRIP BIT_ULL(24)
2469 #define BNXT_FW_CAP_VLAN_TX_INSERT BIT_ULL(25)
2470 #define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED BIT_ULL(26)
2471 #define BNXT_FW_CAP_LIVEPATCH BIT_ULL(27)
2472 #define BNXT_FW_CAP_PTP_PPS BIT_ULL(28)
2473 #define BNXT_FW_CAP_HOT_RESET_IF BIT_ULL(29)
2474 #define BNXT_FW_CAP_RING_MONITOR BIT_ULL(30)
2475 #define BNXT_FW_CAP_DBG_QCAPS BIT_ULL(31)
2476 #define BNXT_FW_CAP_PTP BIT_ULL(32)
2477 #define BNXT_FW_CAP_THRESHOLD_TEMP_SUPPORTED BIT_ULL(33)
2478 #define BNXT_FW_CAP_DFLT_VLAN_TPID_PCP BIT_ULL(34)
2479 #define BNXT_FW_CAP_PRE_RESV_VNICS BIT_ULL(35)
2480 #define BNXT_FW_CAP_BACKING_STORE_V2 BIT_ULL(36)
2481 #define BNXT_FW_CAP_VNIC_TUNNEL_TPA BIT_ULL(37)
2482 #define BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO BIT_ULL(38)
2483 #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V3 BIT_ULL(39)
2484 #define BNXT_FW_CAP_VNIC_RE_FLUSH BIT_ULL(40)
2485
2486 u32 fw_dbg_cap;
2487
2488#define BNXT_NEW_RM(bp) ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
2489#define BNXT_PTP_USE_RTC(bp) (!BNXT_MH(bp) && \
2490 ((bp)->fw_cap & BNXT_FW_CAP_PTP_RTC))
2491#define BNXT_SUPPORTS_NTUPLE_VNIC(bp) \
2492 (BNXT_PF(bp) && ((bp)->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V3))
2493
2494#define BNXT_SUPPORTS_MULTI_RSS_CTX(bp) \
2495 (BNXT_PF(bp) && BNXT_SUPPORTS_NTUPLE_VNIC(bp) && \
2496 ((bp)->rss_cap & BNXT_RSS_CAP_MULTI_RSS_CTX))
2497#define BNXT_SUPPORTS_QUEUE_API(bp) \
2498 (BNXT_PF(bp) && BNXT_SUPPORTS_NTUPLE_VNIC(bp) && \
2499 ((bp)->fw_cap & BNXT_FW_CAP_VNIC_RE_FLUSH))
2500#define BNXT_RDMA_SRIOV_EN(bp) \
2501 ((bp)->fw_cap & BNXT_FW_CAP_ENABLE_RDMA_SRIOV)
2502#define BNXT_ROCE_VF_RESC_CAP(bp) \
2503 ((bp)->fw_cap & BNXT_FW_CAP_ROCE_VF_RESC_MGMT_SUPPORTED)
2504
2505 u32 hwrm_spec_code;
2506 u16 hwrm_cmd_seq;
2507 u16 hwrm_cmd_kong_seq;
2508 struct dma_pool *hwrm_dma_pool;
2509 struct hlist_head hwrm_pending_list;
2510
2511 struct rtnl_link_stats64 net_stats_prev;
2512 struct bnxt_stats_mem port_stats;
2513 struct bnxt_stats_mem rx_port_stats_ext;
2514 struct bnxt_stats_mem tx_port_stats_ext;
2515 u16 fw_rx_stats_ext_size;
2516 u16 fw_tx_stats_ext_size;
2517 u16 hw_ring_stats_size;
2518 u8 pri2cos_idx[8];
2519 u8 pri2cos_valid;
2520
2521 struct bnxt_total_ring_err_stats ring_err_stats_prev;
2522
2523 u16 hwrm_max_req_len;
2524 u16 hwrm_max_ext_req_len;
2525 unsigned int hwrm_cmd_timeout;
2526 unsigned int hwrm_cmd_max_timeout;
2527 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */
2528 struct hwrm_ver_get_output ver_resp;
2529#define FW_VER_STR_LEN 32
2530#define BC_HWRM_STR_LEN 21
2531#define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
2532 char fw_ver_str[FW_VER_STR_LEN];
2533 char hwrm_ver_supp[FW_VER_STR_LEN];
2534 char nvm_cfg_ver[FW_VER_STR_LEN];
2535 u64 fw_ver_code;
2536#define BNXT_FW_VER_CODE(maj, min, bld, rsv) \
2537 ((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv))
2538#define BNXT_FW_MAJ(bp) ((bp)->fw_ver_code >> 48)
2539#define BNXT_FW_BLD(bp) (((bp)->fw_ver_code >> 16) & 0xffff)
2540
2541 u16 vxlan_fw_dst_port_id;
2542 u16 nge_fw_dst_port_id;
2543 u16 vxlan_gpe_fw_dst_port_id;
2544 __be16 vxlan_port;
2545 __be16 nge_port;
2546 __be16 vxlan_gpe_port;
2547 u8 port_partition_type;
2548 u8 port_count;
2549 u16 br_mode;
2550
2551 struct bnxt_coal_cap coal_cap;
2552 struct bnxt_coal rx_coal;
2553 struct bnxt_coal tx_coal;
2554
2555 u32 stats_coal_ticks;
2556#define BNXT_DEF_STATS_COAL_TICKS 1000000
2557#define BNXT_MIN_STATS_COAL_TICKS 250000
2558#define BNXT_MAX_STATS_COAL_TICKS 1000000
2559
2560 struct work_struct sp_task;
2561 unsigned long sp_event;
2562#define BNXT_RX_MASK_SP_EVENT 0
2563#define BNXT_RX_NTP_FLTR_SP_EVENT 1
2564#define BNXT_LINK_CHNG_SP_EVENT 2
2565#define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
2566#define BNXT_RESET_TASK_SP_EVENT 6
2567#define BNXT_RST_RING_SP_EVENT 7
2568#define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8
2569#define BNXT_PERIODIC_STATS_SP_EVENT 9
2570#define BNXT_HWRM_PORT_MODULE_SP_EVENT 10
2571#define BNXT_RESET_TASK_SILENT_SP_EVENT 11
2572#define BNXT_LINK_SPEED_CHNG_SP_EVENT 14
2573#define BNXT_FLOW_STATS_SP_EVENT 15
2574#define BNXT_UPDATE_PHY_SP_EVENT 16
2575#define BNXT_RING_COAL_NOW_SP_EVENT 17
2576#define BNXT_FW_RESET_NOTIFY_SP_EVENT 18
2577#define BNXT_FW_EXCEPTION_SP_EVENT 19
2578#define BNXT_LINK_CFG_CHANGE_SP_EVENT 21
2579#define BNXT_THERMAL_THRESHOLD_SP_EVENT 22
2580#define BNXT_FW_ECHO_REQUEST_SP_EVENT 23
2581#define BNXT_RESTART_ULP_SP_EVENT 24
2582
2583 struct delayed_work fw_reset_task;
2584 int fw_reset_state;
2585#define BNXT_FW_RESET_STATE_POLL_VF 1
2586#define BNXT_FW_RESET_STATE_RESET_FW 2
2587#define BNXT_FW_RESET_STATE_ENABLE_DEV 3
2588#define BNXT_FW_RESET_STATE_POLL_FW 4
2589#define BNXT_FW_RESET_STATE_OPENING 5
2590#define BNXT_FW_RESET_STATE_POLL_FW_DOWN 6
2591
2592 u16 fw_reset_min_dsecs;
2593#define BNXT_DFLT_FW_RST_MIN_DSECS 20
2594 u16 fw_reset_max_dsecs;
2595#define BNXT_DFLT_FW_RST_MAX_DSECS 60
2596 unsigned long fw_reset_timestamp;
2597
2598 struct bnxt_fw_health *fw_health;
2599
2600 struct bnxt_hw_resc hw_resc;
2601 struct bnxt_pf_info pf;
2602 struct bnxt_ctx_mem_info *ctx;
2603#ifdef CONFIG_BNXT_SRIOV
2604 int nr_vfs;
2605 struct bnxt_vf_info vf;
2606 wait_queue_head_t sriov_cfg_wait;
2607 bool sriov_cfg;
2608#define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
2609#endif
2610
2611#if BITS_PER_LONG == 32
2612 /* ensure atomic 64-bit doorbell writes on 32-bit systems. */
2613 spinlock_t db_lock;
2614#endif
2615 int db_offset; /* db_offset within db_size */
2616 int db_size;
2617
2618#define BNXT_NTP_FLTR_MAX_FLTR 4096
2619#define BNXT_MAX_FLTR (BNXT_NTP_FLTR_MAX_FLTR + BNXT_L2_FLTR_MAX_FLTR)
2620#define BNXT_NTP_FLTR_HASH_SIZE 512
2621#define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
2622 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
2623 spinlock_t ntp_fltr_lock; /* for hash table add, del */
2624
2625 unsigned long *ntp_fltr_bmap;
2626 int ntp_fltr_count;
2627 int max_fltr;
2628
2629#define BNXT_L2_FLTR_MAX_FLTR 1024
2630#define BNXT_L2_FLTR_HASH_SIZE 32
2631#define BNXT_L2_FLTR_HASH_MASK (BNXT_L2_FLTR_HASH_SIZE - 1)
2632 struct hlist_head l2_fltr_hash_tbl[BNXT_L2_FLTR_HASH_SIZE];
2633
2634 u32 hash_seed;
2635 u64 toeplitz_prefix;
2636
2637 struct list_head usr_fltr_list;
2638
2639 /* To protect link related settings during link changes and
2640 * ethtool settings changes.
2641 */
2642 struct mutex link_lock;
2643 struct bnxt_link_info link_info;
2644 struct ethtool_keee eee;
2645 u32 lpi_tmr_lo;
2646 u32 lpi_tmr_hi;
2647
2648 /* copied from flags and flags2 in hwrm_port_phy_qcaps_output */
2649 u32 phy_flags;
2650#define BNXT_PHY_FL_EEE_CAP PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED
2651#define BNXT_PHY_FL_EXT_LPBK PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED
2652#define BNXT_PHY_FL_AN_PHY_LPBK PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED
2653#define BNXT_PHY_FL_SHARED_PORT_CFG PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED
2654#define BNXT_PHY_FL_PORT_STATS_NO_RESET PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET
2655#define BNXT_PHY_FL_NO_PHY_LPBK PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED
2656#define BNXT_PHY_FL_FW_MANAGED_LKDN PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN
2657#define BNXT_PHY_FL_NO_FCS PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS
2658#define BNXT_PHY_FL_NO_PAUSE (PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED << 8)
2659#define BNXT_PHY_FL_NO_PFC (PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED << 8)
2660#define BNXT_PHY_FL_BANK_SEL (PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED << 8)
2661#define BNXT_PHY_FL_SPEEDS2 (PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED << 8)
2662
2663 u8 num_tests;
2664 struct bnxt_test_info *test_info;
2665
2666 u8 wol_filter_id;
2667 u8 wol;
2668
2669 u8 num_leds;
2670 struct bnxt_led_info leds[BNXT_MAX_LED];
2671 u16 dump_flag;
2672#define BNXT_DUMP_LIVE 0
2673#define BNXT_DUMP_CRASH 1
2674#define BNXT_DUMP_DRIVER 2
2675
2676 struct bpf_prog *xdp_prog;
2677
2678 struct bnxt_ptp_cfg *ptp_cfg;
2679 u8 ptp_all_rx_tstamp;
2680
2681 /* devlink interface and vf-rep structs */
2682 struct devlink *dl;
2683 struct devlink_port dl_port;
2684 enum devlink_eswitch_mode eswitch_mode;
2685 struct bnxt_vf_rep **vf_reps; /* array of vf-rep ptrs */
2686 u16 *cfa_code_map; /* cfa_code -> vf_idx map */
2687 u8 dsn[8];
2688 struct bnxt_tc_info *tc_info;
2689 struct list_head tc_indr_block_list;
2690 struct dentry *debugfs_pdev;
2691#ifdef CONFIG_BNXT_HWMON
2692 struct device *hwmon_dev;
2693 u8 warn_thresh_temp;
2694 u8 crit_thresh_temp;
2695 u8 fatal_thresh_temp;
2696 u8 shutdown_thresh_temp;
2697#endif
2698 u32 thermal_threshold_type;
2699 enum board_idx board_idx;
2700
2701 struct bnxt_ctx_pg_info *fw_crash_mem;
2702 u32 fw_crash_len;
2703 struct bnxt_bs_trace_info bs_trace[BNXT_TRACE_MAX];
2704};
2705
2706#define BNXT_NUM_RX_RING_STATS 8
2707#define BNXT_NUM_TX_RING_STATS 8
2708#define BNXT_NUM_TPA_RING_STATS 4
2709#define BNXT_NUM_TPA_RING_STATS_P5 5
2710#define BNXT_NUM_TPA_RING_STATS_P7 6
2711
2712#define BNXT_RING_STATS_SIZE_P5 \
2713 ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \
2714 BNXT_NUM_TPA_RING_STATS_P5) * 8)
2715
2716#define BNXT_RING_STATS_SIZE_P7 \
2717 ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \
2718 BNXT_NUM_TPA_RING_STATS_P7) * 8)
2719
2720#define BNXT_GET_RING_STATS64(sw, counter) \
2721 (*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))
2722
2723#define BNXT_GET_RX_PORT_STATS64(sw, counter) \
2724 (*((sw) + offsetof(struct rx_port_stats, counter) / 8))
2725
2726#define BNXT_GET_TX_PORT_STATS64(sw, counter) \
2727 (*((sw) + offsetof(struct tx_port_stats, counter) / 8))
2728
2729#define BNXT_PORT_STATS_SIZE \
2730 (sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024)
2731
2732#define BNXT_TX_PORT_STATS_BYTE_OFFSET \
2733 (sizeof(struct rx_port_stats) + 512)
2734
2735#define BNXT_RX_STATS_OFFSET(counter) \
2736 (offsetof(struct rx_port_stats, counter) / 8)
2737
2738#define BNXT_TX_STATS_OFFSET(counter) \
2739 ((offsetof(struct tx_port_stats, counter) + \
2740 BNXT_TX_PORT_STATS_BYTE_OFFSET) / 8)
2741
2742#define BNXT_RX_STATS_EXT_OFFSET(counter) \
2743 (offsetof(struct rx_port_stats_ext, counter) / 8)
2744
2745#define BNXT_RX_STATS_EXT_NUM_LEGACY \
2746 BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)
2747
2748#define BNXT_TX_STATS_EXT_OFFSET(counter) \
2749 (offsetof(struct tx_port_stats_ext, counter) / 8)
2750
2751#define BNXT_HW_FEATURE_VLAN_ALL_RX \
2752 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)
2753#define BNXT_HW_FEATURE_VLAN_ALL_TX \
2754 (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX)
2755
2756#define I2C_DEV_ADDR_A0 0xa0
2757#define I2C_DEV_ADDR_A2 0xa2
2758#define SFF_DIAG_SUPPORT_OFFSET 0x5c
2759#define SFF_MODULE_ID_SFP 0x3
2760#define SFF_MODULE_ID_QSFP 0xc
2761#define SFF_MODULE_ID_QSFP_PLUS 0xd
2762#define SFF_MODULE_ID_QSFP28 0x11
2763#define BNXT_MAX_PHY_I2C_RESP_SIZE 64
2764
2765static inline u32 bnxt_tx_avail(struct bnxt *bp,
2766 const struct bnxt_tx_ring_info *txr)
2767{
2768 u32 used = READ_ONCE(txr->tx_prod) - READ_ONCE(txr->tx_cons);
2769
2770 return bp->tx_ring_size - (used & bp->tx_ring_mask);
2771}
2772
2773static inline void bnxt_writeq(struct bnxt *bp, u64 val,
2774 volatile void __iomem *addr)
2775{
2776#if BITS_PER_LONG == 32
2777 spin_lock(&bp->db_lock);
2778 lo_hi_writeq(val, addr);
2779 spin_unlock(&bp->db_lock);
2780#else
2781 writeq(val, addr);
2782#endif
2783}
2784
2785static inline void bnxt_writeq_relaxed(struct bnxt *bp, u64 val,
2786 volatile void __iomem *addr)
2787{
2788#if BITS_PER_LONG == 32
2789 spin_lock(&bp->db_lock);
2790 lo_hi_writeq_relaxed(val, addr);
2791 spin_unlock(&bp->db_lock);
2792#else
2793 writeq_relaxed(val, addr);
2794#endif
2795}
2796
2797/* For TX and RX ring doorbells with no ordering guarantee*/
2798static inline void bnxt_db_write_relaxed(struct bnxt *bp,
2799 struct bnxt_db_info *db, u32 idx)
2800{
2801 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
2802 bnxt_writeq_relaxed(bp, db->db_key64 | DB_RING_IDX(db, idx),
2803 db->doorbell);
2804 } else {
2805 u32 db_val = db->db_key32 | DB_RING_IDX(db, idx);
2806
2807 writel_relaxed(db_val, db->doorbell);
2808 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2809 writel_relaxed(db_val, db->doorbell);
2810 }
2811}
2812
2813/* For TX and RX ring doorbells */
2814static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
2815 u32 idx)
2816{
2817 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
2818 bnxt_writeq(bp, db->db_key64 | DB_RING_IDX(db, idx),
2819 db->doorbell);
2820 } else {
2821 u32 db_val = db->db_key32 | DB_RING_IDX(db, idx);
2822
2823 writel(db_val, db->doorbell);
2824 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2825 writel(db_val, db->doorbell);
2826 }
2827}
2828
2829/* Must hold rtnl_lock */
2830static inline bool bnxt_sriov_cfg(struct bnxt *bp)
2831{
2832#if defined(CONFIG_BNXT_SRIOV)
2833 return BNXT_PF(bp) && (bp->pf.active_vfs || bp->sriov_cfg);
2834#else
2835 return false;
2836#endif
2837}
2838
2839extern const u16 bnxt_bstore_to_trace[];
2840extern const u16 bnxt_lhint_arr[];
2841
2842int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
2843 u16 prod, gfp_t gfp);
2844void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
2845u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);
2846bool bnxt_bs_trace_avail(struct bnxt *bp, u16 type);
2847void bnxt_set_tpa_flags(struct bnxt *bp);
2848void bnxt_set_ring_params(struct bnxt *);
2849void bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
2850void bnxt_insert_usr_fltr(struct bnxt *bp, struct bnxt_filter_base *fltr);
2851void bnxt_del_one_usr_fltr(struct bnxt *bp, struct bnxt_filter_base *fltr);
2852int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap,
2853 int bmap_size, bool async_only);
2854int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp);
2855void bnxt_del_l2_filter(struct bnxt *bp, struct bnxt_l2_filter *fltr);
2856struct bnxt_l2_filter *bnxt_alloc_new_l2_filter(struct bnxt *bp,
2857 struct bnxt_l2_key *key,
2858 u16 flags);
2859int bnxt_hwrm_l2_filter_free(struct bnxt *bp, struct bnxt_l2_filter *fltr);
2860int bnxt_hwrm_l2_filter_alloc(struct bnxt *bp, struct bnxt_l2_filter *fltr);
2861int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
2862 struct bnxt_ntuple_filter *fltr);
2863int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
2864 struct bnxt_ntuple_filter *fltr);
2865int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2866 u32 tpa_flags);
2867void bnxt_fill_ipv6_mask(__be32 mask[4]);
2868void bnxt_set_dflt_rss_indir_tbl(struct bnxt *bp,
2869 struct ethtool_rxfh_context *rss_ctx);
2870int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings);
2871int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic);
2872int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2873 unsigned int start_rx_ring_idx,
2874 unsigned int nr_rings);
2875int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
2876int bnxt_nq_rings_in_use(struct bnxt *bp);
2877int bnxt_hwrm_set_coal(struct bnxt *);
2878size_t bnxt_copy_ctx_mem(struct bnxt *bp, struct bnxt_ctx_mem_type *ctxm,
2879 void *buf, size_t offset);
2880void bnxt_free_ctx_mem(struct bnxt *bp, bool force);
2881int bnxt_num_tx_to_cp(struct bnxt *bp, int tx);
2882unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
2883unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
2884unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
2885unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
2886int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
2887void bnxt_tx_disable(struct bnxt *bp);
2888void bnxt_tx_enable(struct bnxt *bp);
2889void bnxt_sched_reset_txr(struct bnxt *bp, struct bnxt_tx_ring_info *txr,
2890 u16 curr);
2891void bnxt_report_link(struct bnxt *bp);
2892int bnxt_update_link(struct bnxt *bp, bool chng_link_state);
2893int bnxt_hwrm_set_pause(struct bnxt *);
2894int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
2895int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset);
2896int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
2897int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
2898int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
2899int bnxt_hwrm_func_qcaps(struct bnxt *bp);
2900int bnxt_hwrm_fw_set_time(struct bnxt *);
2901int bnxt_hwrm_vnic_update(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2902 u8 valid);
2903int bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic);
2904int __bnxt_setup_vnic_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic);
2905void bnxt_del_one_rss_ctx(struct bnxt *bp, struct bnxt_rss_ctx *rss_ctx,
2906 bool all);
2907int bnxt_open_nic(struct bnxt *, bool, bool);
2908int bnxt_half_open_nic(struct bnxt *bp);
2909void bnxt_half_close_nic(struct bnxt *bp);
2910void bnxt_reenable_sriov(struct bnxt *bp);
2911void bnxt_close_nic(struct bnxt *, bool, bool);
2912void bnxt_get_ring_err_stats(struct bnxt *bp,
2913 struct bnxt_total_ring_err_stats *stats);
2914bool bnxt_rfs_capable(struct bnxt *bp, bool new_rss_ctx);
2915int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
2916 u32 *reg_buf);
2917void bnxt_fw_exception(struct bnxt *bp);
2918void bnxt_fw_reset(struct bnxt *bp);
2919int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
2920 int tx_xdp);
2921int bnxt_fw_init_one(struct bnxt *bp);
2922bool bnxt_hwrm_reset_permitted(struct bnxt *bp);
2923int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
2924struct bnxt_ntuple_filter *bnxt_lookup_ntp_filter_from_idx(struct bnxt *bp,
2925 struct bnxt_ntuple_filter *fltr, u32 idx);
2926u32 bnxt_get_ntp_filter_idx(struct bnxt *bp, struct flow_keys *fkeys,
2927 const struct sk_buff *skb);
2928int bnxt_insert_ntp_filter(struct bnxt *bp, struct bnxt_ntuple_filter *fltr,
2929 u32 idx);
2930void bnxt_del_ntp_filter(struct bnxt *bp, struct bnxt_ntuple_filter *fltr);
2931int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
2932int bnxt_restore_pf_fw_resources(struct bnxt *bp);
2933int bnxt_get_port_parent_id(struct net_device *dev,
2934 struct netdev_phys_item_id *ppid);
2935void bnxt_dim_work(struct work_struct *work);
2936int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);
2937void bnxt_print_device_info(struct bnxt *bp);
2938#endif