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1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32
33#include <linux/dma-mapping.h>
34#include <linux/pagemap.h>
35#include <linux/pci.h>
36#include <linux/seq_file.h>
37#include <linux/slab.h>
38#include <linux/swap.h>
39
40#include <drm/drm_device.h>
41#include <drm/drm_file.h>
42#include <drm/drm_prime.h>
43#include <drm/radeon_drm.h>
44#include <drm/ttm/ttm_bo.h>
45#include <drm/ttm/ttm_placement.h>
46#include <drm/ttm/ttm_range_manager.h>
47#include <drm/ttm/ttm_tt.h>
48
49#include "radeon_reg.h"
50#include "radeon.h"
51#include "radeon_ttm.h"
52
53static void radeon_ttm_debugfs_init(struct radeon_device *rdev);
54
55static int radeon_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
56 struct ttm_resource *bo_mem);
57static void radeon_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm);
58
59struct radeon_device *radeon_get_rdev(struct ttm_device *bdev)
60{
61 struct radeon_mman *mman;
62 struct radeon_device *rdev;
63
64 mman = container_of(bdev, struct radeon_mman, bdev);
65 rdev = container_of(mman, struct radeon_device, mman);
66 return rdev;
67}
68
69static int radeon_ttm_init_vram(struct radeon_device *rdev)
70{
71 return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_VRAM,
72 false, rdev->mc.real_vram_size >> PAGE_SHIFT);
73}
74
75static int radeon_ttm_init_gtt(struct radeon_device *rdev)
76{
77 return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_TT,
78 true, rdev->mc.gtt_size >> PAGE_SHIFT);
79}
80
81static void radeon_evict_flags(struct ttm_buffer_object *bo,
82 struct ttm_placement *placement)
83{
84 static const struct ttm_place placements = {
85 .fpfn = 0,
86 .lpfn = 0,
87 .mem_type = TTM_PL_SYSTEM,
88 .flags = 0
89 };
90
91 struct radeon_bo *rbo;
92
93 if (!radeon_ttm_bo_is_radeon_bo(bo)) {
94 placement->placement = &placements;
95 placement->busy_placement = &placements;
96 placement->num_placement = 1;
97 placement->num_busy_placement = 1;
98 return;
99 }
100 rbo = container_of(bo, struct radeon_bo, tbo);
101 switch (bo->resource->mem_type) {
102 case TTM_PL_VRAM:
103 if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
104 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
105 else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size &&
106 bo->resource->start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) {
107 unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
108 int i;
109
110 /* Try evicting to the CPU inaccessible part of VRAM
111 * first, but only set GTT as busy placement, so this
112 * BO will be evicted to GTT rather than causing other
113 * BOs to be evicted from VRAM
114 */
115 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM |
116 RADEON_GEM_DOMAIN_GTT);
117 rbo->placement.num_busy_placement = 0;
118 for (i = 0; i < rbo->placement.num_placement; i++) {
119 if (rbo->placements[i].mem_type == TTM_PL_VRAM) {
120 if (rbo->placements[i].fpfn < fpfn)
121 rbo->placements[i].fpfn = fpfn;
122 } else {
123 rbo->placement.busy_placement =
124 &rbo->placements[i];
125 rbo->placement.num_busy_placement = 1;
126 }
127 }
128 } else
129 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
130 break;
131 case TTM_PL_TT:
132 default:
133 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
134 }
135 *placement = rbo->placement;
136}
137
138static int radeon_move_blit(struct ttm_buffer_object *bo,
139 bool evict,
140 struct ttm_resource *new_mem,
141 struct ttm_resource *old_mem)
142{
143 struct radeon_device *rdev;
144 uint64_t old_start, new_start;
145 struct radeon_fence *fence;
146 unsigned num_pages;
147 int r, ridx;
148
149 rdev = radeon_get_rdev(bo->bdev);
150 ridx = radeon_copy_ring_index(rdev);
151 old_start = (u64)old_mem->start << PAGE_SHIFT;
152 new_start = (u64)new_mem->start << PAGE_SHIFT;
153
154 switch (old_mem->mem_type) {
155 case TTM_PL_VRAM:
156 old_start += rdev->mc.vram_start;
157 break;
158 case TTM_PL_TT:
159 old_start += rdev->mc.gtt_start;
160 break;
161 default:
162 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
163 return -EINVAL;
164 }
165 switch (new_mem->mem_type) {
166 case TTM_PL_VRAM:
167 new_start += rdev->mc.vram_start;
168 break;
169 case TTM_PL_TT:
170 new_start += rdev->mc.gtt_start;
171 break;
172 default:
173 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
174 return -EINVAL;
175 }
176 if (!rdev->ring[ridx].ready) {
177 DRM_ERROR("Trying to move memory with ring turned off.\n");
178 return -EINVAL;
179 }
180
181 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
182
183 num_pages = PFN_UP(new_mem->size) * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
184 fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->base.resv);
185 if (IS_ERR(fence))
186 return PTR_ERR(fence);
187
188 r = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, false, new_mem);
189 radeon_fence_unref(&fence);
190 return r;
191}
192
193static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict,
194 struct ttm_operation_ctx *ctx,
195 struct ttm_resource *new_mem,
196 struct ttm_place *hop)
197{
198 struct ttm_resource *old_mem = bo->resource;
199 struct radeon_device *rdev;
200 int r;
201
202 if (new_mem->mem_type == TTM_PL_TT) {
203 r = radeon_ttm_tt_bind(bo->bdev, bo->ttm, new_mem);
204 if (r)
205 return r;
206 }
207
208 r = ttm_bo_wait_ctx(bo, ctx);
209 if (r)
210 return r;
211
212 rdev = radeon_get_rdev(bo->bdev);
213 if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM &&
214 bo->ttm == NULL)) {
215 ttm_bo_move_null(bo, new_mem);
216 goto out;
217 }
218 if (old_mem->mem_type == TTM_PL_SYSTEM &&
219 new_mem->mem_type == TTM_PL_TT) {
220 ttm_bo_move_null(bo, new_mem);
221 goto out;
222 }
223
224 if (old_mem->mem_type == TTM_PL_TT &&
225 new_mem->mem_type == TTM_PL_SYSTEM) {
226 radeon_ttm_tt_unbind(bo->bdev, bo->ttm);
227 ttm_resource_free(bo, &bo->resource);
228 ttm_bo_assign_mem(bo, new_mem);
229 goto out;
230 }
231 if (rdev->ring[radeon_copy_ring_index(rdev)].ready &&
232 rdev->asic->copy.copy != NULL) {
233 if ((old_mem->mem_type == TTM_PL_SYSTEM &&
234 new_mem->mem_type == TTM_PL_VRAM) ||
235 (old_mem->mem_type == TTM_PL_VRAM &&
236 new_mem->mem_type == TTM_PL_SYSTEM)) {
237 hop->fpfn = 0;
238 hop->lpfn = 0;
239 hop->mem_type = TTM_PL_TT;
240 hop->flags = 0;
241 return -EMULTIHOP;
242 }
243
244 r = radeon_move_blit(bo, evict, new_mem, old_mem);
245 } else {
246 r = -ENODEV;
247 }
248
249 if (r) {
250 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
251 if (r)
252 return r;
253 }
254
255out:
256 /* update statistics */
257 atomic64_add(bo->base.size, &rdev->num_bytes_moved);
258 radeon_bo_move_notify(bo);
259 return 0;
260}
261
262static int radeon_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *mem)
263{
264 struct radeon_device *rdev = radeon_get_rdev(bdev);
265 size_t bus_size = (size_t)mem->size;
266
267 switch (mem->mem_type) {
268 case TTM_PL_SYSTEM:
269 /* system memory */
270 return 0;
271 case TTM_PL_TT:
272#if IS_ENABLED(CONFIG_AGP)
273 if (rdev->flags & RADEON_IS_AGP) {
274 /* RADEON_IS_AGP is set only if AGP is active */
275 mem->bus.offset = (mem->start << PAGE_SHIFT) +
276 rdev->mc.agp_base;
277 mem->bus.is_iomem = !rdev->agp->cant_use_aperture;
278 mem->bus.caching = ttm_write_combined;
279 }
280#endif
281 break;
282 case TTM_PL_VRAM:
283 mem->bus.offset = mem->start << PAGE_SHIFT;
284 /* check if it's visible */
285 if ((mem->bus.offset + bus_size) > rdev->mc.visible_vram_size)
286 return -EINVAL;
287 mem->bus.offset += rdev->mc.aper_base;
288 mem->bus.is_iomem = true;
289 mem->bus.caching = ttm_write_combined;
290#ifdef __alpha__
291 /*
292 * Alpha: use bus.addr to hold the ioremap() return,
293 * so we can modify bus.base below.
294 */
295 mem->bus.addr = ioremap_wc(mem->bus.offset, bus_size);
296 if (!mem->bus.addr)
297 return -ENOMEM;
298
299 /*
300 * Alpha: Use just the bus offset plus
301 * the hose/domain memory base for bus.base.
302 * It then can be used to build PTEs for VRAM
303 * access, as done in ttm_bo_vm_fault().
304 */
305 mem->bus.offset = (mem->bus.offset & 0x0ffffffffUL) +
306 rdev->hose->dense_mem_base;
307#endif
308 break;
309 default:
310 return -EINVAL;
311 }
312 return 0;
313}
314
315/*
316 * TTM backend functions.
317 */
318struct radeon_ttm_tt {
319 struct ttm_tt ttm;
320 u64 offset;
321
322 uint64_t userptr;
323 struct mm_struct *usermm;
324 uint32_t userflags;
325 bool bound;
326};
327
328/* prepare the sg table with the user pages */
329static int radeon_ttm_tt_pin_userptr(struct ttm_device *bdev, struct ttm_tt *ttm)
330{
331 struct radeon_device *rdev = radeon_get_rdev(bdev);
332 struct radeon_ttm_tt *gtt = (void *)ttm;
333 unsigned pinned = 0;
334 int r;
335
336 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
337 enum dma_data_direction direction = write ?
338 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
339
340 if (current->mm != gtt->usermm)
341 return -EPERM;
342
343 if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
344 /* check that we only pin down anonymous memory
345 to prevent problems with writeback */
346 unsigned long end = gtt->userptr + (u64)ttm->num_pages * PAGE_SIZE;
347 struct vm_area_struct *vma;
348 vma = find_vma(gtt->usermm, gtt->userptr);
349 if (!vma || vma->vm_file || vma->vm_end < end)
350 return -EPERM;
351 }
352
353 do {
354 unsigned num_pages = ttm->num_pages - pinned;
355 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
356 struct page **pages = ttm->pages + pinned;
357
358 r = get_user_pages(userptr, num_pages, write ? FOLL_WRITE : 0,
359 pages);
360 if (r < 0)
361 goto release_pages;
362
363 pinned += r;
364
365 } while (pinned < ttm->num_pages);
366
367 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
368 (u64)ttm->num_pages << PAGE_SHIFT,
369 GFP_KERNEL);
370 if (r)
371 goto release_sg;
372
373 r = dma_map_sgtable(rdev->dev, ttm->sg, direction, 0);
374 if (r)
375 goto release_sg;
376
377 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
378 ttm->num_pages);
379
380 return 0;
381
382release_sg:
383 kfree(ttm->sg);
384
385release_pages:
386 release_pages(ttm->pages, pinned);
387 return r;
388}
389
390static void radeon_ttm_tt_unpin_userptr(struct ttm_device *bdev, struct ttm_tt *ttm)
391{
392 struct radeon_device *rdev = radeon_get_rdev(bdev);
393 struct radeon_ttm_tt *gtt = (void *)ttm;
394 struct sg_page_iter sg_iter;
395
396 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
397 enum dma_data_direction direction = write ?
398 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
399
400 /* double check that we don't free the table twice */
401 if (!ttm->sg || !ttm->sg->sgl)
402 return;
403
404 /* free the sg table and pages again */
405 dma_unmap_sgtable(rdev->dev, ttm->sg, direction, 0);
406
407 for_each_sgtable_page(ttm->sg, &sg_iter, 0) {
408 struct page *page = sg_page_iter_page(&sg_iter);
409 if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY))
410 set_page_dirty(page);
411
412 mark_page_accessed(page);
413 put_page(page);
414 }
415
416 sg_free_table(ttm->sg);
417}
418
419static bool radeon_ttm_backend_is_bound(struct ttm_tt *ttm)
420{
421 struct radeon_ttm_tt *gtt = (void*)ttm;
422
423 return (gtt->bound);
424}
425
426static int radeon_ttm_backend_bind(struct ttm_device *bdev,
427 struct ttm_tt *ttm,
428 struct ttm_resource *bo_mem)
429{
430 struct radeon_ttm_tt *gtt = (void*)ttm;
431 struct radeon_device *rdev = radeon_get_rdev(bdev);
432 uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ |
433 RADEON_GART_PAGE_WRITE;
434 int r;
435
436 if (gtt->bound)
437 return 0;
438
439 if (gtt->userptr) {
440 radeon_ttm_tt_pin_userptr(bdev, ttm);
441 flags &= ~RADEON_GART_PAGE_WRITE;
442 }
443
444 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
445 if (!ttm->num_pages) {
446 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
447 ttm->num_pages, bo_mem, ttm);
448 }
449 if (ttm->caching == ttm_cached)
450 flags |= RADEON_GART_PAGE_SNOOP;
451 r = radeon_gart_bind(rdev, gtt->offset, ttm->num_pages,
452 ttm->pages, gtt->ttm.dma_address, flags);
453 if (r) {
454 DRM_ERROR("failed to bind %u pages at 0x%08X\n",
455 ttm->num_pages, (unsigned)gtt->offset);
456 return r;
457 }
458 gtt->bound = true;
459 return 0;
460}
461
462static void radeon_ttm_backend_unbind(struct ttm_device *bdev, struct ttm_tt *ttm)
463{
464 struct radeon_ttm_tt *gtt = (void *)ttm;
465 struct radeon_device *rdev = radeon_get_rdev(bdev);
466
467 if (gtt->userptr)
468 radeon_ttm_tt_unpin_userptr(bdev, ttm);
469
470 if (!gtt->bound)
471 return;
472
473 radeon_gart_unbind(rdev, gtt->offset, ttm->num_pages);
474
475 gtt->bound = false;
476}
477
478static void radeon_ttm_backend_destroy(struct ttm_device *bdev, struct ttm_tt *ttm)
479{
480 struct radeon_ttm_tt *gtt = (void *)ttm;
481
482 ttm_tt_fini(>t->ttm);
483 kfree(gtt);
484}
485
486static struct ttm_tt *radeon_ttm_tt_create(struct ttm_buffer_object *bo,
487 uint32_t page_flags)
488{
489 struct radeon_ttm_tt *gtt;
490 enum ttm_caching caching;
491 struct radeon_bo *rbo;
492#if IS_ENABLED(CONFIG_AGP)
493 struct radeon_device *rdev = radeon_get_rdev(bo->bdev);
494
495 if (rdev->flags & RADEON_IS_AGP) {
496 return ttm_agp_tt_create(bo, rdev->agp->bridge, page_flags);
497 }
498#endif
499 rbo = container_of(bo, struct radeon_bo, tbo);
500
501 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
502 if (gtt == NULL) {
503 return NULL;
504 }
505
506 if (rbo->flags & RADEON_GEM_GTT_UC)
507 caching = ttm_uncached;
508 else if (rbo->flags & RADEON_GEM_GTT_WC)
509 caching = ttm_write_combined;
510 else
511 caching = ttm_cached;
512
513 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) {
514 kfree(gtt);
515 return NULL;
516 }
517 return >t->ttm;
518}
519
520static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct radeon_device *rdev,
521 struct ttm_tt *ttm)
522{
523#if IS_ENABLED(CONFIG_AGP)
524 if (rdev->flags & RADEON_IS_AGP)
525 return NULL;
526#endif
527
528 if (!ttm)
529 return NULL;
530 return container_of(ttm, struct radeon_ttm_tt, ttm);
531}
532
533static int radeon_ttm_tt_populate(struct ttm_device *bdev,
534 struct ttm_tt *ttm,
535 struct ttm_operation_ctx *ctx)
536{
537 struct radeon_device *rdev = radeon_get_rdev(bdev);
538 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
539 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
540
541 if (gtt && gtt->userptr) {
542 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
543 if (!ttm->sg)
544 return -ENOMEM;
545
546 ttm->page_flags |= TTM_TT_FLAG_EXTERNAL;
547 return 0;
548 }
549
550 if (slave && ttm->sg) {
551 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
552 ttm->num_pages);
553 return 0;
554 }
555
556 return ttm_pool_alloc(&rdev->mman.bdev.pool, ttm, ctx);
557}
558
559static void radeon_ttm_tt_unpopulate(struct ttm_device *bdev, struct ttm_tt *ttm)
560{
561 struct radeon_device *rdev = radeon_get_rdev(bdev);
562 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
563 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
564
565 radeon_ttm_tt_unbind(bdev, ttm);
566
567 if (gtt && gtt->userptr) {
568 kfree(ttm->sg);
569 ttm->page_flags &= ~TTM_TT_FLAG_EXTERNAL;
570 return;
571 }
572
573 if (slave)
574 return;
575
576 return ttm_pool_free(&rdev->mman.bdev.pool, ttm);
577}
578
579int radeon_ttm_tt_set_userptr(struct radeon_device *rdev,
580 struct ttm_tt *ttm, uint64_t addr,
581 uint32_t flags)
582{
583 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
584
585 if (gtt == NULL)
586 return -EINVAL;
587
588 gtt->userptr = addr;
589 gtt->usermm = current->mm;
590 gtt->userflags = flags;
591 return 0;
592}
593
594bool radeon_ttm_tt_is_bound(struct ttm_device *bdev,
595 struct ttm_tt *ttm)
596{
597#if IS_ENABLED(CONFIG_AGP)
598 struct radeon_device *rdev = radeon_get_rdev(bdev);
599 if (rdev->flags & RADEON_IS_AGP)
600 return ttm_agp_is_bound(ttm);
601#endif
602 return radeon_ttm_backend_is_bound(ttm);
603}
604
605static int radeon_ttm_tt_bind(struct ttm_device *bdev,
606 struct ttm_tt *ttm,
607 struct ttm_resource *bo_mem)
608{
609#if IS_ENABLED(CONFIG_AGP)
610 struct radeon_device *rdev = radeon_get_rdev(bdev);
611#endif
612
613 if (!bo_mem)
614 return -EINVAL;
615#if IS_ENABLED(CONFIG_AGP)
616 if (rdev->flags & RADEON_IS_AGP)
617 return ttm_agp_bind(ttm, bo_mem);
618#endif
619
620 return radeon_ttm_backend_bind(bdev, ttm, bo_mem);
621}
622
623static void radeon_ttm_tt_unbind(struct ttm_device *bdev,
624 struct ttm_tt *ttm)
625{
626#if IS_ENABLED(CONFIG_AGP)
627 struct radeon_device *rdev = radeon_get_rdev(bdev);
628
629 if (rdev->flags & RADEON_IS_AGP) {
630 ttm_agp_unbind(ttm);
631 return;
632 }
633#endif
634 radeon_ttm_backend_unbind(bdev, ttm);
635}
636
637static void radeon_ttm_tt_destroy(struct ttm_device *bdev,
638 struct ttm_tt *ttm)
639{
640#if IS_ENABLED(CONFIG_AGP)
641 struct radeon_device *rdev = radeon_get_rdev(bdev);
642
643 if (rdev->flags & RADEON_IS_AGP) {
644 ttm_agp_destroy(ttm);
645 return;
646 }
647#endif
648 radeon_ttm_backend_destroy(bdev, ttm);
649}
650
651bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev,
652 struct ttm_tt *ttm)
653{
654 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
655
656 if (gtt == NULL)
657 return false;
658
659 return !!gtt->userptr;
660}
661
662bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev,
663 struct ttm_tt *ttm)
664{
665 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
666
667 if (gtt == NULL)
668 return false;
669
670 return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
671}
672
673static struct ttm_device_funcs radeon_bo_driver = {
674 .ttm_tt_create = &radeon_ttm_tt_create,
675 .ttm_tt_populate = &radeon_ttm_tt_populate,
676 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
677 .ttm_tt_destroy = &radeon_ttm_tt_destroy,
678 .eviction_valuable = ttm_bo_eviction_valuable,
679 .evict_flags = &radeon_evict_flags,
680 .move = &radeon_bo_move,
681 .io_mem_reserve = &radeon_ttm_io_mem_reserve,
682};
683
684int radeon_ttm_init(struct radeon_device *rdev)
685{
686 int r;
687
688 /* No others user of address space so set it to 0 */
689 r = ttm_device_init(&rdev->mman.bdev, &radeon_bo_driver, rdev->dev,
690 rdev->ddev->anon_inode->i_mapping,
691 rdev->ddev->vma_offset_manager,
692 rdev->need_swiotlb,
693 dma_addressing_limited(&rdev->pdev->dev));
694 if (r) {
695 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
696 return r;
697 }
698 rdev->mman.initialized = true;
699
700 r = radeon_ttm_init_vram(rdev);
701 if (r) {
702 DRM_ERROR("Failed initializing VRAM heap.\n");
703 return r;
704 }
705 /* Change the size here instead of the init above so only lpfn is affected */
706 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
707
708 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
709 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
710 NULL, &rdev->stolen_vga_memory);
711 if (r) {
712 return r;
713 }
714 r = radeon_bo_reserve(rdev->stolen_vga_memory, false);
715 if (r)
716 return r;
717 r = radeon_bo_pin(rdev->stolen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
718 radeon_bo_unreserve(rdev->stolen_vga_memory);
719 if (r) {
720 radeon_bo_unref(&rdev->stolen_vga_memory);
721 return r;
722 }
723 DRM_INFO("radeon: %uM of VRAM memory ready\n",
724 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
725
726 r = radeon_ttm_init_gtt(rdev);
727 if (r) {
728 DRM_ERROR("Failed initializing GTT heap.\n");
729 return r;
730 }
731 DRM_INFO("radeon: %uM of GTT memory ready.\n",
732 (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
733
734 radeon_ttm_debugfs_init(rdev);
735
736 return 0;
737}
738
739void radeon_ttm_fini(struct radeon_device *rdev)
740{
741 int r;
742
743 if (!rdev->mman.initialized)
744 return;
745
746 if (rdev->stolen_vga_memory) {
747 r = radeon_bo_reserve(rdev->stolen_vga_memory, false);
748 if (r == 0) {
749 radeon_bo_unpin(rdev->stolen_vga_memory);
750 radeon_bo_unreserve(rdev->stolen_vga_memory);
751 }
752 radeon_bo_unref(&rdev->stolen_vga_memory);
753 }
754 ttm_range_man_fini(&rdev->mman.bdev, TTM_PL_VRAM);
755 ttm_range_man_fini(&rdev->mman.bdev, TTM_PL_TT);
756 ttm_device_fini(&rdev->mman.bdev);
757 radeon_gart_fini(rdev);
758 rdev->mman.initialized = false;
759 DRM_INFO("radeon: ttm finalized\n");
760}
761
762/* this should only be called at bootup or when userspace
763 * isn't running */
764void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
765{
766 struct ttm_resource_manager *man;
767
768 if (!rdev->mman.initialized)
769 return;
770
771 man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM);
772 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
773 man->size = size >> PAGE_SHIFT;
774}
775
776#if defined(CONFIG_DEBUG_FS)
777
778static int radeon_ttm_page_pool_show(struct seq_file *m, void *data)
779{
780 struct radeon_device *rdev = m->private;
781
782 return ttm_pool_debugfs(&rdev->mman.bdev.pool, m);
783}
784
785DEFINE_SHOW_ATTRIBUTE(radeon_ttm_page_pool);
786
787static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
788{
789 struct radeon_device *rdev = inode->i_private;
790 i_size_write(inode, rdev->mc.mc_vram_size);
791 filep->private_data = inode->i_private;
792 return 0;
793}
794
795static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
796 size_t size, loff_t *pos)
797{
798 struct radeon_device *rdev = f->private_data;
799 ssize_t result = 0;
800 int r;
801
802 if (size & 0x3 || *pos & 0x3)
803 return -EINVAL;
804
805 while (size) {
806 unsigned long flags;
807 uint32_t value;
808
809 if (*pos >= rdev->mc.mc_vram_size)
810 return result;
811
812 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
813 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
814 if (rdev->family >= CHIP_CEDAR)
815 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
816 value = RREG32(RADEON_MM_DATA);
817 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
818
819 r = put_user(value, (uint32_t __user *)buf);
820 if (r)
821 return r;
822
823 result += 4;
824 buf += 4;
825 *pos += 4;
826 size -= 4;
827 }
828
829 return result;
830}
831
832static const struct file_operations radeon_ttm_vram_fops = {
833 .owner = THIS_MODULE,
834 .open = radeon_ttm_vram_open,
835 .read = radeon_ttm_vram_read,
836 .llseek = default_llseek
837};
838
839static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
840{
841 struct radeon_device *rdev = inode->i_private;
842 i_size_write(inode, rdev->mc.gtt_size);
843 filep->private_data = inode->i_private;
844 return 0;
845}
846
847static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
848 size_t size, loff_t *pos)
849{
850 struct radeon_device *rdev = f->private_data;
851 ssize_t result = 0;
852 int r;
853
854 while (size) {
855 loff_t p = *pos / PAGE_SIZE;
856 unsigned off = *pos & ~PAGE_MASK;
857 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
858 struct page *page;
859 void *ptr;
860
861 if (p >= rdev->gart.num_cpu_pages)
862 return result;
863
864 page = rdev->gart.pages[p];
865 if (page) {
866 ptr = kmap_local_page(page);
867 ptr += off;
868
869 r = copy_to_user(buf, ptr, cur_size);
870 kunmap_local(ptr);
871 } else
872 r = clear_user(buf, cur_size);
873
874 if (r)
875 return -EFAULT;
876
877 result += cur_size;
878 buf += cur_size;
879 *pos += cur_size;
880 size -= cur_size;
881 }
882
883 return result;
884}
885
886static const struct file_operations radeon_ttm_gtt_fops = {
887 .owner = THIS_MODULE,
888 .open = radeon_ttm_gtt_open,
889 .read = radeon_ttm_gtt_read,
890 .llseek = default_llseek
891};
892
893#endif
894
895static void radeon_ttm_debugfs_init(struct radeon_device *rdev)
896{
897#if defined(CONFIG_DEBUG_FS)
898 struct drm_minor *minor = rdev->ddev->primary;
899 struct dentry *root = minor->debugfs_root;
900
901 debugfs_create_file("radeon_vram", 0444, root, rdev,
902 &radeon_ttm_vram_fops);
903 debugfs_create_file("radeon_gtt", 0444, root, rdev,
904 &radeon_ttm_gtt_fops);
905 debugfs_create_file("ttm_page_pool", 0444, root, rdev,
906 &radeon_ttm_page_pool_fops);
907 ttm_resource_manager_create_debugfs(ttm_manager_type(&rdev->mman.bdev,
908 TTM_PL_VRAM),
909 root, "radeon_vram_mm");
910 ttm_resource_manager_create_debugfs(ttm_manager_type(&rdev->mman.bdev,
911 TTM_PL_TT),
912 root, "radeon_gtt_mm");
913#endif
914}
1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32
33#include <linux/debugfs.h>
34#include <linux/dma-mapping.h>
35#include <linux/pagemap.h>
36#include <linux/pci.h>
37#include <linux/seq_file.h>
38#include <linux/slab.h>
39#include <linux/swap.h>
40
41#include <drm/drm_device.h>
42#include <drm/drm_file.h>
43#include <drm/drm_prime.h>
44#include <drm/radeon_drm.h>
45#include <drm/ttm/ttm_bo.h>
46#include <drm/ttm/ttm_placement.h>
47#include <drm/ttm/ttm_range_manager.h>
48#include <drm/ttm/ttm_tt.h>
49
50#include "radeon_reg.h"
51#include "radeon.h"
52#include "radeon_ttm.h"
53
54static void radeon_ttm_debugfs_init(struct radeon_device *rdev);
55
56static int radeon_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
57 struct ttm_resource *bo_mem);
58static void radeon_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm);
59
60struct radeon_device *radeon_get_rdev(struct ttm_device *bdev)
61{
62 struct radeon_mman *mman;
63 struct radeon_device *rdev;
64
65 mman = container_of(bdev, struct radeon_mman, bdev);
66 rdev = container_of(mman, struct radeon_device, mman);
67 return rdev;
68}
69
70static int radeon_ttm_init_vram(struct radeon_device *rdev)
71{
72 return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_VRAM,
73 false, rdev->mc.real_vram_size >> PAGE_SHIFT);
74}
75
76static int radeon_ttm_init_gtt(struct radeon_device *rdev)
77{
78 return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_TT,
79 true, rdev->mc.gtt_size >> PAGE_SHIFT);
80}
81
82static void radeon_evict_flags(struct ttm_buffer_object *bo,
83 struct ttm_placement *placement)
84{
85 static const struct ttm_place placements = {
86 .fpfn = 0,
87 .lpfn = 0,
88 .mem_type = TTM_PL_SYSTEM,
89 .flags = 0
90 };
91
92 struct radeon_bo *rbo;
93
94 if (!radeon_ttm_bo_is_radeon_bo(bo)) {
95 placement->placement = &placements;
96 placement->num_placement = 1;
97 return;
98 }
99 rbo = container_of(bo, struct radeon_bo, tbo);
100 switch (bo->resource->mem_type) {
101 case TTM_PL_VRAM:
102 if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
103 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
104 else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size &&
105 bo->resource->start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) {
106 unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
107 int i;
108
109 /* Try evicting to the CPU inaccessible part of VRAM
110 * first, but only set GTT as busy placement, so this
111 * BO will be evicted to GTT rather than causing other
112 * BOs to be evicted from VRAM
113 */
114 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM |
115 RADEON_GEM_DOMAIN_GTT);
116 for (i = 0; i < rbo->placement.num_placement; i++) {
117 if (rbo->placements[i].mem_type == TTM_PL_VRAM) {
118 if (rbo->placements[i].fpfn < fpfn)
119 rbo->placements[i].fpfn = fpfn;
120 rbo->placements[0].flags |= TTM_PL_FLAG_DESIRED;
121 }
122 }
123 } else
124 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
125 break;
126 case TTM_PL_TT:
127 default:
128 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
129 }
130 *placement = rbo->placement;
131}
132
133static int radeon_move_blit(struct ttm_buffer_object *bo,
134 bool evict,
135 struct ttm_resource *new_mem,
136 struct ttm_resource *old_mem)
137{
138 struct radeon_device *rdev;
139 uint64_t old_start, new_start;
140 struct radeon_fence *fence;
141 unsigned num_pages;
142 int r, ridx;
143
144 rdev = radeon_get_rdev(bo->bdev);
145 ridx = radeon_copy_ring_index(rdev);
146 old_start = (u64)old_mem->start << PAGE_SHIFT;
147 new_start = (u64)new_mem->start << PAGE_SHIFT;
148
149 switch (old_mem->mem_type) {
150 case TTM_PL_VRAM:
151 old_start += rdev->mc.vram_start;
152 break;
153 case TTM_PL_TT:
154 old_start += rdev->mc.gtt_start;
155 break;
156 default:
157 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
158 return -EINVAL;
159 }
160 switch (new_mem->mem_type) {
161 case TTM_PL_VRAM:
162 new_start += rdev->mc.vram_start;
163 break;
164 case TTM_PL_TT:
165 new_start += rdev->mc.gtt_start;
166 break;
167 default:
168 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
169 return -EINVAL;
170 }
171 if (!rdev->ring[ridx].ready) {
172 DRM_ERROR("Trying to move memory with ring turned off.\n");
173 return -EINVAL;
174 }
175
176 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
177
178 num_pages = PFN_UP(new_mem->size) * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
179 fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->base.resv);
180 if (IS_ERR(fence))
181 return PTR_ERR(fence);
182
183 r = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, false, new_mem);
184 radeon_fence_unref(&fence);
185 return r;
186}
187
188static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict,
189 struct ttm_operation_ctx *ctx,
190 struct ttm_resource *new_mem,
191 struct ttm_place *hop)
192{
193 struct ttm_resource *old_mem = bo->resource;
194 struct radeon_device *rdev;
195 int r;
196
197 if (new_mem->mem_type == TTM_PL_TT) {
198 r = radeon_ttm_tt_bind(bo->bdev, bo->ttm, new_mem);
199 if (r)
200 return r;
201 }
202
203 r = ttm_bo_wait_ctx(bo, ctx);
204 if (r)
205 return r;
206
207 rdev = radeon_get_rdev(bo->bdev);
208 if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM &&
209 bo->ttm == NULL)) {
210 ttm_bo_move_null(bo, new_mem);
211 goto out;
212 }
213 if (old_mem->mem_type == TTM_PL_SYSTEM &&
214 new_mem->mem_type == TTM_PL_TT) {
215 ttm_bo_move_null(bo, new_mem);
216 goto out;
217 }
218
219 if (old_mem->mem_type == TTM_PL_TT &&
220 new_mem->mem_type == TTM_PL_SYSTEM) {
221 radeon_ttm_tt_unbind(bo->bdev, bo->ttm);
222 ttm_bo_move_null(bo, new_mem);
223 goto out;
224 }
225 if (rdev->ring[radeon_copy_ring_index(rdev)].ready &&
226 rdev->asic->copy.copy != NULL) {
227 if ((old_mem->mem_type == TTM_PL_SYSTEM &&
228 new_mem->mem_type == TTM_PL_VRAM) ||
229 (old_mem->mem_type == TTM_PL_VRAM &&
230 new_mem->mem_type == TTM_PL_SYSTEM)) {
231 hop->fpfn = 0;
232 hop->lpfn = 0;
233 hop->mem_type = TTM_PL_TT;
234 hop->flags = 0;
235 return -EMULTIHOP;
236 }
237
238 r = radeon_move_blit(bo, evict, new_mem, old_mem);
239 } else {
240 r = -ENODEV;
241 }
242
243 if (r) {
244 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
245 if (r)
246 return r;
247 }
248
249out:
250 /* update statistics */
251 atomic64_add(bo->base.size, &rdev->num_bytes_moved);
252 radeon_bo_move_notify(bo);
253 return 0;
254}
255
256static int radeon_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *mem)
257{
258 struct radeon_device *rdev = radeon_get_rdev(bdev);
259 size_t bus_size = (size_t)mem->size;
260
261 switch (mem->mem_type) {
262 case TTM_PL_SYSTEM:
263 /* system memory */
264 return 0;
265 case TTM_PL_TT:
266#if IS_ENABLED(CONFIG_AGP)
267 if (rdev->flags & RADEON_IS_AGP) {
268 /* RADEON_IS_AGP is set only if AGP is active */
269 mem->bus.offset = (mem->start << PAGE_SHIFT) +
270 rdev->mc.agp_base;
271 mem->bus.is_iomem = !rdev->agp->cant_use_aperture;
272 mem->bus.caching = ttm_write_combined;
273 }
274#endif
275 break;
276 case TTM_PL_VRAM:
277 mem->bus.offset = mem->start << PAGE_SHIFT;
278 /* check if it's visible */
279 if ((mem->bus.offset + bus_size) > rdev->mc.visible_vram_size)
280 return -EINVAL;
281 mem->bus.offset += rdev->mc.aper_base;
282 mem->bus.is_iomem = true;
283 mem->bus.caching = ttm_write_combined;
284#ifdef __alpha__
285 /*
286 * Alpha: use bus.addr to hold the ioremap() return,
287 * so we can modify bus.base below.
288 */
289 mem->bus.addr = ioremap_wc(mem->bus.offset, bus_size);
290 if (!mem->bus.addr)
291 return -ENOMEM;
292
293 /*
294 * Alpha: Use just the bus offset plus
295 * the hose/domain memory base for bus.base.
296 * It then can be used to build PTEs for VRAM
297 * access, as done in ttm_bo_vm_fault().
298 */
299 mem->bus.offset = (mem->bus.offset & 0x0ffffffffUL) +
300 rdev->hose->dense_mem_base;
301#endif
302 break;
303 default:
304 return -EINVAL;
305 }
306 return 0;
307}
308
309/*
310 * TTM backend functions.
311 */
312struct radeon_ttm_tt {
313 struct ttm_tt ttm;
314 u64 offset;
315
316 uint64_t userptr;
317 struct mm_struct *usermm;
318 uint32_t userflags;
319 bool bound;
320};
321
322/* prepare the sg table with the user pages */
323static int radeon_ttm_tt_pin_userptr(struct ttm_device *bdev, struct ttm_tt *ttm)
324{
325 struct radeon_device *rdev = radeon_get_rdev(bdev);
326 struct radeon_ttm_tt *gtt = (void *)ttm;
327 unsigned pinned = 0;
328 int r;
329
330 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
331 enum dma_data_direction direction = write ?
332 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
333
334 if (current->mm != gtt->usermm)
335 return -EPERM;
336
337 if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
338 /* check that we only pin down anonymous memory
339 to prevent problems with writeback */
340 unsigned long end = gtt->userptr + (u64)ttm->num_pages * PAGE_SIZE;
341 struct vm_area_struct *vma;
342 vma = find_vma(gtt->usermm, gtt->userptr);
343 if (!vma || vma->vm_file || vma->vm_end < end)
344 return -EPERM;
345 }
346
347 do {
348 unsigned num_pages = ttm->num_pages - pinned;
349 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
350 struct page **pages = ttm->pages + pinned;
351
352 r = get_user_pages(userptr, num_pages, write ? FOLL_WRITE : 0,
353 pages);
354 if (r < 0)
355 goto release_pages;
356
357 pinned += r;
358
359 } while (pinned < ttm->num_pages);
360
361 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
362 (u64)ttm->num_pages << PAGE_SHIFT,
363 GFP_KERNEL);
364 if (r)
365 goto release_sg;
366
367 r = dma_map_sgtable(rdev->dev, ttm->sg, direction, 0);
368 if (r)
369 goto release_sg;
370
371 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
372 ttm->num_pages);
373
374 return 0;
375
376release_sg:
377 kfree(ttm->sg);
378
379release_pages:
380 release_pages(ttm->pages, pinned);
381 return r;
382}
383
384static void radeon_ttm_tt_unpin_userptr(struct ttm_device *bdev, struct ttm_tt *ttm)
385{
386 struct radeon_device *rdev = radeon_get_rdev(bdev);
387 struct radeon_ttm_tt *gtt = (void *)ttm;
388 struct sg_page_iter sg_iter;
389
390 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
391 enum dma_data_direction direction = write ?
392 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
393
394 /* double check that we don't free the table twice */
395 if (!ttm->sg || !ttm->sg->sgl)
396 return;
397
398 /* free the sg table and pages again */
399 dma_unmap_sgtable(rdev->dev, ttm->sg, direction, 0);
400
401 for_each_sgtable_page(ttm->sg, &sg_iter, 0) {
402 struct page *page = sg_page_iter_page(&sg_iter);
403 if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY))
404 set_page_dirty(page);
405
406 mark_page_accessed(page);
407 put_page(page);
408 }
409
410 sg_free_table(ttm->sg);
411}
412
413static bool radeon_ttm_backend_is_bound(struct ttm_tt *ttm)
414{
415 struct radeon_ttm_tt *gtt = (void*)ttm;
416
417 return (gtt->bound);
418}
419
420static int radeon_ttm_backend_bind(struct ttm_device *bdev,
421 struct ttm_tt *ttm,
422 struct ttm_resource *bo_mem)
423{
424 struct radeon_ttm_tt *gtt = (void*)ttm;
425 struct radeon_device *rdev = radeon_get_rdev(bdev);
426 uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ |
427 RADEON_GART_PAGE_WRITE;
428 int r;
429
430 if (gtt->bound)
431 return 0;
432
433 if (gtt->userptr) {
434 radeon_ttm_tt_pin_userptr(bdev, ttm);
435 flags &= ~RADEON_GART_PAGE_WRITE;
436 }
437
438 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
439 if (!ttm->num_pages) {
440 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
441 ttm->num_pages, bo_mem, ttm);
442 }
443 if (ttm->caching == ttm_cached)
444 flags |= RADEON_GART_PAGE_SNOOP;
445 r = radeon_gart_bind(rdev, gtt->offset, ttm->num_pages,
446 ttm->pages, gtt->ttm.dma_address, flags);
447 if (r) {
448 DRM_ERROR("failed to bind %u pages at 0x%08X\n",
449 ttm->num_pages, (unsigned)gtt->offset);
450 return r;
451 }
452 gtt->bound = true;
453 return 0;
454}
455
456static void radeon_ttm_backend_unbind(struct ttm_device *bdev, struct ttm_tt *ttm)
457{
458 struct radeon_ttm_tt *gtt = (void *)ttm;
459 struct radeon_device *rdev = radeon_get_rdev(bdev);
460
461 if (gtt->userptr)
462 radeon_ttm_tt_unpin_userptr(bdev, ttm);
463
464 if (!gtt->bound)
465 return;
466
467 radeon_gart_unbind(rdev, gtt->offset, ttm->num_pages);
468
469 gtt->bound = false;
470}
471
472static void radeon_ttm_backend_destroy(struct ttm_device *bdev, struct ttm_tt *ttm)
473{
474 struct radeon_ttm_tt *gtt = (void *)ttm;
475
476 ttm_tt_fini(>t->ttm);
477 kfree(gtt);
478}
479
480static struct ttm_tt *radeon_ttm_tt_create(struct ttm_buffer_object *bo,
481 uint32_t page_flags)
482{
483 struct radeon_ttm_tt *gtt;
484 enum ttm_caching caching;
485 struct radeon_bo *rbo;
486#if IS_ENABLED(CONFIG_AGP)
487 struct radeon_device *rdev = radeon_get_rdev(bo->bdev);
488
489 if (rdev->flags & RADEON_IS_AGP) {
490 return ttm_agp_tt_create(bo, rdev->agp->bridge, page_flags);
491 }
492#endif
493 rbo = container_of(bo, struct radeon_bo, tbo);
494
495 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
496 if (gtt == NULL) {
497 return NULL;
498 }
499
500 if (rbo->flags & RADEON_GEM_GTT_UC)
501 caching = ttm_uncached;
502 else if (rbo->flags & RADEON_GEM_GTT_WC)
503 caching = ttm_write_combined;
504 else
505 caching = ttm_cached;
506
507 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) {
508 kfree(gtt);
509 return NULL;
510 }
511 return >t->ttm;
512}
513
514static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct radeon_device *rdev,
515 struct ttm_tt *ttm)
516{
517#if IS_ENABLED(CONFIG_AGP)
518 if (rdev->flags & RADEON_IS_AGP)
519 return NULL;
520#endif
521
522 if (!ttm)
523 return NULL;
524 return container_of(ttm, struct radeon_ttm_tt, ttm);
525}
526
527static int radeon_ttm_tt_populate(struct ttm_device *bdev,
528 struct ttm_tt *ttm,
529 struct ttm_operation_ctx *ctx)
530{
531 struct radeon_device *rdev = radeon_get_rdev(bdev);
532 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
533 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
534
535 if (gtt && gtt->userptr) {
536 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
537 if (!ttm->sg)
538 return -ENOMEM;
539
540 ttm->page_flags |= TTM_TT_FLAG_EXTERNAL;
541 return 0;
542 }
543
544 if (slave && ttm->sg) {
545 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
546 ttm->num_pages);
547 return 0;
548 }
549
550 return ttm_pool_alloc(&rdev->mman.bdev.pool, ttm, ctx);
551}
552
553static void radeon_ttm_tt_unpopulate(struct ttm_device *bdev, struct ttm_tt *ttm)
554{
555 struct radeon_device *rdev = radeon_get_rdev(bdev);
556 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
557 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
558
559 radeon_ttm_tt_unbind(bdev, ttm);
560
561 if (gtt && gtt->userptr) {
562 kfree(ttm->sg);
563 ttm->page_flags &= ~TTM_TT_FLAG_EXTERNAL;
564 return;
565 }
566
567 if (slave)
568 return;
569
570 return ttm_pool_free(&rdev->mman.bdev.pool, ttm);
571}
572
573int radeon_ttm_tt_set_userptr(struct radeon_device *rdev,
574 struct ttm_tt *ttm, uint64_t addr,
575 uint32_t flags)
576{
577 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
578
579 if (gtt == NULL)
580 return -EINVAL;
581
582 gtt->userptr = addr;
583 gtt->usermm = current->mm;
584 gtt->userflags = flags;
585 return 0;
586}
587
588bool radeon_ttm_tt_is_bound(struct ttm_device *bdev,
589 struct ttm_tt *ttm)
590{
591#if IS_ENABLED(CONFIG_AGP)
592 struct radeon_device *rdev = radeon_get_rdev(bdev);
593 if (rdev->flags & RADEON_IS_AGP)
594 return ttm_agp_is_bound(ttm);
595#endif
596 return radeon_ttm_backend_is_bound(ttm);
597}
598
599static int radeon_ttm_tt_bind(struct ttm_device *bdev,
600 struct ttm_tt *ttm,
601 struct ttm_resource *bo_mem)
602{
603#if IS_ENABLED(CONFIG_AGP)
604 struct radeon_device *rdev = radeon_get_rdev(bdev);
605#endif
606
607 if (!bo_mem)
608 return -EINVAL;
609#if IS_ENABLED(CONFIG_AGP)
610 if (rdev->flags & RADEON_IS_AGP)
611 return ttm_agp_bind(ttm, bo_mem);
612#endif
613
614 return radeon_ttm_backend_bind(bdev, ttm, bo_mem);
615}
616
617static void radeon_ttm_tt_unbind(struct ttm_device *bdev,
618 struct ttm_tt *ttm)
619{
620#if IS_ENABLED(CONFIG_AGP)
621 struct radeon_device *rdev = radeon_get_rdev(bdev);
622
623 if (rdev->flags & RADEON_IS_AGP) {
624 ttm_agp_unbind(ttm);
625 return;
626 }
627#endif
628 radeon_ttm_backend_unbind(bdev, ttm);
629}
630
631static void radeon_ttm_tt_destroy(struct ttm_device *bdev,
632 struct ttm_tt *ttm)
633{
634#if IS_ENABLED(CONFIG_AGP)
635 struct radeon_device *rdev = radeon_get_rdev(bdev);
636
637 if (rdev->flags & RADEON_IS_AGP) {
638 ttm_agp_destroy(ttm);
639 return;
640 }
641#endif
642 radeon_ttm_backend_destroy(bdev, ttm);
643}
644
645bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev,
646 struct ttm_tt *ttm)
647{
648 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
649
650 if (gtt == NULL)
651 return false;
652
653 return !!gtt->userptr;
654}
655
656bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev,
657 struct ttm_tt *ttm)
658{
659 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
660
661 if (gtt == NULL)
662 return false;
663
664 return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
665}
666
667static struct ttm_device_funcs radeon_bo_driver = {
668 .ttm_tt_create = &radeon_ttm_tt_create,
669 .ttm_tt_populate = &radeon_ttm_tt_populate,
670 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
671 .ttm_tt_destroy = &radeon_ttm_tt_destroy,
672 .eviction_valuable = ttm_bo_eviction_valuable,
673 .evict_flags = &radeon_evict_flags,
674 .move = &radeon_bo_move,
675 .io_mem_reserve = &radeon_ttm_io_mem_reserve,
676};
677
678int radeon_ttm_init(struct radeon_device *rdev)
679{
680 int r;
681
682 /* No others user of address space so set it to 0 */
683 r = ttm_device_init(&rdev->mman.bdev, &radeon_bo_driver, rdev->dev,
684 rdev_to_drm(rdev)->anon_inode->i_mapping,
685 rdev_to_drm(rdev)->vma_offset_manager,
686 rdev->need_swiotlb,
687 dma_addressing_limited(&rdev->pdev->dev));
688 if (r) {
689 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
690 return r;
691 }
692 rdev->mman.initialized = true;
693
694 r = radeon_ttm_init_vram(rdev);
695 if (r) {
696 DRM_ERROR("Failed initializing VRAM heap.\n");
697 return r;
698 }
699 /* Change the size here instead of the init above so only lpfn is affected */
700 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
701
702 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
703 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
704 NULL, &rdev->stolen_vga_memory);
705 if (r) {
706 return r;
707 }
708 r = radeon_bo_reserve(rdev->stolen_vga_memory, false);
709 if (r)
710 return r;
711 r = radeon_bo_pin(rdev->stolen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
712 radeon_bo_unreserve(rdev->stolen_vga_memory);
713 if (r) {
714 radeon_bo_unref(&rdev->stolen_vga_memory);
715 return r;
716 }
717 DRM_INFO("radeon: %uM of VRAM memory ready\n",
718 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
719
720 r = radeon_ttm_init_gtt(rdev);
721 if (r) {
722 DRM_ERROR("Failed initializing GTT heap.\n");
723 return r;
724 }
725 DRM_INFO("radeon: %uM of GTT memory ready.\n",
726 (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
727
728 radeon_ttm_debugfs_init(rdev);
729
730 return 0;
731}
732
733void radeon_ttm_fini(struct radeon_device *rdev)
734{
735 int r;
736
737 if (!rdev->mman.initialized)
738 return;
739
740 if (rdev->stolen_vga_memory) {
741 r = radeon_bo_reserve(rdev->stolen_vga_memory, false);
742 if (r == 0) {
743 radeon_bo_unpin(rdev->stolen_vga_memory);
744 radeon_bo_unreserve(rdev->stolen_vga_memory);
745 }
746 radeon_bo_unref(&rdev->stolen_vga_memory);
747 }
748 ttm_range_man_fini(&rdev->mman.bdev, TTM_PL_VRAM);
749 ttm_range_man_fini(&rdev->mman.bdev, TTM_PL_TT);
750 ttm_device_fini(&rdev->mman.bdev);
751 radeon_gart_fini(rdev);
752 rdev->mman.initialized = false;
753 DRM_INFO("radeon: ttm finalized\n");
754}
755
756/* this should only be called at bootup or when userspace
757 * isn't running */
758void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
759{
760 struct ttm_resource_manager *man;
761
762 if (!rdev->mman.initialized)
763 return;
764
765 man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM);
766 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
767 man->size = size >> PAGE_SHIFT;
768}
769
770#if defined(CONFIG_DEBUG_FS)
771
772static int radeon_ttm_page_pool_show(struct seq_file *m, void *data)
773{
774 struct radeon_device *rdev = m->private;
775
776 return ttm_pool_debugfs(&rdev->mman.bdev.pool, m);
777}
778
779DEFINE_SHOW_ATTRIBUTE(radeon_ttm_page_pool);
780
781static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
782{
783 struct radeon_device *rdev = inode->i_private;
784 i_size_write(inode, rdev->mc.mc_vram_size);
785 filep->private_data = inode->i_private;
786 return 0;
787}
788
789static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
790 size_t size, loff_t *pos)
791{
792 struct radeon_device *rdev = f->private_data;
793 ssize_t result = 0;
794 int r;
795
796 if (size & 0x3 || *pos & 0x3)
797 return -EINVAL;
798
799 while (size) {
800 unsigned long flags;
801 uint32_t value;
802
803 if (*pos >= rdev->mc.mc_vram_size)
804 return result;
805
806 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
807 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
808 if (rdev->family >= CHIP_CEDAR)
809 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
810 value = RREG32(RADEON_MM_DATA);
811 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
812
813 r = put_user(value, (uint32_t __user *)buf);
814 if (r)
815 return r;
816
817 result += 4;
818 buf += 4;
819 *pos += 4;
820 size -= 4;
821 }
822
823 return result;
824}
825
826static const struct file_operations radeon_ttm_vram_fops = {
827 .owner = THIS_MODULE,
828 .open = radeon_ttm_vram_open,
829 .read = radeon_ttm_vram_read,
830 .llseek = default_llseek
831};
832
833static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
834{
835 struct radeon_device *rdev = inode->i_private;
836 i_size_write(inode, rdev->mc.gtt_size);
837 filep->private_data = inode->i_private;
838 return 0;
839}
840
841static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
842 size_t size, loff_t *pos)
843{
844 struct radeon_device *rdev = f->private_data;
845 ssize_t result = 0;
846 int r;
847
848 while (size) {
849 loff_t p = *pos / PAGE_SIZE;
850 unsigned off = *pos & ~PAGE_MASK;
851 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
852 struct page *page;
853 void *ptr;
854
855 if (p >= rdev->gart.num_cpu_pages)
856 return result;
857
858 page = rdev->gart.pages[p];
859 if (page) {
860 ptr = kmap_local_page(page);
861 ptr += off;
862
863 r = copy_to_user(buf, ptr, cur_size);
864 kunmap_local(ptr);
865 } else
866 r = clear_user(buf, cur_size);
867
868 if (r)
869 return -EFAULT;
870
871 result += cur_size;
872 buf += cur_size;
873 *pos += cur_size;
874 size -= cur_size;
875 }
876
877 return result;
878}
879
880static const struct file_operations radeon_ttm_gtt_fops = {
881 .owner = THIS_MODULE,
882 .open = radeon_ttm_gtt_open,
883 .read = radeon_ttm_gtt_read,
884 .llseek = default_llseek
885};
886
887#endif
888
889static void radeon_ttm_debugfs_init(struct radeon_device *rdev)
890{
891#if defined(CONFIG_DEBUG_FS)
892 struct drm_minor *minor = rdev_to_drm(rdev)->primary;
893 struct dentry *root = minor->debugfs_root;
894
895 debugfs_create_file("radeon_vram", 0444, root, rdev,
896 &radeon_ttm_vram_fops);
897 debugfs_create_file("radeon_gtt", 0444, root, rdev,
898 &radeon_ttm_gtt_fops);
899 debugfs_create_file("ttm_page_pool", 0444, root, rdev,
900 &radeon_ttm_page_pool_fops);
901 ttm_resource_manager_create_debugfs(ttm_manager_type(&rdev->mman.bdev,
902 TTM_PL_VRAM),
903 root, "radeon_vram_mm");
904 ttm_resource_manager_create_debugfs(ttm_manager_type(&rdev->mman.bdev,
905 TTM_PL_TT),
906 root, "radeon_gtt_mm");
907#endif
908}