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1/*
2 * SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation
4 */
5
6#include <linux/clk.h>
7#include <linux/delay.h>
8#include <linux/interconnect.h>
9#include <linux/irq.h>
10#include <linux/irqchip.h>
11#include <linux/irqdesc.h>
12#include <linux/irqchip/chained_irq.h>
13#include <linux/of_platform.h>
14#include <linux/platform_device.h>
15#include <linux/pm_runtime.h>
16#include <linux/reset.h>
17
18#include "msm_mdss.h"
19#include "msm_kms.h"
20
21#define HW_REV 0x0
22#define HW_INTR_STATUS 0x0010
23
24#define UBWC_DEC_HW_VERSION 0x58
25#define UBWC_STATIC 0x144
26#define UBWC_CTRL_2 0x150
27#define UBWC_PREDICTION_MODE 0x154
28
29#define MIN_IB_BW 400000000UL /* Min ib vote 400MB */
30
31#define DEFAULT_REG_BW 153600 /* Used in mdss fbdev driver */
32
33struct msm_mdss {
34 struct device *dev;
35
36 void __iomem *mmio;
37 struct clk_bulk_data *clocks;
38 size_t num_clocks;
39 bool is_mdp5;
40 struct {
41 unsigned long enabled_mask;
42 struct irq_domain *domain;
43 } irq_controller;
44 const struct msm_mdss_data *mdss_data;
45 struct icc_path *mdp_path[2];
46 u32 num_mdp_paths;
47 struct icc_path *reg_bus_path;
48};
49
50static int msm_mdss_parse_data_bus_icc_path(struct device *dev,
51 struct msm_mdss *msm_mdss)
52{
53 struct icc_path *path0;
54 struct icc_path *path1;
55 struct icc_path *reg_bus_path;
56
57 path0 = devm_of_icc_get(dev, "mdp0-mem");
58 if (IS_ERR_OR_NULL(path0))
59 return PTR_ERR_OR_ZERO(path0);
60
61 msm_mdss->mdp_path[0] = path0;
62 msm_mdss->num_mdp_paths = 1;
63
64 path1 = devm_of_icc_get(dev, "mdp1-mem");
65 if (!IS_ERR_OR_NULL(path1)) {
66 msm_mdss->mdp_path[1] = path1;
67 msm_mdss->num_mdp_paths++;
68 }
69
70 reg_bus_path = of_icc_get(dev, "cpu-cfg");
71 if (!IS_ERR_OR_NULL(reg_bus_path))
72 msm_mdss->reg_bus_path = reg_bus_path;
73
74 return 0;
75}
76
77static void msm_mdss_irq(struct irq_desc *desc)
78{
79 struct msm_mdss *msm_mdss = irq_desc_get_handler_data(desc);
80 struct irq_chip *chip = irq_desc_get_chip(desc);
81 u32 interrupts;
82
83 chained_irq_enter(chip, desc);
84
85 interrupts = readl_relaxed(msm_mdss->mmio + HW_INTR_STATUS);
86
87 while (interrupts) {
88 irq_hw_number_t hwirq = fls(interrupts) - 1;
89 int rc;
90
91 rc = generic_handle_domain_irq(msm_mdss->irq_controller.domain,
92 hwirq);
93 if (rc < 0) {
94 dev_err(msm_mdss->dev, "handle irq fail: irq=%lu rc=%d\n",
95 hwirq, rc);
96 break;
97 }
98
99 interrupts &= ~(1 << hwirq);
100 }
101
102 chained_irq_exit(chip, desc);
103}
104
105static void msm_mdss_irq_mask(struct irq_data *irqd)
106{
107 struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd);
108
109 /* memory barrier */
110 smp_mb__before_atomic();
111 clear_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);
112 /* memory barrier */
113 smp_mb__after_atomic();
114}
115
116static void msm_mdss_irq_unmask(struct irq_data *irqd)
117{
118 struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd);
119
120 /* memory barrier */
121 smp_mb__before_atomic();
122 set_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);
123 /* memory barrier */
124 smp_mb__after_atomic();
125}
126
127static struct irq_chip msm_mdss_irq_chip = {
128 .name = "msm_mdss",
129 .irq_mask = msm_mdss_irq_mask,
130 .irq_unmask = msm_mdss_irq_unmask,
131};
132
133static struct lock_class_key msm_mdss_lock_key, msm_mdss_request_key;
134
135static int msm_mdss_irqdomain_map(struct irq_domain *domain,
136 unsigned int irq, irq_hw_number_t hwirq)
137{
138 struct msm_mdss *msm_mdss = domain->host_data;
139
140 irq_set_lockdep_class(irq, &msm_mdss_lock_key, &msm_mdss_request_key);
141 irq_set_chip_and_handler(irq, &msm_mdss_irq_chip, handle_level_irq);
142
143 return irq_set_chip_data(irq, msm_mdss);
144}
145
146static const struct irq_domain_ops msm_mdss_irqdomain_ops = {
147 .map = msm_mdss_irqdomain_map,
148 .xlate = irq_domain_xlate_onecell,
149};
150
151static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss)
152{
153 struct device *dev;
154 struct irq_domain *domain;
155
156 dev = msm_mdss->dev;
157
158 domain = irq_domain_add_linear(dev->of_node, 32,
159 &msm_mdss_irqdomain_ops, msm_mdss);
160 if (!domain) {
161 dev_err(dev, "failed to add irq_domain\n");
162 return -EINVAL;
163 }
164
165 msm_mdss->irq_controller.enabled_mask = 0;
166 msm_mdss->irq_controller.domain = domain;
167
168 return 0;
169}
170
171static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss)
172{
173 const struct msm_mdss_data *data = msm_mdss->mdss_data;
174
175 writel_relaxed(data->ubwc_static, msm_mdss->mmio + UBWC_STATIC);
176}
177
178static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss)
179{
180 const struct msm_mdss_data *data = msm_mdss->mdss_data;
181 u32 value = (data->ubwc_swizzle & 0x1) |
182 (data->highest_bank_bit & 0x3) << 4 |
183 (data->macrotile_mode & 0x1) << 12;
184
185 if (data->ubwc_enc_version == UBWC_3_0)
186 value |= BIT(10);
187
188 if (data->ubwc_enc_version == UBWC_1_0)
189 value |= BIT(8);
190
191 writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
192}
193
194static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss)
195{
196 const struct msm_mdss_data *data = msm_mdss->mdss_data;
197 u32 value = (data->ubwc_swizzle & 0x7) |
198 (data->ubwc_static & 0x1) << 3 |
199 (data->highest_bank_bit & 0x7) << 4 |
200 (data->macrotile_mode & 0x1) << 12;
201
202 writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
203
204 if (data->ubwc_enc_version == UBWC_3_0) {
205 writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2);
206 writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE);
207 } else {
208 if (data->ubwc_dec_version == UBWC_4_3)
209 writel_relaxed(3, msm_mdss->mmio + UBWC_CTRL_2);
210 else
211 writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2);
212 writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE);
213 }
214}
215
216const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev)
217{
218 struct msm_mdss *mdss;
219
220 if (!dev)
221 return ERR_PTR(-EINVAL);
222
223 mdss = dev_get_drvdata(dev);
224
225 return mdss->mdss_data;
226}
227
228static int msm_mdss_enable(struct msm_mdss *msm_mdss)
229{
230 int ret, i;
231
232 /*
233 * Several components have AXI clocks that can only be turned on if
234 * the interconnect is enabled (non-zero bandwidth). Let's make sure
235 * that the interconnects are at least at a minimum amount.
236 */
237 for (i = 0; i < msm_mdss->num_mdp_paths; i++)
238 icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW));
239
240 if (msm_mdss->mdss_data && msm_mdss->mdss_data->reg_bus_bw)
241 icc_set_bw(msm_mdss->reg_bus_path, 0,
242 msm_mdss->mdss_data->reg_bus_bw);
243 else
244 icc_set_bw(msm_mdss->reg_bus_path, 0,
245 DEFAULT_REG_BW);
246
247 ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks);
248 if (ret) {
249 dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret);
250 return ret;
251 }
252
253 /*
254 * Register access requires MDSS_MDP_CLK, which is not enabled by the
255 * mdss on mdp5 hardware. Skip it for now.
256 */
257 if (msm_mdss->is_mdp5 || !msm_mdss->mdss_data)
258 return 0;
259
260 /*
261 * ubwc config is part of the "mdss" region which is not accessible
262 * from the rest of the driver. hardcode known configurations here
263 *
264 * Decoder version can be read from the UBWC_DEC_HW_VERSION reg,
265 * UBWC_n and the rest of params comes from hw data.
266 */
267 switch (msm_mdss->mdss_data->ubwc_dec_version) {
268 case 0: /* no UBWC */
269 case UBWC_1_0:
270 /* do nothing */
271 break;
272 case UBWC_2_0:
273 msm_mdss_setup_ubwc_dec_20(msm_mdss);
274 break;
275 case UBWC_3_0:
276 msm_mdss_setup_ubwc_dec_30(msm_mdss);
277 break;
278 case UBWC_4_0:
279 case UBWC_4_3:
280 msm_mdss_setup_ubwc_dec_40(msm_mdss);
281 break;
282 default:
283 dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n",
284 msm_mdss->mdss_data->ubwc_dec_version);
285 dev_err(msm_mdss->dev, "HW_REV: 0x%x\n",
286 readl_relaxed(msm_mdss->mmio + HW_REV));
287 dev_err(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n",
288 readl_relaxed(msm_mdss->mmio + UBWC_DEC_HW_VERSION));
289 break;
290 }
291
292 return ret;
293}
294
295static int msm_mdss_disable(struct msm_mdss *msm_mdss)
296{
297 int i;
298
299 clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks);
300
301 for (i = 0; i < msm_mdss->num_mdp_paths; i++)
302 icc_set_bw(msm_mdss->mdp_path[i], 0, 0);
303
304 if (msm_mdss->reg_bus_path)
305 icc_set_bw(msm_mdss->reg_bus_path, 0, 0);
306
307 return 0;
308}
309
310static void msm_mdss_destroy(struct msm_mdss *msm_mdss)
311{
312 struct platform_device *pdev = to_platform_device(msm_mdss->dev);
313 int irq;
314
315 pm_runtime_suspend(msm_mdss->dev);
316 pm_runtime_disable(msm_mdss->dev);
317 irq_domain_remove(msm_mdss->irq_controller.domain);
318 msm_mdss->irq_controller.domain = NULL;
319 irq = platform_get_irq(pdev, 0);
320 irq_set_chained_handler_and_data(irq, NULL, NULL);
321}
322
323static int msm_mdss_reset(struct device *dev)
324{
325 struct reset_control *reset;
326
327 reset = reset_control_get_optional_exclusive(dev, NULL);
328 if (!reset) {
329 /* Optional reset not specified */
330 return 0;
331 } else if (IS_ERR(reset)) {
332 return dev_err_probe(dev, PTR_ERR(reset),
333 "failed to acquire mdss reset\n");
334 }
335
336 reset_control_assert(reset);
337 /*
338 * Tests indicate that reset has to be held for some period of time,
339 * make it one frame in a typical system
340 */
341 msleep(20);
342 reset_control_deassert(reset);
343
344 reset_control_put(reset);
345
346 return 0;
347}
348
349/*
350 * MDP5 MDSS uses at most three specified clocks.
351 */
352#define MDP5_MDSS_NUM_CLOCKS 3
353static int mdp5_mdss_parse_clock(struct platform_device *pdev, struct clk_bulk_data **clocks)
354{
355 struct clk_bulk_data *bulk;
356 int num_clocks = 0;
357 int ret;
358
359 if (!pdev)
360 return -EINVAL;
361
362 bulk = devm_kcalloc(&pdev->dev, MDP5_MDSS_NUM_CLOCKS, sizeof(struct clk_bulk_data), GFP_KERNEL);
363 if (!bulk)
364 return -ENOMEM;
365
366 bulk[num_clocks++].id = "iface";
367 bulk[num_clocks++].id = "bus";
368 bulk[num_clocks++].id = "vsync";
369
370 ret = devm_clk_bulk_get_optional(&pdev->dev, num_clocks, bulk);
371 if (ret)
372 return ret;
373
374 *clocks = bulk;
375
376 return num_clocks;
377}
378
379static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5)
380{
381 struct msm_mdss *msm_mdss;
382 int ret;
383 int irq;
384
385 ret = msm_mdss_reset(&pdev->dev);
386 if (ret)
387 return ERR_PTR(ret);
388
389 msm_mdss = devm_kzalloc(&pdev->dev, sizeof(*msm_mdss), GFP_KERNEL);
390 if (!msm_mdss)
391 return ERR_PTR(-ENOMEM);
392
393 msm_mdss->mdss_data = of_device_get_match_data(&pdev->dev);
394
395 msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss");
396 if (IS_ERR(msm_mdss->mmio))
397 return ERR_CAST(msm_mdss->mmio);
398
399 dev_dbg(&pdev->dev, "mapped mdss address space @%pK\n", msm_mdss->mmio);
400
401 ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss);
402 if (ret)
403 return ERR_PTR(ret);
404
405 if (is_mdp5)
406 ret = mdp5_mdss_parse_clock(pdev, &msm_mdss->clocks);
407 else
408 ret = devm_clk_bulk_get_all(&pdev->dev, &msm_mdss->clocks);
409 if (ret < 0) {
410 dev_err(&pdev->dev, "failed to parse clocks, ret=%d\n", ret);
411 return ERR_PTR(ret);
412 }
413 msm_mdss->num_clocks = ret;
414 msm_mdss->is_mdp5 = is_mdp5;
415
416 msm_mdss->dev = &pdev->dev;
417
418 irq = platform_get_irq(pdev, 0);
419 if (irq < 0)
420 return ERR_PTR(irq);
421
422 ret = _msm_mdss_irq_domain_add(msm_mdss);
423 if (ret)
424 return ERR_PTR(ret);
425
426 irq_set_chained_handler_and_data(irq, msm_mdss_irq,
427 msm_mdss);
428
429 pm_runtime_enable(&pdev->dev);
430
431 return msm_mdss;
432}
433
434static int __maybe_unused mdss_runtime_suspend(struct device *dev)
435{
436 struct msm_mdss *mdss = dev_get_drvdata(dev);
437
438 DBG("");
439
440 return msm_mdss_disable(mdss);
441}
442
443static int __maybe_unused mdss_runtime_resume(struct device *dev)
444{
445 struct msm_mdss *mdss = dev_get_drvdata(dev);
446
447 DBG("");
448
449 return msm_mdss_enable(mdss);
450}
451
452static int __maybe_unused mdss_pm_suspend(struct device *dev)
453{
454
455 if (pm_runtime_suspended(dev))
456 return 0;
457
458 return mdss_runtime_suspend(dev);
459}
460
461static int __maybe_unused mdss_pm_resume(struct device *dev)
462{
463 if (pm_runtime_suspended(dev))
464 return 0;
465
466 return mdss_runtime_resume(dev);
467}
468
469static const struct dev_pm_ops mdss_pm_ops = {
470 SET_SYSTEM_SLEEP_PM_OPS(mdss_pm_suspend, mdss_pm_resume)
471 SET_RUNTIME_PM_OPS(mdss_runtime_suspend, mdss_runtime_resume, NULL)
472};
473
474static int mdss_probe(struct platform_device *pdev)
475{
476 struct msm_mdss *mdss;
477 bool is_mdp5 = of_device_is_compatible(pdev->dev.of_node, "qcom,mdss");
478 struct device *dev = &pdev->dev;
479 int ret;
480
481 mdss = msm_mdss_init(pdev, is_mdp5);
482 if (IS_ERR(mdss))
483 return PTR_ERR(mdss);
484
485 platform_set_drvdata(pdev, mdss);
486
487 /*
488 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
489 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
490 * Populate the children devices, find the MDP5/DPU node, and then add
491 * the interfaces to our components list.
492 */
493 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
494 if (ret) {
495 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
496 msm_mdss_destroy(mdss);
497 return ret;
498 }
499
500 return 0;
501}
502
503static void mdss_remove(struct platform_device *pdev)
504{
505 struct msm_mdss *mdss = platform_get_drvdata(pdev);
506
507 of_platform_depopulate(&pdev->dev);
508
509 msm_mdss_destroy(mdss);
510}
511
512static const struct msm_mdss_data msm8998_data = {
513 .ubwc_enc_version = UBWC_1_0,
514 .ubwc_dec_version = UBWC_1_0,
515 .highest_bank_bit = 2,
516 .reg_bus_bw = 76800,
517};
518
519static const struct msm_mdss_data qcm2290_data = {
520 /* no UBWC */
521 .highest_bank_bit = 0x2,
522 .reg_bus_bw = 76800,
523};
524
525static const struct msm_mdss_data sc7180_data = {
526 .ubwc_enc_version = UBWC_2_0,
527 .ubwc_dec_version = UBWC_2_0,
528 .ubwc_static = 0x1e,
529 .highest_bank_bit = 0x3,
530 .reg_bus_bw = 76800,
531};
532
533static const struct msm_mdss_data sc7280_data = {
534 .ubwc_enc_version = UBWC_3_0,
535 .ubwc_dec_version = UBWC_4_0,
536 .ubwc_swizzle = 6,
537 .ubwc_static = 1,
538 .highest_bank_bit = 1,
539 .macrotile_mode = 1,
540 .reg_bus_bw = 74000,
541};
542
543static const struct msm_mdss_data sc8180x_data = {
544 .ubwc_enc_version = UBWC_3_0,
545 .ubwc_dec_version = UBWC_3_0,
546 .highest_bank_bit = 3,
547 .macrotile_mode = 1,
548 .reg_bus_bw = 76800,
549};
550
551static const struct msm_mdss_data sc8280xp_data = {
552 .ubwc_enc_version = UBWC_4_0,
553 .ubwc_dec_version = UBWC_4_0,
554 .ubwc_swizzle = 6,
555 .ubwc_static = 1,
556 .highest_bank_bit = 3,
557 .macrotile_mode = 1,
558 .reg_bus_bw = 76800,
559};
560
561static const struct msm_mdss_data sdm670_data = {
562 .ubwc_enc_version = UBWC_2_0,
563 .ubwc_dec_version = UBWC_2_0,
564 .highest_bank_bit = 1,
565 .reg_bus_bw = 76800,
566};
567
568static const struct msm_mdss_data sdm845_data = {
569 .ubwc_enc_version = UBWC_2_0,
570 .ubwc_dec_version = UBWC_2_0,
571 .highest_bank_bit = 2,
572 .reg_bus_bw = 76800,
573};
574
575static const struct msm_mdss_data sm6350_data = {
576 .ubwc_enc_version = UBWC_2_0,
577 .ubwc_dec_version = UBWC_2_0,
578 .ubwc_swizzle = 6,
579 .ubwc_static = 0x1e,
580 .highest_bank_bit = 1,
581 .reg_bus_bw = 76800,
582};
583
584static const struct msm_mdss_data sm8150_data = {
585 .ubwc_enc_version = UBWC_3_0,
586 .ubwc_dec_version = UBWC_3_0,
587 .highest_bank_bit = 2,
588 .reg_bus_bw = 76800,
589};
590
591static const struct msm_mdss_data sm6115_data = {
592 .ubwc_enc_version = UBWC_1_0,
593 .ubwc_dec_version = UBWC_2_0,
594 .ubwc_swizzle = 7,
595 .ubwc_static = 0x11f,
596 .highest_bank_bit = 0x1,
597 .reg_bus_bw = 76800,
598};
599
600static const struct msm_mdss_data sm6125_data = {
601 .ubwc_enc_version = UBWC_1_0,
602 .ubwc_dec_version = UBWC_3_0,
603 .ubwc_swizzle = 1,
604 .highest_bank_bit = 1,
605};
606
607static const struct msm_mdss_data sm8250_data = {
608 .ubwc_enc_version = UBWC_4_0,
609 .ubwc_dec_version = UBWC_4_0,
610 .ubwc_swizzle = 6,
611 .ubwc_static = 1,
612 /* TODO: highest_bank_bit = 2 for LP_DDR4 */
613 .highest_bank_bit = 3,
614 .macrotile_mode = 1,
615 .reg_bus_bw = 76800,
616};
617
618static const struct msm_mdss_data sm8350_data = {
619 .ubwc_enc_version = UBWC_4_0,
620 .ubwc_dec_version = UBWC_4_0,
621 .ubwc_swizzle = 6,
622 .ubwc_static = 1,
623 /* TODO: highest_bank_bit = 2 for LP_DDR4 */
624 .highest_bank_bit = 3,
625 .macrotile_mode = 1,
626 .reg_bus_bw = 74000,
627};
628
629static const struct msm_mdss_data sm8550_data = {
630 .ubwc_enc_version = UBWC_4_0,
631 .ubwc_dec_version = UBWC_4_3,
632 .ubwc_swizzle = 6,
633 .ubwc_static = 1,
634 /* TODO: highest_bank_bit = 2 for LP_DDR4 */
635 .highest_bank_bit = 3,
636 .macrotile_mode = 1,
637 .reg_bus_bw = 57000,
638};
639static const struct of_device_id mdss_dt_match[] = {
640 { .compatible = "qcom,mdss" },
641 { .compatible = "qcom,msm8998-mdss", .data = &msm8998_data },
642 { .compatible = "qcom,qcm2290-mdss", .data = &qcm2290_data },
643 { .compatible = "qcom,sdm670-mdss", .data = &sdm670_data },
644 { .compatible = "qcom,sdm845-mdss", .data = &sdm845_data },
645 { .compatible = "qcom,sc7180-mdss", .data = &sc7180_data },
646 { .compatible = "qcom,sc7280-mdss", .data = &sc7280_data },
647 { .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data },
648 { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
649 { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
650 { .compatible = "qcom,sm6125-mdss", .data = &sm6125_data },
651 { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
652 { .compatible = "qcom,sm6375-mdss", .data = &sm6350_data },
653 { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
654 { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
655 { .compatible = "qcom,sm8350-mdss", .data = &sm8350_data },
656 { .compatible = "qcom,sm8450-mdss", .data = &sm8350_data },
657 { .compatible = "qcom,sm8550-mdss", .data = &sm8550_data },
658 { .compatible = "qcom,sm8650-mdss", .data = &sm8550_data},
659 {}
660};
661MODULE_DEVICE_TABLE(of, mdss_dt_match);
662
663static struct platform_driver mdss_platform_driver = {
664 .probe = mdss_probe,
665 .remove_new = mdss_remove,
666 .driver = {
667 .name = "msm-mdss",
668 .of_match_table = mdss_dt_match,
669 .pm = &mdss_pm_ops,
670 },
671};
672
673void __init msm_mdss_register(void)
674{
675 platform_driver_register(&mdss_platform_driver);
676}
677
678void __exit msm_mdss_unregister(void)
679{
680 platform_driver_unregister(&mdss_platform_driver);
681}
1/*
2 * SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation
4 */
5
6#include <linux/bitfield.h>
7#include <linux/clk.h>
8#include <linux/delay.h>
9#include <linux/interconnect.h>
10#include <linux/irq.h>
11#include <linux/irqchip.h>
12#include <linux/irqdesc.h>
13#include <linux/irqchip/chained_irq.h>
14#include <linux/of_platform.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/reset.h>
18
19#include "msm_mdss.h"
20#include "msm_kms.h"
21
22#include <generated/mdss.xml.h>
23
24#define MIN_IB_BW 400000000UL /* Min ib vote 400MB */
25
26#define DEFAULT_REG_BW 153600 /* Used in mdss fbdev driver */
27
28struct msm_mdss {
29 struct device *dev;
30
31 void __iomem *mmio;
32 struct clk_bulk_data *clocks;
33 size_t num_clocks;
34 bool is_mdp5;
35 struct {
36 unsigned long enabled_mask;
37 struct irq_domain *domain;
38 } irq_controller;
39 const struct msm_mdss_data *mdss_data;
40 struct icc_path *mdp_path[2];
41 u32 num_mdp_paths;
42 struct icc_path *reg_bus_path;
43};
44
45static int msm_mdss_parse_data_bus_icc_path(struct device *dev,
46 struct msm_mdss *msm_mdss)
47{
48 struct icc_path *path0;
49 struct icc_path *path1;
50 struct icc_path *reg_bus_path;
51
52 path0 = devm_of_icc_get(dev, "mdp0-mem");
53 if (IS_ERR_OR_NULL(path0))
54 return PTR_ERR_OR_ZERO(path0);
55
56 msm_mdss->mdp_path[0] = path0;
57 msm_mdss->num_mdp_paths = 1;
58
59 path1 = devm_of_icc_get(dev, "mdp1-mem");
60 if (!IS_ERR_OR_NULL(path1)) {
61 msm_mdss->mdp_path[1] = path1;
62 msm_mdss->num_mdp_paths++;
63 }
64
65 reg_bus_path = of_icc_get(dev, "cpu-cfg");
66 if (!IS_ERR_OR_NULL(reg_bus_path))
67 msm_mdss->reg_bus_path = reg_bus_path;
68
69 return 0;
70}
71
72static void msm_mdss_irq(struct irq_desc *desc)
73{
74 struct msm_mdss *msm_mdss = irq_desc_get_handler_data(desc);
75 struct irq_chip *chip = irq_desc_get_chip(desc);
76 u32 interrupts;
77
78 chained_irq_enter(chip, desc);
79
80 interrupts = readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_INTR_STATUS);
81
82 while (interrupts) {
83 irq_hw_number_t hwirq = fls(interrupts) - 1;
84 int rc;
85
86 rc = generic_handle_domain_irq(msm_mdss->irq_controller.domain,
87 hwirq);
88 if (rc < 0) {
89 dev_err(msm_mdss->dev, "handle irq fail: irq=%lu rc=%d\n",
90 hwirq, rc);
91 break;
92 }
93
94 interrupts &= ~(1 << hwirq);
95 }
96
97 chained_irq_exit(chip, desc);
98}
99
100static void msm_mdss_irq_mask(struct irq_data *irqd)
101{
102 struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd);
103
104 /* memory barrier */
105 smp_mb__before_atomic();
106 clear_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);
107 /* memory barrier */
108 smp_mb__after_atomic();
109}
110
111static void msm_mdss_irq_unmask(struct irq_data *irqd)
112{
113 struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd);
114
115 /* memory barrier */
116 smp_mb__before_atomic();
117 set_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);
118 /* memory barrier */
119 smp_mb__after_atomic();
120}
121
122static struct irq_chip msm_mdss_irq_chip = {
123 .name = "msm_mdss",
124 .irq_mask = msm_mdss_irq_mask,
125 .irq_unmask = msm_mdss_irq_unmask,
126};
127
128static struct lock_class_key msm_mdss_lock_key, msm_mdss_request_key;
129
130static int msm_mdss_irqdomain_map(struct irq_domain *domain,
131 unsigned int irq, irq_hw_number_t hwirq)
132{
133 struct msm_mdss *msm_mdss = domain->host_data;
134
135 irq_set_lockdep_class(irq, &msm_mdss_lock_key, &msm_mdss_request_key);
136 irq_set_chip_and_handler(irq, &msm_mdss_irq_chip, handle_level_irq);
137
138 return irq_set_chip_data(irq, msm_mdss);
139}
140
141static const struct irq_domain_ops msm_mdss_irqdomain_ops = {
142 .map = msm_mdss_irqdomain_map,
143 .xlate = irq_domain_xlate_onecell,
144};
145
146static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss)
147{
148 struct device *dev;
149 struct irq_domain *domain;
150
151 dev = msm_mdss->dev;
152
153 domain = irq_domain_add_linear(dev->of_node, 32,
154 &msm_mdss_irqdomain_ops, msm_mdss);
155 if (!domain) {
156 dev_err(dev, "failed to add irq_domain\n");
157 return -EINVAL;
158 }
159
160 msm_mdss->irq_controller.enabled_mask = 0;
161 msm_mdss->irq_controller.domain = domain;
162
163 return 0;
164}
165
166static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss)
167{
168 const struct msm_mdss_data *data = msm_mdss->mdss_data;
169
170 writel_relaxed(data->ubwc_static, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);
171}
172
173static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss)
174{
175 const struct msm_mdss_data *data = msm_mdss->mdss_data;
176 u32 value = (data->ubwc_swizzle & 0x1) |
177 (data->highest_bank_bit & 0x3) << 4 |
178 (data->macrotile_mode & 0x1) << 12;
179
180 if (data->ubwc_enc_version == UBWC_3_0)
181 value |= BIT(10);
182
183 if (data->ubwc_enc_version == UBWC_1_0)
184 value |= BIT(8);
185
186 writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);
187}
188
189static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss)
190{
191 const struct msm_mdss_data *data = msm_mdss->mdss_data;
192 u32 value = (data->ubwc_swizzle & 0x7) |
193 (data->ubwc_static & 0x1) << 3 |
194 (data->highest_bank_bit & 0x7) << 4 |
195 (data->macrotile_mode & 0x1) << 12;
196
197 writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);
198
199 if (data->ubwc_enc_version == UBWC_3_0) {
200 writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
201 writel_relaxed(0, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);
202 } else {
203 if (data->ubwc_dec_version == UBWC_4_3)
204 writel_relaxed(3, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
205 else
206 writel_relaxed(2, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
207 writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);
208 }
209}
210
211#define MDSS_HW_MAJ_MIN \
212 (MDSS_HW_VERSION_MAJOR__MASK | MDSS_HW_VERSION_MINOR__MASK)
213
214#define MDSS_HW_MSM8996 0x1007
215#define MDSS_HW_MSM8937 0x100e
216#define MDSS_HW_MSM8953 0x1010
217#define MDSS_HW_MSM8998 0x3000
218#define MDSS_HW_SDM660 0x3002
219#define MDSS_HW_SDM630 0x3003
220
221/*
222 * MDP5 platforms use generic qcom,mdp5 compat string, so we have to generate this data
223 */
224static const struct msm_mdss_data *msm_mdss_generate_mdp5_mdss_data(struct msm_mdss *mdss)
225{
226 struct msm_mdss_data *data;
227 u32 hw_rev;
228
229 data = devm_kzalloc(mdss->dev, sizeof(*data), GFP_KERNEL);
230 if (!data)
231 return NULL;
232
233 hw_rev = readl_relaxed(mdss->mmio + REG_MDSS_HW_VERSION);
234 hw_rev = FIELD_GET(MDSS_HW_MAJ_MIN, hw_rev);
235
236 if (hw_rev == MDSS_HW_MSM8996 ||
237 hw_rev == MDSS_HW_MSM8937 ||
238 hw_rev == MDSS_HW_MSM8953 ||
239 hw_rev == MDSS_HW_MSM8998 ||
240 hw_rev == MDSS_HW_SDM660 ||
241 hw_rev == MDSS_HW_SDM630) {
242 data->ubwc_dec_version = UBWC_1_0;
243 data->ubwc_enc_version = UBWC_1_0;
244 }
245
246 if (hw_rev == MDSS_HW_MSM8996 ||
247 hw_rev == MDSS_HW_MSM8998)
248 data->highest_bank_bit = 2;
249 else
250 data->highest_bank_bit = 1;
251
252 return data;
253}
254
255const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev)
256{
257 struct msm_mdss *mdss;
258
259 if (!dev)
260 return ERR_PTR(-EINVAL);
261
262 mdss = dev_get_drvdata(dev);
263
264 /*
265 * We could not do it at the probe time, since hw revision register was
266 * not readable. Fill data structure now for the MDP5 platforms.
267 */
268 if (!mdss->mdss_data && mdss->is_mdp5)
269 mdss->mdss_data = msm_mdss_generate_mdp5_mdss_data(mdss);
270
271 return mdss->mdss_data;
272}
273
274static int msm_mdss_enable(struct msm_mdss *msm_mdss)
275{
276 int ret, i;
277
278 /*
279 * Several components have AXI clocks that can only be turned on if
280 * the interconnect is enabled (non-zero bandwidth). Let's make sure
281 * that the interconnects are at least at a minimum amount.
282 */
283 for (i = 0; i < msm_mdss->num_mdp_paths; i++)
284 icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW));
285
286 if (msm_mdss->mdss_data && msm_mdss->mdss_data->reg_bus_bw)
287 icc_set_bw(msm_mdss->reg_bus_path, 0,
288 msm_mdss->mdss_data->reg_bus_bw);
289 else
290 icc_set_bw(msm_mdss->reg_bus_path, 0,
291 DEFAULT_REG_BW);
292
293 ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks);
294 if (ret) {
295 dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret);
296 return ret;
297 }
298
299 /*
300 * Register access requires MDSS_MDP_CLK, which is not enabled by the
301 * mdss on mdp5 hardware. Skip it for now.
302 */
303 if (msm_mdss->is_mdp5 || !msm_mdss->mdss_data)
304 return 0;
305
306 /*
307 * ubwc config is part of the "mdss" region which is not accessible
308 * from the rest of the driver. hardcode known configurations here
309 *
310 * Decoder version can be read from the UBWC_DEC_HW_VERSION reg,
311 * UBWC_n and the rest of params comes from hw data.
312 */
313 switch (msm_mdss->mdss_data->ubwc_dec_version) {
314 case 0: /* no UBWC */
315 case UBWC_1_0:
316 /* do nothing */
317 break;
318 case UBWC_2_0:
319 msm_mdss_setup_ubwc_dec_20(msm_mdss);
320 break;
321 case UBWC_3_0:
322 msm_mdss_setup_ubwc_dec_30(msm_mdss);
323 break;
324 case UBWC_4_0:
325 case UBWC_4_3:
326 msm_mdss_setup_ubwc_dec_40(msm_mdss);
327 break;
328 default:
329 dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n",
330 msm_mdss->mdss_data->ubwc_dec_version);
331 dev_err(msm_mdss->dev, "HW_REV: 0x%x\n",
332 readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_VERSION));
333 dev_err(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n",
334 readl_relaxed(msm_mdss->mmio + REG_MDSS_UBWC_DEC_HW_VERSION));
335 break;
336 }
337
338 return ret;
339}
340
341static int msm_mdss_disable(struct msm_mdss *msm_mdss)
342{
343 int i;
344
345 clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks);
346
347 for (i = 0; i < msm_mdss->num_mdp_paths; i++)
348 icc_set_bw(msm_mdss->mdp_path[i], 0, 0);
349
350 if (msm_mdss->reg_bus_path)
351 icc_set_bw(msm_mdss->reg_bus_path, 0, 0);
352
353 return 0;
354}
355
356static void msm_mdss_destroy(struct msm_mdss *msm_mdss)
357{
358 struct platform_device *pdev = to_platform_device(msm_mdss->dev);
359 int irq;
360
361 pm_runtime_suspend(msm_mdss->dev);
362 pm_runtime_disable(msm_mdss->dev);
363 irq_domain_remove(msm_mdss->irq_controller.domain);
364 msm_mdss->irq_controller.domain = NULL;
365 irq = platform_get_irq(pdev, 0);
366 irq_set_chained_handler_and_data(irq, NULL, NULL);
367}
368
369static int msm_mdss_reset(struct device *dev)
370{
371 struct reset_control *reset;
372
373 reset = reset_control_get_optional_exclusive(dev, NULL);
374 if (!reset) {
375 /* Optional reset not specified */
376 return 0;
377 } else if (IS_ERR(reset)) {
378 return dev_err_probe(dev, PTR_ERR(reset),
379 "failed to acquire mdss reset\n");
380 }
381
382 reset_control_assert(reset);
383 /*
384 * Tests indicate that reset has to be held for some period of time,
385 * make it one frame in a typical system
386 */
387 msleep(20);
388 reset_control_deassert(reset);
389
390 reset_control_put(reset);
391
392 return 0;
393}
394
395/*
396 * MDP5 MDSS uses at most three specified clocks.
397 */
398#define MDP5_MDSS_NUM_CLOCKS 3
399static int mdp5_mdss_parse_clock(struct platform_device *pdev, struct clk_bulk_data **clocks)
400{
401 struct clk_bulk_data *bulk;
402 int num_clocks = 0;
403 int ret;
404
405 if (!pdev)
406 return -EINVAL;
407
408 bulk = devm_kcalloc(&pdev->dev, MDP5_MDSS_NUM_CLOCKS, sizeof(struct clk_bulk_data), GFP_KERNEL);
409 if (!bulk)
410 return -ENOMEM;
411
412 bulk[num_clocks++].id = "iface";
413 bulk[num_clocks++].id = "bus";
414 bulk[num_clocks++].id = "vsync";
415
416 ret = devm_clk_bulk_get_optional(&pdev->dev, num_clocks, bulk);
417 if (ret)
418 return ret;
419
420 *clocks = bulk;
421
422 return num_clocks;
423}
424
425static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5)
426{
427 struct msm_mdss *msm_mdss;
428 int ret;
429 int irq;
430
431 ret = msm_mdss_reset(&pdev->dev);
432 if (ret)
433 return ERR_PTR(ret);
434
435 msm_mdss = devm_kzalloc(&pdev->dev, sizeof(*msm_mdss), GFP_KERNEL);
436 if (!msm_mdss)
437 return ERR_PTR(-ENOMEM);
438
439 msm_mdss->mdss_data = of_device_get_match_data(&pdev->dev);
440
441 msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss");
442 if (IS_ERR(msm_mdss->mmio))
443 return ERR_CAST(msm_mdss->mmio);
444
445 dev_dbg(&pdev->dev, "mapped mdss address space @%pK\n", msm_mdss->mmio);
446
447 ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss);
448 if (ret)
449 return ERR_PTR(ret);
450
451 if (is_mdp5)
452 ret = mdp5_mdss_parse_clock(pdev, &msm_mdss->clocks);
453 else
454 ret = devm_clk_bulk_get_all(&pdev->dev, &msm_mdss->clocks);
455 if (ret < 0) {
456 dev_err(&pdev->dev, "failed to parse clocks, ret=%d\n", ret);
457 return ERR_PTR(ret);
458 }
459 msm_mdss->num_clocks = ret;
460 msm_mdss->is_mdp5 = is_mdp5;
461
462 msm_mdss->dev = &pdev->dev;
463
464 irq = platform_get_irq(pdev, 0);
465 if (irq < 0)
466 return ERR_PTR(irq);
467
468 ret = _msm_mdss_irq_domain_add(msm_mdss);
469 if (ret)
470 return ERR_PTR(ret);
471
472 irq_set_chained_handler_and_data(irq, msm_mdss_irq,
473 msm_mdss);
474
475 pm_runtime_enable(&pdev->dev);
476
477 return msm_mdss;
478}
479
480static int __maybe_unused mdss_runtime_suspend(struct device *dev)
481{
482 struct msm_mdss *mdss = dev_get_drvdata(dev);
483
484 DBG("");
485
486 return msm_mdss_disable(mdss);
487}
488
489static int __maybe_unused mdss_runtime_resume(struct device *dev)
490{
491 struct msm_mdss *mdss = dev_get_drvdata(dev);
492
493 DBG("");
494
495 return msm_mdss_enable(mdss);
496}
497
498static int __maybe_unused mdss_pm_suspend(struct device *dev)
499{
500
501 if (pm_runtime_suspended(dev))
502 return 0;
503
504 return mdss_runtime_suspend(dev);
505}
506
507static int __maybe_unused mdss_pm_resume(struct device *dev)
508{
509 if (pm_runtime_suspended(dev))
510 return 0;
511
512 return mdss_runtime_resume(dev);
513}
514
515static const struct dev_pm_ops mdss_pm_ops = {
516 SET_SYSTEM_SLEEP_PM_OPS(mdss_pm_suspend, mdss_pm_resume)
517 SET_RUNTIME_PM_OPS(mdss_runtime_suspend, mdss_runtime_resume, NULL)
518};
519
520static int mdss_probe(struct platform_device *pdev)
521{
522 struct msm_mdss *mdss;
523 bool is_mdp5 = of_device_is_compatible(pdev->dev.of_node, "qcom,mdss");
524 struct device *dev = &pdev->dev;
525 int ret;
526
527 mdss = msm_mdss_init(pdev, is_mdp5);
528 if (IS_ERR(mdss))
529 return PTR_ERR(mdss);
530
531 platform_set_drvdata(pdev, mdss);
532
533 /*
534 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
535 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
536 * Populate the children devices, find the MDP5/DPU node, and then add
537 * the interfaces to our components list.
538 */
539 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
540 if (ret) {
541 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
542 msm_mdss_destroy(mdss);
543 return ret;
544 }
545
546 return 0;
547}
548
549static void mdss_remove(struct platform_device *pdev)
550{
551 struct msm_mdss *mdss = platform_get_drvdata(pdev);
552
553 of_platform_depopulate(&pdev->dev);
554
555 msm_mdss_destroy(mdss);
556}
557
558static const struct msm_mdss_data msm8998_data = {
559 .ubwc_enc_version = UBWC_1_0,
560 .ubwc_dec_version = UBWC_1_0,
561 .highest_bank_bit = 2,
562 .reg_bus_bw = 76800,
563};
564
565static const struct msm_mdss_data qcm2290_data = {
566 /* no UBWC */
567 .highest_bank_bit = 0x2,
568 .reg_bus_bw = 76800,
569};
570
571static const struct msm_mdss_data sa8775p_data = {
572 .ubwc_enc_version = UBWC_4_0,
573 .ubwc_dec_version = UBWC_4_0,
574 .ubwc_swizzle = 4,
575 .ubwc_static = 1,
576 .highest_bank_bit = 0,
577 .macrotile_mode = 1,
578 .reg_bus_bw = 74000,
579};
580
581static const struct msm_mdss_data sc7180_data = {
582 .ubwc_enc_version = UBWC_2_0,
583 .ubwc_dec_version = UBWC_2_0,
584 .ubwc_static = 0x1e,
585 .highest_bank_bit = 0x1,
586 .reg_bus_bw = 76800,
587};
588
589static const struct msm_mdss_data sc7280_data = {
590 .ubwc_enc_version = UBWC_3_0,
591 .ubwc_dec_version = UBWC_4_0,
592 .ubwc_swizzle = 6,
593 .ubwc_static = 1,
594 .highest_bank_bit = 1,
595 .macrotile_mode = 1,
596 .reg_bus_bw = 74000,
597};
598
599static const struct msm_mdss_data sc8180x_data = {
600 .ubwc_enc_version = UBWC_3_0,
601 .ubwc_dec_version = UBWC_3_0,
602 .highest_bank_bit = 3,
603 .macrotile_mode = 1,
604 .reg_bus_bw = 76800,
605};
606
607static const struct msm_mdss_data sc8280xp_data = {
608 .ubwc_enc_version = UBWC_4_0,
609 .ubwc_dec_version = UBWC_4_0,
610 .ubwc_swizzle = 6,
611 .ubwc_static = 1,
612 .highest_bank_bit = 3,
613 .macrotile_mode = 1,
614 .reg_bus_bw = 76800,
615};
616
617static const struct msm_mdss_data sdm670_data = {
618 .ubwc_enc_version = UBWC_2_0,
619 .ubwc_dec_version = UBWC_2_0,
620 .highest_bank_bit = 1,
621 .reg_bus_bw = 76800,
622};
623
624static const struct msm_mdss_data sdm845_data = {
625 .ubwc_enc_version = UBWC_2_0,
626 .ubwc_dec_version = UBWC_2_0,
627 .highest_bank_bit = 2,
628 .reg_bus_bw = 76800,
629};
630
631static const struct msm_mdss_data sm6350_data = {
632 .ubwc_enc_version = UBWC_2_0,
633 .ubwc_dec_version = UBWC_2_0,
634 .ubwc_swizzle = 6,
635 .ubwc_static = 0x1e,
636 .highest_bank_bit = 1,
637 .reg_bus_bw = 76800,
638};
639
640static const struct msm_mdss_data sm7150_data = {
641 .ubwc_enc_version = UBWC_2_0,
642 .ubwc_dec_version = UBWC_2_0,
643 .highest_bank_bit = 1,
644 .reg_bus_bw = 76800,
645};
646
647static const struct msm_mdss_data sm8150_data = {
648 .ubwc_enc_version = UBWC_3_0,
649 .ubwc_dec_version = UBWC_3_0,
650 .highest_bank_bit = 2,
651 .reg_bus_bw = 76800,
652};
653
654static const struct msm_mdss_data sm6115_data = {
655 .ubwc_enc_version = UBWC_1_0,
656 .ubwc_dec_version = UBWC_2_0,
657 .ubwc_swizzle = 7,
658 .ubwc_static = 0x11f,
659 .highest_bank_bit = 0x1,
660 .reg_bus_bw = 76800,
661};
662
663static const struct msm_mdss_data sm6125_data = {
664 .ubwc_enc_version = UBWC_1_0,
665 .ubwc_dec_version = UBWC_3_0,
666 .ubwc_swizzle = 1,
667 .highest_bank_bit = 1,
668};
669
670static const struct msm_mdss_data sm8250_data = {
671 .ubwc_enc_version = UBWC_4_0,
672 .ubwc_dec_version = UBWC_4_0,
673 .ubwc_swizzle = 6,
674 .ubwc_static = 1,
675 /* TODO: highest_bank_bit = 2 for LP_DDR4 */
676 .highest_bank_bit = 3,
677 .macrotile_mode = 1,
678 .reg_bus_bw = 76800,
679};
680
681static const struct msm_mdss_data sm8350_data = {
682 .ubwc_enc_version = UBWC_4_0,
683 .ubwc_dec_version = UBWC_4_0,
684 .ubwc_swizzle = 6,
685 .ubwc_static = 1,
686 /* TODO: highest_bank_bit = 2 for LP_DDR4 */
687 .highest_bank_bit = 3,
688 .macrotile_mode = 1,
689 .reg_bus_bw = 74000,
690};
691
692static const struct msm_mdss_data sm8550_data = {
693 .ubwc_enc_version = UBWC_4_0,
694 .ubwc_dec_version = UBWC_4_3,
695 .ubwc_swizzle = 6,
696 .ubwc_static = 1,
697 /* TODO: highest_bank_bit = 2 for LP_DDR4 */
698 .highest_bank_bit = 3,
699 .macrotile_mode = 1,
700 .reg_bus_bw = 57000,
701};
702
703static const struct msm_mdss_data x1e80100_data = {
704 .ubwc_enc_version = UBWC_4_0,
705 .ubwc_dec_version = UBWC_4_3,
706 .ubwc_swizzle = 6,
707 .ubwc_static = 1,
708 /* TODO: highest_bank_bit = 2 for LP_DDR4 */
709 .highest_bank_bit = 3,
710 .macrotile_mode = 1,
711 /* TODO: Add reg_bus_bw with real value */
712};
713
714static const struct of_device_id mdss_dt_match[] = {
715 { .compatible = "qcom,mdss" },
716 { .compatible = "qcom,msm8998-mdss", .data = &msm8998_data },
717 { .compatible = "qcom,qcm2290-mdss", .data = &qcm2290_data },
718 { .compatible = "qcom,sa8775p-mdss", .data = &sa8775p_data },
719 { .compatible = "qcom,sdm670-mdss", .data = &sdm670_data },
720 { .compatible = "qcom,sdm845-mdss", .data = &sdm845_data },
721 { .compatible = "qcom,sc7180-mdss", .data = &sc7180_data },
722 { .compatible = "qcom,sc7280-mdss", .data = &sc7280_data },
723 { .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data },
724 { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
725 { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
726 { .compatible = "qcom,sm6125-mdss", .data = &sm6125_data },
727 { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
728 { .compatible = "qcom,sm6375-mdss", .data = &sm6350_data },
729 { .compatible = "qcom,sm7150-mdss", .data = &sm7150_data },
730 { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
731 { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
732 { .compatible = "qcom,sm8350-mdss", .data = &sm8350_data },
733 { .compatible = "qcom,sm8450-mdss", .data = &sm8350_data },
734 { .compatible = "qcom,sm8550-mdss", .data = &sm8550_data },
735 { .compatible = "qcom,sm8650-mdss", .data = &sm8550_data},
736 { .compatible = "qcom,x1e80100-mdss", .data = &x1e80100_data},
737 {}
738};
739MODULE_DEVICE_TABLE(of, mdss_dt_match);
740
741static struct platform_driver mdss_platform_driver = {
742 .probe = mdss_probe,
743 .remove = mdss_remove,
744 .driver = {
745 .name = "msm-mdss",
746 .of_match_table = mdss_dt_match,
747 .pm = &mdss_pm_ops,
748 },
749};
750
751void __init msm_mdss_register(void)
752{
753 platform_driver_register(&mdss_platform_driver);
754}
755
756void __exit msm_mdss_unregister(void)
757{
758 platform_driver_unregister(&mdss_platform_driver);
759}