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1/*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "amdgpu.h"
25#include "amdgpu_jpeg.h"
26#include "amdgpu_pm.h"
27#include "soc15.h"
28#include "soc15d.h"
29#include "jpeg_v2_0.h"
30#include "jpeg_v4_0_5.h"
31#include "mmsch_v4_0.h"
32
33#include "vcn/vcn_4_0_5_offset.h"
34#include "vcn/vcn_4_0_5_sh_mask.h"
35#include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
36
37#define regUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f
38
39static void jpeg_v4_0_5_set_dec_ring_funcs(struct amdgpu_device *adev);
40static void jpeg_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);
41static int jpeg_v4_0_5_set_powergating_state(void *handle,
42 enum amd_powergating_state state);
43
44static void jpeg_v4_0_5_dec_ring_set_wptr(struct amdgpu_ring *ring);
45
46/**
47 * jpeg_v4_0_5_early_init - set function pointers
48 *
49 * @handle: amdgpu_device pointer
50 *
51 * Set ring and irq function pointers
52 */
53static int jpeg_v4_0_5_early_init(void *handle)
54{
55 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
56
57
58 adev->jpeg.num_jpeg_inst = 1;
59 adev->jpeg.num_jpeg_rings = 1;
60
61 jpeg_v4_0_5_set_dec_ring_funcs(adev);
62 jpeg_v4_0_5_set_irq_funcs(adev);
63
64 return 0;
65}
66
67/**
68 * jpeg_v4_0_5_sw_init - sw init for JPEG block
69 *
70 * @handle: amdgpu_device pointer
71 *
72 * Load firmware and sw initialization
73 */
74static int jpeg_v4_0_5_sw_init(void *handle)
75{
76 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
77 struct amdgpu_ring *ring;
78 int r;
79
80 /* JPEG TRAP */
81 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
82 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
83 if (r)
84 return r;
85
86 /* JPEG DJPEG POISON EVENT */
87 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
88 VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->irq);
89 if (r)
90 return r;
91
92 /* JPEG EJPEG POISON EVENT */
93 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
94 VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->irq);
95 if (r)
96 return r;
97
98 r = amdgpu_jpeg_sw_init(adev);
99 if (r)
100 return r;
101
102 r = amdgpu_jpeg_resume(adev);
103 if (r)
104 return r;
105
106 ring = adev->jpeg.inst->ring_dec;
107 ring->use_doorbell = true;
108 ring->doorbell_index = amdgpu_sriov_vf(adev) ?
109 (((adev->doorbell_index.vcn.vcn_ring0_1) << 1) + 4) :
110 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1);
111 ring->vm_hub = AMDGPU_MMHUB0(0);
112
113 sprintf(ring->name, "jpeg_dec");
114 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
115 AMDGPU_RING_PRIO_DEFAULT, NULL);
116 if (r)
117 return r;
118
119 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET;
120 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH);
121
122 return 0;
123}
124
125/**
126 * jpeg_v4_0_5_sw_fini - sw fini for JPEG block
127 *
128 * @handle: amdgpu_device pointer
129 *
130 * JPEG suspend and free up sw allocation
131 */
132static int jpeg_v4_0_5_sw_fini(void *handle)
133{
134 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
135 int r;
136
137 r = amdgpu_jpeg_suspend(adev);
138 if (r)
139 return r;
140
141 r = amdgpu_jpeg_sw_fini(adev);
142
143 return r;
144}
145
146/**
147 * jpeg_v4_0_5_hw_init - start and test JPEG block
148 *
149 * @handle: amdgpu_device pointer
150 *
151 */
152static int jpeg_v4_0_5_hw_init(void *handle)
153{
154 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
155 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
156 int r;
157
158 r = amdgpu_ring_test_helper(ring);
159 if (r)
160 return r;
161
162 DRM_DEV_INFO(adev->dev, "JPEG decode initialized successfully.\n");
163
164 return 0;
165}
166
167/**
168 * jpeg_v4_0_5_hw_fini - stop the hardware block
169 *
170 * @handle: amdgpu_device pointer
171 *
172 * Stop the JPEG block, mark ring as not ready any more
173 */
174static int jpeg_v4_0_5_hw_fini(void *handle)
175{
176 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
177
178 cancel_delayed_work_sync(&adev->vcn.idle_work);
179 if (!amdgpu_sriov_vf(adev)) {
180 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
181 RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
182 jpeg_v4_0_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
183 }
184
185 return 0;
186}
187
188/**
189 * jpeg_v4_0_5_suspend - suspend JPEG block
190 *
191 * @handle: amdgpu_device pointer
192 *
193 * HW fini and suspend JPEG block
194 */
195static int jpeg_v4_0_5_suspend(void *handle)
196{
197 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
198 int r;
199
200 r = jpeg_v4_0_5_hw_fini(adev);
201 if (r)
202 return r;
203
204 r = amdgpu_jpeg_suspend(adev);
205
206 return r;
207}
208
209/**
210 * jpeg_v4_0_5_resume - resume JPEG block
211 *
212 * @handle: amdgpu_device pointer
213 *
214 * Resume firmware and hw init JPEG block
215 */
216static int jpeg_v4_0_5_resume(void *handle)
217{
218 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
219 int r;
220
221 r = amdgpu_jpeg_resume(adev);
222 if (r)
223 return r;
224
225 r = jpeg_v4_0_5_hw_init(adev);
226
227 return r;
228}
229
230static void jpeg_v4_0_5_disable_clock_gating(struct amdgpu_device *adev)
231{
232 uint32_t data = 0;
233
234 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);
235 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) {
236 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
237 data &= (~JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK);
238 } else {
239 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
240 }
241
242 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
243 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
244 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data);
245
246 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);
247 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
248 | JPEG_CGC_GATE__JPEG2_DEC_MASK
249 | JPEG_CGC_GATE__JMCIF_MASK
250 | JPEG_CGC_GATE__JRBBM_MASK);
251 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data);
252}
253
254static void jpeg_v4_0_5_enable_clock_gating(struct amdgpu_device *adev)
255{
256 uint32_t data = 0;
257
258 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);
259 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) {
260 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
261 data |= JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK;
262 } else {
263 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
264 }
265
266 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
267 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
268 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data);
269
270 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);
271 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
272 |JPEG_CGC_GATE__JPEG2_DEC_MASK
273 |JPEG_CGC_GATE__JMCIF_MASK
274 |JPEG_CGC_GATE__JRBBM_MASK);
275 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data);
276}
277
278static int jpeg_v4_0_5_disable_static_power_gating(struct amdgpu_device *adev)
279{
280 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
281 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_IPX_DLDO_CONFIG),
282 1 << UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG__SHIFT);
283 SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS,
284 0, UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK);
285 }
286
287 /* disable anti hang mechanism */
288 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,
289 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
290
291 /* keep the JPEG in static PG mode */
292 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,
293 ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK);
294
295 return 0;
296}
297
298static int jpeg_v4_0_5_enable_static_power_gating(struct amdgpu_device *adev)
299{
300 /* enable anti hang mechanism */
301 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS),
302 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
303 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
304
305 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
306 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_IPX_DLDO_CONFIG),
307 2 << UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG__SHIFT);
308 SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS,
309 1 << UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS__SHIFT,
310 UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK);
311 }
312
313 return 0;
314}
315
316/**
317 * jpeg_v4_0_5_start - start JPEG block
318 *
319 * @adev: amdgpu_device pointer
320 *
321 * Setup and start the JPEG block
322 */
323static int jpeg_v4_0_5_start(struct amdgpu_device *adev)
324{
325 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
326 int r;
327
328 if (adev->pm.dpm_enabled)
329 amdgpu_dpm_enable_jpeg(adev, true);
330
331 /* doorbell programming is done for every playback */
332 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
333 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
334
335 WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL,
336 ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT |
337 VCN_JPEG_DB_CTRL__EN_MASK);
338
339 /* disable power gating */
340 r = jpeg_v4_0_5_disable_static_power_gating(adev);
341 if (r)
342 return r;
343
344 /* JPEG disable CGC */
345 jpeg_v4_0_5_disable_clock_gating(adev);
346
347 /* MJPEG global tiling registers */
348 WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG,
349 adev->gfx.config.gb_addr_config);
350
351
352 /* enable JMI channel */
353 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0,
354 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
355
356 /* enable System Interrupt for JRBC */
357 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN),
358 JPEG_SYS_INT_EN__DJRBC_MASK,
359 ~JPEG_SYS_INT_EN__DJRBC_MASK);
360
361 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0);
362 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
363 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
364 lower_32_bits(ring->gpu_addr));
365 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
366 upper_32_bits(ring->gpu_addr));
367 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR, 0);
368 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0);
369 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, 0x00000002L);
370 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_SIZE, ring->ring_size / 4);
371 ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);
372
373 return 0;
374}
375
376/**
377 * jpeg_v4_0_5_stop - stop JPEG block
378 *
379 * @adev: amdgpu_device pointer
380 *
381 * stop the JPEG block
382 */
383static int jpeg_v4_0_5_stop(struct amdgpu_device *adev)
384{
385 int r;
386
387 /* reset JMI */
388 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL),
389 UVD_JMI_CNTL__SOFT_RESET_MASK,
390 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
391
392 jpeg_v4_0_5_enable_clock_gating(adev);
393
394 /* enable power gating */
395 r = jpeg_v4_0_5_enable_static_power_gating(adev);
396 if (r)
397 return r;
398
399 if (adev->pm.dpm_enabled)
400 amdgpu_dpm_enable_jpeg(adev, false);
401
402 return 0;
403}
404
405/**
406 * jpeg_v4_0_5_dec_ring_get_rptr - get read pointer
407 *
408 * @ring: amdgpu_ring pointer
409 *
410 * Returns the current hardware read pointer
411 */
412static uint64_t jpeg_v4_0_5_dec_ring_get_rptr(struct amdgpu_ring *ring)
413{
414 struct amdgpu_device *adev = ring->adev;
415
416 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR);
417}
418
419/**
420 * jpeg_v4_0_5_dec_ring_get_wptr - get write pointer
421 *
422 * @ring: amdgpu_ring pointer
423 *
424 * Returns the current hardware write pointer
425 */
426static uint64_t jpeg_v4_0_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
427{
428 struct amdgpu_device *adev = ring->adev;
429
430 if (ring->use_doorbell)
431 return *ring->wptr_cpu_addr;
432 else
433 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);
434}
435
436/**
437 * jpeg_v4_0_5_dec_ring_set_wptr - set write pointer
438 *
439 * @ring: amdgpu_ring pointer
440 *
441 * Commits the write pointer to the hardware
442 */
443static void jpeg_v4_0_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
444{
445 struct amdgpu_device *adev = ring->adev;
446
447 if (ring->use_doorbell) {
448 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
449 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
450 } else {
451 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
452 }
453}
454
455static bool jpeg_v4_0_5_is_idle(void *handle)
456{
457 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
458 int ret = 1;
459
460 ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) &
461 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
462 UVD_JRBC_STATUS__RB_JOB_DONE_MASK));
463
464 return ret;
465}
466
467static int jpeg_v4_0_5_wait_for_idle(void *handle)
468{
469 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
470
471 return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS,
472 UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
473 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
474}
475
476static int jpeg_v4_0_5_set_clockgating_state(void *handle,
477 enum amd_clockgating_state state)
478{
479 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
480 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
481
482 if (enable) {
483 if (!jpeg_v4_0_5_is_idle(handle))
484 return -EBUSY;
485 jpeg_v4_0_5_enable_clock_gating(adev);
486 } else {
487 jpeg_v4_0_5_disable_clock_gating(adev);
488 }
489
490 return 0;
491}
492
493static int jpeg_v4_0_5_set_powergating_state(void *handle,
494 enum amd_powergating_state state)
495{
496 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
497 int ret;
498
499 if (amdgpu_sriov_vf(adev)) {
500 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE;
501 return 0;
502 }
503
504 if (state == adev->jpeg.cur_state)
505 return 0;
506
507 if (state == AMD_PG_STATE_GATE)
508 ret = jpeg_v4_0_5_stop(adev);
509 else
510 ret = jpeg_v4_0_5_start(adev);
511
512 if (!ret)
513 adev->jpeg.cur_state = state;
514
515 return ret;
516}
517
518static int jpeg_v4_0_5_process_interrupt(struct amdgpu_device *adev,
519 struct amdgpu_irq_src *source,
520 struct amdgpu_iv_entry *entry)
521{
522 DRM_DEBUG("IH: JPEG TRAP\n");
523
524 switch (entry->src_id) {
525 case VCN_4_0__SRCID__JPEG_DECODE:
526 amdgpu_fence_process(adev->jpeg.inst->ring_dec);
527 break;
528 case VCN_4_0__SRCID_DJPEG0_POISON:
529 case VCN_4_0__SRCID_EJPEG0_POISON:
530 amdgpu_jpeg_process_poison_irq(adev, source, entry);
531 break;
532 default:
533 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n",
534 entry->src_id, entry->src_data[0]);
535 break;
536 }
537
538 return 0;
539}
540
541static const struct amd_ip_funcs jpeg_v4_0_5_ip_funcs = {
542 .name = "jpeg_v4_0_5",
543 .early_init = jpeg_v4_0_5_early_init,
544 .late_init = NULL,
545 .sw_init = jpeg_v4_0_5_sw_init,
546 .sw_fini = jpeg_v4_0_5_sw_fini,
547 .hw_init = jpeg_v4_0_5_hw_init,
548 .hw_fini = jpeg_v4_0_5_hw_fini,
549 .suspend = jpeg_v4_0_5_suspend,
550 .resume = jpeg_v4_0_5_resume,
551 .is_idle = jpeg_v4_0_5_is_idle,
552 .wait_for_idle = jpeg_v4_0_5_wait_for_idle,
553 .check_soft_reset = NULL,
554 .pre_soft_reset = NULL,
555 .soft_reset = NULL,
556 .post_soft_reset = NULL,
557 .set_clockgating_state = jpeg_v4_0_5_set_clockgating_state,
558 .set_powergating_state = jpeg_v4_0_5_set_powergating_state,
559};
560
561static const struct amdgpu_ring_funcs jpeg_v4_0_5_dec_ring_vm_funcs = {
562 .type = AMDGPU_RING_TYPE_VCN_JPEG,
563 .align_mask = 0xf,
564 .get_rptr = jpeg_v4_0_5_dec_ring_get_rptr,
565 .get_wptr = jpeg_v4_0_5_dec_ring_get_wptr,
566 .set_wptr = jpeg_v4_0_5_dec_ring_set_wptr,
567 .emit_frame_size =
568 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
569 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
570 8 + /* jpeg_v4_0_5_dec_ring_emit_vm_flush */
571 18 + 18 + /* jpeg_v4_0_5_dec_ring_emit_fence x2 vm fence */
572 8 + 16,
573 .emit_ib_size = 22, /* jpeg_v4_0_5_dec_ring_emit_ib */
574 .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
575 .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
576 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
577 .test_ring = amdgpu_jpeg_dec_ring_test_ring,
578 .test_ib = amdgpu_jpeg_dec_ring_test_ib,
579 .insert_nop = jpeg_v2_0_dec_ring_nop,
580 .insert_start = jpeg_v2_0_dec_ring_insert_start,
581 .insert_end = jpeg_v2_0_dec_ring_insert_end,
582 .pad_ib = amdgpu_ring_generic_pad_ib,
583 .begin_use = amdgpu_jpeg_ring_begin_use,
584 .end_use = amdgpu_jpeg_ring_end_use,
585 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
586 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
587 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
588};
589
590static void jpeg_v4_0_5_set_dec_ring_funcs(struct amdgpu_device *adev)
591{
592 adev->jpeg.inst->ring_dec->funcs = &jpeg_v4_0_5_dec_ring_vm_funcs;
593 DRM_DEV_INFO(adev->dev, "JPEG decode is enabled in VM mode\n");
594}
595
596static const struct amdgpu_irq_src_funcs jpeg_v4_0_5_irq_funcs = {
597 .process = jpeg_v4_0_5_process_interrupt,
598};
599
600static void jpeg_v4_0_5_set_irq_funcs(struct amdgpu_device *adev)
601{
602 adev->jpeg.inst->irq.num_types = 1;
603 adev->jpeg.inst->irq.funcs = &jpeg_v4_0_5_irq_funcs;
604}
605
606const struct amdgpu_ip_block_version jpeg_v4_0_5_ip_block = {
607 .type = AMD_IP_BLOCK_TYPE_JPEG,
608 .major = 4,
609 .minor = 0,
610 .rev = 5,
611 .funcs = &jpeg_v4_0_5_ip_funcs,
612};
613
1/*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "amdgpu.h"
25#include "amdgpu_jpeg.h"
26#include "amdgpu_pm.h"
27#include "soc15.h"
28#include "soc15d.h"
29#include "jpeg_v2_0.h"
30#include "jpeg_v4_0_5.h"
31#include "mmsch_v4_0.h"
32
33#include "vcn/vcn_4_0_5_offset.h"
34#include "vcn/vcn_4_0_5_sh_mask.h"
35#include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
36
37#define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL
38#define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX
39#define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA
40#define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX
41
42#define regUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f
43#define regJPEG_DEC_GFX10_ADDR_CONFIG_INTERNAL_OFFSET 0x4026
44#define regJPEG_SYS_INT_EN_INTERNAL_OFFSET 0x4141
45#define regJPEG_CGC_CTRL_INTERNAL_OFFSET 0x4161
46#define regJPEG_CGC_GATE_INTERNAL_OFFSET 0x4160
47#define regUVD_NO_OP_INTERNAL_OFFSET 0x0029
48
49static void jpeg_v4_0_5_set_dec_ring_funcs(struct amdgpu_device *adev);
50static void jpeg_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);
51static int jpeg_v4_0_5_set_powergating_state(void *handle,
52 enum amd_powergating_state state);
53
54static void jpeg_v4_0_5_dec_ring_set_wptr(struct amdgpu_ring *ring);
55
56static int amdgpu_ih_clientid_jpeg[] = {
57 SOC15_IH_CLIENTID_VCN,
58 SOC15_IH_CLIENTID_VCN1
59};
60
61/**
62 * jpeg_v4_0_5_early_init - set function pointers
63 *
64 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
65 *
66 * Set ring and irq function pointers
67 */
68static int jpeg_v4_0_5_early_init(struct amdgpu_ip_block *ip_block)
69{
70 struct amdgpu_device *adev = ip_block->adev;
71
72 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
73 case IP_VERSION(4, 0, 5):
74 adev->jpeg.num_jpeg_inst = 1;
75 break;
76 case IP_VERSION(4, 0, 6):
77 adev->jpeg.num_jpeg_inst = 2;
78 break;
79 default:
80 DRM_DEV_ERROR(adev->dev,
81 "Failed to init vcn ip block(UVD_HWIP:0x%x)\n",
82 amdgpu_ip_version(adev, UVD_HWIP, 0));
83 return -EINVAL;
84 }
85
86 adev->jpeg.num_jpeg_rings = 1;
87
88 jpeg_v4_0_5_set_dec_ring_funcs(adev);
89 jpeg_v4_0_5_set_irq_funcs(adev);
90
91 return 0;
92}
93
94/**
95 * jpeg_v4_0_5_sw_init - sw init for JPEG block
96 *
97 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
98 *
99 * Load firmware and sw initialization
100 */
101static int jpeg_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block)
102{
103 struct amdgpu_device *adev = ip_block->adev;
104 struct amdgpu_ring *ring;
105 int r, i;
106
107 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
108 if (adev->jpeg.harvest_config & (1 << i))
109 continue;
110
111 /* JPEG TRAP */
112 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i],
113 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq);
114 if (r)
115 return r;
116
117 /* JPEG DJPEG POISON EVENT */
118 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i],
119 VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst[i].irq);
120 if (r)
121 return r;
122
123 /* JPEG EJPEG POISON EVENT */
124 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i],
125 VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst[i].irq);
126 if (r)
127 return r;
128 }
129
130 r = amdgpu_jpeg_sw_init(adev);
131 if (r)
132 return r;
133
134 r = amdgpu_jpeg_resume(adev);
135 if (r)
136 return r;
137
138 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
139 if (adev->jpeg.harvest_config & (1 << i))
140 continue;
141
142 ring = adev->jpeg.inst[i].ring_dec;
143 ring->use_doorbell = true;
144 ring->vm_hub = AMDGPU_MMHUB0(0);
145 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8 * i;
146 sprintf(ring->name, "jpeg_dec_%d", i);
147 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq,
148 0, AMDGPU_RING_PRIO_DEFAULT, NULL);
149 if (r)
150 return r;
151
152 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET;
153 adev->jpeg.inst[i].external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, i, regUVD_JPEG_PITCH);
154 }
155
156 /* TODO: Add queue reset mask when FW fully supports it */
157 adev->jpeg.supported_reset =
158 amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]);
159 r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
160 if (r)
161 return r;
162
163 return 0;
164}
165
166/**
167 * jpeg_v4_0_5_sw_fini - sw fini for JPEG block
168 *
169 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
170 *
171 * JPEG suspend and free up sw allocation
172 */
173static int jpeg_v4_0_5_sw_fini(struct amdgpu_ip_block *ip_block)
174{
175 struct amdgpu_device *adev = ip_block->adev;
176 int r;
177
178 r = amdgpu_jpeg_suspend(adev);
179 if (r)
180 return r;
181
182 amdgpu_jpeg_sysfs_reset_mask_fini(adev);
183 r = amdgpu_jpeg_sw_fini(adev);
184
185 return r;
186}
187
188/**
189 * jpeg_v4_0_5_hw_init - start and test JPEG block
190 *
191 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
192 *
193 */
194static int jpeg_v4_0_5_hw_init(struct amdgpu_ip_block *ip_block)
195{
196 struct amdgpu_device *adev = ip_block->adev;
197 struct amdgpu_ring *ring;
198 int i, r = 0;
199
200 // TODO: Enable ring test with DPG support
201 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG) {
202 return 0;
203 }
204
205 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
206 if (adev->jpeg.harvest_config & (1 << i))
207 continue;
208
209 ring = adev->jpeg.inst[i].ring_dec;
210 r = amdgpu_ring_test_helper(ring);
211 if (r)
212 return r;
213 }
214
215 return 0;
216}
217
218/**
219 * jpeg_v4_0_5_hw_fini - stop the hardware block
220 *
221 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
222 *
223 * Stop the JPEG block, mark ring as not ready any more
224 */
225static int jpeg_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block)
226{
227 struct amdgpu_device *adev = ip_block->adev;
228 int i;
229
230 cancel_delayed_work_sync(&adev->jpeg.idle_work);
231
232 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
233 if (adev->jpeg.harvest_config & (1 << i))
234 continue;
235
236 if (!amdgpu_sriov_vf(adev)) {
237 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
238 RREG32_SOC15(JPEG, i, regUVD_JRBC_STATUS))
239 jpeg_v4_0_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
240 }
241 }
242 return 0;
243}
244
245/**
246 * jpeg_v4_0_5_suspend - suspend JPEG block
247 *
248 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
249 *
250 * HW fini and suspend JPEG block
251 */
252static int jpeg_v4_0_5_suspend(struct amdgpu_ip_block *ip_block)
253{
254 int r;
255
256 r = jpeg_v4_0_5_hw_fini(ip_block);
257 if (r)
258 return r;
259
260 r = amdgpu_jpeg_suspend(ip_block->adev);
261
262 return r;
263}
264
265/**
266 * jpeg_v4_0_5_resume - resume JPEG block
267 *
268 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
269 *
270 * Resume firmware and hw init JPEG block
271 */
272static int jpeg_v4_0_5_resume(struct amdgpu_ip_block *ip_block)
273{
274 int r;
275
276 r = amdgpu_jpeg_resume(ip_block->adev);
277 if (r)
278 return r;
279
280 r = jpeg_v4_0_5_hw_init(ip_block);
281
282 return r;
283}
284
285static void jpeg_v4_0_5_disable_clock_gating(struct amdgpu_device *adev, int inst)
286{
287 uint32_t data = 0;
288
289 data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL);
290 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) {
291 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
292 data &= (~JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK);
293 } else {
294 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
295 }
296
297 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
298 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
299 WREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL, data);
300
301 data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE);
302 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
303 | JPEG_CGC_GATE__JPEG2_DEC_MASK
304 | JPEG_CGC_GATE__JMCIF_MASK
305 | JPEG_CGC_GATE__JRBBM_MASK);
306 WREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE, data);
307}
308
309static void jpeg_v4_0_5_enable_clock_gating(struct amdgpu_device *adev, int inst)
310{
311 uint32_t data = 0;
312
313 data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL);
314 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) {
315 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
316 data |= JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK;
317 } else {
318 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
319 }
320
321 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
322 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
323 WREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL, data);
324
325 data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE);
326 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
327 |JPEG_CGC_GATE__JPEG2_DEC_MASK
328 |JPEG_CGC_GATE__JMCIF_MASK
329 |JPEG_CGC_GATE__JRBBM_MASK);
330 WREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE, data);
331}
332
333static void jpeg_engine_4_0_5_dpg_clock_gating_mode(struct amdgpu_device *adev,
334 int inst_idx, uint8_t indirect)
335{
336 uint32_t data = 0;
337
338 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
339 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
340 else
341 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
342
343 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
344 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
345 WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regJPEG_CGC_CTRL_INTERNAL_OFFSET, data, indirect);
346
347 data = 0;
348 WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regJPEG_CGC_GATE_INTERNAL_OFFSET,
349 data, indirect);
350}
351
352static int jpeg_v4_0_5_disable_static_power_gating(struct amdgpu_device *adev, int inst)
353{
354 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
355 WREG32(SOC15_REG_OFFSET(JPEG, inst, regUVD_IPX_DLDO_CONFIG),
356 1 << UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG__SHIFT);
357 SOC15_WAIT_ON_RREG(JPEG, inst, regUVD_IPX_DLDO_STATUS,
358 0, UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK);
359 }
360
361 /* disable anti hang mechanism */
362 WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS), 0,
363 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
364
365 /* keep the JPEG in static PG mode */
366 WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS), 0,
367 ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK);
368
369 return 0;
370}
371
372static int jpeg_v4_0_5_enable_static_power_gating(struct amdgpu_device *adev, int inst)
373{
374 /* enable anti hang mechanism */
375 WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS),
376 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
377 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
378
379 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
380 WREG32(SOC15_REG_OFFSET(JPEG, inst, regUVD_IPX_DLDO_CONFIG),
381 2 << UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG__SHIFT);
382 SOC15_WAIT_ON_RREG(JPEG, inst, regUVD_IPX_DLDO_STATUS,
383 1 << UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS__SHIFT,
384 UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK);
385 }
386
387 return 0;
388}
389
390/**
391 * jpeg_v4_0_5_start_dpg_mode - Jpeg start with dpg mode
392 *
393 * @adev: amdgpu_device pointer
394 * @inst_idx: instance number index
395 * @indirect: indirectly write sram
396 *
397 * Start JPEG block with dpg mode
398 */
399static void jpeg_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
400{
401 struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec;
402 uint32_t reg_data = 0;
403
404 /* enable anti hang mechanism */
405 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);
406 reg_data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK;
407 reg_data |= 0x1;
408 WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data);
409
410 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
411 WREG32(SOC15_REG_OFFSET(JPEG, inst_idx, regUVD_IPX_DLDO_CONFIG),
412 2 << UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG__SHIFT);
413 SOC15_WAIT_ON_RREG(JPEG, inst_idx, regUVD_IPX_DLDO_STATUS,
414 1 << UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS__SHIFT,
415 UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK);
416 }
417
418 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);
419 reg_data |= UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK;
420 WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data);
421
422 if (indirect)
423 adev->jpeg.inst[inst_idx].dpg_sram_curr_addr =
424 (uint32_t *)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr;
425
426 jpeg_engine_4_0_5_dpg_clock_gating_mode(adev, inst_idx, indirect);
427
428 /* MJPEG global tiling registers */
429 WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regJPEG_DEC_GFX10_ADDR_CONFIG_INTERNAL_OFFSET,
430 adev->gfx.config.gb_addr_config, indirect);
431 /* enable System Interrupt for JRBC */
432 WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regJPEG_SYS_INT_EN_INTERNAL_OFFSET,
433 JPEG_SYS_INT_EN__DJRBC_MASK, indirect);
434
435 /* add nop to workaround PSP size check */
436 WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regUVD_NO_OP_INTERNAL_OFFSET, 0, indirect);
437
438 if (indirect)
439 amdgpu_jpeg_psp_update_sram(adev, inst_idx, 0);
440
441 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_VMID, 0);
442 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
443 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
444 lower_32_bits(ring->gpu_addr));
445 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
446 upper_32_bits(ring->gpu_addr));
447 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_RPTR, 0);
448 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR, 0);
449 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_CNTL, 0x00000002L);
450 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_SIZE, ring->ring_size / 4);
451 ring->wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR);
452}
453
454/**
455 * jpeg_v4_0_5_stop_dpg_mode - Jpeg stop with dpg mode
456 *
457 * @adev: amdgpu_device pointer
458 * @inst_idx: instance number index
459 *
460 * Stop JPEG block with dpg mode
461 */
462static void jpeg_v4_0_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
463{
464 uint32_t reg_data = 0;
465
466 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);
467 reg_data &= ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK;
468 WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data);
469
470}
471
472/**
473 * jpeg_v4_0_5_start - start JPEG block
474 *
475 * @adev: amdgpu_device pointer
476 *
477 * Setup and start the JPEG block
478 */
479static int jpeg_v4_0_5_start(struct amdgpu_device *adev)
480{
481 struct amdgpu_ring *ring;
482 int r, i;
483
484 if (adev->pm.dpm_enabled)
485 amdgpu_dpm_enable_jpeg(adev, true);
486
487 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
488 if (adev->jpeg.harvest_config & (1 << i))
489 continue;
490
491 ring = adev->jpeg.inst[i].ring_dec;
492 /* doorbell programming is done for every playback */
493 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
494 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i, i);
495
496 WREG32_SOC15(VCN, i, regVCN_JPEG_DB_CTRL,
497 ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT |
498 VCN_JPEG_DB_CTRL__EN_MASK);
499
500 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG) {
501 jpeg_v4_0_5_start_dpg_mode(adev, i, adev->jpeg.indirect_sram);
502 continue;
503 }
504
505 /* disable power gating */
506 r = jpeg_v4_0_5_disable_static_power_gating(adev, i);
507 if (r)
508 return r;
509
510 /* JPEG disable CGC */
511 jpeg_v4_0_5_disable_clock_gating(adev, i);
512
513 /* MJPEG global tiling registers */
514 WREG32_SOC15(JPEG, i, regJPEG_DEC_GFX10_ADDR_CONFIG,
515 adev->gfx.config.gb_addr_config);
516
517 /* enable JMI channel */
518 WREG32_P(SOC15_REG_OFFSET(JPEG, i, regUVD_JMI_CNTL), 0,
519 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
520
521 /* enable System Interrupt for JRBC */
522 WREG32_P(SOC15_REG_OFFSET(JPEG, i, regJPEG_SYS_INT_EN),
523 JPEG_SYS_INT_EN__DJRBC_MASK,
524 ~JPEG_SYS_INT_EN__DJRBC_MASK);
525
526 WREG32_SOC15(JPEG, i, regUVD_LMI_JRBC_RB_VMID, 0);
527 WREG32_SOC15(JPEG, i, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
528 WREG32_SOC15(JPEG, i, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
529 lower_32_bits(ring->gpu_addr));
530 WREG32_SOC15(JPEG, i, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
531 upper_32_bits(ring->gpu_addr));
532 WREG32_SOC15(JPEG, i, regUVD_JRBC_RB_RPTR, 0);
533 WREG32_SOC15(JPEG, i, regUVD_JRBC_RB_WPTR, 0);
534 WREG32_SOC15(JPEG, i, regUVD_JRBC_RB_CNTL, 0x00000002L);
535 WREG32_SOC15(JPEG, i, regUVD_JRBC_RB_SIZE, ring->ring_size / 4);
536 ring->wptr = RREG32_SOC15(JPEG, i, regUVD_JRBC_RB_WPTR);
537 }
538
539 return 0;
540}
541
542/**
543 * jpeg_v4_0_5_stop - stop JPEG block
544 *
545 * @adev: amdgpu_device pointer
546 *
547 * stop the JPEG block
548 */
549static int jpeg_v4_0_5_stop(struct amdgpu_device *adev)
550{
551 int r, i;
552
553 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
554 if (adev->jpeg.harvest_config & (1 << i))
555 continue;
556
557 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG) {
558 jpeg_v4_0_5_stop_dpg_mode(adev, i);
559 continue;
560 }
561
562 /* reset JMI */
563 WREG32_P(SOC15_REG_OFFSET(JPEG, i, regUVD_JMI_CNTL),
564 UVD_JMI_CNTL__SOFT_RESET_MASK,
565 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
566
567 jpeg_v4_0_5_enable_clock_gating(adev, i);
568
569 /* enable power gating */
570 r = jpeg_v4_0_5_enable_static_power_gating(adev, i);
571 if (r)
572 return r;
573 }
574 if (adev->pm.dpm_enabled)
575 amdgpu_dpm_enable_jpeg(adev, false);
576
577 return 0;
578}
579
580/**
581 * jpeg_v4_0_5_dec_ring_get_rptr - get read pointer
582 *
583 * @ring: amdgpu_ring pointer
584 *
585 * Returns the current hardware read pointer
586 */
587static uint64_t jpeg_v4_0_5_dec_ring_get_rptr(struct amdgpu_ring *ring)
588{
589 struct amdgpu_device *adev = ring->adev;
590
591 return RREG32_SOC15(JPEG, ring->me, regUVD_JRBC_RB_RPTR);
592}
593
594/**
595 * jpeg_v4_0_5_dec_ring_get_wptr - get write pointer
596 *
597 * @ring: amdgpu_ring pointer
598 *
599 * Returns the current hardware write pointer
600 */
601static uint64_t jpeg_v4_0_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
602{
603 struct amdgpu_device *adev = ring->adev;
604
605 if (ring->use_doorbell)
606 return *ring->wptr_cpu_addr;
607 else
608 return RREG32_SOC15(JPEG, ring->me, regUVD_JRBC_RB_WPTR);
609}
610
611/**
612 * jpeg_v4_0_5_dec_ring_set_wptr - set write pointer
613 *
614 * @ring: amdgpu_ring pointer
615 *
616 * Commits the write pointer to the hardware
617 */
618static void jpeg_v4_0_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
619{
620 struct amdgpu_device *adev = ring->adev;
621
622 if (ring->use_doorbell) {
623 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
624 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
625 } else {
626 WREG32_SOC15(JPEG, ring->me, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
627 }
628}
629
630static bool jpeg_v4_0_5_is_idle(void *handle)
631{
632 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
633 int i, ret = 1;
634
635 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
636 if (adev->jpeg.harvest_config & (1 << i))
637 continue;
638
639 ret &= (((RREG32_SOC15(JPEG, i, regUVD_JRBC_STATUS) &
640 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
641 UVD_JRBC_STATUS__RB_JOB_DONE_MASK));
642 }
643 return ret;
644}
645
646static int jpeg_v4_0_5_wait_for_idle(struct amdgpu_ip_block *ip_block)
647{
648 struct amdgpu_device *adev = ip_block->adev;
649 int i;
650
651 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
652 if (adev->jpeg.harvest_config & (1 << i))
653 continue;
654
655 return SOC15_WAIT_ON_RREG(JPEG, i, regUVD_JRBC_STATUS,
656 UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
657 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
658 }
659
660 return 0;
661}
662
663static int jpeg_v4_0_5_set_clockgating_state(void *handle,
664 enum amd_clockgating_state state)
665{
666 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
667 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
668 int i;
669
670 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
671 if (adev->jpeg.harvest_config & (1 << i))
672 continue;
673
674 if (enable) {
675 if (!jpeg_v4_0_5_is_idle(handle))
676 return -EBUSY;
677
678 jpeg_v4_0_5_enable_clock_gating(adev, i);
679 } else {
680 jpeg_v4_0_5_disable_clock_gating(adev, i);
681 }
682 }
683
684 return 0;
685}
686
687static int jpeg_v4_0_5_set_powergating_state(void *handle,
688 enum amd_powergating_state state)
689{
690 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
691 int ret;
692
693 if (amdgpu_sriov_vf(adev)) {
694 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE;
695 return 0;
696 }
697
698 if (state == adev->jpeg.cur_state)
699 return 0;
700
701 if (state == AMD_PG_STATE_GATE)
702 ret = jpeg_v4_0_5_stop(adev);
703 else
704 ret = jpeg_v4_0_5_start(adev);
705
706 if (!ret)
707 adev->jpeg.cur_state = state;
708
709 return ret;
710}
711
712static int jpeg_v4_0_5_process_interrupt(struct amdgpu_device *adev,
713 struct amdgpu_irq_src *source,
714 struct amdgpu_iv_entry *entry)
715{
716 uint32_t ip_instance;
717
718 DRM_DEBUG("IH: JPEG TRAP\n");
719
720 switch (entry->client_id) {
721 case SOC15_IH_CLIENTID_VCN:
722 ip_instance = 0;
723 break;
724 case SOC15_IH_CLIENTID_VCN1:
725 ip_instance = 1;
726 break;
727 default:
728 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
729 return 0;
730 }
731
732 switch (entry->src_id) {
733 case VCN_4_0__SRCID__JPEG_DECODE:
734 amdgpu_fence_process(adev->jpeg.inst[ip_instance].ring_dec);
735 break;
736 case VCN_4_0__SRCID_DJPEG0_POISON:
737 case VCN_4_0__SRCID_EJPEG0_POISON:
738 amdgpu_jpeg_process_poison_irq(adev, source, entry);
739 break;
740 default:
741 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n",
742 entry->src_id, entry->src_data[0]);
743 break;
744 }
745
746 return 0;
747}
748
749static const struct amd_ip_funcs jpeg_v4_0_5_ip_funcs = {
750 .name = "jpeg_v4_0_5",
751 .early_init = jpeg_v4_0_5_early_init,
752 .sw_init = jpeg_v4_0_5_sw_init,
753 .sw_fini = jpeg_v4_0_5_sw_fini,
754 .hw_init = jpeg_v4_0_5_hw_init,
755 .hw_fini = jpeg_v4_0_5_hw_fini,
756 .suspend = jpeg_v4_0_5_suspend,
757 .resume = jpeg_v4_0_5_resume,
758 .is_idle = jpeg_v4_0_5_is_idle,
759 .wait_for_idle = jpeg_v4_0_5_wait_for_idle,
760 .set_clockgating_state = jpeg_v4_0_5_set_clockgating_state,
761 .set_powergating_state = jpeg_v4_0_5_set_powergating_state,
762};
763
764static const struct amdgpu_ring_funcs jpeg_v4_0_5_dec_ring_vm_funcs = {
765 .type = AMDGPU_RING_TYPE_VCN_JPEG,
766 .align_mask = 0xf,
767 .get_rptr = jpeg_v4_0_5_dec_ring_get_rptr,
768 .get_wptr = jpeg_v4_0_5_dec_ring_get_wptr,
769 .set_wptr = jpeg_v4_0_5_dec_ring_set_wptr,
770 .parse_cs = jpeg_v2_dec_ring_parse_cs,
771 .emit_frame_size =
772 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
773 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
774 8 + /* jpeg_v4_0_5_dec_ring_emit_vm_flush */
775 18 + 18 + /* jpeg_v4_0_5_dec_ring_emit_fence x2 vm fence */
776 8 + 16,
777 .emit_ib_size = 22, /* jpeg_v4_0_5_dec_ring_emit_ib */
778 .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
779 .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
780 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
781 .test_ring = amdgpu_jpeg_dec_ring_test_ring,
782 .test_ib = amdgpu_jpeg_dec_ring_test_ib,
783 .insert_nop = jpeg_v2_0_dec_ring_nop,
784 .insert_start = jpeg_v2_0_dec_ring_insert_start,
785 .insert_end = jpeg_v2_0_dec_ring_insert_end,
786 .pad_ib = amdgpu_ring_generic_pad_ib,
787 .begin_use = amdgpu_jpeg_ring_begin_use,
788 .end_use = amdgpu_jpeg_ring_end_use,
789 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
790 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
791 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
792};
793
794static void jpeg_v4_0_5_set_dec_ring_funcs(struct amdgpu_device *adev)
795{
796 int i;
797
798 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
799 if (adev->jpeg.harvest_config & (1 << i))
800 continue;
801
802 adev->jpeg.inst[i].ring_dec->funcs = &jpeg_v4_0_5_dec_ring_vm_funcs;
803 adev->jpeg.inst[i].ring_dec->me = i;
804 }
805}
806
807static const struct amdgpu_irq_src_funcs jpeg_v4_0_5_irq_funcs = {
808 .process = jpeg_v4_0_5_process_interrupt,
809};
810
811static void jpeg_v4_0_5_set_irq_funcs(struct amdgpu_device *adev)
812{
813 int i;
814
815 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
816 if (adev->jpeg.harvest_config & (1 << i))
817 continue;
818
819 adev->jpeg.inst[i].irq.num_types = 1;
820 adev->jpeg.inst[i].irq.funcs = &jpeg_v4_0_5_irq_funcs;
821 }
822}
823
824const struct amdgpu_ip_block_version jpeg_v4_0_5_ip_block = {
825 .type = AMD_IP_BLOCK_TYPE_JPEG,
826 .major = 4,
827 .minor = 0,
828 .rev = 5,
829 .funcs = &jpeg_v4_0_5_ip_funcs,
830};
831