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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016-2022 NVIDIA Corporation
4 *
5 * Author: Thierry Reding <treding@nvidia.com>
6 * Dipen Patel <dpatel@nvidia.com>
7 */
8
9#include <linux/gpio/driver.h>
10#include <linux/hte.h>
11#include <linux/interrupt.h>
12#include <linux/irq.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/platform_device.h>
16#include <linux/seq_file.h>
17
18#include <dt-bindings/gpio/tegra186-gpio.h>
19#include <dt-bindings/gpio/tegra194-gpio.h>
20#include <dt-bindings/gpio/tegra234-gpio.h>
21#include <dt-bindings/gpio/tegra241-gpio.h>
22
23/* security registers */
24#define TEGRA186_GPIO_CTL_SCR 0x0c
25#define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28)
26#define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27)
27
28#define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)
29
30#define TEGRA186_GPIO_VM 0x00
31#define TEGRA186_GPIO_VM_RW_MASK 0x03
32#define TEGRA186_GPIO_SCR 0x04
33#define TEGRA186_GPIO_SCR_PIN_SIZE 0x08
34#define TEGRA186_GPIO_SCR_PORT_SIZE 0x40
35#define TEGRA186_GPIO_SCR_SEC_WEN BIT(28)
36#define TEGRA186_GPIO_SCR_SEC_REN BIT(27)
37#define TEGRA186_GPIO_SCR_SEC_G1W BIT(9)
38#define TEGRA186_GPIO_SCR_SEC_G1R BIT(1)
39#define TEGRA186_GPIO_FULL_ACCESS (TEGRA186_GPIO_SCR_SEC_WEN | \
40 TEGRA186_GPIO_SCR_SEC_REN | \
41 TEGRA186_GPIO_SCR_SEC_G1R | \
42 TEGRA186_GPIO_SCR_SEC_G1W)
43#define TEGRA186_GPIO_SCR_SEC_ENABLE (TEGRA186_GPIO_SCR_SEC_WEN | \
44 TEGRA186_GPIO_SCR_SEC_REN)
45
46/* control registers */
47#define TEGRA186_GPIO_ENABLE_CONFIG 0x00
48#define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
49#define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
50#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
51#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
52#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
53#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
54#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
55#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
56#define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5)
57#define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
58#define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC BIT(7)
59
60#define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
61#define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
62
63#define TEGRA186_GPIO_INPUT 0x08
64#define TEGRA186_GPIO_INPUT_HIGH BIT(0)
65
66#define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
67#define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
68
69#define TEGRA186_GPIO_OUTPUT_VALUE 0x10
70#define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
71
72#define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
73
74#define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
75
76struct tegra_gpio_port {
77 const char *name;
78 unsigned int bank;
79 unsigned int port;
80 unsigned int pins;
81};
82
83struct tegra186_pin_range {
84 unsigned int offset;
85 const char *group;
86};
87
88struct tegra_gpio_soc {
89 const struct tegra_gpio_port *ports;
90 unsigned int num_ports;
91 const char *name;
92 unsigned int instance;
93
94 unsigned int num_irqs_per_bank;
95
96 const struct tegra186_pin_range *pin_ranges;
97 unsigned int num_pin_ranges;
98 const char *pinmux;
99 bool has_gte;
100 bool has_vm_support;
101};
102
103struct tegra_gpio {
104 struct gpio_chip gpio;
105 unsigned int num_irq;
106 unsigned int *irq;
107
108 const struct tegra_gpio_soc *soc;
109 unsigned int num_irqs_per_bank;
110 unsigned int num_banks;
111
112 void __iomem *secure;
113 void __iomem *base;
114};
115
116static const struct tegra_gpio_port *
117tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
118{
119 unsigned int start = 0, i;
120
121 for (i = 0; i < gpio->soc->num_ports; i++) {
122 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
123
124 if (*pin >= start && *pin < start + port->pins) {
125 *pin -= start;
126 return port;
127 }
128
129 start += port->pins;
130 }
131
132 return NULL;
133}
134
135static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
136 unsigned int pin)
137{
138 const struct tegra_gpio_port *port;
139 unsigned int offset;
140
141 port = tegra186_gpio_get_port(gpio, &pin);
142 if (!port)
143 return NULL;
144
145 offset = port->bank * 0x1000 + port->port * 0x200;
146
147 return gpio->base + offset + pin * 0x20;
148}
149
150static void __iomem *tegra186_gpio_get_secure_base(struct tegra_gpio *gpio,
151 unsigned int pin)
152{
153 const struct tegra_gpio_port *port;
154 unsigned int offset;
155
156 port = tegra186_gpio_get_port(gpio, &pin);
157 if (!port)
158 return NULL;
159
160 offset = port->bank * 0x1000 + port->port * TEGRA186_GPIO_SCR_PORT_SIZE;
161
162 return gpio->secure + offset + pin * TEGRA186_GPIO_SCR_PIN_SIZE;
163}
164
165static inline bool tegra186_gpio_is_accessible(struct tegra_gpio *gpio, unsigned int pin)
166{
167 void __iomem *secure;
168 u32 value;
169
170 secure = tegra186_gpio_get_secure_base(gpio, pin);
171
172 if (gpio->soc->has_vm_support) {
173 value = readl(secure + TEGRA186_GPIO_VM);
174 if ((value & TEGRA186_GPIO_VM_RW_MASK) != TEGRA186_GPIO_VM_RW_MASK)
175 return false;
176 }
177
178 value = __raw_readl(secure + TEGRA186_GPIO_SCR);
179
180 if ((value & TEGRA186_GPIO_SCR_SEC_ENABLE) == 0)
181 return true;
182
183 if ((value & TEGRA186_GPIO_FULL_ACCESS) == TEGRA186_GPIO_FULL_ACCESS)
184 return true;
185
186 return false;
187}
188
189static int tegra186_init_valid_mask(struct gpio_chip *chip,
190 unsigned long *valid_mask, unsigned int ngpios)
191{
192 struct tegra_gpio *gpio = gpiochip_get_data(chip);
193 unsigned int j;
194
195 for (j = 0; j < ngpios; j++) {
196 if (!tegra186_gpio_is_accessible(gpio, j))
197 clear_bit(j, valid_mask);
198 }
199 return 0;
200}
201
202static int tegra186_gpio_get_direction(struct gpio_chip *chip,
203 unsigned int offset)
204{
205 struct tegra_gpio *gpio = gpiochip_get_data(chip);
206 void __iomem *base;
207 u32 value;
208
209 base = tegra186_gpio_get_base(gpio, offset);
210 if (WARN_ON(base == NULL))
211 return -ENODEV;
212
213 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
214 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
215 return GPIO_LINE_DIRECTION_OUT;
216
217 return GPIO_LINE_DIRECTION_IN;
218}
219
220static int tegra186_gpio_direction_input(struct gpio_chip *chip,
221 unsigned int offset)
222{
223 struct tegra_gpio *gpio = gpiochip_get_data(chip);
224 void __iomem *base;
225 u32 value;
226
227 base = tegra186_gpio_get_base(gpio, offset);
228 if (WARN_ON(base == NULL))
229 return -ENODEV;
230
231 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
232 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
233 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
234
235 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
236 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
237 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
238 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
239
240 return 0;
241}
242
243static int tegra186_gpio_direction_output(struct gpio_chip *chip,
244 unsigned int offset, int level)
245{
246 struct tegra_gpio *gpio = gpiochip_get_data(chip);
247 void __iomem *base;
248 u32 value;
249
250 /* configure output level first */
251 chip->set(chip, offset, level);
252
253 base = tegra186_gpio_get_base(gpio, offset);
254 if (WARN_ON(base == NULL))
255 return -EINVAL;
256
257 /* set the direction */
258 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
259 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
260 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
261
262 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
263 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
264 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
265 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
266
267 return 0;
268}
269
270#define HTE_BOTH_EDGES (HTE_RISING_EDGE_TS | HTE_FALLING_EDGE_TS)
271
272static int tegra186_gpio_en_hw_ts(struct gpio_chip *gc, u32 offset,
273 unsigned long flags)
274{
275 struct tegra_gpio *gpio;
276 void __iomem *base;
277 int value;
278
279 if (!gc)
280 return -EINVAL;
281
282 gpio = gpiochip_get_data(gc);
283 if (!gpio)
284 return -ENODEV;
285
286 base = tegra186_gpio_get_base(gpio, offset);
287 if (WARN_ON(base == NULL))
288 return -EINVAL;
289
290 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
291 value |= TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;
292
293 if (flags == HTE_BOTH_EDGES) {
294 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
295 } else if (flags == HTE_RISING_EDGE_TS) {
296 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
297 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
298 } else if (flags == HTE_FALLING_EDGE_TS) {
299 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
300 }
301
302 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
303
304 return 0;
305}
306
307static int tegra186_gpio_dis_hw_ts(struct gpio_chip *gc, u32 offset,
308 unsigned long flags)
309{
310 struct tegra_gpio *gpio;
311 void __iomem *base;
312 int value;
313
314 if (!gc)
315 return -EINVAL;
316
317 gpio = gpiochip_get_data(gc);
318 if (!gpio)
319 return -ENODEV;
320
321 base = tegra186_gpio_get_base(gpio, offset);
322 if (WARN_ON(base == NULL))
323 return -EINVAL;
324
325 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
326 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;
327 if (flags == HTE_BOTH_EDGES) {
328 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
329 } else if (flags == HTE_RISING_EDGE_TS) {
330 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
331 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
332 } else if (flags == HTE_FALLING_EDGE_TS) {
333 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
334 }
335 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
336
337 return 0;
338}
339
340static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
341{
342 struct tegra_gpio *gpio = gpiochip_get_data(chip);
343 void __iomem *base;
344 u32 value;
345
346 base = tegra186_gpio_get_base(gpio, offset);
347 if (WARN_ON(base == NULL))
348 return -ENODEV;
349
350 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
351 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
352 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
353 else
354 value = readl(base + TEGRA186_GPIO_INPUT);
355
356 return value & BIT(0);
357}
358
359static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
360 int level)
361{
362 struct tegra_gpio *gpio = gpiochip_get_data(chip);
363 void __iomem *base;
364 u32 value;
365
366 base = tegra186_gpio_get_base(gpio, offset);
367 if (WARN_ON(base == NULL))
368 return;
369
370 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
371 if (level == 0)
372 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
373 else
374 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
375
376 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
377}
378
379static int tegra186_gpio_set_config(struct gpio_chip *chip,
380 unsigned int offset,
381 unsigned long config)
382{
383 struct tegra_gpio *gpio = gpiochip_get_data(chip);
384 u32 debounce, value;
385 void __iomem *base;
386
387 base = tegra186_gpio_get_base(gpio, offset);
388 if (base == NULL)
389 return -ENXIO;
390
391 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
392 return -ENOTSUPP;
393
394 debounce = pinconf_to_config_argument(config);
395
396 /*
397 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce
398 * time.
399 */
400 if (debounce > 255000)
401 return -EINVAL;
402
403 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC);
404
405 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce);
406 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL);
407
408 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
409 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE;
410 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
411
412 return 0;
413}
414
415static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
416{
417 struct tegra_gpio *gpio = gpiochip_get_data(chip);
418 struct pinctrl_dev *pctldev;
419 struct device_node *np;
420 unsigned int i, j;
421 int err;
422
423 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
424 return 0;
425
426 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
427 if (!np)
428 return -ENODEV;
429
430 pctldev = of_pinctrl_get(np);
431 of_node_put(np);
432 if (!pctldev)
433 return -EPROBE_DEFER;
434
435 for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
436 unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
437 const char *group = gpio->soc->pin_ranges[i].group;
438
439 port = pin / 8;
440 pin = pin % 8;
441
442 if (port >= gpio->soc->num_ports) {
443 dev_warn(chip->parent, "invalid port %u for %s\n",
444 port, group);
445 continue;
446 }
447
448 for (j = 0; j < port; j++)
449 pin += gpio->soc->ports[j].pins;
450
451 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
452 if (err < 0)
453 return err;
454 }
455
456 return 0;
457}
458
459static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
460 const struct of_phandle_args *spec,
461 u32 *flags)
462{
463 struct tegra_gpio *gpio = gpiochip_get_data(chip);
464 unsigned int port, pin, i, offset = 0;
465
466 if (WARN_ON(chip->of_gpio_n_cells < 2))
467 return -EINVAL;
468
469 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
470 return -EINVAL;
471
472 port = spec->args[0] / 8;
473 pin = spec->args[0] % 8;
474
475 if (port >= gpio->soc->num_ports) {
476 dev_err(chip->parent, "invalid port number: %u\n", port);
477 return -EINVAL;
478 }
479
480 for (i = 0; i < port; i++)
481 offset += gpio->soc->ports[i].pins;
482
483 if (flags)
484 *flags = spec->args[1];
485
486 return offset + pin;
487}
488
489#define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio)
490
491static void tegra186_irq_ack(struct irq_data *data)
492{
493 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
494 struct tegra_gpio *gpio = to_tegra_gpio(gc);
495 void __iomem *base;
496
497 base = tegra186_gpio_get_base(gpio, data->hwirq);
498 if (WARN_ON(base == NULL))
499 return;
500
501 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
502}
503
504static void tegra186_irq_mask(struct irq_data *data)
505{
506 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
507 struct tegra_gpio *gpio = to_tegra_gpio(gc);
508 void __iomem *base;
509 u32 value;
510
511 base = tegra186_gpio_get_base(gpio, data->hwirq);
512 if (WARN_ON(base == NULL))
513 return;
514
515 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
516 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
517 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
518
519 gpiochip_disable_irq(&gpio->gpio, data->hwirq);
520}
521
522static void tegra186_irq_unmask(struct irq_data *data)
523{
524 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
525 struct tegra_gpio *gpio = to_tegra_gpio(gc);
526 void __iomem *base;
527 u32 value;
528
529 base = tegra186_gpio_get_base(gpio, data->hwirq);
530 if (WARN_ON(base == NULL))
531 return;
532
533 gpiochip_enable_irq(&gpio->gpio, data->hwirq);
534
535 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
536 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
537 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
538}
539
540static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
541{
542 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
543 struct tegra_gpio *gpio = to_tegra_gpio(gc);
544 void __iomem *base;
545 u32 value;
546
547 base = tegra186_gpio_get_base(gpio, data->hwirq);
548 if (WARN_ON(base == NULL))
549 return -ENODEV;
550
551 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
552 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
553 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
554
555 switch (type & IRQ_TYPE_SENSE_MASK) {
556 case IRQ_TYPE_NONE:
557 break;
558
559 case IRQ_TYPE_EDGE_RISING:
560 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
561 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
562 break;
563
564 case IRQ_TYPE_EDGE_FALLING:
565 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
566 break;
567
568 case IRQ_TYPE_EDGE_BOTH:
569 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
570 break;
571
572 case IRQ_TYPE_LEVEL_HIGH:
573 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
574 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
575 break;
576
577 case IRQ_TYPE_LEVEL_LOW:
578 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
579 break;
580
581 default:
582 return -EINVAL;
583 }
584
585 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
586
587 if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
588 irq_set_handler_locked(data, handle_level_irq);
589 else
590 irq_set_handler_locked(data, handle_edge_irq);
591
592 if (data->parent_data)
593 return irq_chip_set_type_parent(data, type);
594
595 return 0;
596}
597
598static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on)
599{
600 if (data->parent_data)
601 return irq_chip_set_wake_parent(data, on);
602
603 return 0;
604}
605
606static void tegra186_irq_print_chip(struct irq_data *data, struct seq_file *p)
607{
608 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
609
610 seq_printf(p, dev_name(gc->parent));
611}
612
613static const struct irq_chip tegra186_gpio_irq_chip = {
614 .irq_ack = tegra186_irq_ack,
615 .irq_mask = tegra186_irq_mask,
616 .irq_unmask = tegra186_irq_unmask,
617 .irq_set_type = tegra186_irq_set_type,
618 .irq_set_wake = tegra186_irq_set_wake,
619 .irq_print_chip = tegra186_irq_print_chip,
620 .flags = IRQCHIP_IMMUTABLE,
621 GPIOCHIP_IRQ_RESOURCE_HELPERS,
622};
623
624static void tegra186_gpio_irq(struct irq_desc *desc)
625{
626 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
627 struct irq_domain *domain = gpio->gpio.irq.domain;
628 struct irq_chip *chip = irq_desc_get_chip(desc);
629 unsigned int parent = irq_desc_get_irq(desc);
630 unsigned int i, j, offset = 0;
631
632 chained_irq_enter(chip, desc);
633
634 for (i = 0; i < gpio->soc->num_ports; i++) {
635 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
636 unsigned int pin;
637 unsigned long value;
638 void __iomem *base;
639
640 base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
641
642 /* skip ports that are not associated with this bank */
643 for (j = 0; j < gpio->num_irqs_per_bank; j++) {
644 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j])
645 break;
646 }
647
648 if (j == gpio->num_irqs_per_bank)
649 goto skip;
650
651 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
652
653 for_each_set_bit(pin, &value, port->pins) {
654 int ret = generic_handle_domain_irq(domain, offset + pin);
655 WARN_RATELIMIT(ret, "hwirq = %d", offset + pin);
656 }
657
658skip:
659 offset += port->pins;
660 }
661
662 chained_irq_exit(chip, desc);
663}
664
665static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain,
666 struct irq_fwspec *fwspec,
667 unsigned long *hwirq,
668 unsigned int *type)
669{
670 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
671 unsigned int port, pin, i, offset = 0;
672
673 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2))
674 return -EINVAL;
675
676 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells))
677 return -EINVAL;
678
679 port = fwspec->param[0] / 8;
680 pin = fwspec->param[0] % 8;
681
682 if (port >= gpio->soc->num_ports)
683 return -EINVAL;
684
685 for (i = 0; i < port; i++)
686 offset += gpio->soc->ports[i].pins;
687
688 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
689 *hwirq = offset + pin;
690
691 return 0;
692}
693
694static int tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,
695 union gpio_irq_fwspec *gfwspec,
696 unsigned int parent_hwirq,
697 unsigned int parent_type)
698{
699 struct tegra_gpio *gpio = gpiochip_get_data(chip);
700 struct irq_fwspec *fwspec = &gfwspec->fwspec;
701
702 fwspec->fwnode = chip->irq.parent_domain->fwnode;
703 fwspec->param_count = 3;
704 fwspec->param[0] = gpio->soc->instance;
705 fwspec->param[1] = parent_hwirq;
706 fwspec->param[2] = parent_type;
707
708 return 0;
709}
710
711static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
712 unsigned int hwirq,
713 unsigned int type,
714 unsigned int *parent_hwirq,
715 unsigned int *parent_type)
716{
717 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
718 *parent_type = type;
719
720 return 0;
721}
722
723static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip,
724 unsigned int offset)
725{
726 struct tegra_gpio *gpio = gpiochip_get_data(chip);
727 unsigned int i;
728
729 for (i = 0; i < gpio->soc->num_ports; i++) {
730 if (offset < gpio->soc->ports[i].pins)
731 break;
732
733 offset -= gpio->soc->ports[i].pins;
734 }
735
736 return offset + i * 8;
737}
738
739static const struct of_device_id tegra186_pmc_of_match[] = {
740 { .compatible = "nvidia,tegra186-pmc" },
741 { .compatible = "nvidia,tegra194-pmc" },
742 { .compatible = "nvidia,tegra234-pmc" },
743 { /* sentinel */ }
744};
745
746static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
747{
748 struct device *dev = gpio->gpio.parent;
749 unsigned int i;
750 u32 value;
751
752 for (i = 0; i < gpio->soc->num_ports; i++) {
753 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
754 unsigned int offset, p = port->port;
755 void __iomem *base;
756
757 base = gpio->secure + port->bank * 0x1000 + 0x800;
758
759 value = readl(base + TEGRA186_GPIO_CTL_SCR);
760
761 /*
762 * For controllers that haven't been locked down yet, make
763 * sure to program the default interrupt route mapping.
764 */
765 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
766 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
767 /*
768 * On Tegra194 and later, each pin can be routed to one or more
769 * interrupts.
770 */
771 dev_dbg(dev, "programming default interrupt routing for port %s\n",
772 port->name);
773
774 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, 0);
775
776 /*
777 * By default we only want to route GPIO pins to IRQ 0. This works
778 * only under the assumption that we're running as the host kernel
779 * and hence all GPIO pins are owned by Linux.
780 *
781 * For cases where Linux is the guest OS, the hypervisor will have
782 * to configure the interrupt routing and pass only the valid
783 * interrupts via device tree.
784 */
785 value = readl(base + offset);
786 value = BIT(port->pins) - 1;
787 writel(value, base + offset);
788 }
789 }
790}
791
792static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio)
793{
794 struct device *dev = gpio->gpio.parent;
795
796 if (gpio->num_irq > gpio->num_banks) {
797 if (gpio->num_irq % gpio->num_banks != 0)
798 goto error;
799 }
800
801 if (gpio->num_irq < gpio->num_banks)
802 goto error;
803
804 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks;
805
806 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank)
807 goto error;
808
809 return 0;
810
811error:
812 dev_err(dev, "invalid number of interrupts (%u) for %u banks\n",
813 gpio->num_irq, gpio->num_banks);
814 return -EINVAL;
815}
816
817static int tegra186_gpio_probe(struct platform_device *pdev)
818{
819 unsigned int i, j, offset;
820 struct gpio_irq_chip *irq;
821 struct tegra_gpio *gpio;
822 struct device_node *np;
823 char **names;
824 int err;
825
826 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
827 if (!gpio)
828 return -ENOMEM;
829
830 gpio->soc = device_get_match_data(&pdev->dev);
831 gpio->gpio.label = gpio->soc->name;
832 gpio->gpio.parent = &pdev->dev;
833
834 /* count the number of banks in the controller */
835 for (i = 0; i < gpio->soc->num_ports; i++)
836 if (gpio->soc->ports[i].bank > gpio->num_banks)
837 gpio->num_banks = gpio->soc->ports[i].bank;
838
839 gpio->num_banks++;
840
841 /* get register apertures */
842 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security");
843 if (IS_ERR(gpio->secure)) {
844 gpio->secure = devm_platform_ioremap_resource(pdev, 0);
845 if (IS_ERR(gpio->secure))
846 return PTR_ERR(gpio->secure);
847 }
848
849 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
850 if (IS_ERR(gpio->base)) {
851 gpio->base = devm_platform_ioremap_resource(pdev, 1);
852 if (IS_ERR(gpio->base))
853 return PTR_ERR(gpio->base);
854 }
855
856 err = platform_irq_count(pdev);
857 if (err < 0)
858 return err;
859
860 gpio->num_irq = err;
861
862 err = tegra186_gpio_irqs_per_bank(gpio);
863 if (err < 0)
864 return err;
865
866 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
867 GFP_KERNEL);
868 if (!gpio->irq)
869 return -ENOMEM;
870
871 for (i = 0; i < gpio->num_irq; i++) {
872 err = platform_get_irq(pdev, i);
873 if (err < 0)
874 return err;
875
876 gpio->irq[i] = err;
877 }
878
879 gpio->gpio.request = gpiochip_generic_request;
880 gpio->gpio.free = gpiochip_generic_free;
881 gpio->gpio.get_direction = tegra186_gpio_get_direction;
882 gpio->gpio.direction_input = tegra186_gpio_direction_input;
883 gpio->gpio.direction_output = tegra186_gpio_direction_output;
884 gpio->gpio.get = tegra186_gpio_get;
885 gpio->gpio.set = tegra186_gpio_set;
886 gpio->gpio.set_config = tegra186_gpio_set_config;
887 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
888 gpio->gpio.init_valid_mask = tegra186_init_valid_mask;
889 if (gpio->soc->has_gte) {
890 gpio->gpio.en_hw_timestamp = tegra186_gpio_en_hw_ts;
891 gpio->gpio.dis_hw_timestamp = tegra186_gpio_dis_hw_ts;
892 }
893
894 gpio->gpio.base = -1;
895
896 for (i = 0; i < gpio->soc->num_ports; i++)
897 gpio->gpio.ngpio += gpio->soc->ports[i].pins;
898
899 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
900 sizeof(*names), GFP_KERNEL);
901 if (!names)
902 return -ENOMEM;
903
904 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
905 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
906 char *name;
907
908 for (j = 0; j < port->pins; j++) {
909 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
910 "P%s.%02x", port->name, j);
911 if (!name)
912 return -ENOMEM;
913
914 names[offset + j] = name;
915 }
916
917 offset += port->pins;
918 }
919
920 gpio->gpio.names = (const char * const *)names;
921
922#if defined(CONFIG_OF_GPIO)
923 gpio->gpio.of_gpio_n_cells = 2;
924 gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
925#endif /* CONFIG_OF_GPIO */
926
927 irq = &gpio->gpio.irq;
928 gpio_irq_chip_set_chip(irq, &tegra186_gpio_irq_chip);
929 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
930 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq;
931 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec;
932 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq;
933 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate;
934 irq->handler = handle_simple_irq;
935 irq->default_type = IRQ_TYPE_NONE;
936 irq->parent_handler = tegra186_gpio_irq;
937 irq->parent_handler_data = gpio;
938 irq->num_parents = gpio->num_irq;
939
940 /*
941 * To simplify things, use a single interrupt per bank for now. Some
942 * chips support up to 8 interrupts per bank, which can be useful to
943 * distribute the load and decrease the processing latency for GPIOs
944 * but it also requires a more complicated interrupt routing than we
945 * currently program.
946 */
947 if (gpio->num_irqs_per_bank > 1) {
948 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks,
949 sizeof(*irq->parents), GFP_KERNEL);
950 if (!irq->parents)
951 return -ENOMEM;
952
953 for (i = 0; i < gpio->num_banks; i++)
954 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank];
955
956 irq->num_parents = gpio->num_banks;
957 } else {
958 irq->num_parents = gpio->num_irq;
959 irq->parents = gpio->irq;
960 }
961
962 if (gpio->soc->num_irqs_per_bank > 1)
963 tegra186_gpio_init_route_mapping(gpio);
964
965 np = of_find_matching_node(NULL, tegra186_pmc_of_match);
966 if (np) {
967 if (of_device_is_available(np)) {
968 irq->parent_domain = irq_find_host(np);
969 of_node_put(np);
970
971 if (!irq->parent_domain)
972 return -EPROBE_DEFER;
973 } else {
974 of_node_put(np);
975 }
976 }
977
978 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
979 sizeof(*irq->map), GFP_KERNEL);
980 if (!irq->map)
981 return -ENOMEM;
982
983 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
984 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
985
986 for (j = 0; j < port->pins; j++)
987 irq->map[offset + j] = irq->parents[port->bank];
988
989 offset += port->pins;
990 }
991
992 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
993}
994
995#define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
996 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \
997 .name = #_name, \
998 .bank = _bank, \
999 .port = _port, \
1000 .pins = _pins, \
1001 }
1002
1003static const struct tegra_gpio_port tegra186_main_ports[] = {
1004 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
1005 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),
1006 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7),
1007 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6),
1008 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8),
1009 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6),
1010 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6),
1011 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7),
1012 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8),
1013 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8),
1014 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1),
1015 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8),
1016 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),
1017 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7),
1018 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4),
1019 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7),
1020 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6),
1021 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6),
1022 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4),
1023 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8),
1024 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7),
1025 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),
1026 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),
1027};
1028
1029static const struct tegra_gpio_soc tegra186_main_soc = {
1030 .num_ports = ARRAY_SIZE(tegra186_main_ports),
1031 .ports = tegra186_main_ports,
1032 .name = "tegra186-gpio",
1033 .instance = 0,
1034 .num_irqs_per_bank = 1,
1035 .has_vm_support = false,
1036};
1037
1038#define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1039 [TEGRA186_AON_GPIO_PORT_##_name] = { \
1040 .name = #_name, \
1041 .bank = _bank, \
1042 .port = _port, \
1043 .pins = _pins, \
1044 }
1045
1046static const struct tegra_gpio_port tegra186_aon_ports[] = {
1047 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),
1048 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6),
1049 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8),
1050 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8),
1051 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4),
1052 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8),
1053 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3),
1054 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5),
1055};
1056
1057static const struct tegra_gpio_soc tegra186_aon_soc = {
1058 .num_ports = ARRAY_SIZE(tegra186_aon_ports),
1059 .ports = tegra186_aon_ports,
1060 .name = "tegra186-gpio-aon",
1061 .instance = 1,
1062 .num_irqs_per_bank = 1,
1063 .has_vm_support = false,
1064};
1065
1066#define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1067 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \
1068 .name = #_name, \
1069 .bank = _bank, \
1070 .port = _port, \
1071 .pins = _pins, \
1072 }
1073
1074static const struct tegra_gpio_port tegra194_main_ports[] = {
1075 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),
1076 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2),
1077 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8),
1078 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4),
1079 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8),
1080 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6),
1081 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8),
1082 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8),
1083 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5),
1084 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6),
1085 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8),
1086 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4),
1087 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),
1088 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3),
1089 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6),
1090 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8),
1091 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8),
1092 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6),
1093 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8),
1094 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8),
1095 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1),
1096 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8),
1097 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2),
1098 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8),
1099 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8),
1100 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8),
1101 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2),
1102 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
1103};
1104
1105static const struct tegra186_pin_range tegra194_main_pin_ranges[] = {
1106 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" },
1107 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" },
1108};
1109
1110static const struct tegra_gpio_soc tegra194_main_soc = {
1111 .num_ports = ARRAY_SIZE(tegra194_main_ports),
1112 .ports = tegra194_main_ports,
1113 .name = "tegra194-gpio",
1114 .instance = 0,
1115 .num_irqs_per_bank = 8,
1116 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
1117 .pin_ranges = tegra194_main_pin_ranges,
1118 .pinmux = "nvidia,tegra194-pinmux",
1119 .has_vm_support = true,
1120};
1121
1122#define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1123 [TEGRA194_AON_GPIO_PORT_##_name] = { \
1124 .name = #_name, \
1125 .bank = _bank, \
1126 .port = _port, \
1127 .pins = _pins, \
1128 }
1129
1130static const struct tegra_gpio_port tegra194_aon_ports[] = {
1131 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),
1132 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),
1133 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),
1134 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3),
1135 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7)
1136};
1137
1138static const struct tegra_gpio_soc tegra194_aon_soc = {
1139 .num_ports = ARRAY_SIZE(tegra194_aon_ports),
1140 .ports = tegra194_aon_ports,
1141 .name = "tegra194-gpio-aon",
1142 .instance = 1,
1143 .num_irqs_per_bank = 8,
1144 .has_gte = true,
1145 .has_vm_support = false,
1146};
1147
1148#define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1149 [TEGRA234_MAIN_GPIO_PORT_##_name] = { \
1150 .name = #_name, \
1151 .bank = _bank, \
1152 .port = _port, \
1153 .pins = _pins, \
1154 }
1155
1156static const struct tegra_gpio_port tegra234_main_ports[] = {
1157 TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8),
1158 TEGRA234_MAIN_GPIO_PORT( B, 0, 3, 1),
1159 TEGRA234_MAIN_GPIO_PORT( C, 5, 1, 8),
1160 TEGRA234_MAIN_GPIO_PORT( D, 5, 2, 4),
1161 TEGRA234_MAIN_GPIO_PORT( E, 5, 3, 8),
1162 TEGRA234_MAIN_GPIO_PORT( F, 5, 4, 6),
1163 TEGRA234_MAIN_GPIO_PORT( G, 4, 0, 8),
1164 TEGRA234_MAIN_GPIO_PORT( H, 4, 1, 8),
1165 TEGRA234_MAIN_GPIO_PORT( I, 4, 2, 7),
1166 TEGRA234_MAIN_GPIO_PORT( J, 5, 0, 6),
1167 TEGRA234_MAIN_GPIO_PORT( K, 3, 0, 8),
1168 TEGRA234_MAIN_GPIO_PORT( L, 3, 1, 4),
1169 TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8),
1170 TEGRA234_MAIN_GPIO_PORT( N, 2, 1, 8),
1171 TEGRA234_MAIN_GPIO_PORT( P, 2, 2, 8),
1172 TEGRA234_MAIN_GPIO_PORT( Q, 2, 3, 8),
1173 TEGRA234_MAIN_GPIO_PORT( R, 2, 4, 6),
1174 TEGRA234_MAIN_GPIO_PORT( X, 1, 0, 8),
1175 TEGRA234_MAIN_GPIO_PORT( Y, 1, 1, 8),
1176 TEGRA234_MAIN_GPIO_PORT( Z, 1, 2, 8),
1177 TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8),
1178 TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4),
1179 TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2),
1180 TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4),
1181 TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8),
1182};
1183
1184static const struct tegra_gpio_soc tegra234_main_soc = {
1185 .num_ports = ARRAY_SIZE(tegra234_main_ports),
1186 .ports = tegra234_main_ports,
1187 .name = "tegra234-gpio",
1188 .instance = 0,
1189 .num_irqs_per_bank = 8,
1190 .has_vm_support = true,
1191};
1192
1193#define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1194 [TEGRA234_AON_GPIO_PORT_##_name] = { \
1195 .name = #_name, \
1196 .bank = _bank, \
1197 .port = _port, \
1198 .pins = _pins, \
1199 }
1200
1201static const struct tegra_gpio_port tegra234_aon_ports[] = {
1202 TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8),
1203 TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4),
1204 TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8),
1205 TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3),
1206 TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8),
1207 TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1),
1208};
1209
1210static const struct tegra_gpio_soc tegra234_aon_soc = {
1211 .num_ports = ARRAY_SIZE(tegra234_aon_ports),
1212 .ports = tegra234_aon_ports,
1213 .name = "tegra234-gpio-aon",
1214 .instance = 1,
1215 .num_irqs_per_bank = 8,
1216 .has_gte = true,
1217 .has_vm_support = false,
1218};
1219
1220#define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1221 [TEGRA241_MAIN_GPIO_PORT_##_name] = { \
1222 .name = #_name, \
1223 .bank = _bank, \
1224 .port = _port, \
1225 .pins = _pins, \
1226 }
1227
1228static const struct tegra_gpio_port tegra241_main_ports[] = {
1229 TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8),
1230 TEGRA241_MAIN_GPIO_PORT(B, 0, 1, 8),
1231 TEGRA241_MAIN_GPIO_PORT(C, 0, 2, 2),
1232 TEGRA241_MAIN_GPIO_PORT(D, 0, 3, 6),
1233 TEGRA241_MAIN_GPIO_PORT(E, 0, 4, 8),
1234 TEGRA241_MAIN_GPIO_PORT(F, 1, 0, 8),
1235 TEGRA241_MAIN_GPIO_PORT(G, 1, 1, 8),
1236 TEGRA241_MAIN_GPIO_PORT(H, 1, 2, 8),
1237 TEGRA241_MAIN_GPIO_PORT(J, 1, 3, 8),
1238 TEGRA241_MAIN_GPIO_PORT(K, 1, 4, 4),
1239 TEGRA241_MAIN_GPIO_PORT(L, 1, 5, 6),
1240};
1241
1242static const struct tegra_gpio_soc tegra241_main_soc = {
1243 .num_ports = ARRAY_SIZE(tegra241_main_ports),
1244 .ports = tegra241_main_ports,
1245 .name = "tegra241-gpio",
1246 .instance = 0,
1247 .num_irqs_per_bank = 8,
1248 .has_vm_support = false,
1249};
1250
1251#define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1252 [TEGRA241_AON_GPIO_PORT_##_name] = { \
1253 .name = #_name, \
1254 .bank = _bank, \
1255 .port = _port, \
1256 .pins = _pins, \
1257 }
1258
1259static const struct tegra_gpio_port tegra241_aon_ports[] = {
1260 TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8),
1261 TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4),
1262};
1263
1264static const struct tegra_gpio_soc tegra241_aon_soc = {
1265 .num_ports = ARRAY_SIZE(tegra241_aon_ports),
1266 .ports = tegra241_aon_ports,
1267 .name = "tegra241-gpio-aon",
1268 .instance = 1,
1269 .num_irqs_per_bank = 8,
1270 .has_vm_support = false,
1271};
1272
1273static const struct of_device_id tegra186_gpio_of_match[] = {
1274 {
1275 .compatible = "nvidia,tegra186-gpio",
1276 .data = &tegra186_main_soc
1277 }, {
1278 .compatible = "nvidia,tegra186-gpio-aon",
1279 .data = &tegra186_aon_soc
1280 }, {
1281 .compatible = "nvidia,tegra194-gpio",
1282 .data = &tegra194_main_soc
1283 }, {
1284 .compatible = "nvidia,tegra194-gpio-aon",
1285 .data = &tegra194_aon_soc
1286 }, {
1287 .compatible = "nvidia,tegra234-gpio",
1288 .data = &tegra234_main_soc
1289 }, {
1290 .compatible = "nvidia,tegra234-gpio-aon",
1291 .data = &tegra234_aon_soc
1292 }, {
1293 /* sentinel */
1294 }
1295};
1296MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match);
1297
1298static const struct acpi_device_id tegra186_gpio_acpi_match[] = {
1299 { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc },
1300 { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc },
1301 { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc },
1302 { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc },
1303 { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc },
1304 { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc },
1305 {}
1306};
1307MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match);
1308
1309static struct platform_driver tegra186_gpio_driver = {
1310 .driver = {
1311 .name = "tegra186-gpio",
1312 .of_match_table = tegra186_gpio_of_match,
1313 .acpi_match_table = tegra186_gpio_acpi_match,
1314 },
1315 .probe = tegra186_gpio_probe,
1316};
1317module_platform_driver(tegra186_gpio_driver);
1318
1319MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
1320MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1321MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016-2022 NVIDIA Corporation
4 *
5 * Author: Thierry Reding <treding@nvidia.com>
6 * Dipen Patel <dpatel@nvidia.com>
7 */
8
9#include <linux/gpio/driver.h>
10#include <linux/hte.h>
11#include <linux/interrupt.h>
12#include <linux/irq.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/platform_device.h>
16#include <linux/property.h>
17#include <linux/seq_file.h>
18
19#include <dt-bindings/gpio/tegra186-gpio.h>
20#include <dt-bindings/gpio/tegra194-gpio.h>
21#include <dt-bindings/gpio/tegra234-gpio.h>
22#include <dt-bindings/gpio/tegra241-gpio.h>
23
24/* security registers */
25#define TEGRA186_GPIO_CTL_SCR 0x0c
26#define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28)
27#define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27)
28
29#define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)
30
31#define TEGRA186_GPIO_VM 0x00
32#define TEGRA186_GPIO_VM_RW_MASK 0x03
33#define TEGRA186_GPIO_SCR 0x04
34#define TEGRA186_GPIO_SCR_PIN_SIZE 0x08
35#define TEGRA186_GPIO_SCR_PORT_SIZE 0x40
36#define TEGRA186_GPIO_SCR_SEC_WEN BIT(28)
37#define TEGRA186_GPIO_SCR_SEC_REN BIT(27)
38#define TEGRA186_GPIO_SCR_SEC_G1W BIT(9)
39#define TEGRA186_GPIO_SCR_SEC_G1R BIT(1)
40
41/* control registers */
42#define TEGRA186_GPIO_ENABLE_CONFIG 0x00
43#define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
44#define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
45#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
46#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
47#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
48#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
49#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
50#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
51#define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5)
52#define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
53#define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC BIT(7)
54
55#define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
56#define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
57
58#define TEGRA186_GPIO_INPUT 0x08
59#define TEGRA186_GPIO_INPUT_HIGH BIT(0)
60
61#define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
62#define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
63
64#define TEGRA186_GPIO_OUTPUT_VALUE 0x10
65#define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
66
67#define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
68
69#define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
70
71struct tegra_gpio_port {
72 const char *name;
73 unsigned int bank;
74 unsigned int port;
75 unsigned int pins;
76};
77
78struct tegra186_pin_range {
79 unsigned int offset;
80 const char *group;
81};
82
83struct tegra_gpio_soc {
84 const struct tegra_gpio_port *ports;
85 unsigned int num_ports;
86 const char *name;
87 unsigned int instance;
88
89 unsigned int num_irqs_per_bank;
90
91 const struct tegra186_pin_range *pin_ranges;
92 unsigned int num_pin_ranges;
93 const char *pinmux;
94 bool has_gte;
95 bool has_vm_support;
96};
97
98struct tegra_gpio {
99 struct gpio_chip gpio;
100 unsigned int num_irq;
101 unsigned int *irq;
102
103 const struct tegra_gpio_soc *soc;
104 unsigned int num_irqs_per_bank;
105 unsigned int num_banks;
106
107 void __iomem *secure;
108 void __iomem *base;
109};
110
111static const struct tegra_gpio_port *
112tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
113{
114 unsigned int start = 0, i;
115
116 for (i = 0; i < gpio->soc->num_ports; i++) {
117 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
118
119 if (*pin >= start && *pin < start + port->pins) {
120 *pin -= start;
121 return port;
122 }
123
124 start += port->pins;
125 }
126
127 return NULL;
128}
129
130static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
131 unsigned int pin)
132{
133 const struct tegra_gpio_port *port;
134 unsigned int offset;
135
136 port = tegra186_gpio_get_port(gpio, &pin);
137 if (!port)
138 return NULL;
139
140 offset = port->bank * 0x1000 + port->port * 0x200;
141
142 return gpio->base + offset + pin * 0x20;
143}
144
145static void __iomem *tegra186_gpio_get_secure_base(struct tegra_gpio *gpio,
146 unsigned int pin)
147{
148 const struct tegra_gpio_port *port;
149 unsigned int offset;
150
151 port = tegra186_gpio_get_port(gpio, &pin);
152 if (!port)
153 return NULL;
154
155 offset = port->bank * 0x1000 + port->port * TEGRA186_GPIO_SCR_PORT_SIZE;
156
157 return gpio->secure + offset + pin * TEGRA186_GPIO_SCR_PIN_SIZE;
158}
159
160static inline bool tegra186_gpio_is_accessible(struct tegra_gpio *gpio, unsigned int pin)
161{
162 void __iomem *secure;
163 u32 value;
164
165 secure = tegra186_gpio_get_secure_base(gpio, pin);
166
167 if (gpio->soc->has_vm_support) {
168 value = readl(secure + TEGRA186_GPIO_VM);
169 if ((value & TEGRA186_GPIO_VM_RW_MASK) != TEGRA186_GPIO_VM_RW_MASK)
170 return false;
171 }
172
173 value = __raw_readl(secure + TEGRA186_GPIO_SCR);
174
175 /*
176 * When SCR_SEC_[R|W]EN is unset, then we have full read/write access to all the
177 * registers for given GPIO pin.
178 * When SCR_SEC[R|W]EN is set, then there is need to further check the accompanying
179 * SCR_SEC_G1[R|W] bit to determine read/write access to all the registers for given
180 * GPIO pin.
181 */
182
183 if (((value & TEGRA186_GPIO_SCR_SEC_REN) == 0 ||
184 ((value & TEGRA186_GPIO_SCR_SEC_REN) && (value & TEGRA186_GPIO_SCR_SEC_G1R))) &&
185 ((value & TEGRA186_GPIO_SCR_SEC_WEN) == 0 ||
186 ((value & TEGRA186_GPIO_SCR_SEC_WEN) && (value & TEGRA186_GPIO_SCR_SEC_G1W))))
187 return true;
188
189 return false;
190}
191
192static int tegra186_init_valid_mask(struct gpio_chip *chip,
193 unsigned long *valid_mask, unsigned int ngpios)
194{
195 struct tegra_gpio *gpio = gpiochip_get_data(chip);
196 unsigned int j;
197
198 for (j = 0; j < ngpios; j++) {
199 if (!tegra186_gpio_is_accessible(gpio, j))
200 clear_bit(j, valid_mask);
201 }
202 return 0;
203}
204
205static int tegra186_gpio_get_direction(struct gpio_chip *chip,
206 unsigned int offset)
207{
208 struct tegra_gpio *gpio = gpiochip_get_data(chip);
209 void __iomem *base;
210 u32 value;
211
212 base = tegra186_gpio_get_base(gpio, offset);
213 if (WARN_ON(base == NULL))
214 return -ENODEV;
215
216 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
217 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
218 return GPIO_LINE_DIRECTION_OUT;
219
220 return GPIO_LINE_DIRECTION_IN;
221}
222
223static int tegra186_gpio_direction_input(struct gpio_chip *chip,
224 unsigned int offset)
225{
226 struct tegra_gpio *gpio = gpiochip_get_data(chip);
227 void __iomem *base;
228 u32 value;
229
230 base = tegra186_gpio_get_base(gpio, offset);
231 if (WARN_ON(base == NULL))
232 return -ENODEV;
233
234 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
235 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
236 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
237
238 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
239 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
240 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
241 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
242
243 return 0;
244}
245
246static int tegra186_gpio_direction_output(struct gpio_chip *chip,
247 unsigned int offset, int level)
248{
249 struct tegra_gpio *gpio = gpiochip_get_data(chip);
250 void __iomem *base;
251 u32 value;
252
253 /* configure output level first */
254 chip->set(chip, offset, level);
255
256 base = tegra186_gpio_get_base(gpio, offset);
257 if (WARN_ON(base == NULL))
258 return -EINVAL;
259
260 /* set the direction */
261 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
262 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
263 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
264
265 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
266 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
267 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
268 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
269
270 return 0;
271}
272
273#define HTE_BOTH_EDGES (HTE_RISING_EDGE_TS | HTE_FALLING_EDGE_TS)
274
275static int tegra186_gpio_en_hw_ts(struct gpio_chip *gc, u32 offset,
276 unsigned long flags)
277{
278 struct tegra_gpio *gpio;
279 void __iomem *base;
280 int value;
281
282 if (!gc)
283 return -EINVAL;
284
285 gpio = gpiochip_get_data(gc);
286 if (!gpio)
287 return -ENODEV;
288
289 base = tegra186_gpio_get_base(gpio, offset);
290 if (WARN_ON(base == NULL))
291 return -EINVAL;
292
293 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
294 value |= TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;
295
296 if (flags == HTE_BOTH_EDGES) {
297 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
298 } else if (flags == HTE_RISING_EDGE_TS) {
299 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
300 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
301 } else if (flags == HTE_FALLING_EDGE_TS) {
302 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
303 }
304
305 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
306
307 return 0;
308}
309
310static int tegra186_gpio_dis_hw_ts(struct gpio_chip *gc, u32 offset,
311 unsigned long flags)
312{
313 struct tegra_gpio *gpio;
314 void __iomem *base;
315 int value;
316
317 if (!gc)
318 return -EINVAL;
319
320 gpio = gpiochip_get_data(gc);
321 if (!gpio)
322 return -ENODEV;
323
324 base = tegra186_gpio_get_base(gpio, offset);
325 if (WARN_ON(base == NULL))
326 return -EINVAL;
327
328 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
329 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;
330 if (flags == HTE_BOTH_EDGES) {
331 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
332 } else if (flags == HTE_RISING_EDGE_TS) {
333 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
334 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
335 } else if (flags == HTE_FALLING_EDGE_TS) {
336 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
337 }
338 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
339
340 return 0;
341}
342
343static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
344{
345 struct tegra_gpio *gpio = gpiochip_get_data(chip);
346 void __iomem *base;
347 u32 value;
348
349 base = tegra186_gpio_get_base(gpio, offset);
350 if (WARN_ON(base == NULL))
351 return -ENODEV;
352
353 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
354 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
355 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
356 else
357 value = readl(base + TEGRA186_GPIO_INPUT);
358
359 return value & BIT(0);
360}
361
362static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
363 int level)
364{
365 struct tegra_gpio *gpio = gpiochip_get_data(chip);
366 void __iomem *base;
367 u32 value;
368
369 base = tegra186_gpio_get_base(gpio, offset);
370 if (WARN_ON(base == NULL))
371 return;
372
373 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
374 if (level == 0)
375 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
376 else
377 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
378
379 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
380}
381
382static int tegra186_gpio_set_config(struct gpio_chip *chip,
383 unsigned int offset,
384 unsigned long config)
385{
386 struct tegra_gpio *gpio = gpiochip_get_data(chip);
387 u32 debounce, value;
388 void __iomem *base;
389
390 base = tegra186_gpio_get_base(gpio, offset);
391 if (base == NULL)
392 return -ENXIO;
393
394 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
395 return -ENOTSUPP;
396
397 debounce = pinconf_to_config_argument(config);
398
399 /*
400 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce
401 * time.
402 */
403 if (debounce > 255000)
404 return -EINVAL;
405
406 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC);
407
408 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce);
409 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL);
410
411 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
412 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE;
413 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
414
415 return 0;
416}
417
418static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
419{
420 struct tegra_gpio *gpio = gpiochip_get_data(chip);
421 struct pinctrl_dev *pctldev;
422 struct device_node *np;
423 unsigned int i, j;
424 int err;
425
426 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
427 return 0;
428
429 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
430 if (!np)
431 return -ENODEV;
432
433 pctldev = of_pinctrl_get(np);
434 of_node_put(np);
435 if (!pctldev)
436 return -EPROBE_DEFER;
437
438 for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
439 unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
440 const char *group = gpio->soc->pin_ranges[i].group;
441
442 port = pin / 8;
443 pin = pin % 8;
444
445 if (port >= gpio->soc->num_ports) {
446 dev_warn(chip->parent, "invalid port %u for %s\n",
447 port, group);
448 continue;
449 }
450
451 for (j = 0; j < port; j++)
452 pin += gpio->soc->ports[j].pins;
453
454 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
455 if (err < 0)
456 return err;
457 }
458
459 return 0;
460}
461
462static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
463 const struct of_phandle_args *spec,
464 u32 *flags)
465{
466 struct tegra_gpio *gpio = gpiochip_get_data(chip);
467 unsigned int port, pin, i, offset = 0;
468
469 if (WARN_ON(chip->of_gpio_n_cells < 2))
470 return -EINVAL;
471
472 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
473 return -EINVAL;
474
475 port = spec->args[0] / 8;
476 pin = spec->args[0] % 8;
477
478 if (port >= gpio->soc->num_ports) {
479 dev_err(chip->parent, "invalid port number: %u\n", port);
480 return -EINVAL;
481 }
482
483 for (i = 0; i < port; i++)
484 offset += gpio->soc->ports[i].pins;
485
486 if (flags)
487 *flags = spec->args[1];
488
489 return offset + pin;
490}
491
492#define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio)
493
494static void tegra186_irq_ack(struct irq_data *data)
495{
496 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
497 struct tegra_gpio *gpio = to_tegra_gpio(gc);
498 void __iomem *base;
499
500 base = tegra186_gpio_get_base(gpio, data->hwirq);
501 if (WARN_ON(base == NULL))
502 return;
503
504 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
505}
506
507static void tegra186_irq_mask(struct irq_data *data)
508{
509 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
510 struct tegra_gpio *gpio = to_tegra_gpio(gc);
511 void __iomem *base;
512 u32 value;
513
514 base = tegra186_gpio_get_base(gpio, data->hwirq);
515 if (WARN_ON(base == NULL))
516 return;
517
518 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
519 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
520 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
521
522 gpiochip_disable_irq(&gpio->gpio, data->hwirq);
523}
524
525static void tegra186_irq_unmask(struct irq_data *data)
526{
527 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
528 struct tegra_gpio *gpio = to_tegra_gpio(gc);
529 void __iomem *base;
530 u32 value;
531
532 base = tegra186_gpio_get_base(gpio, data->hwirq);
533 if (WARN_ON(base == NULL))
534 return;
535
536 gpiochip_enable_irq(&gpio->gpio, data->hwirq);
537
538 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
539 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
540 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
541}
542
543static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
544{
545 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
546 struct tegra_gpio *gpio = to_tegra_gpio(gc);
547 void __iomem *base;
548 u32 value;
549
550 base = tegra186_gpio_get_base(gpio, data->hwirq);
551 if (WARN_ON(base == NULL))
552 return -ENODEV;
553
554 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
555 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
556 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
557
558 switch (type & IRQ_TYPE_SENSE_MASK) {
559 case IRQ_TYPE_NONE:
560 break;
561
562 case IRQ_TYPE_EDGE_RISING:
563 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
564 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
565 break;
566
567 case IRQ_TYPE_EDGE_FALLING:
568 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
569 break;
570
571 case IRQ_TYPE_EDGE_BOTH:
572 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
573 break;
574
575 case IRQ_TYPE_LEVEL_HIGH:
576 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
577 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
578 break;
579
580 case IRQ_TYPE_LEVEL_LOW:
581 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
582 break;
583
584 default:
585 return -EINVAL;
586 }
587
588 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
589
590 if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
591 irq_set_handler_locked(data, handle_level_irq);
592 else
593 irq_set_handler_locked(data, handle_edge_irq);
594
595 if (data->parent_data)
596 return irq_chip_set_type_parent(data, type);
597
598 return 0;
599}
600
601static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on)
602{
603 if (data->parent_data)
604 return irq_chip_set_wake_parent(data, on);
605
606 return 0;
607}
608
609static void tegra186_irq_print_chip(struct irq_data *data, struct seq_file *p)
610{
611 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
612
613 seq_puts(p, dev_name(gc->parent));
614}
615
616static const struct irq_chip tegra186_gpio_irq_chip = {
617 .irq_ack = tegra186_irq_ack,
618 .irq_mask = tegra186_irq_mask,
619 .irq_unmask = tegra186_irq_unmask,
620 .irq_set_type = tegra186_irq_set_type,
621 .irq_set_wake = tegra186_irq_set_wake,
622 .irq_print_chip = tegra186_irq_print_chip,
623 .flags = IRQCHIP_IMMUTABLE,
624 GPIOCHIP_IRQ_RESOURCE_HELPERS,
625};
626
627static void tegra186_gpio_irq(struct irq_desc *desc)
628{
629 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
630 struct irq_domain *domain = gpio->gpio.irq.domain;
631 struct irq_chip *chip = irq_desc_get_chip(desc);
632 unsigned int parent = irq_desc_get_irq(desc);
633 unsigned int i, j, offset = 0;
634
635 chained_irq_enter(chip, desc);
636
637 for (i = 0; i < gpio->soc->num_ports; i++) {
638 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
639 unsigned int pin;
640 unsigned long value;
641 void __iomem *base;
642
643 base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
644
645 /* skip ports that are not associated with this bank */
646 for (j = 0; j < gpio->num_irqs_per_bank; j++) {
647 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j])
648 break;
649 }
650
651 if (j == gpio->num_irqs_per_bank)
652 goto skip;
653
654 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
655
656 for_each_set_bit(pin, &value, port->pins) {
657 int ret = generic_handle_domain_irq(domain, offset + pin);
658 WARN_RATELIMIT(ret, "hwirq = %d", offset + pin);
659 }
660
661skip:
662 offset += port->pins;
663 }
664
665 chained_irq_exit(chip, desc);
666}
667
668static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain,
669 struct irq_fwspec *fwspec,
670 unsigned long *hwirq,
671 unsigned int *type)
672{
673 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
674 unsigned int port, pin, i, offset = 0;
675
676 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2))
677 return -EINVAL;
678
679 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells))
680 return -EINVAL;
681
682 port = fwspec->param[0] / 8;
683 pin = fwspec->param[0] % 8;
684
685 if (port >= gpio->soc->num_ports)
686 return -EINVAL;
687
688 for (i = 0; i < port; i++)
689 offset += gpio->soc->ports[i].pins;
690
691 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
692 *hwirq = offset + pin;
693
694 return 0;
695}
696
697static int tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,
698 union gpio_irq_fwspec *gfwspec,
699 unsigned int parent_hwirq,
700 unsigned int parent_type)
701{
702 struct tegra_gpio *gpio = gpiochip_get_data(chip);
703 struct irq_fwspec *fwspec = &gfwspec->fwspec;
704
705 fwspec->fwnode = chip->irq.parent_domain->fwnode;
706 fwspec->param_count = 3;
707 fwspec->param[0] = gpio->soc->instance;
708 fwspec->param[1] = parent_hwirq;
709 fwspec->param[2] = parent_type;
710
711 return 0;
712}
713
714static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
715 unsigned int hwirq,
716 unsigned int type,
717 unsigned int *parent_hwirq,
718 unsigned int *parent_type)
719{
720 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
721 *parent_type = type;
722
723 return 0;
724}
725
726static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip,
727 unsigned int offset)
728{
729 struct tegra_gpio *gpio = gpiochip_get_data(chip);
730 unsigned int i;
731
732 for (i = 0; i < gpio->soc->num_ports; i++) {
733 if (offset < gpio->soc->ports[i].pins)
734 break;
735
736 offset -= gpio->soc->ports[i].pins;
737 }
738
739 return offset + i * 8;
740}
741
742static const struct of_device_id tegra186_pmc_of_match[] = {
743 { .compatible = "nvidia,tegra186-pmc" },
744 { .compatible = "nvidia,tegra194-pmc" },
745 { .compatible = "nvidia,tegra234-pmc" },
746 { /* sentinel */ }
747};
748
749static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
750{
751 struct device *dev = gpio->gpio.parent;
752 unsigned int i;
753 u32 value;
754
755 for (i = 0; i < gpio->soc->num_ports; i++) {
756 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
757 unsigned int offset, p = port->port;
758 void __iomem *base;
759
760 base = gpio->secure + port->bank * 0x1000 + 0x800;
761
762 value = readl(base + TEGRA186_GPIO_CTL_SCR);
763
764 /*
765 * For controllers that haven't been locked down yet, make
766 * sure to program the default interrupt route mapping.
767 */
768 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
769 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
770 /*
771 * On Tegra194 and later, each pin can be routed to one or more
772 * interrupts.
773 */
774 dev_dbg(dev, "programming default interrupt routing for port %s\n",
775 port->name);
776
777 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, 0);
778
779 /*
780 * By default we only want to route GPIO pins to IRQ 0. This works
781 * only under the assumption that we're running as the host kernel
782 * and hence all GPIO pins are owned by Linux.
783 *
784 * For cases where Linux is the guest OS, the hypervisor will have
785 * to configure the interrupt routing and pass only the valid
786 * interrupts via device tree.
787 */
788 value = readl(base + offset);
789 value = BIT(port->pins) - 1;
790 writel(value, base + offset);
791 }
792 }
793}
794
795static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio)
796{
797 struct device *dev = gpio->gpio.parent;
798
799 if (gpio->num_irq > gpio->num_banks) {
800 if (gpio->num_irq % gpio->num_banks != 0)
801 goto error;
802 }
803
804 if (gpio->num_irq < gpio->num_banks)
805 goto error;
806
807 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks;
808
809 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank)
810 goto error;
811
812 return 0;
813
814error:
815 dev_err(dev, "invalid number of interrupts (%u) for %u banks\n",
816 gpio->num_irq, gpio->num_banks);
817 return -EINVAL;
818}
819
820static int tegra186_gpio_probe(struct platform_device *pdev)
821{
822 unsigned int i, j, offset;
823 struct gpio_irq_chip *irq;
824 struct tegra_gpio *gpio;
825 struct device_node *np;
826 char **names;
827 int err;
828
829 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
830 if (!gpio)
831 return -ENOMEM;
832
833 gpio->soc = device_get_match_data(&pdev->dev);
834 gpio->gpio.label = gpio->soc->name;
835 gpio->gpio.parent = &pdev->dev;
836
837 /* count the number of banks in the controller */
838 for (i = 0; i < gpio->soc->num_ports; i++)
839 if (gpio->soc->ports[i].bank > gpio->num_banks)
840 gpio->num_banks = gpio->soc->ports[i].bank;
841
842 gpio->num_banks++;
843
844 /* get register apertures */
845 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security");
846 if (IS_ERR(gpio->secure)) {
847 gpio->secure = devm_platform_ioremap_resource(pdev, 0);
848 if (IS_ERR(gpio->secure))
849 return PTR_ERR(gpio->secure);
850 }
851
852 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
853 if (IS_ERR(gpio->base)) {
854 gpio->base = devm_platform_ioremap_resource(pdev, 1);
855 if (IS_ERR(gpio->base))
856 return PTR_ERR(gpio->base);
857 }
858
859 err = platform_irq_count(pdev);
860 if (err < 0)
861 return err;
862
863 gpio->num_irq = err;
864
865 err = tegra186_gpio_irqs_per_bank(gpio);
866 if (err < 0)
867 return err;
868
869 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
870 GFP_KERNEL);
871 if (!gpio->irq)
872 return -ENOMEM;
873
874 for (i = 0; i < gpio->num_irq; i++) {
875 err = platform_get_irq(pdev, i);
876 if (err < 0)
877 return err;
878
879 gpio->irq[i] = err;
880 }
881
882 gpio->gpio.request = gpiochip_generic_request;
883 gpio->gpio.free = gpiochip_generic_free;
884 gpio->gpio.get_direction = tegra186_gpio_get_direction;
885 gpio->gpio.direction_input = tegra186_gpio_direction_input;
886 gpio->gpio.direction_output = tegra186_gpio_direction_output;
887 gpio->gpio.get = tegra186_gpio_get;
888 gpio->gpio.set = tegra186_gpio_set;
889 gpio->gpio.set_config = tegra186_gpio_set_config;
890 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
891 gpio->gpio.init_valid_mask = tegra186_init_valid_mask;
892 if (gpio->soc->has_gte) {
893 gpio->gpio.en_hw_timestamp = tegra186_gpio_en_hw_ts;
894 gpio->gpio.dis_hw_timestamp = tegra186_gpio_dis_hw_ts;
895 }
896
897 gpio->gpio.base = -1;
898
899 for (i = 0; i < gpio->soc->num_ports; i++)
900 gpio->gpio.ngpio += gpio->soc->ports[i].pins;
901
902 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
903 sizeof(*names), GFP_KERNEL);
904 if (!names)
905 return -ENOMEM;
906
907 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
908 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
909 char *name;
910
911 for (j = 0; j < port->pins; j++) {
912 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
913 "P%s.%02x", port->name, j);
914 if (!name)
915 return -ENOMEM;
916
917 names[offset + j] = name;
918 }
919
920 offset += port->pins;
921 }
922
923 gpio->gpio.names = (const char * const *)names;
924
925#if defined(CONFIG_OF_GPIO)
926 gpio->gpio.of_gpio_n_cells = 2;
927 gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
928#endif /* CONFIG_OF_GPIO */
929
930 irq = &gpio->gpio.irq;
931 gpio_irq_chip_set_chip(irq, &tegra186_gpio_irq_chip);
932 irq->fwnode = dev_fwnode(&pdev->dev);
933 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq;
934 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec;
935 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq;
936 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate;
937 irq->handler = handle_simple_irq;
938 irq->default_type = IRQ_TYPE_NONE;
939 irq->parent_handler = tegra186_gpio_irq;
940 irq->parent_handler_data = gpio;
941 irq->num_parents = gpio->num_irq;
942
943 /*
944 * To simplify things, use a single interrupt per bank for now. Some
945 * chips support up to 8 interrupts per bank, which can be useful to
946 * distribute the load and decrease the processing latency for GPIOs
947 * but it also requires a more complicated interrupt routing than we
948 * currently program.
949 */
950 if (gpio->num_irqs_per_bank > 1) {
951 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks,
952 sizeof(*irq->parents), GFP_KERNEL);
953 if (!irq->parents)
954 return -ENOMEM;
955
956 for (i = 0; i < gpio->num_banks; i++)
957 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank];
958
959 irq->num_parents = gpio->num_banks;
960 } else {
961 irq->num_parents = gpio->num_irq;
962 irq->parents = gpio->irq;
963 }
964
965 if (gpio->soc->num_irqs_per_bank > 1)
966 tegra186_gpio_init_route_mapping(gpio);
967
968 np = of_find_matching_node(NULL, tegra186_pmc_of_match);
969 if (np) {
970 if (of_device_is_available(np)) {
971 irq->parent_domain = irq_find_host(np);
972 of_node_put(np);
973
974 if (!irq->parent_domain)
975 return -EPROBE_DEFER;
976 } else {
977 of_node_put(np);
978 }
979 }
980
981 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
982 sizeof(*irq->map), GFP_KERNEL);
983 if (!irq->map)
984 return -ENOMEM;
985
986 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
987 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
988
989 for (j = 0; j < port->pins; j++)
990 irq->map[offset + j] = irq->parents[port->bank];
991
992 offset += port->pins;
993 }
994
995 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
996}
997
998#define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
999 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \
1000 .name = #_name, \
1001 .bank = _bank, \
1002 .port = _port, \
1003 .pins = _pins, \
1004 }
1005
1006static const struct tegra_gpio_port tegra186_main_ports[] = {
1007 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
1008 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),
1009 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7),
1010 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6),
1011 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8),
1012 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6),
1013 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6),
1014 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7),
1015 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8),
1016 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8),
1017 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1),
1018 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8),
1019 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),
1020 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7),
1021 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4),
1022 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7),
1023 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6),
1024 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6),
1025 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4),
1026 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8),
1027 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7),
1028 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),
1029 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),
1030};
1031
1032static const struct tegra_gpio_soc tegra186_main_soc = {
1033 .num_ports = ARRAY_SIZE(tegra186_main_ports),
1034 .ports = tegra186_main_ports,
1035 .name = "tegra186-gpio",
1036 .instance = 0,
1037 .num_irqs_per_bank = 1,
1038 .has_vm_support = false,
1039};
1040
1041#define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1042 [TEGRA186_AON_GPIO_PORT_##_name] = { \
1043 .name = #_name, \
1044 .bank = _bank, \
1045 .port = _port, \
1046 .pins = _pins, \
1047 }
1048
1049static const struct tegra_gpio_port tegra186_aon_ports[] = {
1050 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),
1051 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6),
1052 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8),
1053 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8),
1054 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4),
1055 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8),
1056 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3),
1057 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5),
1058};
1059
1060static const struct tegra_gpio_soc tegra186_aon_soc = {
1061 .num_ports = ARRAY_SIZE(tegra186_aon_ports),
1062 .ports = tegra186_aon_ports,
1063 .name = "tegra186-gpio-aon",
1064 .instance = 1,
1065 .num_irqs_per_bank = 1,
1066 .has_vm_support = false,
1067};
1068
1069#define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1070 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \
1071 .name = #_name, \
1072 .bank = _bank, \
1073 .port = _port, \
1074 .pins = _pins, \
1075 }
1076
1077static const struct tegra_gpio_port tegra194_main_ports[] = {
1078 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),
1079 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2),
1080 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8),
1081 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4),
1082 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8),
1083 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6),
1084 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8),
1085 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8),
1086 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5),
1087 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6),
1088 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8),
1089 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4),
1090 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),
1091 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3),
1092 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6),
1093 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8),
1094 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8),
1095 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6),
1096 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8),
1097 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8),
1098 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1),
1099 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8),
1100 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2),
1101 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8),
1102 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8),
1103 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8),
1104 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2),
1105 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
1106};
1107
1108static const struct tegra186_pin_range tegra194_main_pin_ranges[] = {
1109 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" },
1110 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" },
1111};
1112
1113static const struct tegra_gpio_soc tegra194_main_soc = {
1114 .num_ports = ARRAY_SIZE(tegra194_main_ports),
1115 .ports = tegra194_main_ports,
1116 .name = "tegra194-gpio",
1117 .instance = 0,
1118 .num_irqs_per_bank = 8,
1119 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
1120 .pin_ranges = tegra194_main_pin_ranges,
1121 .pinmux = "nvidia,tegra194-pinmux",
1122 .has_vm_support = true,
1123};
1124
1125#define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1126 [TEGRA194_AON_GPIO_PORT_##_name] = { \
1127 .name = #_name, \
1128 .bank = _bank, \
1129 .port = _port, \
1130 .pins = _pins, \
1131 }
1132
1133static const struct tegra_gpio_port tegra194_aon_ports[] = {
1134 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),
1135 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),
1136 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),
1137 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3),
1138 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7)
1139};
1140
1141static const struct tegra_gpio_soc tegra194_aon_soc = {
1142 .num_ports = ARRAY_SIZE(tegra194_aon_ports),
1143 .ports = tegra194_aon_ports,
1144 .name = "tegra194-gpio-aon",
1145 .instance = 1,
1146 .num_irqs_per_bank = 8,
1147 .has_gte = true,
1148 .has_vm_support = false,
1149};
1150
1151#define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1152 [TEGRA234_MAIN_GPIO_PORT_##_name] = { \
1153 .name = #_name, \
1154 .bank = _bank, \
1155 .port = _port, \
1156 .pins = _pins, \
1157 }
1158
1159static const struct tegra_gpio_port tegra234_main_ports[] = {
1160 TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8),
1161 TEGRA234_MAIN_GPIO_PORT( B, 0, 3, 1),
1162 TEGRA234_MAIN_GPIO_PORT( C, 5, 1, 8),
1163 TEGRA234_MAIN_GPIO_PORT( D, 5, 2, 4),
1164 TEGRA234_MAIN_GPIO_PORT( E, 5, 3, 8),
1165 TEGRA234_MAIN_GPIO_PORT( F, 5, 4, 6),
1166 TEGRA234_MAIN_GPIO_PORT( G, 4, 0, 8),
1167 TEGRA234_MAIN_GPIO_PORT( H, 4, 1, 8),
1168 TEGRA234_MAIN_GPIO_PORT( I, 4, 2, 7),
1169 TEGRA234_MAIN_GPIO_PORT( J, 5, 0, 6),
1170 TEGRA234_MAIN_GPIO_PORT( K, 3, 0, 8),
1171 TEGRA234_MAIN_GPIO_PORT( L, 3, 1, 4),
1172 TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8),
1173 TEGRA234_MAIN_GPIO_PORT( N, 2, 1, 8),
1174 TEGRA234_MAIN_GPIO_PORT( P, 2, 2, 8),
1175 TEGRA234_MAIN_GPIO_PORT( Q, 2, 3, 8),
1176 TEGRA234_MAIN_GPIO_PORT( R, 2, 4, 6),
1177 TEGRA234_MAIN_GPIO_PORT( X, 1, 0, 8),
1178 TEGRA234_MAIN_GPIO_PORT( Y, 1, 1, 8),
1179 TEGRA234_MAIN_GPIO_PORT( Z, 1, 2, 8),
1180 TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8),
1181 TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4),
1182 TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2),
1183 TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4),
1184 TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8),
1185};
1186
1187static const struct tegra_gpio_soc tegra234_main_soc = {
1188 .num_ports = ARRAY_SIZE(tegra234_main_ports),
1189 .ports = tegra234_main_ports,
1190 .name = "tegra234-gpio",
1191 .instance = 0,
1192 .num_irqs_per_bank = 8,
1193 .has_vm_support = true,
1194};
1195
1196#define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1197 [TEGRA234_AON_GPIO_PORT_##_name] = { \
1198 .name = #_name, \
1199 .bank = _bank, \
1200 .port = _port, \
1201 .pins = _pins, \
1202 }
1203
1204static const struct tegra_gpio_port tegra234_aon_ports[] = {
1205 TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8),
1206 TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4),
1207 TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8),
1208 TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3),
1209 TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8),
1210 TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1),
1211};
1212
1213static const struct tegra_gpio_soc tegra234_aon_soc = {
1214 .num_ports = ARRAY_SIZE(tegra234_aon_ports),
1215 .ports = tegra234_aon_ports,
1216 .name = "tegra234-gpio-aon",
1217 .instance = 1,
1218 .num_irqs_per_bank = 8,
1219 .has_gte = true,
1220 .has_vm_support = false,
1221};
1222
1223#define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1224 [TEGRA241_MAIN_GPIO_PORT_##_name] = { \
1225 .name = #_name, \
1226 .bank = _bank, \
1227 .port = _port, \
1228 .pins = _pins, \
1229 }
1230
1231static const struct tegra_gpio_port tegra241_main_ports[] = {
1232 TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8),
1233 TEGRA241_MAIN_GPIO_PORT(B, 0, 1, 8),
1234 TEGRA241_MAIN_GPIO_PORT(C, 0, 2, 2),
1235 TEGRA241_MAIN_GPIO_PORT(D, 0, 3, 6),
1236 TEGRA241_MAIN_GPIO_PORT(E, 0, 4, 8),
1237 TEGRA241_MAIN_GPIO_PORT(F, 1, 0, 8),
1238 TEGRA241_MAIN_GPIO_PORT(G, 1, 1, 8),
1239 TEGRA241_MAIN_GPIO_PORT(H, 1, 2, 8),
1240 TEGRA241_MAIN_GPIO_PORT(J, 1, 3, 8),
1241 TEGRA241_MAIN_GPIO_PORT(K, 1, 4, 4),
1242 TEGRA241_MAIN_GPIO_PORT(L, 1, 5, 6),
1243};
1244
1245static const struct tegra_gpio_soc tegra241_main_soc = {
1246 .num_ports = ARRAY_SIZE(tegra241_main_ports),
1247 .ports = tegra241_main_ports,
1248 .name = "tegra241-gpio",
1249 .instance = 0,
1250 .num_irqs_per_bank = 8,
1251 .has_vm_support = false,
1252};
1253
1254#define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1255 [TEGRA241_AON_GPIO_PORT_##_name] = { \
1256 .name = #_name, \
1257 .bank = _bank, \
1258 .port = _port, \
1259 .pins = _pins, \
1260 }
1261
1262static const struct tegra_gpio_port tegra241_aon_ports[] = {
1263 TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8),
1264 TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4),
1265};
1266
1267static const struct tegra_gpio_soc tegra241_aon_soc = {
1268 .num_ports = ARRAY_SIZE(tegra241_aon_ports),
1269 .ports = tegra241_aon_ports,
1270 .name = "tegra241-gpio-aon",
1271 .instance = 1,
1272 .num_irqs_per_bank = 8,
1273 .has_vm_support = false,
1274};
1275
1276static const struct of_device_id tegra186_gpio_of_match[] = {
1277 {
1278 .compatible = "nvidia,tegra186-gpio",
1279 .data = &tegra186_main_soc
1280 }, {
1281 .compatible = "nvidia,tegra186-gpio-aon",
1282 .data = &tegra186_aon_soc
1283 }, {
1284 .compatible = "nvidia,tegra194-gpio",
1285 .data = &tegra194_main_soc
1286 }, {
1287 .compatible = "nvidia,tegra194-gpio-aon",
1288 .data = &tegra194_aon_soc
1289 }, {
1290 .compatible = "nvidia,tegra234-gpio",
1291 .data = &tegra234_main_soc
1292 }, {
1293 .compatible = "nvidia,tegra234-gpio-aon",
1294 .data = &tegra234_aon_soc
1295 }, {
1296 /* sentinel */
1297 }
1298};
1299MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match);
1300
1301static const struct acpi_device_id tegra186_gpio_acpi_match[] = {
1302 { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc },
1303 { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc },
1304 { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc },
1305 { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc },
1306 { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc },
1307 { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc },
1308 {}
1309};
1310MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match);
1311
1312static struct platform_driver tegra186_gpio_driver = {
1313 .driver = {
1314 .name = "tegra186-gpio",
1315 .of_match_table = tegra186_gpio_of_match,
1316 .acpi_match_table = tegra186_gpio_acpi_match,
1317 },
1318 .probe = tegra186_gpio_probe,
1319};
1320module_platform_driver(tegra186_gpio_driver);
1321
1322MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
1323MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1324MODULE_LICENSE("GPL v2");