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v6.8
  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Keymile kmcoge4 Device Tree Source, based on the P2041RDB DTS
  4 *
  5 * (C) Copyright 2014
  6 * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
  7 *
  8 * Copyright 2011 Freescale Semiconductor Inc.
  9 */
 10
 11/include/ "p2041si-pre.dtsi"
 12
 13/ {
 14	model = "keymile,kmcoge4";
 15	compatible = "keymile,kmcoge4", "keymile,kmp204x";
 16	#address-cells = <2>;
 17	#size-cells = <2>;
 18	interrupt-parent = <&mpic>;
 19
 20	memory {
 21		device_type = "memory";
 22	};
 23
 24	reserved-memory {
 25		#address-cells = <2>;
 26		#size-cells = <2>;
 27		ranges;
 28
 29		bman_fbpr: bman-fbpr {
 30			size = <0 0x1000000>;
 31			alignment = <0 0x1000000>;
 32		};
 33		qman_fqd: qman-fqd {
 34			size = <0 0x400000>;
 35			alignment = <0 0x400000>;
 36		};
 37		qman_pfdr: qman-pfdr {
 38			size = <0 0x2000000>;
 39			alignment = <0 0x2000000>;
 40		};
 41	};
 42
 43	dcsr: dcsr@f00000000 {
 44		ranges = <0x00000000 0xf 0x00000000 0x01008000>;
 45	};
 46
 47	bportals: bman-portals@ff4000000 {
 48		ranges = <0x0 0xf 0xf4000000 0x200000>;
 49	};
 50
 51	qportals: qman-portals@ff4200000 {
 52		ranges = <0x0 0xf 0xf4200000 0x200000>;
 53	};
 54
 55	soc: soc@ffe000000 {
 56		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
 57		reg = <0xf 0xfe000000 0 0x00001000>;
 58		spi@110000 {
 59			flash@0 {
 60				#address-cells = <1>;
 61				#size-cells = <1>;
 62				compatible = "spansion,s25fl256s1", "jedec,spi-nor";
 63				reg = <0>;
 64				spi-max-frequency = <20000000>; /* input clock */
 65			};
 66
 67			network_clock@1 {
 68				compatible = "zarlink,zl30343";
 69				reg = <1>;
 70				spi-max-frequency = <8000000>;
 71			};
 72
 73			flash@2 {
 74				#address-cells = <1>;
 75				#size-cells = <1>;
 76				compatible = "micron,m25p32", "jedec,spi-nor";
 77				reg = <2>;
 78				spi-max-frequency = <15000000>;
 79			};
 80		};
 81
 82		sdhc@114000 {
 83			status = "disabled";
 84		};
 85
 86		i2c@119000 {
 87			status = "disabled";
 88		};
 89
 90		i2c@119100 {
 91			status = "disabled";
 92		};
 93
 94		usb0: usb@210000 {
 95			status = "disabled";
 96		};
 97
 98		usb1: usb@211000 {
 99			status = "disabled";
100		};
101
102		sata@220000 {
103			status = "disabled";
104		};
105
106		sata@221000 {
107			status = "disabled";
108		};
109
110		fman0: fman@400000 {
111			enet0: ethernet@e0000 {
112				phy-connection-type = "sgmii";
113				fixed-link {
114					speed = <1000>;
115					full-duplex;
116				};
117			};
118			mdio0: mdio@e1120 {
119				front_phy: ethernet-phy@11 {
120					reg = <0x11>;
121				};
122			};
123
124			enet1: ethernet@e2000 {
125				phy-connection-type = "sgmii";
126				fixed-link {
127					speed = <1000>;
128					full-duplex;
129				};
130			};
131			enet2: ethernet@e4000 {
132				status = "disabled";
133			};
134
135			enet3: ethernet@e6000 {
136				status = "disabled";
137			};
138			enet4: ethernet@e8000 {
139				phy-handle = <&front_phy>;
140				phy-connection-type = "rgmii";
141			};
142			enet5: ethernet@f0000 {
143				status = "disabled";
144			};
145		};
146	};
147
148	rio: rapidio@ffe0c0000 {
149		status = "disabled";
150	};
151
152	lbc: localbus@ffe124000 {
153		reg = <0xf 0xfe124000 0 0x1000>;
154		ranges = <0 0 0xf 0xffa00000 0x00040000		/* LB 0 */
155			  1 0 0xf 0xfb000000 0x00010000		/* LB 1 */
156			  2 0 0xf 0xd0000000 0x10000000		/* LB 2 */
157			  3 0 0xf 0xe0000000 0x10000000>;	/* LB 3 */
158
159		nand@0,0 {
160			#address-cells = <1>;
161			#size-cells = <1>;
162			compatible = "fsl,elbc-fcm-nand";
163			reg = <0 0 0x40000>;
164		};
165
166		board-control@1,0 {
167			compatible = "keymile,qriox";
168			reg = <1 0 0x80>;
169		};
170
171		chassis-mgmt@3,0 {
172			compatible = "keymile,bfticu";
173			interrupt-controller;
174			#interrupt-cells = <2>;
175			reg = <3 0 0x100>;
176			interrupt-parent = <&mpic>;
177			interrupts = <6 1 0 0>;
178		};
179	};
180
181	pci0: pcie@ffe200000 {
182		reg = <0xf 0xfe200000 0 0x1000>;
183		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
184			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
185		pcie@0 {
186			ranges = <0x02000000 0 0xe0000000
187				  0x02000000 0 0xe0000000
188				  0 0x20000000
189
190				  0x01000000 0 0x00000000
191				  0x01000000 0 0x00000000
192				  0 0x00010000>;
193		};
194	};
195
196	pci1: pcie@ffe201000 {
197		status = "disabled";
198	};
199
200	pci2: pcie@ffe202000 {
201		reg = <0xf 0xfe202000 0 0x1000>;
202		ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
203			  0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>;
204		pcie@0 {
205			ranges = <0x02000000 0 0xe0000000
206				  0x02000000 0 0xe0000000
207				  0 0x20000000
208
209				  0x01000000 0 0x00000000
210				  0x01000000 0 0x00000000
211				  0 0x00010000>;
212		};
213	};
214};
215
216/include/ "p2041si-post.dtsi"
v6.13.7
  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Keymile kmcoge4 Device Tree Source, based on the P2041RDB DTS
  4 *
  5 * (C) Copyright 2014
  6 * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
  7 *
  8 * Copyright 2011 Freescale Semiconductor Inc.
  9 */
 10
 11/include/ "p2041si-pre.dtsi"
 12
 13/ {
 14	model = "keymile,kmcoge4";
 15	compatible = "keymile,kmcoge4", "keymile,kmp204x";
 16	#address-cells = <2>;
 17	#size-cells = <2>;
 18	interrupt-parent = <&mpic>;
 19
 20	memory {
 21		device_type = "memory";
 22	};
 23
 24	reserved-memory {
 25		#address-cells = <2>;
 26		#size-cells = <2>;
 27		ranges;
 28
 29		bman_fbpr: bman-fbpr {
 30			size = <0 0x1000000>;
 31			alignment = <0 0x1000000>;
 32		};
 33		qman_fqd: qman-fqd {
 34			size = <0 0x400000>;
 35			alignment = <0 0x400000>;
 36		};
 37		qman_pfdr: qman-pfdr {
 38			size = <0 0x2000000>;
 39			alignment = <0 0x2000000>;
 40		};
 41	};
 42
 43	dcsr: dcsr@f00000000 {
 44		ranges = <0x00000000 0xf 0x00000000 0x01008000>;
 45	};
 46
 47	bportals: bman-portals@ff4000000 {
 48		ranges = <0x0 0xf 0xf4000000 0x200000>;
 49	};
 50
 51	qportals: qman-portals@ff4200000 {
 52		ranges = <0x0 0xf 0xf4200000 0x200000>;
 53	};
 54
 55	soc: soc@ffe000000 {
 56		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
 57		reg = <0xf 0xfe000000 0 0x00001000>;
 58		spi@110000 {
 59			flash@0 {
 60				#address-cells = <1>;
 61				#size-cells = <1>;
 62				compatible = "spansion,s25fl256s1", "jedec,spi-nor";
 63				reg = <0>;
 64				spi-max-frequency = <20000000>; /* input clock */
 65			};
 66
 67			network_clock@1 {
 68				compatible = "zarlink,zl30343";
 69				reg = <1>;
 70				spi-max-frequency = <8000000>;
 71			};
 72
 73			flash@2 {
 74				#address-cells = <1>;
 75				#size-cells = <1>;
 76				compatible = "micron,m25p32", "jedec,spi-nor";
 77				reg = <2>;
 78				spi-max-frequency = <15000000>;
 79			};
 80		};
 81
 82		sdhc@114000 {
 83			status = "disabled";
 84		};
 85
 86		i2c@119000 {
 87			status = "disabled";
 88		};
 89
 90		i2c@119100 {
 91			status = "disabled";
 92		};
 93
 94		usb0: usb@210000 {
 95			status = "disabled";
 96		};
 97
 98		usb1: usb@211000 {
 99			status = "disabled";
100		};
101
102		sata@220000 {
103			status = "disabled";
104		};
105
106		sata@221000 {
107			status = "disabled";
108		};
109
110		fman0: fman@400000 {
111			enet0: ethernet@e0000 {
112				phy-connection-type = "sgmii";
113				fixed-link {
114					speed = <1000>;
115					full-duplex;
116				};
117			};
118			mdio0: mdio@e1120 {
119				front_phy: ethernet-phy@11 {
120					reg = <0x11>;
121				};
122			};
123
124			enet1: ethernet@e2000 {
125				phy-connection-type = "sgmii";
126				fixed-link {
127					speed = <1000>;
128					full-duplex;
129				};
130			};
131			enet2: ethernet@e4000 {
132				status = "disabled";
133			};
134
135			enet3: ethernet@e6000 {
136				status = "disabled";
137			};
138			enet4: ethernet@e8000 {
139				phy-handle = <&front_phy>;
140				phy-connection-type = "rgmii";
141			};
142			enet5: ethernet@f0000 {
143				status = "disabled";
144			};
145		};
146	};
147
148	rio: rapidio@ffe0c0000 {
149		status = "disabled";
150	};
151
152	lbc: localbus@ffe124000 {
153		reg = <0xf 0xfe124000 0 0x1000>;
154		ranges = <0 0 0xf 0xffa00000 0x00040000		/* LB 0 */
155			  1 0 0xf 0xfb000000 0x00010000		/* LB 1 */
156			  2 0 0xf 0xd0000000 0x10000000		/* LB 2 */
157			  3 0 0xf 0xe0000000 0x10000000>;	/* LB 3 */
158
159		nand@0,0 {
160			#address-cells = <1>;
161			#size-cells = <1>;
162			compatible = "fsl,elbc-fcm-nand";
163			reg = <0 0 0x40000>;
164		};
165
166		board-control@1,0 {
167			compatible = "keymile,qriox";
168			reg = <1 0 0x80>;
169		};
170
171		chassis-mgmt@3,0 {
172			compatible = "keymile,bfticu";
173			interrupt-controller;
174			#interrupt-cells = <2>;
175			reg = <3 0 0x100>;
176			interrupt-parent = <&mpic>;
177			interrupts = <6 1 0 0>;
178		};
179	};
180
181	pci0: pcie@ffe200000 {
182		reg = <0xf 0xfe200000 0 0x1000>;
183		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
184			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
185		pcie@0 {
186			ranges = <0x02000000 0 0xe0000000
187				  0x02000000 0 0xe0000000
188				  0 0x20000000
189
190				  0x01000000 0 0x00000000
191				  0x01000000 0 0x00000000
192				  0 0x00010000>;
193		};
194	};
195
196	pci1: pcie@ffe201000 {
197		status = "disabled";
198	};
199
200	pci2: pcie@ffe202000 {
201		reg = <0xf 0xfe202000 0 0x1000>;
202		ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
203			  0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>;
204		pcie@0 {
205			ranges = <0x02000000 0 0xe0000000
206				  0x02000000 0 0xe0000000
207				  0 0x20000000
208
209				  0x01000000 0 0x00000000
210				  0x01000000 0 0x00000000
211				  0 0x00010000>;
212		};
213	};
214};
215
216/include/ "p2041si-post.dtsi"