1/* SPDX-License-Identifier: GPL-2.0 */
 2#ifndef __ASM_RC32434_IRQ_H
 3#define __ASM_RC32434_IRQ_H
 4
 5#define NR_IRQS 256
 6
 7#include <asm/mach-generic/irq.h>
 8#include <asm/mach-rc32434/rb.h>
 9
10/* Interrupt Controller */
11#define IC_GROUP0_PEND		(REGBASE + 0x38000)
12#define IC_GROUP0_MASK		(REGBASE + 0x38008)
13#define IC_GROUP_OFFSET		0x0C
14
15#define NUM_INTR_GROUPS		5
16
17/* 16550 UARTs */
18#define GROUP0_IRQ_BASE		8	/* GRP2 IRQ numbers start here */
19					/* GRP3 IRQ numbers start here */
20#define GROUP1_IRQ_BASE		(GROUP0_IRQ_BASE + 32)
21					/* GRP4 IRQ numbers start here */
22#define GROUP2_IRQ_BASE		(GROUP1_IRQ_BASE + 32)
23					/* GRP5 IRQ numbers start here */
24#define GROUP3_IRQ_BASE		(GROUP2_IRQ_BASE + 32)
25#define GROUP4_IRQ_BASE		(GROUP3_IRQ_BASE + 32)
26
27#define UART0_IRQ		(GROUP3_IRQ_BASE + 0)
28
29#define ETH0_DMA_RX_IRQ		(GROUP1_IRQ_BASE + 0)
30#define ETH0_DMA_TX_IRQ		(GROUP1_IRQ_BASE + 1)
31#define ETH0_RX_OVR_IRQ		(GROUP3_IRQ_BASE + 9)
32#define ETH0_TX_UND_IRQ		(GROUP3_IRQ_BASE + 10)
33
34#define GPIO_MAPPED_IRQ_BASE	GROUP4_IRQ_BASE
35#define GPIO_MAPPED_IRQ_GROUP	4
36
37#endif	/* __ASM_RC32434_IRQ_H */

 1/* SPDX-License-Identifier: GPL-2.0 */
 2#ifndef __ASM_RC32434_IRQ_H
 3#define __ASM_RC32434_IRQ_H
 4
 5#define NR_IRQS 256
 6
 7#include <asm/mach-generic/irq.h>
 8#include <asm/mach-rc32434/rb.h>
 9
10/* Interrupt Controller */
11#define IC_GROUP0_PEND		(REGBASE + 0x38000)
12#define IC_GROUP0_MASK		(REGBASE + 0x38008)
13#define IC_GROUP_OFFSET		0x0C
14
15#define NUM_INTR_GROUPS		5
16
17/* 16550 UARTs */
18#define GROUP0_IRQ_BASE		8	/* GRP2 IRQ numbers start here */
19					/* GRP3 IRQ numbers start here */
20#define GROUP1_IRQ_BASE		(GROUP0_IRQ_BASE + 32)
21					/* GRP4 IRQ numbers start here */
22#define GROUP2_IRQ_BASE		(GROUP1_IRQ_BASE + 32)
23					/* GRP5 IRQ numbers start here */
24#define GROUP3_IRQ_BASE		(GROUP2_IRQ_BASE + 32)
25#define GROUP4_IRQ_BASE		(GROUP3_IRQ_BASE + 32)
26
27#define UART0_IRQ		(GROUP3_IRQ_BASE + 0)
28
29#define ETH0_DMA_RX_IRQ		(GROUP1_IRQ_BASE + 0)
30#define ETH0_DMA_TX_IRQ		(GROUP1_IRQ_BASE + 1)
31#define ETH0_RX_OVR_IRQ		(GROUP3_IRQ_BASE + 9)
32#define ETH0_TX_UND_IRQ		(GROUP3_IRQ_BASE + 10)
33
34#define GPIO_MAPPED_IRQ_BASE	GROUP4_IRQ_BASE
35#define GPIO_MAPPED_IRQ_GROUP	4
36
37#endif	/* __ASM_RC32434_IRQ_H */