1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
 4 */
 5
 6#ifndef VFIO_CDX_PRIVATE_H
 7#define VFIO_CDX_PRIVATE_H
 8
 9#define VFIO_CDX_OFFSET_SHIFT    40
10
11static inline u64 vfio_cdx_index_to_offset(u32 index)
12{
13	return ((u64)(index) << VFIO_CDX_OFFSET_SHIFT);
14}
15
 
 
 
 
 
 
 
 
16struct vfio_cdx_region {
17	u32			flags;
18	u32			type;
19	u64			addr;
20	resource_size_t		size;
21};
22
23struct vfio_cdx_device {
24	struct vfio_device	vdev;
25	struct vfio_cdx_region	*regions;
 
26	u32			flags;
27#define BME_SUPPORT BIT(0)
 
 
28};
 
 
 
 
 
 
 
29
30#endif /* VFIO_CDX_PRIVATE_H */

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
 4 */
 5
 6#ifndef VFIO_CDX_PRIVATE_H
 7#define VFIO_CDX_PRIVATE_H
 8
 9#define VFIO_CDX_OFFSET_SHIFT    40
10
11static inline u64 vfio_cdx_index_to_offset(u32 index)
12{
13	return ((u64)(index) << VFIO_CDX_OFFSET_SHIFT);
14}
15
16struct vfio_cdx_irq {
17	u32			flags;
18	u32			count;
19	int			irq_no;
20	struct eventfd_ctx	*trigger;
21	char			*name;
22};
23
24struct vfio_cdx_region {
25	u32			flags;
26	u32			type;
27	u64			addr;
28	resource_size_t		size;
29};
30
31struct vfio_cdx_device {
32	struct vfio_device	vdev;
33	struct vfio_cdx_region	*regions;
34	struct vfio_cdx_irq	*cdx_irqs;
35	u32			flags;
36#define BME_SUPPORT BIT(0)
37	u32			msi_count;
38	u8			config_msi;
39};
40
41int vfio_cdx_set_irqs_ioctl(struct vfio_cdx_device *vdev,
42			    u32 flags, unsigned int index,
43			    unsigned int start, unsigned int count,
44			    void *data);
45
46void vfio_cdx_irqs_cleanup(struct vfio_cdx_device *vdev);
47
48#endif /* VFIO_CDX_PRIVATE_H */